From 0f3d6b06ea06e5b0295e4a8222a25bc95a70c026 Mon Sep 17 00:00:00 2001 From: Nagabhushana Netagunte Date: Sat, 3 Sep 2011 22:21:04 -0400 Subject: da850: modifications for Logic PD Rev.3 AM18xx EVM AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. Signed-off-by: Rajashekhara, Sudhakar Signed-off-by: Nagabhushana Netagunte Signed-off-by: Sandeep Paulraj --- arch/arm/include/asm/arch-davinci/hardware.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/arch-davinci') diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 4a3af7d3b6..692d50755a 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -159,6 +159,10 @@ typedef volatile unsigned int * dv_reg_p; #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) -- cgit v1.2.1