From d3daba10f159cca7e9d24c6f154926a9b92c75e3 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Tue, 10 Dec 2013 15:02:22 +0530 Subject: ARM: AM43xx: EPOS_EVM: Add support for LPDDR2 AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-am33xx/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/include/asm/arch-am33xx/cpu.h') diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 3ee37dc4e7..9febfa2719 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -401,6 +401,11 @@ struct cm_perpll { unsigned int cpgmac0clkctrl; /* offset 0xB20 */ }; +struct cm_device_inst { + unsigned int cm_clkout1_ctrl; + unsigned int cm_dll_ctrl; +}; + struct cm_dpll { unsigned int resv1; unsigned int clktimer2clk; /* offset 0x04 */ -- cgit v1.2.1