From 7a139959d0de14a7efd0fe12b49b18e939468525 Mon Sep 17 00:00:00 2001 From: Alexey Ignatov Date: Sun, 12 Oct 2014 01:43:30 +0400 Subject: ARM: mxs: tools: Add support for boot progress display flag mkimage -T mxs now support new flag in config file: DISPLAYPROGRESS - makes boot process print HTLLC characters for each BootROM instruction. Signed-off-by: Alexey Ignatov --- arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg | 1 + arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 1 + arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg index 1520bba3fb..83953daf28 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 55510e9cd8..e7028092a2 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index bb78cb0c84..3f7bf59924 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,3 +1,4 @@ +DISPLAYPROGRESS SECTION 0x0 BOOTABLE TAG LAST LOAD 0x1000 spl/u-boot-spl.bin -- cgit v1.2.1 From db544b9662622826b8482c126c116ec366fcd58c Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Thu, 13 Nov 2014 17:59:15 +0100 Subject: imx: fix exception vectors relocation in imx27 Commit 3ff46cc4 fixed exception vectors setting in the general ARM case, by either copying the exception and indirect vector tables to normal (0x00000000) or high (0xFFFF0000) vectors address, or setting VBAR to U-Boot's base if applicable. i.MX27 SoC is ARM926E-JS, thus has only normal and high options, but does not provide RAM at 0xFFFF0000 and has only ROM at 0x00000000; it is therefore not possible to move or change its exception vectors. Besides, i.MX27 ROM code does provide an indirect vectors table but at a non-standard address and with the reset and reserved vectors missing. Turn the current vector relocation code into a weak routine called after relocate_code from crt0, and add strong version for i.MX27. Series-Cc: Heiko Schocher Signed-off-by: Albert ARIBAUD Reviewed-by: Stefano Babic Tested-by: Stefano Babic Tested-by: Philippe Reynes Tested-by: Philippe Reynes --- arch/arm/cpu/arm926ejs/mx27/Makefile | 4 +++ arch/arm/cpu/arm926ejs/mx27/relocate.S | 51 ++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) create mode 100644 arch/arm/cpu/arm926ejs/mx27/relocate.S (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm926ejs/mx27/Makefile b/arch/arm/cpu/arm926ejs/mx27/Makefile index 4976bbb89b..0edf1445fe 100644 --- a/arch/arm/cpu/arm926ejs/mx27/Makefile +++ b/arch/arm/cpu/arm926ejs/mx27/Makefile @@ -5,3 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y = generic.o reset.o timer.o + +ifndef CONFIG_SPL_BUILD +obj-y += relocate.o +endif diff --git a/arch/arm/cpu/arm926ejs/mx27/relocate.S b/arch/arm/cpu/arm926ejs/mx27/relocate.S new file mode 100644 index 0000000000..0c4b272889 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx27/relocate.S @@ -0,0 +1,51 @@ +/* + * relocate - i.MX27-specific vector relocation + * + * Copyright (c) 2013 Albert ARIBAUD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/* + * The i.MX27 SoC is very specific with respect to exceptions: it + * does not provide RAM at the high vectors address (0xFFFF0000), + * thus only the low address (0x00000000) is useable; but that is + * in ROM. Therefore, vectors cannot be changed at all. + * + * However, these ROM-based vectors actually just perform indirect + * calls through pointers located in RAM at SoC-specific addresses, + * as follows: + * + * Offset Exception Use by ROM code + * 0x00000000 reset indirect branch to [0x00000014] + * 0x00000004 undefined instruction indirect branch to [0xfffffef0] + * 0x00000008 software interrupt indirect branch to [0xfffffef4] + * 0x0000000c prefetch abort indirect branch to [0xfffffef8] + * 0x00000010 data abort indirect branch to [0xfffffefc] + * 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000 + * 0x00000018 IRQ indirect branch to [0xffffff00] + * 0x0000001c FIQ indirect branch to [0xffffff04] + * + * In order to initialize exceptions on i.MX27, we must copy U-Boot's + * indirect (not exception!) vector table into 0xfffffef0..0xffffff04 + * taking care not to copy vectors number 5 (reserved exception). + */ + + .section .text.relocate_vectors,"ax",%progbits + +ENTRY(relocate_vectors) + + ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */ + ldr r1, =32 /* size of vector table */ + add r0, r0, r1 /* skip to indirect table */ + ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */ + ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */ + stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */ + + bx lr + +ENDPROC(relocate_vectors) -- cgit v1.2.1 From 32c81ea65cc01103d3a615072690e7b5faf76656 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 14 Nov 2014 11:27:21 -0200 Subject: imx: consolidate set_chipselect_size function Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/soc.c | 31 ------------------------------- 1 file changed, 31 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 2d53669c89..3753c14df3 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) } #endif -void set_chipselect_size(int const cs_size) -{ - unsigned int reg; - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - reg = readl(&iomuxc_regs->gpr1); - - switch (cs_size) { - case CS0_128: - reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */ - reg |= 0x5; - break; - case CS0_64M_CS1_64M: - reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */ - reg |= 0x1B; - break; - case CS0_64M_CS1_32M_CS2_32M: - reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */ - reg |= 0x4B; - break; - case CS0_32M_CS1_32M_CS2_32M_CS3_32M: - reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */ - reg |= 0x249; - break; - default: - printf("Unknown chip select size: %d\n", cs_size); - break; - } - - writel(reg, &iomuxc_regs->gpr1); -} - #ifdef CONFIG_MX53 void boot_mode_apply(unsigned cfg_val) { -- cgit v1.2.1 From cf202d268b5d27b84a8c6df1d749ed3967451be4 Mon Sep 17 00:00:00 2001 From: Nitin Garg Date: Thu, 20 Nov 2014 21:14:12 +0800 Subject: mx6: clock: Add thermal clock enable function Add api to check and enable pll3 as required for thermal sensor driver. Signed-off-by: Ye.Li Signed-off-by: Nitin Garg --- arch/arm/cpu/armv7/mx6/clock.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 6c9c78c11a..80b11aaf50 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -673,6 +673,36 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +static void enable_pll3(void) +{ + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + + /* make sure pll3 is enabled */ + if ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { + /* enable pll's power */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, + &anatop->usb1_pll_480_ctrl_set); + writel(0x80, &anatop->ana_misc2_clr); + /* wait for pll lock */ + while ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) + ; + /* disable bypass */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, + &anatop->usb1_pll_480_ctrl_clr); + /* enable pll output */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, + &anatop->usb1_pll_480_ctrl_set); + } +} + +void enable_thermal_clk(void) +{ + enable_pll3(); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { -- cgit v1.2.1 From 7a264168473b8a9ad94352d55a0392ae251676a8 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Thu, 20 Nov 2014 21:14:14 +0800 Subject: mx6: thermal: Check cpu temperature via thermal sensor Add imx6 thermal device to mx6 soc file. Read the cpu temperature using this device to access onchip thermal sensor. Signed-off-by: Ye.Li Signed-off-by: Nitin Garg --- arch/arm/cpu/armv7/mx6/soc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5fd2a63a1d..5f5f497201 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include enum ldo_reg { LDO_ARM, @@ -37,6 +39,19 @@ struct scu_regs { u32 fpga_rev; }; +#if defined(CONFIG_IMX6_THERMAL) +static const struct imx_thermal_plat imx6_thermal_plat = { + .regs = (void *)ANATOP_BASE_ADDR, + .fuse_bank = 1, + .fuse_word = 6, +}; + +U_BOOT_DEVICE(imx6_thermal) = { + .name = "imx_thermal", + .platdata = &imx6_thermal_plat, +}; +#endif + u32 get_nr_cpus(void) { struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; -- cgit v1.2.1 From 8d29cef5887887157f54f98493440ce5c824d5cb Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Fri, 21 Nov 2014 12:47:22 +0200 Subject: arm: mx6: introduce disable_sata_clock Implement disable_sata_clock for mx6 SoCs. Signed-off-by: Nikita Kiryanov Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/clock.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 80b11aaf50..ab7ac3d703 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -596,6 +596,14 @@ int enable_sata_clock(void) ungate_sata_clock(); return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA); } + +void disable_sata_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); +} #endif int enable_pcie_clock(void) -- cgit v1.2.1 From 10ee8ecafbb4405ac77f6df081325630617aa7cd Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Fri, 21 Nov 2014 12:47:23 +0200 Subject: sata: implement reset_sata for dwc_ahsata Add reset_sata() to the sata driver interface and implement it for dwc_ahsata. This function cleans up after sata_init(), and therefore accepts a device number like sata_init() does. A dummy implementation is provided for the rest of the drivers. Signed-off-by: Nikita Kiryanov Cc: Simon Glass Cc: Stefano Babic --- arch/arm/cpu/armv7/omap-common/sata.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index 3b4dd3f5d7..a24baa1337 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -74,6 +74,11 @@ int init_sata(int dev) return ret; } +int reset_sata(int dev) +{ + return 0; +} + /* On OMAP platforms SATA provides the SCSI subsystem */ void scsi_init(void) { -- cgit v1.2.1