From f9162b15c12c009e882574c58457cd31d163dcae Mon Sep 17 00:00:00 2001 From: Akshay Bhat Date: Fri, 29 Jan 2016 15:16:40 -0500 Subject: arm: imx: Add support for GE Bx50v3 boards Add support for GE B450v3, B650v3 and B850v3 boards. The boards are based on Advantech BA16 module which has a i.MX6D processor. The boards support: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat Reviewed-by: Peng Fan --- arch/arm/cpu/armv7/mx6/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index c72a150875..dc0894a0bb 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -60,6 +60,18 @@ config TARGET_CM_FX6 config TARGET_EMBESTMX6BOARDS bool "embestmx6boards" +config TARGET_GE_B450V3 + bool "General Electric B450v3" + select MX6Q + +config TARGET_GE_B650V3 + bool "General Electric B650v3" + select MX6Q + +config TARGET_GE_B850V3 + bool "General Electric B850v3" + select MX6Q + config TARGET_GW_VENTANA bool "gw_ventana" select SUPPORT_SPL @@ -158,6 +170,7 @@ endchoice config SYS_SOC default "mx6" +source "board/ge/bx50v3/Kconfig" source "board/aristainetos/Kconfig" source "board/bachmann/ot1200/Kconfig" source "board/barco/platinum/Kconfig" -- cgit v1.2.1 From e25a0656bac63c5fcd20ef4313dc09c409fc512d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sun, 28 Feb 2016 12:33:17 -0300 Subject: mx7: Distinguish between dual and solo versions Read the number of cores in the fuses to distinguish between the dual and solo versions. Tested on a mx7d sabresd and on a mx7solo warp7. Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- arch/arm/cpu/armv7/mx7/soc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index ba6cfb9dce..073bbc6d01 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -165,6 +165,21 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) return val; } +static bool is_mx7d(void) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + int val; + + val = readl(&fuse->tester4); + if (val & 1) + return false; + else + return true; +} + u32 get_cpu_rev(void) { struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *) @@ -172,6 +187,9 @@ u32 get_cpu_rev(void) u32 reg = readl(&ccm_anatop->digprog); u32 type = (reg >> 16) & 0xff; + if (!is_mx7d()) + type = MXC_CPU_MX7S; + reg &= 0xff; return (type << 12) | reg; } -- cgit v1.2.1 From b777789ebd193587a8e4700dce656523df821370 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 9 Mar 2016 16:13:48 +0800 Subject: imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li Signed-off-by: Peng Fan Acked-by: Stefano Babic --- arch/arm/cpu/armv7/mx6/soc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 91a3debe91..bdd41b07f4 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); + else + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); writel(reg, &mxc_ccm->ccdr); } -- cgit v1.2.1 From e4dc3fc0681bd205b1db6336b0ea3849b5c683e9 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 9 Mar 2016 16:44:36 +0800 Subject: imx: mx6ul: skip setting ahb rate To i.MX6UL, default ARM rate and AHB rate is 396M and 198M, no need to set them. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/soc.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index bdd41b07f4..f29901f8cc 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -328,13 +328,18 @@ int arch_cpu_init(void) */ init_bandgap(); - /* - * When low freq boot is enabled, ROM will not set AHB - * freq, so we need to ensure AHB freq is 132MHz in such - * scenario. - */ - if (mxc_get_clock(MXC_ARM_CLK) == 396000000) - set_ahb_rate(132000000); + if (!IS_ENABLED(CONFIG_MX6UL)) { + /* + * When low freq boot is enabled, ROM will not set AHB + * freq, so we need to ensure AHB freq is 132MHz in such + * scenario. + * + * To i.MX6UL, when power up, default ARM core and + * AHB rate is 396M and 132M. + */ + if (mxc_get_clock(MXC_ARM_CLK) == 396000000) + set_ahb_rate(132000000); + } /* Set perclk to source from OSC 24MHz */ #if defined(CONFIG_MX6SL) -- cgit v1.2.1 From 7082d879164fe7af549ca911a7b675ce698186e1 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 9 Mar 2016 16:44:37 +0800 Subject: imx: mx6ul configure the PMIC_STBY_REQ pin as open drain Configure the PMIC_STBY_REQ pin as open drain 100K according to the design team's requirement for the PMIC_STBY_REQ pin for i.MX 6UltraLite TO1.0. Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/soc.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index f29901f8cc..d4b22ad7f3 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -341,7 +341,17 @@ int arch_cpu_init(void) set_ahb_rate(132000000); } - /* Set perclk to source from OSC 24MHz */ + if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) { + /* + * According to the design team's requirement on i.MX6UL, + * the PMIC_STBY_REQ PAD should be configured as open + * drain 100K (0x0000b8a0). + * Only exists on TO1.0 + */ + writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + } + + /* Set perclk to source from OSC 24MHz */ #if defined(CONFIG_MX6SL) set_preclk_from_osc(); #endif -- cgit v1.2.1 From d78e7f2794f7ae380c0c25027b7872d4f4cca322 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Wed, 9 Mar 2016 16:44:38 +0800 Subject: imx: print ARM clock for clocks command Default print ARM clock for clocks command. Test on i.MX6UL 14x14 evk board: " => clocks PLL_SYS 792 MHz PLL_BUS 528 MHz PLL_OTG 480 MHz PLL_NET 50 MHz ARM 396000 kHz " Signed-off-by: Peng Fan Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/clock.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 88380a6cd9..3b53842e40 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -1183,6 +1183,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("PLL_NET %8d MHz\n", freq / 1000000); printf("\n"); + printf("ARM %8d kHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); #ifdef CONFIG_MXC_SPI -- cgit v1.2.1 From b10d93ee9e56ff1848aaf739d19dd9bd43af4ce9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 2 Mar 2016 14:49:51 +0100 Subject: arm: imx6: Switch DDR3 calibration to wait_for_bit() Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit() to generic implementation of wait_for_bit(). Signed-off-by: Marek Vasut Cc: Stefano Babic Reviewed-by: Stefano Babic --- arch/arm/cpu/armv7/mx6/ddr.c | 44 ++++++++++++-------------------------------- 1 file changed, 12 insertions(+), 32 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index e457febf67..1e7ae28933 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -12,40 +12,20 @@ #include #include #include +#include #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) -static int wait_for_bit(void *reg, const uint32_t mask, bool set) -{ - unsigned int timeout = 1000; - u32 val; - - while (--timeout) { - val = readl(reg); - if (!set) - val = ~val; - - if ((val & mask) == mask) - return 0; - - udelay(1); - } - - printf("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", - __func__, reg, mask, set); - hang(); /* DRAM couldn't be calibrated, game over :-( */ -} - static void reset_read_data_fifos(void) { struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR; /* Reset data FIFOs twice. */ setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); - wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0); + wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); setbits_le32(&mmdc0->mpdgctrl0, 1 << 31); - wait_for_bit(&mmdc0->mpdgctrl0, 1 << 31, 0); + wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 31, 0, 100, 0); } static void precharge_all(const bool cs0_enable, const bool cs1_enable) @@ -60,12 +40,12 @@ static void precharge_all(const bool cs0_enable, const bool cs1_enable) */ if (cs0_enable) { /* CS0 */ writel(0x04008050, &mmdc0->mdscr); - wait_for_bit(&mmdc0->mdscr, 1 << 14, 1); + wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0); } if (cs1_enable) { /* CS1 */ writel(0x04008058, &mmdc0->mdscr); - wait_for_bit(&mmdc0->mdscr, 1 << 14, 1); + wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0); } } @@ -164,7 +144,7 @@ int mmdc_do_write_level_calibration(void) * 7. Upon completion of this process the MMDC de-asserts * the MPWLGCR[HW_WL_EN] */ - wait_for_bit(&mmdc0->mpwlgcr, 1 << 0, 0); + wait_for_bit("MMDC", &mmdc0->mpwlgcr, 1 << 0, 0, 100, 0); /* * 8. check for any errors: check both PHYs for x64 configuration, @@ -289,7 +269,7 @@ int mmdc_do_dqs_calibration(void) writel(0x00008028, &mmdc0->mdscr); /* poll to make sure the con_ack bit was asserted */ - wait_for_bit(&mmdc0->mdscr, 1 << 14, 1); + wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 1, 100, 0); /* * Check MDMISC register CALIB_PER_CS to see which CS calibration @@ -327,7 +307,7 @@ int mmdc_do_dqs_calibration(void) * this bit until it clears to indicate completion of the write access. */ setbits_le32(&mmdc0->mpswdar0, 1); - wait_for_bit(&mmdc0->mpswdar0, 1 << 0, 0); + wait_for_bit("MMDC", &mmdc0->mpswdar0, 1 << 0, 0, 100, 0); /* Set the RD_DL_ABS# bits to their default values * (will be calibrated later in the read delay-line calibration). @@ -372,7 +352,7 @@ int mmdc_do_dqs_calibration(void) setbits_le32(&mmdc0->mpdgctrl0, 5 << 28); /* Poll for completion. MPDGCTRL0[HW_DG_EN] should be 0 */ - wait_for_bit(&mmdc0->mpdgctrl0, 1 << 28, 0); + wait_for_bit("MMDC", &mmdc0->mpdgctrl0, 1 << 28, 0, 100, 0); /* * Check to see if any errors were encountered during calibration @@ -431,7 +411,7 @@ int mmdc_do_dqs_calibration(void) * setting MPRDDLHWCTL[HW_RD_DL_EN] = 0. Also, ensure that * no error bits were set. */ - wait_for_bit(&mmdc0->mprddlhwctl, 1 << 4, 0); + wait_for_bit("MMDC", &mmdc0->mprddlhwctl, 1 << 4, 0, 100, 0); /* check both PHYs for x64 configuration, if x32, check only PHY0 */ if (readl(&mmdc0->mprddlhwctl) & 0x0000000f) @@ -484,7 +464,7 @@ int mmdc_do_dqs_calibration(void) * by setting MPWRDLHWCTL[HW_WR_DL_EN] = 0. * Also, ensure that no error bits were set. */ - wait_for_bit(&mmdc0->mpwrdlhwctl, 1 << 4, 0); + wait_for_bit("MMDC", &mmdc0->mpwrdlhwctl, 1 << 4, 0, 100, 0); /* Check both PHYs for x64 configuration, if x32, check only PHY0 */ if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f) @@ -532,7 +512,7 @@ int mmdc_do_dqs_calibration(void) writel(0x0, &mmdc0->mdscr); /* CS0 */ /* Poll to make sure the con_ack bit is clear */ - wait_for_bit(&mmdc0->mdscr, 1 << 14, 0); + wait_for_bit("MMDC", &mmdc0->mdscr, 1 << 14, 0, 100, 0); /* * Print out the registers that were updated as a result -- cgit v1.2.1 From f7440928e609734f6d24d6769927539762270e1e Mon Sep 17 00:00:00 2001 From: Leonid Iziumtsev Date: Sun, 20 Mar 2016 14:10:55 +0100 Subject: mx27: 16-bit wide watchdog registers Make the watchdog registers 16-bit wide, as they are according to TRM. Signed-off-by: Leonid Iziumtsev Reviewed-by: Fabio Estevam --- arch/arm/cpu/arm926ejs/mx27/reset.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/arm926ejs/mx27/reset.c b/arch/arm/cpu/arm926ejs/mx27/reset.c index f7b4a1c83e..e764986737 100644 --- a/arch/arm/cpu/arm926ejs/mx27/reset.c +++ b/arch/arm/cpu/arm926ejs/mx27/reset.c @@ -27,14 +27,14 @@ void reset_cpu(ulong ignored) { struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; /* Disable watchdog and set Time-Out field to 0 */ - writel(0x00000000, ®s->wcr); + writew(0x0000, ®s->wcr); /* Write Service Sequence */ - writel(0x00005555, ®s->wsr); - writel(0x0000AAAA, ®s->wsr); + writew(0x5555, ®s->wsr); + writew(0xAAAA, ®s->wsr); /* Enable watchdog */ - writel(WCR_WDE, ®s->wcr); + writew(WCR_WDE, ®s->wcr); while (1); /*NOTREACHED*/ -- cgit v1.2.1 From 47173483a322078cb2dbb7f49a614c98b67e3339 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 29 Feb 2016 09:33:22 -0300 Subject: warp7: Add initial support Add the basic support for Warp7 board. For more information about this reference design, please visit: https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- arch/arm/cpu/armv7/mx7/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index 97d62389fd..8e1ddcdaf1 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -18,11 +18,18 @@ config TARGET_MX7DSABRESD select DM select DM_THERMAL +config TARGET_WARP7 + bool "warp7" + select MX7D + select DM + select DM_THERMAL + endchoice config SYS_SOC default "mx7" source "board/freescale/mx7dsabresd/Kconfig" +source "board/warp7/Kconfig" endif -- cgit v1.2.1 From a7f480d92df8a7e525a4b619b09f40f73222647f Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 10 Feb 2016 11:41:26 +0100 Subject: arm: mx6: Add CCV xPress board support This patch add support for the CCV xPress board which is equipped with the i.MX6UL. And provides the following interfaces: - 128MiB DDR - UART - I2C - eMMC (with booting) - Ethernet - USB This patch adds two build targets. One with and one without SPL. The non-SPL version is used for loading U-Boot via USB (imx_usb_loader). Signed-off-by: Stefan Roese Cc: Fabio Estevam Cc: Stefano Babic --- arch/arm/cpu/armv7/mx6/Kconfig | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index dc0894a0bb..31b1175c1c 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -165,6 +165,13 @@ config TARGET_WANDBOARD config TARGET_WARP bool "WaRP" +config TARGET_XPRESS + bool "CCV xPress" + select MX6UL + select DM + select DM_THERMAL + select SUPPORT_SPL + endchoice config SYS_SOC @@ -176,6 +183,7 @@ source "board/bachmann/ot1200/Kconfig" source "board/barco/platinum/Kconfig" source "board/barco/titanium/Kconfig" source "board/boundary/nitrogen6x/Kconfig" +source "board/ccv/xpress/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" source "board/embest/mx6boards/Kconfig" -- cgit v1.2.1 From 9131c18cfa23c1eae8d77b6fcfa2f5e16698d949 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 3 Mar 2016 15:56:01 +0800 Subject: imx: mx6sx: move MX6SX to Kconfig entry If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to "select MX6SX" to boards using i.MX6 SoloX. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Reviewed-by: Fabio Estevam --- arch/arm/cpu/armv7/mx6/Kconfig | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 31b1175c1c..1bcd399093 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -104,12 +104,14 @@ config TARGET_MX6SLEVK config TARGET_MX6SXSABRESD bool "mx6sxsabresd" + select MX6SX select SUPPORT_SPL select DM select DM_THERMAL config TARGET_MX6SXSABREAUTO bool "mx6sxsabreauto" + select MX6SX select DM select DM_THERMAL -- cgit v1.2.1 From 7abeec2234a81ba7880be6f0a6952dec3411bbe7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 3 Mar 2016 15:56:02 +0800 Subject: imx: mx7d: move MX7D to Kconfig entry If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to "select MX7D" to boards using i.MX7 Dual. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam Reviewed-by: Fabio Estevam --- arch/arm/cpu/armv7/mx7/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index 8e1ddcdaf1..ecfa4a2c35 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -15,6 +15,7 @@ choice config TARGET_MX7DSABRESD bool "mx7dsabresd" + select MX7D select DM select DM_THERMAL -- cgit v1.2.1