From 23e2da27d3de94117c099a511c7bfec759ede623 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Tue, 26 Jan 2016 22:01:58 +0800 Subject: imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculation The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li Reviewed-by: Stefano Babic --- arch/arm/cpu/armv7/mx6/clock.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm/cpu/armv7') diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 007204dd4d..88380a6cd9 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -638,10 +638,6 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) } temp = freq * max_pred * max_postd; - if (temp > max) { - puts("Please decrease freq, too large!\n"); - return; - } if (temp < min) { /* * Register: PLL_VIDEO -- cgit v1.2.1