From b45c48a7c30734272371fede01e96f499a314664 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 9 Mar 2015 17:12:00 -0500 Subject: ARM: Introduce erratum workaround for 454179 454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon Tested-by: Matt Porter Reviewed-by: Tom Rini --- arch/arm/cpu/armv7/start.S | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm/cpu/armv7/start.S') diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 89637e2639..8483687879 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -187,6 +187,19 @@ ENTRY(cpu_init_cp15) isb @ Recommended ISB after l2actlr update pop {r1-r5} @ Restore the cpu info - fall through skip_errata_798870: +#endif + +#ifdef CONFIG_ARM_ERRATA_454179 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_454179 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_454179: #endif mov pc, r5 @ back to my caller -- cgit v1.2.1