From eed7c0f727cf8255b193dfefd21d66dfd6dbae94 Mon Sep 17 00:00:00 2001 From: SRICHARAN R Date: Tue, 12 Feb 2013 01:33:41 +0000 Subject: ARM: OMAP5: Add silicon id support for ES2.0 revision. Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs. Signed-off-by: R Sricharan Cc: Tom Rini Cc: Nishanth Menon --- arch/arm/cpu/armv7/omap5/hwinit.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) (limited to 'arch/arm/cpu/armv7/omap5/hwinit.c') diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e447e0..8e66a968af 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -204,17 +204,22 @@ void init_omap_revision(void) */ unsigned int rev = cortex_rev(); - switch (rev) { - case MIDR_CORTEX_A15_R0P0: - switch (readl(CONTROL_ID_CODE)) { - case OMAP5430_CONTROL_ID_CODE_ES1_0: - *omap_si_rev = OMAP5430_ES1_0; - break; - case OMAP5432_CONTROL_ID_CODE_ES1_0: - default: - *omap_si_rev = OMAP5432_ES1_0; - break; - } + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5432_ES1_0; + if (rev == MIDR_CORTEX_A15_R2P2) + *omap_si_rev = OMAP5432_ES2_0; + break; + case OMAP5430_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5432_ES2_0; break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; -- cgit v1.2.1