From 8b457fa828971ac036b15e98e65d99b6354c5496 Mon Sep 17 00:00:00 2001 From: Aneesh V Date: Thu, 16 Jun 2011 23:30:52 +0000 Subject: armv7: adapt omap4 to the new cache maintenance framework adapt omap4 to the new layered cache maintenance framework Signed-off-by: Aneesh V --- arch/arm/cpu/armv7/omap4/board.c | 12 ++++++++++++ arch/arm/cpu/armv7/omap4/lowlevel_init.S | 9 +++++++++ 2 files changed, 21 insertions(+) (limited to 'arch/arm/cpu/armv7/omap4') diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c index fcd29a73e0..de4cc2ab84 100644 --- a/arch/arm/cpu/armv7/omap4/board.c +++ b/arch/arm/cpu/armv7/omap4/board.c @@ -127,3 +127,15 @@ int arch_cpu_init(void) set_muxconf_regs(); return 0; } + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + set_pl310_ctrl_reg(1); +} + +void v7_outer_cache_disable(void) +{ + set_pl310_ctrl_reg(0); +} +#endif diff --git a/arch/arm/cpu/armv7/omap4/lowlevel_init.S b/arch/arm/cpu/armv7/omap4/lowlevel_init.S index 026dfa46ef..6abfbbaa13 100644 --- a/arch/arm/cpu/armv7/omap4/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap4/lowlevel_init.S @@ -45,3 +45,12 @@ lowlevel_init: */ bl s_init pop {ip, pc} + +.globl set_pl310_ctrl_reg +set_pl310_ctrl_reg: + PUSH {r4-r11, lr} @ save registers - ROM code may pollute + @ our registers + LDR r12, =0x102 @ Set PL310 control register - value in R0 + .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 + @ call ROM Code API to set control register + POP {r4-r11, pc} -- cgit v1.2.1