From 1c4044ae4a6030174e8e4eb0aa5b1017c732aadf Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Mon, 11 Aug 2014 11:59:42 +0300 Subject: ARM: keystone: clock: use correct BWADJ field mask for PASSPLLCTL0 The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but by mistake, here is used shift instead of mask, so correct it. Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv7/keystone') diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index 30d76a6603..47fc89398d 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -174,7 +174,7 @@ void init_pll(const struct pll_init_data *data) * bypass disabled */ bwadj = pllm >> 1; - tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) | + tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) | (pllm << PLL_MULT_SHIFT) | (plld & PLL_DIV_MASK) | (pllod << PLL_CLKOD_SHIFT); -- cgit v1.2.1 From e6c9428a2fe584c69374fd2d49ed61fdb1568114 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Thu, 28 Aug 2014 16:07:45 +0300 Subject: keystone2: use readl/writel functions instead of redefinition There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk Acked-by: Vitaly Andrianov --- arch/arm/cpu/armv7/keystone/psc.c | 44 +++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 25 deletions(-) (limited to 'arch/arm/cpu/armv7/keystone') diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c index fa5422f2e8..237e776e87 100644 --- a/arch/arm/cpu/armv7/keystone/psc.c +++ b/arch/arm/cpu/armv7/keystone/psc.c @@ -13,9 +13,6 @@ #include #include -#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr)) -#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr)) - int psc_delay(void) { udelay(10); @@ -51,7 +48,7 @@ int psc_wait(u32 domain_num) retry = 0; do { - ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT); + ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT); ptstat = ptstat & (1 << domain_num); } while ((ptstat != 0) && ((retry += psc_delay()) < PSC_PTSTAT_TIMEOUT_LIMIT)); @@ -67,8 +64,7 @@ u32 psc_get_domain_num(u32 mod_num) u32 domain_num; /* Get the power domain associated with the module number */ - domain_num = DEVICE_REG32_R(KS2_PSC_BASE + - PSC_REG_MDCFG(mod_num)); + domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); domain_num = PSC_REG_MDCFG_GET_PD(domain_num); return domain_num; @@ -102,7 +98,7 @@ int psc_set_state(u32 mod_num, u32 state) * Get the power domain associated with the module number, and reset * isolation functionality */ - v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); + v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); domain_num = PSC_REG_MDCFG_GET_PD(v); reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v); @@ -119,24 +115,22 @@ int psc_set_state(u32 mod_num, u32 state) * change is made if the new state is power down. */ if (state == PSC_REG_VAL_MDCTL_NEXT_ON) { - pdctl = DEVICE_REG32_R(KS2_PSC_BASE + - PSC_REG_PDCTL(domain_num)); + pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_ON); - DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), - pdctl); + __raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); } /* Set the next state for the module to enabled/disabled */ - mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state); mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso); - DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); + __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); /* Trigger the enable */ - ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD); + ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); ptcmd |= (u32)(1<