From 2085ae74dee47ed3da63416aac0305936b43eeea Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Fri, 24 Jul 2015 09:22:10 +0200 Subject: arm1136/arm1176: Merge cache handling code As both cores are similar merge the cache handling code for both CPUs to arm11 directory. Signed-off-by: Alexander Stein Acked-by: Stephen Warren Tested-by: Stephen Warren [trini: Add hunk to arch/arm/cpu/arm1136/Makefile] Signed-off-by: Tom Rini --- arch/arm/cpu/arm1136/Makefile | 2 +- arch/arm/cpu/arm1136/cpu.c | 150 ------------------------------------------ 2 files changed, 1 insertion(+), 151 deletions(-) delete mode 100644 arch/arm/cpu/arm1136/cpu.c (limited to 'arch/arm/cpu/arm1136') diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile index 56a9390b01..dbdafeb47f 100644 --- a/arch/arm/cpu/arm1136/Makefile +++ b/arch/arm/cpu/arm1136/Makefile @@ -6,7 +6,7 @@ # extra-y = start.o -obj-y = cpu.o +obj-y += ../arm11/ obj-$(CONFIG_MX31) += mx31/ obj-$(CONFIG_MX35) += mx35/ diff --git a/arch/arm/cpu/arm1136/cpu.c b/arch/arm/cpu/arm1136/cpu.c deleted file mode 100644 index 5d4b3c2a02..0000000000 --- a/arch/arm/cpu/arm1136/cpu.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * (C) Copyright 2004 Texas Insturments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code - */ - -#include -#include -#include - -static void cache_flush(void); - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * we turn off caches etc ... - */ - - disable_interrupts (); - - /* turn off I/D-cache */ - icache_disable(); - dcache_disable(); - /* flush I/D-cache */ - cache_flush(); - - return 0; -} - -static void cache_flush(void) -{ - unsigned long i = 0; - /* clean entire data cache */ - asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i)); - /* invalidate both caches and flush btb */ - asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i)); - /* mem barrier to sync things */ - asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); -} - -#ifndef CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - -void invalidate_dcache_all(void) -{ - asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); -} - -void flush_dcache_all(void) -{ - asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0)); - asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -} - -static int check_cache_range(unsigned long start, unsigned long stop) -{ - int ok = 1; - - if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (!ok) - debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", - start, stop); - - return ok; -} - -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ - if (!check_cache_range(start, stop)) - return; - - while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); - start += CONFIG_SYS_CACHELINE_SIZE; - } -} - -void flush_dcache_range(unsigned long start, unsigned long stop) -{ - if (!check_cache_range(start, stop)) - return; - - while (start < stop) { - asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start)); - start += CONFIG_SYS_CACHELINE_SIZE; - } - - asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -} - -void flush_cache(unsigned long start, unsigned long size) -{ - flush_dcache_range(start, start + size); -} - -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ -void invalidate_dcache_all(void) -{ -} - -void flush_dcache_all(void) -{ -} - -void invalidate_dcache_range(unsigned long start, unsigned long stop) -{ -} - -void flush_dcache_range(unsigned long start, unsigned long stop) -{ -} - -void flush_cache(unsigned long start, unsigned long size) -{ -} -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ - -#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) -void enable_caches(void) -{ -#ifndef CONFIG_SYS_ICACHE_OFF - icache_enable(); -#endif -#ifndef CONFIG_SYS_DCACHE_OFF - dcache_enable(); -#endif -} -#endif -- cgit v1.2.1