From bb99ad6d8257bf828f150d40f507b30d80a4a7ae Mon Sep 17 00:00:00 2001 From: Ben Warren Date: Thu, 7 Sep 2006 16:50:54 -0400 Subject: Add support for multiple I2C buses Hello, Attached is a patch providing support for multiple I2C buses at the command level. The second part of the patch includes an implementation for the MPC834x CPU and MPC8349EMDS board. /*** Note: This patch replaces ticket DNX#2006083042000018 ***/ Signed-off-by: Ben Warren Overview: 1. Include new 'i2c' command (based on USB implementation) using CONFIG_I2C_CMD_TREE. 2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that the commands to change bus number and speed are only available under the new 'i2c' command mentioned in the first bullet. 3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form of an array of bus-device pairs. Otherwise, it is an array of uchar. CHANGELOG: Added new 'i2c' master command for all I2C interaction. This is conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for setting I2C bus speed as well as changing the active bus if the board has more than one (conditionally compiled with CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses. Updated README. regards, Ben --- README | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'README') diff --git a/README b/README index b78ea6124d..6b94f8482c 100644 --- a/README +++ b/README @@ -1207,7 +1207,12 @@ The following options need to be configured: clock chips. See common/cmd_i2c.c for a description of the command line interface. - CONFIG_HARD_I2C selects the CPM hardware driver for I2C. + CONFIG_I2C_CMD_TREE is a recommended option that places + all I2C commands under a single 'i2c' root command. The + older 'imm', 'imd', 'iprobe' etc. commands are considered + deprecated and may disappear in the future. + + CONFIG_HARD_I2C selects a hardware I2C controller. CONFIG_SOFT_I2C configures u-boot to use a software (aka bit-banging) driver instead of CPM or similar hardware @@ -1312,6 +1317,31 @@ The following options need to be configured: in u-boot bd_info structure based on u-boot environment variable "i2cfast". (see also i2cfast) + CONFIG_I2C_MULTI_BUS + + This option allows the use of multiple I2C buses, each of which + must have a controller. At any point in time, only one bus is + active. To switch to a different bus, use the 'i2c dev' command. + Note that bus numbering is zero-based. + + CFG_I2C_NOPROBES + + This option specifies a list of I2C devices that will be skipped + when the 'i2c probe' command is issued (or 'iprobe' using the legacy + command). If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device + pairs. Otherwise, specify a 1D array of device addresses + + e.g. + #undef CONFIG_I2C_MULTI_BUS + #define CFG_I2C_NOPROBES {0x50,0x68} + + will skip addresses 0x50 and 0x68 on a board with one I2C bus + + #define CONFIG_I2C_MULTI_BUS + #define CFG_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} + + will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 + - SPI Support: CONFIG_SPI Enables SPI driver (so far only tested with @@ -2209,6 +2239,16 @@ Low Level (hardware related) configuration options: CFG_POCMR2_MASK_ATTRIB: (MPC826x only) Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. +- CONFIG_SPD_EEPROM + Get DDR timing information from an I2C EEPROM. Common with pluggable + memory modules such as SODIMMs + SPD_EEPROM_ADDRESS + I2C address of the SPD EEPROM + +- CFG_SPD_BUS_NUM + If SPD EEPROM is on an I2C bus other than the first one, specify here. + Note that the value must resolve to something your driver can deal with. + - CONFIG_ETHER_ON_FEC[12] Define to enable FEC[12] on a 8xx series processor. -- cgit v1.2.1 From 2ad6b513b31070bd0c003792ed1c3e7f5d740357 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 31 Oct 2006 18:44:42 -0600 Subject: mpc83xx: Add support for the MPC8349E-mITX PREREQUISITE PATCHES: * This patch can only be applied after the following patches have been applied: 1) DNX#2006090742000024 "Add support for multiple I2C buses" 2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x" 3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c" 4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems" 5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems" CHANGELOG: * Add support for the Freescale MPC8349E-mITX reference design platform. The second TSEC (Vitesse 7385 switch) is not supported at this time. Signed-off-by: Timur Tabi --- README | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'README') diff --git a/README b/README index 6b94f8482c..5c907c8f07 100644 --- a/README +++ b/README @@ -2249,6 +2249,14 @@ Low Level (hardware related) configuration options: If SPD EEPROM is on an I2C bus other than the first one, specify here. Note that the value must resolve to something your driver can deal with. +- CFG_83XX_DDR_USES_CS0 + Only for 83xx systems. If specified, then DDR should be configured + using CS0 and CS1 instead of CS2 and CS3. + +- CFG_83XX_DDR_USES_CS0 + Only for 83xx systems. If specified, then DDR should be configured + using CS0 and CS1 instead of CS2 and CS3. + - CONFIG_ETHER_ON_FEC[12] Define to enable FEC[12] on a 8xx series processor. -- cgit v1.2.1 From be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 3 Nov 2006 19:15:00 -0600 Subject: mpc83xx: Update 83xx to use fsl_i2c.c Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files. Added multiple I2C bus support to fsl_i2c.c. Signed-off-by: Timur Tabi --- README | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'README') diff --git a/README b/README index 5c907c8f07..d03862b3ef 100644 --- a/README +++ b/README @@ -1342,6 +1342,17 @@ The following options need to be configured: will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 + CFG_SPD_BUS_NUM + + If defined, then this indicates the I2C bus number for DDR SPD. + If not defined, then U-Boot assumes that SPD is on I2C bus 0. + + CONFIG_FSL_I2C + + Define this option if you want to use Freescale's I2C driver in + drivers/fsl_i2c.c. + + - SPI Support: CONFIG_SPI Enables SPI driver (so far only tested with -- cgit v1.2.1