From b401b73d02bb4f97197830e565f19a65577fecc6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Mar 2014 19:58:39 +0100 Subject: aes: Add 'aes' command to access AES-128-CBC Add simple 'aes' command, which allows using the AES-128-CBC encryption and decryption functions from U-Boot command line. Signed-off-by: Marek Vasut --- README | 1 + 1 file changed, 1 insertion(+) (limited to 'README') diff --git a/README b/README index 216f0c70aa..fd717bf085 100644 --- a/README +++ b/README @@ -910,6 +910,7 @@ The following options need to be configured: The default command configuration includes all commands except those marked below with a "*". + CONFIG_CMD_AES AES 128 CBC encrypt/decrypt CONFIG_CMD_ASKENV * ask for env variable CONFIG_CMD_BDI bdinfo CONFIG_CMD_BEDBUG * Include BedBug Debugger -- cgit v1.2.1 From 7e3d473b5ec5ee2cf6220ce15d9f87c565d98b05 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 7 Mar 2014 18:02:01 +0900 Subject: mips: xburst: remove remainders of dead board Commit 54e458de deleted qi_lb60 board support because of the incompatible license issue. There is no board with XBurst CPU. Signed-off-by: Masahiro Yamada Cc: Daniel Schwierzeck --- README | 1 - 1 file changed, 1 deletion(-) (limited to 'README') diff --git a/README b/README index 52a92e73b8..16fdd37357 100644 --- a/README +++ b/README @@ -164,7 +164,6 @@ Directory Hierarchy: /mips Files generic to MIPS architecture /cpu CPU specific files /mips32 Files specific to MIPS32 CPUs - /xburst Files specific to Ingenic XBurst CPUs /lib Architecture specific library files /nds32 Files generic to NDS32 architecture /cpu CPU specific files -- cgit v1.2.1 From 6eae68e450517219a548412cae314cb914bc7a71 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 7 Mar 2014 18:02:02 +0900 Subject: cosmetic: README: add some entries to Directory Hierarchy Signed-off-by: Masahiro Yamada --- README | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README') diff --git a/README b/README index 16fdd37357..f91e0442ad 100644 --- a/README +++ b/README @@ -132,6 +132,10 @@ Directory Hierarchy: ==================== /arch Architecture specific files + /arc Files generic to ARC architecture + /cpu CPU specific files + /arc700 Files specific to ARC 700 CPUs + /lib Architecture specific library files /arm Files generic to ARM architecture /cpu CPU specific files /arm720t Files specific to ARM 720 CPUs @@ -164,6 +168,7 @@ Directory Hierarchy: /mips Files generic to MIPS architecture /cpu CPU specific files /mips32 Files specific to MIPS32 CPUs + /mips64 Files specific to MIPS64 CPUs /lib Architecture specific library files /nds32 Files generic to NDS32 architecture /cpu CPU specific files -- cgit v1.2.1 From fb4a2409b46c98672557bb07dec8e873bef1e23c Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 18 Mar 2014 23:40:26 +0530 Subject: powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: Ruchika Gupta Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- README | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'README') diff --git a/README b/README index 52a92e73b8..4715cfbc25 100644 --- a/README +++ b/README @@ -427,6 +427,10 @@ The following options need to be configured: In this mode, a single differential clock is used to supply clocks to the sysclock, ddrclock and usbclock. + CONFIG_SYS_CPC_REINIT_F + This CONFIG is defined when the CPC is configured as SRAM at the + time of U-boot entry and is required to be re-initialized. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN -- cgit v1.2.1 From dcf1d774bf5c2612538658eac01931895b7a805f Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Fri, 21 Mar 2014 16:21:44 +0800 Subject: QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- README | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'README') diff --git a/README b/README index 4715cfbc25..cb96322fb7 100644 --- a/README +++ b/README @@ -4502,8 +4502,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros are used to identify the storage device (NOR flash, SPI, etc) and the address within that device. -- CONFIG_SYS_QE_FMAN_FW_ADDR - The address in the storage device where the firmware is located. The +- CONFIG_SYS_FMAN_FW_ADDR + The address in the storage device where the FMAN microcode is located. The + meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro + is also specified. + +- CONFIG_SYS_QE_FW_ADDR + The address in the storage device where the QE microcode is located. The meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro is also specified. -- cgit v1.2.1 From 34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 27 Mar 2014 17:54:47 -0700 Subject: driver/ddr/fsl: Add DDR4 support to Freescale DDR driver Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun --- README | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'README') diff --git a/README b/README index cb96322fb7..bbd7399f53 100644 --- a/README +++ b/README @@ -458,6 +458,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DDRC_GEN3 Freescale DDR3 controller. + CONFIG_SYS_FSL_DDRC_GEN4 + Freescale DDR4 controller. + CONFIG_SYS_FSL_DDRC_ARM_GEN3 Freescale DDR3 controller for ARM-based SoCs. @@ -473,7 +476,15 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR3 Board config to use DDR3. It can be enabled for SoCs with - Freescale DDR3 controllers. + Freescale DDR3 or DDR3L controllers. + + CONFIG_SYS_FSL_DDR3L + Board config to use DDR3L. It can be enabled for SoCs with + DDR3L controllers. + + CONFIG_SYS_FSL_DDR4 + Board config to use DDR4. It can be enabled for SoCs with + DDR4 controllers. CONFIG_SYS_FSL_IFC_BE Defines the IFC controller register space as Big Endian -- cgit v1.2.1 From aade20046b7ab5bd9b2afe84ccb31f0adf0c5e1e Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 17 Apr 2014 15:33:46 +0800 Subject: mpc85xx/t104x: Add deep sleep framework support When T104x soc wakes up from deep sleep, control is passed to the primary core that starts executing uboot. After re-initialized some IP blocks, like DDRC, kernel will take responsibility to continue to restore environment it leaves before. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- README | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'README') diff --git a/README b/README index bbd7399f53..017a13df4d 100644 --- a/README +++ b/README @@ -431,6 +431,10 @@ The following options need to be configured: This CONFIG is defined when the CPC is configured as SRAM at the time of U-boot entry and is required to be re-initialized. + CONFIG_DEEP_SLEEP + Inidcates this SoC supports deep sleep feature. If deep sleep is + supported, core will start to execute uboot when wakes up. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN -- cgit v1.2.1 From 651fcf6019eec1a65d4227082e12bc6ad4576f41 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:12:31 +0530 Subject: powerpc:Add support of SPL non-relocation Current SPL code base has BSS section placed after reset_vector. This means they have to relocate to use the global variables. This put an implicit requirement of having SPL size = Memory/2. To avoid relocation: - Move bss_section within SPL range - Modify relocate_code() Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- README | 3 +++ 1 file changed, 3 insertions(+) (limited to 'README') diff --git a/README b/README index 017a13df4d..52283e22d7 100644 --- a/README +++ b/README @@ -3332,6 +3332,9 @@ FIT uImage format: continuing (the hardware starts execution after just loading the first page rather than the full 4K). + CONFIG_SPL_SKIP_RELOCATE + Avoid SPL relocation + CONFIG_SPL_NAND_BASE Include nand_base.c in the SPL. Requires CONFIG_SPL_NAND_DRIVERS. -- cgit v1.2.1 From 89ad7be8e713f33ec677cf4576e0c9b0ed83f7c6 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 8 Apr 2014 19:13:34 +0530 Subject: Makefile: Add support of CONFIG_SPL_FSL_PBL Objective of this target to have concatenate binary having - SPL binary in PBL command format - U-boot binary Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- README | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'README') diff --git a/README b/README index 52283e22d7..49dcd37a3c 100644 --- a/README +++ b/README @@ -505,6 +505,10 @@ The following options need to be configured: PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details + CONFIG_SPL_FSL_PBL + It adds a target to create boot binary having SPL binary in PBI format + concatenated with u-boot binary. + CONFIG_SYS_FSL_DDR_BE Defines the DDR controller register space as Big Endian -- cgit v1.2.1 From 75504e9592745021006cb8905b5ff5a51d9d1cb3 Mon Sep 17 00:00:00 2001 From: Mateusz Zalega Date: Wed, 30 Apr 2014 13:07:48 +0200 Subject: usb: dfu: fix boards wo USB cable detection Former usb_cable_connected() patch broke compilation of boards which do not support this feature. I've renamed usb_cable_connected() to g_dnl_usb_cable_connected() and added its default implementation to gadget downloader driver code. There's only one driver of this kind and it's unlikely there'll be another, so there's no point in keeping it in /common. Previously this function was declared in usb.h. I've moved it, since it's more appropriate to keep it in g_dnl.h - usb.h seems to be intended for USB host implementation. Existing code, confronted with default -EOPNOTSUPP return value, continues as if the cable was connected. CONFIG_USB_CABLE_CHECK was removed. Change-Id: Ib9198621adee2811b391c64512f14646cefd0369 Signed-off-by: Mateusz Zalega Acked-by: Marek Vasut Acked-by: Lukasz Majewski --- README | 7 ------- 1 file changed, 7 deletions(-) (limited to 'README') diff --git a/README b/README index 12758dc6e7..b973344184 100644 --- a/README +++ b/README @@ -1484,13 +1484,6 @@ The following options need to be configured: for your device - CONFIG_USBD_PRODUCTID 0xFFFF - Some USB device drivers may need to check USB cable attachment. - In this case you can enable following config in BoardName.h: - CONFIG_USB_CABLE_CHECK - This enables function definition: - - usb_cable_connected() in include/usb.h - Implementation of this function is board-specific. - - ULPI Layer Support: The ULPI (UTMI Low Pin (count) Interface) PHYs are supported via the generic ULPI layer. The generic layer accesses the ULPI PHY -- cgit v1.2.1