From 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 13:59:42 -0800 Subject: driver/ddr: Change Freescale ARM DDR driver to support both big and little endian Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun --- README | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'README') diff --git a/README b/README index 6668631bcc..413d682829 100644 --- a/README +++ b/README @@ -486,6 +486,12 @@ The following options need to be configured: PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details + CONFIG_SYS_FSL_DDR_BE + Defines the DDR controller register space as Big Endian + + CONFIG_SYS_FSL_DDR_LE + Defines the DDR controller register space as Little Endian + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO -- cgit v1.2.1