From 122d805fd4bd478bb83536348291d34ae648364b Mon Sep 17 00:00:00 2001 From: Jagannadha Sutradharudu Teki Date: Thu, 23 Apr 2015 19:52:11 +0530 Subject: Revert "spi: add config option to enable the WP pin function on st micron flashes" This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Note: Even un-reverting this patch couldn't works as expected, based on the latest testing from Heiko Schocher. Signed-off-by: Jagannadha Sutradharudu Teki Cc: Heiko Schocher --- README | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'README') diff --git a/README b/README index fc1fd52f53..82224f75e4 100644 --- a/README +++ b/README @@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support memories can be connected with a given cs line. Currently Xilinx Zynq qspi supports these type of connections. - CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - enable the W#/Vpp signal to disable writing to the status - register on ST MICRON flashes like the N25Q128. - The status register write enable/disable bit, combined with - the W#/VPP signal provides hardware data protection for the - device as follows: When the enable/disable bit is set to 1, - and the W#/VPP signal is driven LOW, the status register - nonvolatile bits become read-only and the WRITE STATUS REGISTER - operation will not execute. The only way to exit this - hardware-protected mode is to drive W#/VPP HIGH. - - SystemACE Support: CONFIG_SYSTEMACE -- cgit v1.2.1