From fa476f75bfff55772f0ebde3d5e02dc745e70f40 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:42 +0000 Subject: mips32: detect L1 cache sizes if they're not defined For boards such as the MIPS Malta with an FPGA core card it is desirable to be able to detect the L1 cache sizes at runtime, since they are not dependant upon the board but on the FPGA bitstream in use. This patch performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are not defined by the board configuration. In cases where the sizes are detected this patch also removes the restriction that the I-cache & D-cache line sizes must be the same, as this is not necessarily true. If the cache sizes are defined by a configuration then they will be hardcoded as before, so this patch will not add overhead to such boards. Signed-off-by: Paul Burton --- arch/mips/cpu/mips32/cache.S | 90 ++++++++++++++++++++++++++++++++++------ arch/mips/cpu/mips32/cpu.c | 73 +++++++++++++++++++++++++++++--- arch/mips/include/asm/mipsregs.h | 6 +++ 3 files changed, 150 insertions(+), 19 deletions(-) diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S index 12f656cad0..22bd844eae 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S @@ -20,15 +20,6 @@ #define RA t9 -/* - * 16kB is the maximum size of instruction and data caches on MIPS 4K, - * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. - * - * Note that the above size is the maximum size of primary cache. U-Boot - * doesn't have L2 cache support for now. - */ -#define MIPS_MAX_CACHE_SIZE 0x10000 - #define INDEX_BASE CKSEG0 .macro cache_op op addr @@ -126,12 +117,85 @@ LEAF(mips_init_dcache) */ NESTED(mips_cache_reset, 0, ra) move RA, ra - li t2, CONFIG_SYS_ICACHE_SIZE - li t3, CONFIG_SYS_DCACHE_SIZE + +#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \ + !defined(CONFIG_SYS_CACHELINE_SIZE) + /* read Config1 for use below */ + mfc0 t5, CP0_CONFIG, 1 +#endif + +#ifdef CONFIG_SYS_CACHELINE_SIZE + li t7, CONFIG_SYS_CACHELINE_SIZE li t8, CONFIG_SYS_CACHELINE_SIZE +#else + /* Detect I-cache line size. */ + srl t8, t5, MIPS_CONF1_IL_SHIFT + andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT) + beqz t8, 1f + li t6, 2 + sllv t8, t6, t8 - li v0, MIPS_MAX_CACHE_SIZE +1: /* Detect D-cache line size. */ + srl t7, t5, MIPS_CONF1_DL_SHIFT + andi t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT) + beqz t7, 1f + li t6, 2 + sllv t7, t6, t7 +1: +#endif +#ifdef CONFIG_SYS_ICACHE_SIZE + li t2, CONFIG_SYS_ICACHE_SIZE +#else + /* Detect I-cache size. */ + srl t6, t5, MIPS_CONF1_IS_SHIFT + andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT) + li t4, 32 + xori t2, t6, 0x7 + beqz t2, 1f + addi t6, t6, 1 + sllv t4, t4, t6 +1: /* At this point t4 == I-cache sets. */ + mul t2, t4, t8 + srl t6, t5, MIPS_CONF1_IA_SHIFT + andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT) + addi t6, t6, 1 + /* At this point t6 == I-cache ways. */ + mul t2, t2, t6 +#endif + +#ifdef CONFIG_SYS_DCACHE_SIZE + li t3, CONFIG_SYS_DCACHE_SIZE +#else + /* Detect D-cache size. */ + srl t6, t5, MIPS_CONF1_DS_SHIFT + andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT) + li t4, 32 + xori t3, t6, 0x7 + beqz t3, 1f + addi t6, t6, 1 + sllv t4, t4, t6 +1: /* At this point t4 == I-cache sets. */ + mul t3, t4, t7 + srl t6, t5, MIPS_CONF1_DA_SHIFT + andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT) + addi t6, t6, 1 + /* At this point t6 == I-cache ways. */ + mul t3, t3, t6 +#endif + + /* Determine the largest L1 cache size */ +#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE) +#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE + li v0, CONFIG_SYS_ICACHE_SIZE +#else + li v0, CONFIG_SYS_DCACHE_SIZE +#endif +#else + move v0, t2 + sltu t1, t2, t3 + movn v0, t3, t1 +#endif /* * Now clear that much memory starting from zero. */ @@ -163,7 +227,7 @@ NESTED(mips_cache_reset, 0, ra) * then initialize D-cache. */ move a1, t3 - move a2, t8 + move a2, t7 PTR_LA v1, mips_init_dcache jalr v1 diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c index 28d5c45683..278865b6ff 100644 --- a/arch/mips/cpu/mips32/cpu.c +++ b/arch/mips/cpu/mips32/cpu.c @@ -34,28 +34,89 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#ifdef CONFIG_SYS_CACHELINE_SIZE + +static inline unsigned long icache_line_size(void) +{ + return CONFIG_SYS_CACHELINE_SIZE; +} + +static inline unsigned long dcache_line_size(void) +{ + return CONFIG_SYS_CACHELINE_SIZE; +} + +#else /* !CONFIG_SYS_CACHELINE_SIZE */ + +static inline unsigned long icache_line_size(void) +{ + unsigned long conf1, il; + conf1 = read_c0_config1(); + il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHIFT; + if (!il) + return 0; + return 2 << il; +} + +static inline unsigned long dcache_line_size(void) +{ + unsigned long conf1, dl; + conf1 = read_c0_config1(); + dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHIFT; + if (!dl) + return 0; + return 2 << dl; +} + +#endif /* !CONFIG_SYS_CACHELINE_SIZE */ + void flush_cache(ulong start_addr, ulong size) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; - unsigned long addr = start_addr & ~(lsize - 1); - unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + unsigned long ilsize = icache_line_size(); + unsigned long dlsize = dcache_line_size(); + unsigned long addr, aend; /* aend will be miscalculated when size is zero, so we return here */ if (size == 0) return; + addr = start_addr & ~(dlsize - 1); + aend = (start_addr + size - 1) & ~(dlsize - 1); + + if (ilsize == dlsize) { + /* flush I-cache & D-cache simultaneously */ + while (1) { + cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_INVALIDATE_I, addr); + if (addr == aend) + break; + addr += dlsize; + } + return; + } + + /* flush D-cache */ while (1) { cache_op(HIT_WRITEBACK_INV_D, addr); + if (addr == aend) + break; + addr += dlsize; + } + + /* flush I-cache */ + addr = start_addr & ~(ilsize - 1); + aend = (start_addr + size - 1) & ~(ilsize - 1); + while (1) { cache_op(HIT_INVALIDATE_I, addr); if (addr == aend) break; - addr += lsize; + addr += ilsize; } } void flush_dcache_range(ulong start_addr, ulong stop) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long lsize = dcache_line_size(); unsigned long addr = start_addr & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1); @@ -69,7 +130,7 @@ void flush_dcache_range(ulong start_addr, ulong stop) void invalidate_dcache_range(ulong start_addr, ulong stop) { - unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; + unsigned long lsize = dcache_line_size(); unsigned long addr = start_addr & ~(lsize - 1); unsigned long aend = (stop - 1) & ~(lsize - 1); diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index be7e5c65ec..3571e4fdf2 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -494,11 +494,17 @@ #define MIPS_CONF1_PC (_ULCAST_(1) << 4) #define MIPS_CONF1_MD (_ULCAST_(1) << 5) #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) +#define MIPS_CONF1_DA_SHIFT 7 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) +#define MIPS_CONF1_DL_SHIFT 10 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) +#define MIPS_CONF1_DS_SHIFT 13 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) +#define MIPS_CONF1_IA_SHIFT 16 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) +#define MIPS_CONF1_IL_SHIFT 19 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) +#define MIPS_CONF1_IS_SHIFT 22 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) -- cgit v1.2.1 From 6011dabd0ae0c01991e4ccd85a15bb2225b7e8bd Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:43 +0000 Subject: pcnet: code style cleanup Fix up the code to match Documentation/CodingStyle. This is mostly removing extraneous spaces. No functional change is intended. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 248 ++++++++++++++++++++++++++-------------------------- 1 file changed, 123 insertions(+), 125 deletions(-) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 283cb48b4e..a30a0bc9ca 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -89,39 +89,39 @@ static pcnet_priv_t *lp; #define PCNET_RESET 0x14 #define PCNET_BDP 0x16 -static u16 pcnet_read_csr (struct eth_device *dev, int index) +static u16 pcnet_read_csr(struct eth_device *dev, int index) { - outw (index, dev->iobase + PCNET_RAP); - return inw (dev->iobase + PCNET_RDP); + outw(index, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_RDP); } -static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) +static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase + PCNET_RAP); - outw (val, dev->iobase + PCNET_RDP); + outw(index, dev->iobase + PCNET_RAP); + outw(val, dev->iobase + PCNET_RDP); } -static u16 pcnet_read_bcr (struct eth_device *dev, int index) +static u16 pcnet_read_bcr(struct eth_device *dev, int index) { - outw (index, dev->iobase + PCNET_RAP); - return inw (dev->iobase + PCNET_BDP); + outw(index, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_BDP); } -static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) +static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) { - outw (index, dev->iobase + PCNET_RAP); - outw (val, dev->iobase + PCNET_BDP); + outw(index, dev->iobase + PCNET_RAP); + outw(val, dev->iobase + PCNET_BDP); } -static void pcnet_reset (struct eth_device *dev) +static void pcnet_reset(struct eth_device *dev) { - inw (dev->iobase + PCNET_RESET); + inw(dev->iobase + PCNET_RESET); } -static int pcnet_check (struct eth_device *dev) +static int pcnet_check(struct eth_device *dev) { - outw (88, dev->iobase + PCNET_RAP); - return (inw (dev->iobase + PCNET_RAP) == 88); + outw(88, dev->iobase + PCNET_RAP); + return inw(dev->iobase + PCNET_RAP) == 88; } static int pcnet_init (struct eth_device *dev, bd_t * bis); @@ -139,63 +139,64 @@ static struct pci_device_id supported[] = { }; -int pcnet_initialize (bd_t * bis) +int pcnet_initialize(bd_t *bis) { pci_dev_t devbusfn; struct eth_device *dev; u16 command, status; int dev_nr = 0; - PCNET_DEBUG1 ("\npcnet_initialize...\n"); + PCNET_DEBUG1("\npcnet_initialize...\n"); for (dev_nr = 0;; dev_nr++) { /* * Find the PCnet PCI device(s). */ - if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { + devbusfn = pci_find_devices(supported, dev_nr); + if (devbusfn < 0) break; - } /* * Allocate and pre-fill the device structure. */ - dev = (struct eth_device *) malloc (sizeof *dev); + dev = (struct eth_device *)malloc(sizeof(*dev)); if (!dev) { printf("pcnet: Can not allocate memory\n"); break; } memset(dev, 0, sizeof(*dev)); - dev->priv = (void *) devbusfn; - sprintf (dev->name, "pcnet#%d", dev_nr); + dev->priv = (void *)devbusfn; + sprintf(dev->name, "pcnet#%d", dev_nr); /* * Setup the PCI device. */ - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, - (unsigned int *) &dev->iobase); - dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, + (unsigned int *)&dev->iobase); + dev->iobase = pci_io_to_phys(devbusfn, dev->iobase); dev->iobase &= ~0xf; - PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", - dev->name, devbusfn, dev->iobase); + PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", + dev->name, devbusfn, dev->iobase); command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; - pci_write_config_word (devbusfn, PCI_COMMAND, command); - pci_read_config_word (devbusfn, PCI_COMMAND, &status); + pci_write_config_word(devbusfn, PCI_COMMAND, command); + pci_read_config_word(devbusfn, PCI_COMMAND, &status); if ((status & command) != command) { - printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); - free (dev); + printf("%s: Couldn't enable IO access or Bus Mastering\n", + dev->name); + free(dev); continue; } - pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); + pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); /* * Probe the PCnet chip. */ - if (pcnet_probe (dev, bis, dev_nr) < 0) { - free (dev); + if (pcnet_probe(dev, bis, dev_nr) < 0) { + free(dev); continue; } @@ -207,15 +208,15 @@ int pcnet_initialize (bd_t * bis) dev->send = pcnet_send; dev->recv = pcnet_recv; - eth_register (dev); + eth_register(dev); } - udelay (10 * 1000); + udelay(10 * 1000); return dev_nr; } -static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) +static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) { int chip_version; char *chipname; @@ -225,17 +226,17 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) #endif /* Reset the PCnet controller */ - pcnet_reset (dev); + pcnet_reset(dev); /* Check if register access is working */ - if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { - printf ("%s: CSR register access check failed\n", dev->name); + if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { + printf("%s: CSR register access check failed\n", dev->name); return -1; } /* Identify the chip */ chip_version = - pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); + pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); if ((chip_version & 0xfff) != 0x003) return -1; chip_version = (chip_version >> 12) & 0xffff; @@ -254,12 +255,12 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) break; #endif default: - printf ("%s: PCnet version %#x not supported\n", - dev->name, chip_version); + printf("%s: PCnet version %#x not supported\n", + dev->name, chip_version); return -1; } - PCNET_DEBUG1 ("AMD %s\n", chipname); + PCNET_DEBUG1("AMD %s\n", chipname); #ifdef PCNET_HAS_PROM /* @@ -270,7 +271,7 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) for (i = 0; i < 3; i++) { unsigned int val; - val = pcnet_read_csr (dev, i + 12) & 0x0ffff; + val = pcnet_read_csr(dev, i + 12) & 0x0ffff; /* There may be endianness issues here. */ dev->enetaddr[2 * i] = val & 0x0ff; dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; @@ -280,35 +281,35 @@ static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) return 0; } -static int pcnet_init (struct eth_device *dev, bd_t * bis) +static int pcnet_init(struct eth_device *dev, bd_t *bis) { int i, val; u32 addr; - PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); + PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); /* Switch pcnet to 32bit mode */ - pcnet_write_bcr (dev, 20, 2); + pcnet_write_bcr(dev, 20, 2); #ifdef CONFIG_PN62 /* Setup LED registers */ - val = pcnet_read_bcr (dev, 2) | 0x1000; - pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ - pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ - pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ - pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ - pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ + val = pcnet_read_bcr(dev, 2) | 0x1000; + pcnet_write_bcr(dev, 2, val); /* enable LEDPE */ + pcnet_write_bcr(dev, 4, 0x5080); /* 100MBit */ + pcnet_write_bcr(dev, 5, 0x40c0); /* LNKSE */ + pcnet_write_bcr(dev, 6, 0x4090); /* TX Activity */ + pcnet_write_bcr(dev, 7, 0x4084); /* RX Activity */ #endif /* Set/reset autoselect bit */ - val = pcnet_read_bcr (dev, 2) & ~2; + val = pcnet_read_bcr(dev, 2) & ~2; val |= 2; - pcnet_write_bcr (dev, 2, val); + pcnet_write_bcr(dev, 2, val); /* Enable auto negotiate, setup, disable fd */ - val = pcnet_read_bcr (dev, 32) & ~0x98; + val = pcnet_read_bcr(dev, 32) & ~0x98; val |= 0x20; - pcnet_write_bcr (dev, 32, val); + pcnet_write_bcr(dev, 32, val); /* * We only maintain one structure because the drivers will never @@ -316,12 +317,12 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis) * must be aligned on 16-byte boundaries. */ if (lp == NULL) { - addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); + addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); addr = (addr + 0xf) & ~0xf; - lp = (pcnet_priv_t *) addr; + lp = (pcnet_priv_t *)addr; } - lp->init_block.mode = cpu_to_le16 (0x0000); + lp->init_block.mode = cpu_to_le16(0x0000); lp->init_block.filter[0] = 0x00000000; lp->init_block.filter[1] = 0x00000000; @@ -330,9 +331,9 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis) */ lp->cur_rx = 0; for (i = 0; i < RX_RING_SIZE; i++) { - lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); - lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); - lp->rx_ring[i].status = cpu_to_le16 (0x8000); + lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]); + lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); + lp->rx_ring[i].status = cpu_to_le16(0x8000); PCNET_DEBUG1 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length, @@ -352,48 +353,48 @@ static int pcnet_init (struct eth_device *dev, bd_t * bis) /* * Setup Init Block. */ - PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); + PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block); for (i = 0; i < 6; i++) { lp->init_block.phys_addr[i] = dev->enetaddr[i]; - PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); + PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]); } - lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | - RX_RING_LEN_BITS); - lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); - lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); + lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | + RX_RING_LEN_BITS); + lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); + lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); - PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", - lp->init_block.tlen_rlen, - lp->init_block.rx_ring, lp->init_block.tx_ring); + PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", + lp->init_block.tlen_rlen, + lp->init_block.rx_ring, lp->init_block.tx_ring); /* * Tell the controller where the Init Block is located. */ - addr = PCI_TO_MEM (dev, &lp->init_block); - pcnet_write_csr (dev, 1, addr & 0xffff); - pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); + addr = PCI_TO_MEM(dev, &lp->init_block); + pcnet_write_csr(dev, 1, addr & 0xffff); + pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); - pcnet_write_csr (dev, 4, 0x0915); - pcnet_write_csr (dev, 0, 0x0001); /* start */ + pcnet_write_csr(dev, 4, 0x0915); + pcnet_write_csr(dev, 0, 0x0001); /* start */ /* Wait for Init Done bit */ for (i = 10000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x0100) + if (pcnet_read_csr(dev, 0) & 0x0100) break; - udelay (10); + udelay(10); } if (i <= 0) { - printf ("%s: TIMEOUT: controller init failed\n", dev->name); - pcnet_reset (dev); + printf("%s: TIMEOUT: controller init failed\n", dev->name); + pcnet_reset(dev); return -1; } /* * Finally start network controller operation. */ - pcnet_write_csr (dev, 0, 0x0002); + pcnet_write_csr(dev, 0, 0x0002); return 0; } @@ -403,20 +404,20 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) int i, status; struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; - PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, - packet); + PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, + packet); /* Wait for completion by testing the OWN bit */ for (i = 1000; i > 0; i--) { - status = le16_to_cpu (entry->status); + status = le16_to_cpu(entry->status); if ((status & 0x8000) == 0) break; - udelay (100); - PCNET_DEBUG2 ("."); + udelay(100); + PCNET_DEBUG2("."); } if (i <= 0) { - printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", - dev->name, lp->cur_tx, status); + printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", + dev->name, lp->cur_tx, status); pkt_len = 0; goto failure; } @@ -426,19 +427,19 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) * set the status with the "ownership" bits last. */ status = 0x8300; - entry->length = le16_to_cpu (-pkt_len); + entry->length = le16_to_cpu(-pkt_len); entry->misc = 0x00000000; - entry->base = PCI_TO_MEM_LE (dev, packet); - entry->status = le16_to_cpu (status); + entry->base = PCI_TO_MEM_LE(dev, packet); + entry->status = le16_to_cpu(status); /* Trigger an immediate send poll. */ - pcnet_write_csr (dev, 0, 0x0008); + pcnet_write_csr(dev, 0, 0x0008); failure: if (++lp->cur_tx >= TX_RING_SIZE) lp->cur_tx = 0; - PCNET_DEBUG2 ("done\n"); + PCNET_DEBUG2("done\n"); return pkt_len; } @@ -453,40 +454,38 @@ static int pcnet_recv (struct eth_device *dev) /* * If we own the next entry, it's a new packet. Send it up. */ - if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { + status = le16_to_cpu(entry->status); + if ((status & 0x8000) != 0) break; - } status >>= 8; if (status != 0x03) { /* There was an error. */ - - printf ("%s: Rx%d", dev->name, lp->cur_rx); - PCNET_DEBUG1 (" (status=0x%x)", status); + printf("%s: Rx%d", dev->name, lp->cur_rx); + PCNET_DEBUG1(" (status=0x%x)", status); if (status & 0x20) - printf (" Frame"); + printf(" Frame"); if (status & 0x10) - printf (" Overflow"); + printf(" Overflow"); if (status & 0x08) - printf (" CRC"); + printf(" CRC"); if (status & 0x04) - printf (" Fifo"); - printf (" Error\n"); - entry->status &= le16_to_cpu (0x03ff); + printf(" Fifo"); + printf(" Error\n"); + entry->status &= le16_to_cpu(0x03ff); } else { - - pkt_len = - (le32_to_cpu (entry->msg_length) & 0xfff) - 4; + pkt_len = (le32_to_cpu(entry->msg_length) & 0xfff) - 4; if (pkt_len < 60) { - printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); + printf("%s: Rx%d: invalid packet length %d\n", + dev->name, lp->cur_rx, pkt_len); } else { - NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); - PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", - lp->cur_rx, pkt_len, - lp->rx_buf[lp->cur_rx]); + NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); + PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", + lp->cur_rx, pkt_len, + lp->rx_buf[lp->cur_rx]); } } - entry->status |= cpu_to_le16 (0x8000); + entry->status |= cpu_to_le16(0x8000); if (++lp->cur_rx >= RX_RING_SIZE) lp->cur_rx = 0; @@ -494,22 +493,21 @@ static int pcnet_recv (struct eth_device *dev) return pkt_len; } -static void pcnet_halt (struct eth_device *dev) +static void pcnet_halt(struct eth_device *dev) { int i; - PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); + PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); /* Reset the PCnet controller */ - pcnet_reset (dev); + pcnet_reset(dev); /* Wait for Stop bit */ for (i = 1000; i > 0; i--) { - if (pcnet_read_csr (dev, 0) & 0x4) + if (pcnet_read_csr(dev, 0) & 0x4) break; - udelay (10); - } - if (i <= 0) { - printf ("%s: TIMEOUT: controller reset failed\n", dev->name); + udelay(10); } + if (i <= 0) + printf("%s: TIMEOUT: controller reset failed\n", dev->name); } -- cgit v1.2.1 From a95400411b0938b1ef6d87090f4b22026c56e55b Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:44 +0000 Subject: pcnet: s/le16_to_cpu/cpu_to_le16/ in pcnet_send This should cause no change to the generated code, but is semantically correct. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index a30a0bc9ca..843a6fcba5 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -427,10 +427,10 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) * set the status with the "ownership" bits last. */ status = 0x8300; - entry->length = le16_to_cpu(-pkt_len); + entry->length = cpu_to_le16(-pkt_len); entry->misc = 0x00000000; entry->base = PCI_TO_MEM_LE(dev, packet); - entry->status = le16_to_cpu(status); + entry->status = cpu_to_le16(status); /* Trigger an immediate send poll. */ pcnet_write_csr(dev, 0, 0x0008); -- cgit v1.2.1 From f3ac866c78f7f0d91eb345967350830d46c3a563 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:45 +0000 Subject: pcnet: add cache flushing & invalidation Ensure that the view of memory from the CPU & the ethernet controller is coherent at the various points where they exchange data. This prevents stale data from being transmitted or received, and prevents the driver from getting stuck waiting for the ethernet controller to update descriptors when in reality it has but the old values are being read from cache. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 843a6fcba5..7b87660281 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -364,6 +364,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) RX_RING_LEN_BITS); lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring); lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring); + flush_dcache_range((unsigned long)lp, (unsigned long)&lp->rx_buf); PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", lp->init_block.tlen_rlen, @@ -407,8 +408,13 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet); + flush_dcache_range((unsigned long)packet, + (unsigned long)packet + pkt_len); + /* Wait for completion by testing the OWN bit */ for (i = 1000; i > 0; i--) { + invalidate_dcache_range((unsigned long)entry, + (unsigned long)entry + sizeof(*entry)); status = le16_to_cpu(entry->status); if ((status & 0x8000) == 0) break; @@ -431,6 +437,8 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) entry->misc = 0x00000000; entry->base = PCI_TO_MEM_LE(dev, packet); entry->status = cpu_to_le16(status); + flush_dcache_range((unsigned long)entry, + (unsigned long)entry + sizeof(*entry)); /* Trigger an immediate send poll. */ pcnet_write_csr(dev, 0, 0x0008); @@ -451,6 +459,8 @@ static int pcnet_recv (struct eth_device *dev) while (1) { entry = &lp->rx_ring[lp->cur_rx]; + invalidate_dcache_range((unsigned long)entry, + (unsigned long)entry + sizeof(*entry)); /* * If we own the next entry, it's a new packet. Send it up. */ @@ -479,6 +489,10 @@ static int pcnet_recv (struct eth_device *dev) printf("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); } else { + invalidate_dcache_range( + (unsigned long)lp->rx_buf[lp->cur_rx], + (unsigned long)lp->rx_buf[lp->cur_rx] + + pkt_len); NetReceive(lp->rx_buf[lp->cur_rx], pkt_len); PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", lp->cur_rx, pkt_len, @@ -486,6 +500,8 @@ static int pcnet_recv (struct eth_device *dev) } } entry->status |= cpu_to_le16(0x8000); + flush_dcache_range((unsigned long)entry, + (unsigned long)entry + sizeof(*entry)); if (++lp->cur_rx >= RX_RING_SIZE) lp->cur_rx = 0; -- cgit v1.2.1 From 62715a2c57c01630af8198ed108874def5a99cf7 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:46 +0000 Subject: pcnet: enable the NOUFLO feature On relatively slow boards (such as the MIPS Malta with an FPGA core card) it can be extremely common for transmits to underflow - to the point where it appears they simply do not work at all. Setting the NOUFLO bit causes the ethernet controller to not begin transmission on the wire until a transmit start point is reached. Setting that transmit start point to the full packet will cause the controller to only transmit the packet once it has buffered it entirely thus preventing any transmit underflows from occuring and allowing the controller to function on slower boards. Signed-off-by: Paul Burton --- drivers/net/pcnet.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 7b87660281..5b248bee43 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -311,6 +311,21 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) val |= 0x20; pcnet_write_bcr(dev, 32, val); + /* + * Enable NOUFLO on supported controllers, with the transmit + * start point set to the full packet. This will cause entire + * packets to be buffered by the ethernet controller before + * transmission, eliminating underflows which are common on + * slower devices. Controllers which do not support NOUFLO will + * simply be left with a larger transmit FIFO threshold. + */ + val = pcnet_read_bcr(dev, 18); + val |= 1 << 11; + pcnet_write_bcr(dev, 18, val); + val = pcnet_read_csr(dev, 80); + val |= 0x3 << 10; + pcnet_write_csr(dev, 80, val); + /* * We only maintain one structure because the drivers will never * be used concurrently. In 32bit mode the RX and TX ring entries -- cgit v1.2.1 From fa5cec032180a997b82b52f0b6075aa548a953cd Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:47 +0000 Subject: pci.h: allow inclusion in assembly source This patch simply #ifdef's out the C-specific parts of pci.h when it is included by an assembly file. This will allow the macros it contains to be used from assembly source as will be done in a followup commit adding support for more modern MIPS Malta boards. Signed-off-by: Paul Burton --- include/pci.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/pci.h b/include/pci.h index d462479667..461f17c058 100644 --- a/include/pci.h +++ b/include/pci.h @@ -417,6 +417,8 @@ #include +#ifndef __ASSEMBLY__ + #ifdef CONFIG_SYS_PCI_64BIT typedef u64 pci_addr_t; typedef u64 pci_size_t; @@ -667,4 +669,6 @@ extern void pci_mpc824x_init (struct pci_controller *hose); #ifdef CONFIG_MPC85xx extern void pci_mpc85xx_init (struct pci_controller *hose); #endif -#endif /* _PCI_H */ + +#endif /* __ASSEMBLY__ */ +#endif /* _PCI_H */ -- cgit v1.2.1 From 7a9d109b00a207b481b05d8e147673da33ad1cd3 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sat, 9 Nov 2013 10:22:08 +0000 Subject: qemu-malta: rename to just "malta" This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton --- arch/mips/cpu/mips32/start.S | 2 +- arch/mips/lib/bootm.c | 12 ++-- board/imgtec/malta/Makefile | 9 +++ board/imgtec/malta/lowlevel_init.S | 69 ++++++++++++++++++++++ board/imgtec/malta/malta.c | 47 +++++++++++++++ board/qemu-malta/Makefile | 9 --- board/qemu-malta/lowlevel_init.S | 69 ---------------------- board/qemu-malta/qemu-malta.c | 47 --------------- boards.cfg | 4 +- include/configs/malta.h | 113 +++++++++++++++++++++++++++++++++++++ include/configs/qemu-malta.h | 113 ------------------------------------- 11 files changed, 247 insertions(+), 247 deletions(-) create mode 100644 board/imgtec/malta/Makefile create mode 100644 board/imgtec/malta/lowlevel_init.S create mode 100644 board/imgtec/malta/malta.c delete mode 100644 board/qemu-malta/Makefile delete mode 100644 board/qemu-malta/lowlevel_init.S delete mode 100644 board/qemu-malta/qemu-malta.c create mode 100644 include/configs/malta.h delete mode 100644 include/configs/qemu-malta.h diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 70ad198cc9..68e59b596f 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -51,7 +51,7 @@ _start: */ .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x0 -#elif defined(CONFIG_QEMU_MALTA) +#elif defined(CONFIG_MALTA) /* * Linux expects the Board ID here. */ diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 66340ea470..1febf29865 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -17,10 +17,10 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#if defined(CONFIG_QEMU_MALTA) -#define mips_boot_qemu_malta 1 +#if defined(CONFIG_MALTA) +#define mips_boot_malta 1 #else -#define mips_boot_qemu_malta 0 +#define mips_boot_malta 0 #endif static int linux_argc; @@ -139,7 +139,7 @@ static void linux_env_set(const char *env_name, const char *env_val) strcpy(linux_env_p, env_name); linux_env_p += strlen(env_name); - if (mips_boot_qemu_malta) { + if (mips_boot_malta) { linux_env_p++; linux_env[++linux_env_idx] = linux_env_p; } else { @@ -196,7 +196,7 @@ static void boot_prep_linux(bootm_headers_t *images) if (cp) linux_env_set("eth1addr", cp); - if (mips_boot_qemu_malta) + if (mips_boot_malta) linux_env_set("modetty0", "38400n8r"); } @@ -210,7 +210,7 @@ static void boot_jump_linux(bootm_headers_t *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); - if (mips_boot_qemu_malta) + if (mips_boot_malta) linux_extra = gd->ram_size; /* we assume that the kernel is in place */ diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile new file mode 100644 index 0000000000..091830dd0f --- /dev/null +++ b/board/imgtec/malta/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = malta.o +obj-y += lowlevel_init.o diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S new file mode 100644 index 0000000000..fa0b6a7d13 --- /dev/null +++ b/board/imgtec/malta/lowlevel_init.S @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include +#include +#include + +#ifdef CONFIG_SYS_BIG_ENDIAN +#define CPU_TO_GT32(_x) ((_x)) +#else +#define CPU_TO_GT32(_x) ( \ + (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ + (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) +#endif + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + + /* + * Load BAR registers of GT64120 as done by YAMON + * + * based on a patch sent by Antony Pavlov + * to the barebox mailing list. + * The subject of the original patch: + * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' + * URL: + * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html + * + * based on write_bootloader() in qemu.git/hw/mips_malta.c + * see GT64120 manual and qemu.git/hw/gt64xxx.c for details + */ + + /* move GT64120 registers from 0x14000000 to 0x1be00000 */ + li t1, KSEG1ADDR(GT_DEF_BASE) + li t0, CPU_TO_GT32(0xdf000000) + sw t0, GT_ISD_OFS(t1) + + /* setup MEM-to-PCI0 mapping */ + li t1, KSEG1ADDR(MALTA_GT_BASE) + + /* setup PCI0 io window to 0x18000000-0x181fffff */ + li t0, CPU_TO_GT32(0xc0000000) + sw t0, GT_PCI0IOLD_OFS(t1) + li t0, CPU_TO_GT32(0x40000000) + sw t0, GT_PCI0IOHD_OFS(t1) + + /* setup PCI0 mem windows */ + li t0, CPU_TO_GT32(0x80000000) + sw t0, GT_PCI0M0LD_OFS(t1) + li t0, CPU_TO_GT32(0x3f000000) + sw t0, GT_PCI0M0HD_OFS(t1) + + li t0, CPU_TO_GT32(0xc1000000) + sw t0, GT_PCI0M1LD_OFS(t1) + li t0, CPU_TO_GT32(0x5e000000) + sw t0, GT_PCI0M1HD_OFS(t1) + + jr ra + nop diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c new file mode 100644 index 0000000000..7eddf1ce66 --- /dev/null +++ b/board/imgtec/malta/malta.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include + +#include +#include +#include +#include + +phys_size_t initdram(int board_type) +{ + return CONFIG_SYS_MEM_SIZE; +} + +int checkboard(void) +{ + puts("Board: MIPS Malta CoreLV (Qemu)\n"); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +void _machine_restart(void) +{ + void __iomem *reset_base; + + reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); + __raw_writel(GORESET, reset_base); +} + +void pci_init_board(void) +{ + set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); + + gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), + 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, + 0x10000000, 0x10000000, 128 * 1024 * 1024, + 0x00000000, 0x00000000, 0x20000); +} diff --git a/board/qemu-malta/Makefile b/board/qemu-malta/Makefile deleted file mode 100644 index 5d727f6f52..0000000000 --- a/board/qemu-malta/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = qemu-malta.o -obj-y += lowlevel_init.o diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S deleted file mode 100644 index fa0b6a7d13..0000000000 --- a/board/qemu-malta/lowlevel_init.S +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include - -#include -#include -#include - -#ifdef CONFIG_SYS_BIG_ENDIAN -#define CPU_TO_GT32(_x) ((_x)) -#else -#define CPU_TO_GT32(_x) ( \ - (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ - (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) -#endif - - .text - .set noreorder - .set mips32 - - .globl lowlevel_init -lowlevel_init: - - /* - * Load BAR registers of GT64120 as done by YAMON - * - * based on a patch sent by Antony Pavlov - * to the barebox mailing list. - * The subject of the original patch: - * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' - * URL: - * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html - * - * based on write_bootloader() in qemu.git/hw/mips_malta.c - * see GT64120 manual and qemu.git/hw/gt64xxx.c for details - */ - - /* move GT64120 registers from 0x14000000 to 0x1be00000 */ - li t1, KSEG1ADDR(GT_DEF_BASE) - li t0, CPU_TO_GT32(0xdf000000) - sw t0, GT_ISD_OFS(t1) - - /* setup MEM-to-PCI0 mapping */ - li t1, KSEG1ADDR(MALTA_GT_BASE) - - /* setup PCI0 io window to 0x18000000-0x181fffff */ - li t0, CPU_TO_GT32(0xc0000000) - sw t0, GT_PCI0IOLD_OFS(t1) - li t0, CPU_TO_GT32(0x40000000) - sw t0, GT_PCI0IOHD_OFS(t1) - - /* setup PCI0 mem windows */ - li t0, CPU_TO_GT32(0x80000000) - sw t0, GT_PCI0M0LD_OFS(t1) - li t0, CPU_TO_GT32(0x3f000000) - sw t0, GT_PCI0M0HD_OFS(t1) - - li t0, CPU_TO_GT32(0xc1000000) - sw t0, GT_PCI0M1LD_OFS(t1) - li t0, CPU_TO_GT32(0x5e000000) - sw t0, GT_PCI0M1HD_OFS(t1) - - jr ra - nop diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c deleted file mode 100644 index 7eddf1ce66..0000000000 --- a/board/qemu-malta/qemu-malta.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include -#include - -#include -#include -#include -#include - -phys_size_t initdram(int board_type) -{ - return CONFIG_SYS_MEM_SIZE; -} - -int checkboard(void) -{ - puts("Board: MIPS Malta CoreLV (Qemu)\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -void _machine_restart(void) -{ - void __iomem *reset_base; - - reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); - __raw_writel(GORESET, reset_base); -} - -void pci_init_board(void) -{ - set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); - - gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), - 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, - 0x10000000, 0x10000000, 128 * 1024 * 1024, - 0x00000000, 0x00000000, 0x20000); -} diff --git a/boards.cfg b/boards.cfg index 375f2d4718..d4b6e53c55 100644 --- a/boards.cfg +++ b/boards.cfg @@ -480,10 +480,10 @@ Active m68k mcf547x_8x - freescale m548xevb Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek -Active mips mips32 - - qemu-malta qemu_malta qemu-malta:MIPS32,SYS_BIG_ENDIAN - -Active mips mips32 - - qemu-malta qemu_maltael qemu-malta:MIPS32,SYS_LITTLE_ENDIAN - Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - +Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN - +Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN - Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM - Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND - Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - diff --git a/include/configs/malta.h b/include/configs/malta.h new file mode 100644 index 0000000000..d067d98782 --- /dev/null +++ b/include/configs/malta.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2013 Gabor Juhos + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _MALTA_CONFIG_H +#define _MALTA_CONFIG_H + +#include +#include + +/* + * System configuration + */ +#define CONFIG_MALTA + +#define CONFIG_PCI +#define CONFIG_PCI_GT64120 +#define CONFIG_PCI_PNP +#define CONFIG_PCNET + +/* + * CPU Configuration + */ +#define CONFIG_SYS_MHZ 250 /* arbitrary value */ +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */ +#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */ +#define CONFIG_SYS_CACHELINE_SIZE 32 /* arbitrary value */ + +#define CONFIG_SWAP_IO_SPACE + +/* + * Memory map + */ +#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ +#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x80800000 + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) + +/* + * Console configuration + */ +#if defined(CONFIG_SYS_LITTLE_ENDIAN) +#define CONFIG_SYS_PROMPT "maltael # " +#else +#define CONFIG_SYS_PROMPT "malta # " +#endif + +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +/* + * Serial driver + */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_UART_BASE) +#define CONFIG_CONS_INDEX 1 + +/* + * Environment + */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Flash configuration + */ +#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* + * Commands + */ +#include + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */ + +#endif /* _MALTA_CONFIG_H */ diff --git a/include/configs/qemu-malta.h b/include/configs/qemu-malta.h deleted file mode 100644 index 03514d165b..0000000000 --- a/include/configs/qemu-malta.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (C) 2013 Gabor Juhos - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#ifndef _QEMU_MALTA_CONFIG_H -#define _QEMU_MALTA_CONFIG_H - -#include -#include - -/* - * System configuration - */ -#define CONFIG_QEMU_MALTA - -#define CONFIG_PCI -#define CONFIG_PCI_GT64120 -#define CONFIG_PCI_PNP -#define CONFIG_PCNET - -/* - * CPU Configuration - */ -#define CONFIG_SYS_MHZ 250 /* arbitrary value */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */ -#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* arbitrary value */ - -#define CONFIG_SWAP_IO_SPACE - -/* - * Memory map - */ -#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ -#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) - -/* - * Console configuration - */ -#if defined(CONFIG_SYS_LITTLE_ENDIAN) -#define CONFIG_SYS_PROMPT "qemu-maltael # " -#else -#define CONFIG_SYS_PROMPT "qemu-malta # " -#endif - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 - -#define CONFIG_AUTO_COMPLETE -#define CONFIG_CMDLINE_EDITING - -/* - * Serial driver - */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_UART_BASE) -#define CONFIG_CONS_INDEX 1 - -/* - * Environment - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE (KSEG1 | MALTA_FLASH_BASE) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE - -/* - * Commands - */ -#include - -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NFS - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_PING - -#define CONFIG_SYS_LONGHELP /* verbose help, undef to save memory */ - -#endif /* _QEMU_MALTA_CONFIG_H */ -- cgit v1.2.1 From a257f6263b51321ecacc69ac1effbcbe2158fe15 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:49 +0000 Subject: malta: setup super I/O UARTs On a real Malta the Super I/O needs to be configured before we are able to access the UARTs. This patch performs that configuration, setting up the UARTs in the same way that YAMON would. Signed-off-by: Paul Burton --- board/imgtec/malta/Makefile | 1 + board/imgtec/malta/malta.c | 10 +++++++ board/imgtec/malta/superio.c | 63 ++++++++++++++++++++++++++++++++++++++++++++ board/imgtec/malta/superio.h | 15 +++++++++++ 4 files changed, 89 insertions(+) create mode 100644 board/imgtec/malta/superio.c create mode 100644 board/imgtec/malta/superio.h diff --git a/board/imgtec/malta/Makefile b/board/imgtec/malta/Makefile index 091830dd0f..19dd3a3c3b 100644 --- a/board/imgtec/malta/Makefile +++ b/board/imgtec/malta/Makefile @@ -7,3 +7,4 @@ obj-y = malta.o obj-y += lowlevel_init.o +obj-y += superio.o diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 7eddf1ce66..09da9eae51 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -12,6 +12,8 @@ #include #include +#include "superio.h" + phys_size_t initdram(int board_type) { return CONFIG_SYS_MEM_SIZE; @@ -36,6 +38,14 @@ void _machine_restart(void) __raw_writel(GORESET, reset_base); } +int board_early_init_f(void) +{ + /* setup FDC37M817 super I/O controller */ + malta_superio_init((void *)CKSEG1ADDR(MALTA_IO_PORT_BASE)); + + return 0; +} + void pci_init_board(void) { set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c new file mode 100644 index 0000000000..eaa14df39e --- /dev/null +++ b/board/imgtec/malta/superio.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * Setup code for the FDC37M817 super I/O controller + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define SIO_CONF_PORT 0x3f0 +#define SIO_DATA_PORT 0x3f1 + +enum sio_conf_key { + SIOCONF_DEVNUM = 0x07, + SIOCONF_ACTIVATE = 0x30, + SIOCONF_ENTER_SETUP = 0x55, + SIOCONF_BASE_HIGH = 0x60, + SIOCONF_BASE_LOW = 0x61, + SIOCONF_PRIMARY_INT = 0x70, + SIOCONF_EXIT_SETUP = 0xaa, + SIOCONF_MODE = 0xf0, +}; + +static struct { + u8 key; + u8 data; +} sio_config[] = { + /* tty0 */ + { SIOCONF_DEVNUM, 0x04 }, + { SIOCONF_BASE_HIGH, 0x03 }, + { SIOCONF_BASE_LOW, 0xf8 }, + { SIOCONF_MODE, 0x02 }, + { SIOCONF_PRIMARY_INT, 0x04 }, + { SIOCONF_ACTIVATE, 0x01 }, + + /* tty1 */ + { SIOCONF_DEVNUM, 0x05 }, + { SIOCONF_BASE_HIGH, 0x02 }, + { SIOCONF_BASE_LOW, 0xf8 }, + { SIOCONF_MODE, 0x02 }, + { SIOCONF_PRIMARY_INT, 0x03 }, + { SIOCONF_ACTIVATE, 0x01 }, +}; + +void malta_superio_init(void *io_base) +{ + unsigned i; + + /* enter config state */ + writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT); + + /* configure peripherals */ + for (i = 0; i < ARRAY_SIZE(sio_config); i++) { + writeb(sio_config[i].key, io_base + SIO_CONF_PORT); + writeb(sio_config[i].data, io_base + SIO_DATA_PORT); + } + + /* exit config state */ + writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT); +} diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h new file mode 100644 index 0000000000..1450da56dd --- /dev/null +++ b/board/imgtec/malta/superio.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * Setup code for the FDC37M817 super I/O controller + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __BOARD_MALTA_SUPERIO_H__ +#define __BOARD_MALTA_SUPERIO_H__ + +extern void malta_superio_init(void *io_base); + +#endif /* __BOARD_MALTA_SUPERIO_H__ */ -- cgit v1.2.1 From baf37f06c5cc51d2b9d71a2c83d5d92de60203a9 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:50 +0000 Subject: malta: support for coreFPGA6 boards This patch adds support for running on Malta boards using coreFPGA6 core cards, including support for the msc01 system controller used with them. The system controller is detected at runtime allowing one U-boot binary to run on a Malta with either. Due to the PCI I/O base differing between Maltas using gt64120 & msc01 system controllers, the UART setup is modified slightly. A second UART is added so that there is one pointing at the correct address for each system controller. The Malta board then defines its own default_serial_console function to select the correct one at runtime. The incorrect UART will simply not function. Tested on: - A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both with and without an L2 cache. - QEMU. Signed-off-by: Paul Burton --- arch/mips/include/asm/malta.h | 35 ++++++-- board/imgtec/malta/lowlevel_init.S | 164 ++++++++++++++++++++++++++++++++++++- board/imgtec/malta/malta.c | 126 ++++++++++++++++++++++++++-- drivers/pci/Makefile | 1 + drivers/pci/pci_msc01.c | 125 ++++++++++++++++++++++++++++ include/configs/malta.h | 4 +- include/msc01.h | 135 ++++++++++++++++++++++++++++++ include/pci_ids.h | 3 + include/pci_msc01.h | 17 ++++ 9 files changed, 594 insertions(+), 16 deletions(-) create mode 100644 drivers/pci/pci_msc01.c create mode 100644 include/msc01.h create mode 100644 include/pci_msc01.h diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index d4d44a299f..0b50a66e07 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -9,15 +9,38 @@ #ifndef _MIPS_ASM_MALTA_H #define _MIPS_ASM_MALTA_H -#define MALTA_IO_PORT_BASE 0x18000000 +#define MALTA_GT_BASE 0x1be00000 +#define MALTA_GT_PCIIO_BASE 0x18000000 +#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8) -#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8) +#define MALTA_MSC01_BIU_BASE 0x1bc80000 +#define MALTA_MSC01_PCI_BASE 0x1bd00000 +#define MALTA_MSC01_PBC_BASE 0x1bd40000 +#define MALTA_MSC01_IP1_BASE 0x1bc00000 +#define MALTA_MSC01_IP1_SIZE 0x00400000 +#define MALTA_MSC01_IP2_BASE1 0x10000000 +#define MALTA_MSC01_IP2_SIZE1 0x08000000 +#define MALTA_MSC01_IP2_BASE2 0x18000000 +#define MALTA_MSC01_IP2_SIZE2 0x04000000 +#define MALTA_MSC01_IP3_BASE 0x1c000000 +#define MALTA_MSC01_IP3_SIZE 0x04000000 +#define MALTA_MSC01_PCIMEM_BASE 0x10000000 +#define MALTA_MSC01_PCIMEM_SIZE 0x10000000 +#define MALTA_MSC01_PCIMEM_MAP 0x10000000 +#define MALTA_MSC01_PCIIO_BASE 0x1b000000 +#define MALTA_MSC01_PCIIO_SIZE 0x00800000 +#define MALTA_MSC01_PCIIO_MAP 0x00000000 +#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) -#define MALTA_GT_BASE 0x1be00000 +#define MALTA_RESET_BASE 0x1f000500 +#define GORESET 0x42 -#define MALTA_RESET_BASE 0x1f000500 -#define GORESET 0x42 +#define MALTA_FLASH_BASE 0x1fc00000 -#define MALTA_FLASH_BASE 0x1fc00000 +#define MALTA_REVISION 0x1fc00010 +#define MALTA_REVISION_CORID_SHF 10 +#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF) +#define MALTA_REVISION_CORID_CORE_LV 1 +#define MALTA_REVISION_CORID_CORE_FPGA6 14 #endif /* _MIPS_ASM_MALTA_H */ diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index fa0b6a7d13..1af34f142f 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -6,6 +6,8 @@ #include #include +#include +#include #include #include @@ -25,6 +27,25 @@ .globl lowlevel_init lowlevel_init: + /* detect the core card */ + li t0, KSEG1ADDR(MALTA_REVISION) + lw t0, 0(t0) + srl t0, t0, MALTA_REVISION_CORID_SHF + andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ + MALTA_REVISION_CORID_SHF) + + /* core cards using the gt64120 system controller */ + li t1, MALTA_REVISION_CORID_CORE_LV + beq t0, t1, _gt64120 + + /* core cards using the MSC01 system controller */ + li t1, MALTA_REVISION_CORID_CORE_FPGA6 + beq t0, t1, _msc01 + nop + + /* unknown system controller */ + b . + nop /* * Load BAR registers of GT64120 as done by YAMON @@ -39,7 +60,7 @@ lowlevel_init: * based on write_bootloader() in qemu.git/hw/mips_malta.c * see GT64120 manual and qemu.git/hw/gt64xxx.c for details */ - +_gt64120: /* move GT64120 registers from 0x14000000 to 0x1be00000 */ li t1, KSEG1ADDR(GT_DEF_BASE) li t0, CPU_TO_GT32(0xdf000000) @@ -67,3 +88,144 @@ lowlevel_init: jr ra nop + + /* + * + */ +_msc01: + /* setup peripheral bus controller clock divide */ + li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE) + li t1, 0x1 << MSC01_PBC_CLKCFG_SHF + sw t1, MSC01_PBC_CLKCFG_OFS(t0) + + /* tweak peripheral bus controller timings */ + li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ + (0x1 << MSC01_PBC_CS0TIM_CAT_SHF) + sw t1, MSC01_PBC_CS0TIM_OFS(t0) + li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ + (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ + (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ + (0x2 << MSC01_PBC_CS0RW_WAT_SHF) + sw t1, MSC01_PBC_CS0RW_OFS(t0) + lw t1, MSC01_PBC_CS0CFG_OFS(t0) + li t2, MSC01_PBC_CS0CFG_DTYP_MSK + and t1, t2 + ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ + (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ + (0x10 << MSC01_PBC_CS0CFG_WS_SHF) + sw t1, MSC01_PBC_CS0CFG_OFS(t0) + + /* setup basic address decode */ + li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE) + li t1, 0x0 + li t2, -CONFIG_SYS_MEM_SIZE + sw t1, MSC01_BIU_MCBAS1L_OFS(t0) + sw t2, MSC01_BIU_MCMSK1L_OFS(t0) + sw t1, MSC01_BIU_MCBAS2L_OFS(t0) + sw t2, MSC01_BIU_MCMSK2L_OFS(t0) + + /* initialise IP1 - unused */ + li t1, MALTA_MSC01_IP1_BASE + li t2, -MALTA_MSC01_IP1_SIZE + sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) + sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) + sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) + sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) + + /* initialise IP2 - PCI */ + li t1, MALTA_MSC01_IP2_BASE1 + li t2, -MALTA_MSC01_IP2_SIZE1 + sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) + sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) + li t1, MALTA_MSC01_IP2_BASE2 + li t2, -MALTA_MSC01_IP2_SIZE2 + sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) + sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) + + /* initialise IP3 - peripheral bus controller */ + li t1, MALTA_MSC01_IP3_BASE + li t2, -MALTA_MSC01_IP3_SIZE + sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) + sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) + sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) + sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) + + /* setup PCI memory */ + li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE) + li t1, MALTA_MSC01_PCIMEM_BASE + li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK + li t3, MALTA_MSC01_PCIMEM_MAP + sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) + sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) + sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) + + /* setup PCI I/O */ + li t1, MALTA_MSC01_PCIIO_BASE + li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK + li t3, MALTA_MSC01_PCIIO_MAP + sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) + sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) + sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) + + /* setup PCI_BAR0 memory window */ + li t1, -CONFIG_SYS_MEM_SIZE + sw t1, MSC01_PCI_BAR0_OFS(t0) + + /* setup PCI to SysCon/CPU translation */ + sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) + sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) + + /* setup PCI vendor & device IDs */ + li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ + (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) + sw t1, MSC01_PCI_HEAD0_OFS(t0) + + /* setup PCI subsystem vendor & device IDs */ + sw t1, MSC01_PCI_HEAD11_OFS(t0) + + /* setup PCI class, revision */ + li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ + (0x1 << MSC01_PCI_HEAD2_REV_SHF) + sw t1, MSC01_PCI_HEAD2_OFS(t0) + + /* ensure a sane setup */ + sw zero, MSC01_PCI_HEAD3_OFS(t0) + sw zero, MSC01_PCI_HEAD4_OFS(t0) + sw zero, MSC01_PCI_HEAD5_OFS(t0) + sw zero, MSC01_PCI_HEAD6_OFS(t0) + sw zero, MSC01_PCI_HEAD7_OFS(t0) + sw zero, MSC01_PCI_HEAD8_OFS(t0) + sw zero, MSC01_PCI_HEAD9_OFS(t0) + sw zero, MSC01_PCI_HEAD10_OFS(t0) + sw zero, MSC01_PCI_HEAD12_OFS(t0) + sw zero, MSC01_PCI_HEAD13_OFS(t0) + sw zero, MSC01_PCI_HEAD14_OFS(t0) + sw zero, MSC01_PCI_HEAD15_OFS(t0) + + /* setup PCI command register */ + li t1, (PCI_COMMAND_FAST_BACK | \ + PCI_COMMAND_SERR | \ + PCI_COMMAND_PARITY | \ + PCI_COMMAND_MASTER | \ + PCI_COMMAND_MEMORY) + sw t1, MSC01_PCI_HEAD1_OFS(t0) + + /* setup PCI byte swapping */ +#ifdef CONFIG_SYS_BIG_ENDIAN + li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ + (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) + sw t1, MSC01_PCI_SWAP_OFS(t0) +#else + sw zero, MSC01_PCI_SWAP_OFS(t0) +#endif + + /* enable PCI host configuration cycles */ + lw t1, MSC01_PCI_CFG_OFS(t0) + li t2, MSC01_PCI_CFG_RA_MSK | \ + MSC01_PCI_CFG_G_MSK | \ + MSC01_PCI_CFG_EN_MSK + or t1, t1, t2 + sw t1, MSC01_PCI_CFG_OFS(t0) + + jr ra + nop diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 09da9eae51..2af00672da 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -1,19 +1,67 @@ /* * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2013 Imagination Technologies * * SPDX-License-Identifier: GPL-2.0 */ #include #include +#include +#include +#include #include #include #include -#include #include "superio.h" +enum core_card { + CORE_UNKNOWN, + CORE_LV, + CORE_FPGA6, +}; + +enum sys_con { + SYSCON_UNKNOWN, + SYSCON_GT64120, + SYSCON_MSC01, +}; + +static enum core_card malta_core_card(void) +{ + u32 corid, rev; + + rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); + corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; + + switch (corid) { + case MALTA_REVISION_CORID_CORE_LV: + return CORE_LV; + + case MALTA_REVISION_CORID_CORE_FPGA6: + return CORE_FPGA6; + + default: + return CORE_UNKNOWN; + } +} + +static enum sys_con malta_sys_con(void) +{ + switch (malta_core_card()) { + case CORE_LV: + return SYSCON_GT64120; + + case CORE_FPGA6: + return SYSCON_MSC01; + + default: + return SYSCON_UNKNOWN; + } +} + phys_size_t initdram(int board_type) { return CONFIG_SYS_MEM_SIZE; @@ -21,7 +69,25 @@ phys_size_t initdram(int board_type) int checkboard(void) { - puts("Board: MIPS Malta CoreLV (Qemu)\n"); + enum core_card core; + + puts("Board: MIPS Malta"); + + core = malta_core_card(); + switch (core) { + case CORE_LV: + puts(" CoreLV"); + break; + + case CORE_FPGA6: + puts(" CoreFPGA6"); + break; + + default: + puts(" CoreUnknown"); + } + + putc('\n'); return 0; } @@ -40,18 +106,62 @@ void _machine_restart(void) int board_early_init_f(void) { + void *io_base; + + /* choose correct PCI I/O base */ + switch (malta_sys_con()) { + case SYSCON_GT64120: + io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); + break; + + case SYSCON_MSC01: + io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); + break; + + default: + return -1; + } + /* setup FDC37M817 super I/O controller */ - malta_superio_init((void *)CKSEG1ADDR(MALTA_IO_PORT_BASE)); + malta_superio_init(io_base); return 0; } +struct serial_device *default_serial_console(void) +{ + switch (malta_sys_con()) { + case SYSCON_GT64120: + return &eserial1_device; + + default: + case SYSCON_MSC01: + return &eserial2_device; + } +} + void pci_init_board(void) { - set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); + switch (malta_sys_con()) { + case SYSCON_GT64120: + set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); + + gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), + 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, + 0x10000000, 0x10000000, 128 * 1024 * 1024, + 0x00000000, 0x00000000, 0x20000); + break; + + default: + case SYSCON_MSC01: + set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); - gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), - 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, - 0x10000000, 0x10000000, 128 * 1024 * 1024, - 0x00000000, 0x00000000, 0x20000); + msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), + 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, + MALTA_MSC01_PCIMEM_MAP, + CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), + MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, + 0x00000000, MALTA_MSC01_PCIIO_SIZE); + break; + } } diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 99d51a6a97..6182a5904d 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o obj-$(CONFIG_PCI) += pci.o pci_auto.o obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o +obj-$(CONFIG_PCI_MSC01) += pci_msc01.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o obj-$(CONFIG_IXP_PCI) += pci_ixp.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c new file mode 100644 index 0000000000..284ffa09b6 --- /dev/null +++ b/drivers/pci/pci_msc01.c @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +struct msc01_pci_controller { + struct pci_controller hose; + void *base; +}; + +static inline struct msc01_pci_controller * +hose_to_msc01(struct pci_controller *hose) +{ + return container_of(hose, struct msc01_pci_controller, hose); +} + +static int msc01_config_access(struct msc01_pci_controller *msc01, + unsigned char access_type, pci_dev_t bdf, + int where, u32 *data) +{ + const u32 aborts = MSC01_PCI_INTSTAT_MA_MSK | MSC01_PCI_INTSTAT_TA_MSK; + void *intstat = msc01->base + MSC01_PCI_INTSTAT_OFS; + void *cfgdata = msc01->base + MSC01_PCI_CFGDATA_OFS; + unsigned int bus = PCI_BUS(bdf); + unsigned int dev = PCI_DEV(bdf); + unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf); + + /* clear abort status */ + __raw_writel(aborts, intstat); + + /* setup address */ + __raw_writel((bus << MSC01_PCI_CFGADDR_BNUM_SHF) | + (dev << MSC01_PCI_CFGADDR_DNUM_SHF) | + (devfn << MSC01_PCI_CFGADDR_FNUM_SHF) | + ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF), + msc01->base + MSC01_PCI_CFGADDR_OFS); + + /* perform access */ + if (access_type == PCI_ACCESS_WRITE) + __raw_writel(*data, cfgdata); + else + *data = __raw_readl(cfgdata); + + /* check for aborts */ + if (__raw_readl(intstat) & aborts) { + /* clear abort status */ + __raw_writel(aborts, intstat); + return -1; + } + + return 0; +} + +static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev, + int where, u32 *value) +{ + struct msc01_pci_controller *msc01 = hose_to_msc01(hose); + + *value = 0xffffffff; + return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value); +} + +static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev, + int where, u32 value) +{ + struct msc01_pci_controller *gt = hose_to_msc01(hose); + u32 data = value; + + return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data); +} + +void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys, + unsigned long sys_size, unsigned long mem_bus, + unsigned long mem_phys, unsigned long mem_size, + unsigned long io_bus, unsigned long io_phys, + unsigned long io_size) +{ + static struct msc01_pci_controller global_msc01; + struct msc01_pci_controller *msc01; + struct pci_controller *hose; + + msc01 = &global_msc01; + msc01->base = base; + + hose = &msc01->hose; + + hose->first_busno = 0; + hose->last_busno = 0; + + /* System memory space */ + pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size, + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + + /* PCI memory space */ + pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size, + PCI_REGION_MEM); + + /* PCI I/O space */ + pci_set_region(&hose->regions[2], io_bus, io_phys, io_size, + PCI_REGION_IO); + + hose->region_count = 3; + + pci_set_ops(hose, + pci_hose_read_config_byte_via_dword, + pci_hose_read_config_word_via_dword, + msc01_read_config_dword, + pci_hose_write_config_byte_via_dword, + pci_hose_write_config_word_via_dword, + msc01_write_config_dword); + + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); +} diff --git a/include/configs/malta.h b/include/configs/malta.h index d067d98782..5e322f6ba6 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -17,6 +17,7 @@ #define CONFIG_PCI #define CONFIG_PCI_GT64120 +#define CONFIG_PCI_MSC01 #define CONFIG_PCI_PNP #define CONFIG_PCNET @@ -76,7 +77,8 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_UART_BASE) +#define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE) +#define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE) #define CONFIG_CONS_INDEX 1 /* diff --git a/include/msc01.h b/include/msc01.h new file mode 100644 index 0000000000..37cf963f13 --- /dev/null +++ b/include/msc01.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MSC01_H__ +#define __MSC01_H__ + +/* + * Bus Interface Unit + */ + +#define MSC01_BIU_IP1BAS1L_OFS 0x0208 +#define MSC01_BIU_IP1MSK1L_OFS 0x0218 +#define MSC01_BIU_IP1BAS2L_OFS 0x0248 +#define MSC01_BIU_IP1MSK2L_OFS 0x0258 +#define MSC01_BIU_IP2BAS1L_OFS 0x0288 +#define MSC01_BIU_IP2MSK1L_OFS 0x0298 +#define MSC01_BIU_IP2BAS2L_OFS 0x02c8 +#define MSC01_BIU_IP2MSK2L_OFS 0x02d8 +#define MSC01_BIU_IP3BAS1L_OFS 0x0308 +#define MSC01_BIU_IP3MSK1L_OFS 0x0318 +#define MSC01_BIU_IP3BAS2L_OFS 0x0348 +#define MSC01_BIU_IP3MSK2L_OFS 0x0358 +#define MSC01_BIU_MCBAS1L_OFS 0x0388 +#define MSC01_BIU_MCMSK1L_OFS 0x0398 +#define MSC01_BIU_MCBAS2L_OFS 0x03c8 +#define MSC01_BIU_MCMSK2L_OFS 0x03d8 + +/* + * PCI Bridge + */ + +#define MSC01_PCI_SC2PMBASL_OFS 0x0208 +#define MSC01_PCI_SC2PMMSKL_OFS 0x0218 +#define MSC01_PCI_SC2PMMAPL_OFS 0x0228 +#define MSC01_PCI_SC2PIOBASL_OFS 0x0248 +#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 +#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 +#define MSC01_PCI_P2SCMSKL_OFS 0x0308 +#define MSC01_PCI_P2SCMAPL_OFS 0x0318 +#define MSC01_PCI_INTSTAT_OFS 0x0608 +#define MSC01_PCI_CFGADDR_OFS 0x0610 +#define MSC01_PCI_CFGDATA_OFS 0x0618 +#define MSC01_PCI_HEAD0_OFS 0x2000 +#define MSC01_PCI_HEAD1_OFS 0x2008 +#define MSC01_PCI_HEAD2_OFS 0x2010 +#define MSC01_PCI_HEAD3_OFS 0x2018 +#define MSC01_PCI_HEAD4_OFS 0x2020 +#define MSC01_PCI_HEAD5_OFS 0x2028 +#define MSC01_PCI_HEAD6_OFS 0x2030 +#define MSC01_PCI_HEAD7_OFS 0x2038 +#define MSC01_PCI_HEAD8_OFS 0x2040 +#define MSC01_PCI_HEAD9_OFS 0x2048 +#define MSC01_PCI_HEAD10_OFS 0x2050 +#define MSC01_PCI_HEAD11_OFS 0x2058 +#define MSC01_PCI_HEAD12_OFS 0x2060 +#define MSC01_PCI_HEAD13_OFS 0x2068 +#define MSC01_PCI_HEAD14_OFS 0x2070 +#define MSC01_PCI_HEAD15_OFS 0x2078 +#define MSC01_PCI_BAR0_OFS 0x2220 +#define MSC01_PCI_CFG_OFS 0x2380 +#define MSC01_PCI_SWAP_OFS 0x2388 + +#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 +#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 + +#define MSC01_PCI_INTSTAT_TA_SHF 6 +#define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF) +#define MSC01_PCI_INTSTAT_MA_SHF 7 +#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF) + +#define MSC01_PCI_CFGADDR_BNUM_SHF 16 +#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF) +#define MSC01_PCI_CFGADDR_DNUM_SHF 11 +#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF) +#define MSC01_PCI_CFGADDR_FNUM_SHF 8 +#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF) +#define MSC01_PCI_CFGADDR_RNUM_SHF 2 +#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF) + +#define MSC01_PCI_HEAD0_VENDORID_SHF 0 +#define MSC01_PCI_HEAD0_DEVICEID_SHF 16 + +#define MSC01_PCI_HEAD2_REV_SHF 0 +#define MSC01_PCI_HEAD2_CLASS_SHF 16 + +#define MSC01_PCI_CFG_EN_SHF 15 +#define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF) +#define MSC01_PCI_CFG_G_SHF 16 +#define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF) +#define MSC01_PCI_CFG_RA_SHF 17 +#define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF) + +#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0 +#define MSC01_PCI_SWAP_IO_BSWAP_SHF 18 + +/* + * Peripheral Bus Controller + */ + +#define MSC01_PBC_CLKCFG_OFS 0x0100 +#define MSC01_PBC_CS0CFG_OFS 0x0400 +#define MSC01_PBC_CS0TIM_OFS 0x0500 +#define MSC01_PBC_CS0RW_OFS 0x0600 + +#define MSC01_PBC_CLKCFG_SHF 0 +#define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF) + +#define MSC01_PBC_CS0CFG_WS_SHF 0 +#define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF) +#define MSC01_PBC_CS0CFG_WSIDLE_SHF 8 +#define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF) +#define MSC01_PBC_CS0CFG_DTYP_SHF 16 +#define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF) +#define MSC01_PBC_CS0CFG_ADM_SHF 20 +#define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF) + +#define MSC01_PBC_CS0TIM_CAT_SHF 0 +#define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF) +#define MSC01_PBC_CS0TIM_CDT_SHF 8 +#define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF) + +#define MSC01_PBC_CS0RW_WAT_SHF 0 +#define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF) +#define MSC01_PBC_CS0RW_WDT_SHF 8 +#define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF) +#define MSC01_PBC_CS0RW_RAT_SHF 16 +#define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF) +#define MSC01_PBC_CS0RW_RDT_SHF 24 +#define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF) + +#endif /* __MSC01_H__ */ diff --git a/include/pci_ids.h b/include/pci_ids.h index 2c6dfd4044..6bab677449 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -2170,6 +2170,9 @@ #define PCI_DEVICE_ID_ENE_720 0x1421 #define PCI_DEVICE_ID_ENE_722 0x1422 +#define PCI_VENDOR_ID_MIPS 0x153f +#define PCI_DEVICE_ID_MIPS_MSC01 0x0001 + #define PCI_SUBVENDOR_ID_PERLE 0x155f #define PCI_SUBDEVICE_ID_PCI_RAS4 0xf001 #define PCI_SUBDEVICE_ID_PCI_RAS8 0xf010 diff --git a/include/pci_msc01.h b/include/pci_msc01.h new file mode 100644 index 0000000000..54945a7a8f --- /dev/null +++ b/include/pci_msc01.h @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCI_MSC01_H__ +#define __PCI_MSC01_H__ + +extern void msc01_pci_init(void *base, unsigned long sys_bus, + unsigned long sys_phys, unsigned long sys_size, + unsigned long mem_bus, unsigned long mem_phys, + unsigned long mem_size, unsigned long io_bus, + unsigned long io_phys, unsigned long io_size); + +#endif /* __PCI_MSC01_H__ */ -- cgit v1.2.1 From e0ada6319bb3eb8bc1f97c00f05508ac0cfffc34 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:51 +0000 Subject: malta: display "U-boot" on the LCD screen Displaying a message on the LCD screen is a simple yet effective way to show the user that the board has booted successfully. Signed-off-by: Paul Burton --- arch/mips/include/asm/malta.h | 10 ++++++++++ board/imgtec/malta/malta.c | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index 0b50a66e07..d8ec57cf48 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -32,6 +32,16 @@ #define MALTA_MSC01_PCIIO_MAP 0x00000000 #define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8) +#define MALTA_ASCIIWORD 0x1f000410 +#define MALTA_ASCIIPOS0 0x1f000418 +#define MALTA_ASCIIPOS1 0x1f000420 +#define MALTA_ASCIIPOS2 0x1f000428 +#define MALTA_ASCIIPOS3 0x1f000430 +#define MALTA_ASCIIPOS4 0x1f000438 +#define MALTA_ASCIIPOS5 0x1f000440 +#define MALTA_ASCIIPOS6 0x1f000448 +#define MALTA_ASCIIPOS7 0x1f000450 + #define MALTA_RESET_BASE 0x1f000500 #define GORESET 0x42 diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 2af00672da..119546ae16 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -29,6 +29,24 @@ enum sys_con { SYSCON_MSC01, }; +static void malta_lcd_puts(const char *str) +{ + int i; + void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); + + /* print up to 8 characters of the string */ + for (i = 0; i < min(strlen(str), 8); i++) { + __raw_writel(str[i], reg); + reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; + } + + /* fill the rest of the display with spaces */ + for (; i < 8; i++) { + __raw_writel(' ', reg); + reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; + } +} + static enum core_card malta_core_card(void) { u32 corid, rev; @@ -71,6 +89,7 @@ int checkboard(void) { enum core_card core; + malta_lcd_puts("U-boot"); puts("Board: MIPS Malta"); core = malta_core_card(); -- cgit v1.2.1 From e0878af8cdfd2178b3a1e3a3448dc75f4cf1b34c Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:52 +0000 Subject: malta: enable CONFIG_PCNET_79C973, PCNET_HAS_PROM, CONFIG_CMD_DHCP This model of the pcnet is used in current Malta boards, at least in the Malta-R rev 3. Enable support for it. The Malta also has the ethernet controller PROM containing its MAC address, so enable support for that in order to read that MAC address. DHCP is a very useful feature to have available for many networks, enable support for it also. Signed-off-by: Paul Burton --- include/configs/malta.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/malta.h b/include/configs/malta.h index 5e322f6ba6..6132ab8652 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -20,6 +20,8 @@ #define CONFIG_PCI_MSC01 #define CONFIG_PCI_PNP #define CONFIG_PCNET +#define CONFIG_PCNET_79C973 +#define PCNET_HAS_PROM /* * CPU Configuration @@ -107,6 +109,7 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_NFS +#define CONFIG_CMD_DHCP #define CONFIG_CMD_PCI #define CONFIG_CMD_PING -- cgit v1.2.1 From 14b4e1a63e580b1993866ec783d958619d485d9c Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:53 +0000 Subject: malta: remove cache size definitions These will now be detected at runtime, allowing a single U-boot configuration to function correctly with different bitstreams. Without this you may need to re-configure, re-build and re-flash U-boot to your Malta if you flash a new bitstream with a different cache configuration to your old bitstream. Signed-off-by: Paul Burton --- include/configs/malta.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/configs/malta.h b/include/configs/malta.h index 6132ab8652..ab5ba95e47 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -29,10 +29,6 @@ #define CONFIG_SYS_MHZ 250 /* arbitrary value */ #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) -#define CONFIG_SYS_DCACHE_SIZE 16384 /* arbitrary value */ -#define CONFIG_SYS_ICACHE_SIZE 16384 /* arbitrary value */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* arbitrary value */ - #define CONFIG_SWAP_IO_SPACE /* -- cgit v1.2.1 From e174bd74c93637e78eb81048891acd4ea61520a9 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:54 +0000 Subject: malta: disable L2 caches Malta boards may be used with cores which support L2 caches, however U-boot does not yet support L2 cache for MIPS. Thus for the moment we'll disable L2 caches by setting the L2B bit in Config2. This is specific to MTI/Imagination MIPS cores which is why this is done for the Malta board rather than generically. Signed-off-by: Paul Burton --- board/imgtec/malta/lowlevel_init.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S index 1af34f142f..ae09c27d07 100644 --- a/board/imgtec/malta/lowlevel_init.S +++ b/board/imgtec/malta/lowlevel_init.S @@ -12,6 +12,7 @@ #include #include #include +#include #ifdef CONFIG_SYS_BIG_ENDIAN #define CPU_TO_GT32(_x) ((_x)) @@ -27,6 +28,12 @@ .globl lowlevel_init lowlevel_init: + /* disable any L2 cache for now */ + sync + mfc0 t0, CP0_CONFIG, 2 + ori t0, t0, 0x1 << 12 + mtc0 t0, CP0_CONFIG, 2 + /* detect the core card */ li t0, KSEG1ADDR(MALTA_REVISION) lw t0, 0(t0) -- cgit v1.2.1 From 3ced12a06baaf90039fa171688d33358b15613d1 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:55 +0000 Subject: malta: enable RTC support This is actually required in order for a Linux kernel to boot successfully on a physical Malta board. Without enabling the RTC, a Malta Linux kernel will get stuck in its estimate_frequencies function on boot. Signed-off-by: Paul Burton --- board/imgtec/malta/malta.c | 8 ++++++++ drivers/rtc/mc146818.c | 2 +- include/configs/malta.h | 5 +++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 119546ae16..2f92259756 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include @@ -147,6 +148,13 @@ int board_early_init_f(void) return 0; } +int misc_init_r(void) +{ + rtc_reset(); + + return 0; +} + struct serial_device *default_serial_console(void) { switch (malta_sys_con()) { diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 5f9d359590..f7cf1064f9 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -15,7 +15,7 @@ #include #include -#ifdef __I386__ +#if defined(__I386__) || defined(CONFIG_MALTA) #include #define in8(p) inb(p) #define out8(p, v) outb(v, p) diff --git a/include/configs/malta.h b/include/configs/malta.h index ab5ba95e47..a0f6a4a7e9 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -23,6 +23,10 @@ #define CONFIG_PCNET_79C973 #define PCNET_HAS_PROM +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_MC146818 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 + /* * CPU Configuration */ @@ -105,6 +109,7 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_NFS +#define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_PCI #define CONFIG_CMD_PING -- cgit v1.2.1 From fba6f45cdcf77985c4bf891322b5442bda1005e0 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:56 +0000 Subject: malta: store environment in flash Allow the environment to be stored in the monitor flash of a Malta board. The environment is stored in the final 128KB of the flash, which both leaves the majority of the flash available for U-boot code and also matches the location which YAMON uses. Signed-off-by: Paul Burton --- include/configs/malta.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/include/configs/malta.h b/include/configs/malta.h index a0f6a4a7e9..b58b6e4a5f 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -83,12 +83,6 @@ #define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE) #define CONFIG_CONS_INDEX 1 -/* - * Environment - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_ENV_SIZE 0x10000 - /* * Flash configuration */ @@ -99,6 +93,15 @@ #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) + /* * Commands */ -- cgit v1.2.1 From 81f98bbd62b66e4a590fe6fe9b0d8231e45beffd Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:57 +0000 Subject: malta: setup PIIX4 interrupt route Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will be left disabled. Linux does not set up this routing but relies upon it having been set up by the bootloader, reading back the IRQ lines which the PIRQ[A:D] signals have been routed to. This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11. This matches the setup used by YAMON. Signed-off-by: Paul Burton --- arch/mips/include/asm/malta.h | 5 +++++ board/imgtec/malta/malta.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index d8ec57cf48..e141eb0ae5 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -53,4 +53,9 @@ #define MALTA_REVISION_CORID_CORE_LV 1 #define MALTA_REVISION_CORID_CORE_FPGA6 14 +#define PCI_CFG_PIIX4_PIRQRCA 0x60 +#define PCI_CFG_PIIX4_PIRQRCB 0x61 +#define PCI_CFG_PIIX4_PIRQRCC 0x62 +#define PCI_CFG_PIIX4_PIRQRCD 0x63 + #endif /* _MIPS_ASM_MALTA_H */ diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 2f92259756..a1a4c01866 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -169,6 +170,8 @@ struct serial_device *default_serial_console(void) void pci_init_board(void) { + pci_dev_t bdf; + switch (malta_sys_con()) { case SYSCON_GT64120: set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); @@ -191,4 +194,15 @@ void pci_init_board(void) 0x00000000, MALTA_MSC01_PCIIO_SIZE); break; } + + bdf = pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB_0, 0); + if (bdf == -1) + panic("Failed to find PIIX4 PCI bridge\n"); + + /* setup PCI interrupt routing */ + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); + pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); } -- cgit v1.2.1 From 024fba5458733a0cb268f3550b16358e104620f7 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:58 +0000 Subject: malta: add script & instructions to flash U-boot This patch adds a script which may be used with MIPS Navigator Console and a MIPS Nagivator Probe in order to flash U-boot to a MIPS Malta development board. Please see the newly added doc/README.malta for usage instructions. Signed-off-by: Paul Burton --- board/imgtec/malta/flash-malta-boot.tcl | 40 +++++++++++++++++++++++++++++++++ doc/README.malta | 16 +++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 board/imgtec/malta/flash-malta-boot.tcl create mode 100644 doc/README.malta diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl new file mode 100644 index 0000000000..0eedf07ace --- /dev/null +++ b/board/imgtec/malta/flash-malta-boot.tcl @@ -0,0 +1,40 @@ +# +# Copyright (C) 2013 Imagination Technologies +# +# Programs a MIPS Malta boot flash with a flat binary image. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +proc flash-boot { binfile } { + puts "flash monitor binary $binfile" + config Coherent on + config CoherencyDuringLoad on + + if {[endian]=="big"} { + puts "CPU in BE mode" + flash device sharp_16x32_be; + } else { + puts "CPU in LE mode" + flash device sharp_16x32; + } + + flash clear all; + flash set 0xBE000000..0xBE0FFFFF + flash erase sector 0xbe000000; + flash erase sector 0xbe020000; + flash erase sector 0xbe040000; + flash erase sector 0xbe060000; + flash erase sector 0xbe080000; + flash erase sector 0xbe0a0000; + flash erase sector 0xbe0c0000; + flash erase sector 0xbe0e0000; + puts "finished erasing boot flash"; + + puts "programming flash, please be patient" + load bin 0xbe000000 $binfile size4 + + flash clear all + config CoherencyDuringLoad off + puts "finished programming boot flash"; +} diff --git a/doc/README.malta b/doc/README.malta new file mode 100644 index 0000000000..a495d02455 --- /dev/null +++ b/doc/README.malta @@ -0,0 +1,16 @@ +MIPS Malta board + +How to flash using a MIPS Navigator Probe: + + - Ensure that your Malta has jumper JP1 fitted. Without this jumper you will + be unable to flash your Malta using a Navigator Probe. + + - Connect Navigator Console to your probe and Malta as usual. + + - Within Navigator Console run the following commands: + + source /path/to/u-boot/board/malta/flash-malta-boot.tcl + reset + flash-boot /path/to/u-boot/u-boot.bin + + - You should now be able to reboot your Malta to a U-boot shell. -- cgit v1.2.1 From f577b42f3304712497e8a7c9a57e0f0e95196071 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Fri, 8 Nov 2013 11:18:59 +0000 Subject: malta: add myself to maintainers This patch adds me as a maintainer of the malta(el) board(s). I have access to physical Malta boards and the desire for U-boot to run well on them. Signed-off-by: Paul Burton --- boards.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards.cfg b/boards.cfg index d4b6e53c55..022392a9ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -482,8 +482,8 @@ Active m68k mcf547x_8x - freescale m548xevb Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - -Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN - -Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN - +Active mips mips32 - imgtec malta malta malta:MIPS32,SYS_BIG_ENDIAN Paul Burton +Active mips mips32 - imgtec malta maltael malta:MIPS32,SYS_LITTLE_ENDIAN Paul Burton Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM - Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND - Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - -- cgit v1.2.1 From ab41305d3b7c1afa29c0b7fafce854c24445423a Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Thu, 24 Oct 2013 14:32:00 +0200 Subject: malta: define CONFIG_MEMSIZE_IN_BYTES The memsize environment variable must contain the memory size in bytes on the Malta board. Otherwise Linux will use wrong memory size which causes a kernel panic. Define CONFIG_MEMSIZE_IN_BYTES in malta.h to avoid that. Signed-off-by: Gabor Juhos Cc: Daniel Schwierzeck Cc: Paul Burton --- include/configs/malta.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/malta.h b/include/configs/malta.h index b58b6e4a5f..4098e724fe 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -15,6 +15,8 @@ */ #define CONFIG_MALTA +#define CONFIG_MEMSIZE_IN_BYTES + #define CONFIG_PCI #define CONFIG_PCI_GT64120 #define CONFIG_PCI_MSC01 -- cgit v1.2.1 From a3e80904fb07cda792e636704e3b3950d1446af3 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Mon, 11 Nov 2013 11:03:26 +0000 Subject: malta: arch/mips/include/asm/malta.h SPDX license tag This patch replaces the GPL-2.0 text with a GPL-2.0 SPDX-License-Identifier tag, and adds Imagination Technologies copyright following my recent changes. Signed-off-by: Paul Burton --- arch/mips/include/asm/malta.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index e141eb0ae5..9b1100bc49 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -1,9 +1,8 @@ /* * Copyright (C) 2013 Gabor Juhos + * Copyright (C) 2013 Imagination Technologies * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _MIPS_ASM_MALTA_H -- cgit v1.2.1 From d770f3961f44295509ad23b7f056d9a37b947601 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Sat, 9 Nov 2013 00:30:14 +0100 Subject: time: fix gcc warnings on MIPS64 Commit 8dfafdde88eb3e71d5569846396ae67a91017232 introduced new gcc warnings on MIPS64: time.c: In function 'tick_to_time': time.c:59:2: warning: comparison of distinct pointer types lacks a cast [enabled by default] time.c:59:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default] In file included from time.c:10:0: ./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *' time.c: In function 'usec_to_tick': time.c:76:2: warning: comparison of distinct pointer types lacks a cast [enabled by default] time.c:76:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default] In file included from time.c:10:0: ./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *' Signed-off-by: Daniel Schwierzeck --- lib/time.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/time.c b/lib/time.c index 111b493a42..09bb05a24d 100644 --- a/lib/time.c +++ b/lib/time.c @@ -51,7 +51,7 @@ unsigned long long __weak notrace get_ticks(void) return ((unsigned long long)gd->timebase_h << 32) | gd->timebase_l; } -static unsigned long long notrace tick_to_time(unsigned long long tick) +static unsigned long long notrace tick_to_time(uint64_t tick) { unsigned int div = get_tbclk(); @@ -71,7 +71,7 @@ unsigned long __weak notrace timer_get_us(void) } static unsigned long long usec_to_tick(unsigned long usec) { - unsigned long long tick = usec * get_tbclk(); + uint64_t tick = usec * get_tbclk(); usec *= get_tbclk(); do_div(tick, 1000000); return tick; -- cgit v1.2.1 From 649acfe149e8a534a17eab54004a51d69b5556ed Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 11 Nov 2013 20:12:19 +0100 Subject: MPC824x: remove obsolete "PN62" board The MPC824x processors have long reached EOL, and the PN62 board has not seen any board-specific updates for more than a decade. It is now causing build issues. Instead of wasting time on things nobody is interested in any more, we rather drop this board. Signed-off-by: Wolfgang Denk Cc: Wolfgang Grandegger cc: Tom Rini --- CREDITS | 2 +- arch/powerpc/cpu/mpc824x/cpu_init.c | 6 +- board/pn62/Makefile | 8 - board/pn62/cmd_pn62.c | 146 ------------------ board/pn62/misc.c | 219 --------------------------- board/pn62/pn62.c | 171 ---------------------- board/pn62/pn62.h | 145 ------------------ boards.cfg | 1 - doc/README.scrapyard | 1 + drivers/net/pcnet.c | 10 -- include/configs/PN62.h | 285 ------------------------------------ 11 files changed, 4 insertions(+), 990 deletions(-) delete mode 100644 board/pn62/Makefile delete mode 100644 board/pn62/cmd_pn62.c delete mode 100644 board/pn62/misc.c delete mode 100644 board/pn62/pn62.c delete mode 100644 board/pn62/pn62.h delete mode 100644 include/configs/PN62.h diff --git a/CREDITS b/CREDITS index 3b657e9005..52f289e06a 100644 --- a/CREDITS +++ b/CREDITS @@ -143,7 +143,7 @@ W: www.freescale.com N: Dr. Wolfgang Grandegger E: wg@denx.de -D: Support for Interphase 4539 T1/E1/J1 PMC, PN62, CCM, SCM boards +D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards W: www.denx.de N: Peter Figuli diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c index 37d796e635..47ac18e757 100644 --- a/arch/powerpc/cpu/mpc824x/cpu_init.c +++ b/arch/powerpc/cpu/mpc824x/cpu_init.c @@ -52,7 +52,7 @@ cpu_init_f (void) CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/ /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/ -#if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62) +#if defined(CONFIG_MUSENKI) /* Why is this here, you ask? Try, just try setting 0x8000 * in PCIACR with CONFIG_WRITE_HALFWORD() * this one was a stumper, and we are annoyed @@ -142,9 +142,7 @@ cpu_init_f (void) CONFIG_READ_WORD(PICR2, val); val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/ -#ifndef CONFIG_PN62 val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/ -#endif CONFIG_WRITE_WORD(PICR2, val); CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR); @@ -186,7 +184,7 @@ cpu_init_f (void) * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if * its not set, we define it to zero in this file */ -#if defined(CONFIG_CU824) || defined(CONFIG_PN62) +#if defined(CONFIG_CU824) CONFIG_WRITE_WORD(MCCR4, (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | diff --git a/board/pn62/Makefile b/board/pn62/Makefile deleted file mode 100644 index 7572ed8610..0000000000 --- a/board/pn62/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = pn62.o cmd_pn62.o misc.o diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c deleted file mode 100644 index a0326b40d6..0000000000 --- a/board/pn62/cmd_pn62.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include "pn62.h" - -#if defined(CONFIG_CMD_BSP) - -/* - * Command led: controls the various LEDs 0..11 on the PN62 card. - */ -int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[]) -{ - unsigned int number, function; - - if (argc != 3) - return cmd_usage(cmdtp); - - number = simple_strtoul(argv[1], NULL, 10); - if (number > PN62_LED_MAX) - return 1; - - function = simple_strtoul(argv[2], NULL, 16); - set_led(number, function); - return 0; -} -U_BOOT_CMD( - led , 3, 1, do_led, - "set LED 0..11 on the PN62 board", - "i fun" - " - set 'i'th LED to function 'fun'" -); - -/* - * Command loadpci: loads a image over PCI. - */ -#define CMD_MOVE_WINDOW 0x1 -#define CMD_BOOT_IMAGE 0x2 - -int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - char *s; - ulong addr = 0, count = 0; - u32 off; - int cmd, rcode = 0; - - /* pre-set load_addr */ - if ((s = getenv("loadaddr")) != NULL) { - addr = simple_strtoul(s, NULL, 16); - } - - switch (argc) { - case 1: - break; - case 2: - addr = simple_strtoul(argv[1], NULL, 16); - break; - default: - return cmd_usage(cmdtp); - } - - printf ("## Ready for image download ...\n"); - - show_startup_phase(12); - - while (1) { - /* Alive indicator */ - i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY); - - /* Toggle status LEDs */ - cmd = (count / 200) % 4; /* downscale */ - set_led(4, cmd == 0 ? LED_1 : LED_0); - set_led(5, cmd == 1 ? LED_1 : LED_0); - set_led(6, cmd == 2 ? LED_1 : LED_0); - set_led(7, cmd == 3 ? LED_1 : LED_0); - udelay(1000); - count++; - - cmd = i2155x_read_scrapad(BOOT_CMD); - - if (cmd == BOOT_CMD_MOVE) { - off = i2155x_read_scrapad(BOOT_DATA); - off += addr; - i2155x_set_bar_base(3, off); - printf ("## BAR3 Addr moved = 0x%08x\n", off); - i2155x_write_scrapad(BOOT_CMD, ~cmd); - show_startup_phase(13); - } - else if (cmd == BOOT_CMD_BOOT) { - set_led(4, LED_1); - set_led(5, LED_1); - set_led(6, LED_1); - set_led(7, LED_1); - - i2155x_write_scrapad(BOOT_CMD, ~cmd); - show_startup_phase(14); - break; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - printf("\nAbort\n"); - return 0; - } - - } - - /* Repoint to the default shared memory */ - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); - - load_addr = addr; - printf ("## Start Addr = 0x%08lx\n", addr); - - show_startup_phase(15); - - /* Loading ok, check if we should attempt an auto-start */ - if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) { - char *local_args[2]; - local_args[0] = argv[0]; - local_args[1] = NULL; - - printf ("Automatic boot of image at addr 0x%08lX ...\n", - load_addr); - rcode = do_bootm (cmdtp, 0, 1, local_args); - } - - return rcode; -} - -U_BOOT_CMD( - loadpci, 2, 1, do_loadpci, - "load binary file over PCI", - "[addr]\n" - " - load binary file over PCI to address 'addr'" -); - -#endif diff --git a/board/pn62/misc.c b/board/pn62/misc.c deleted file mode 100644 index 98e0dfa518..0000000000 --- a/board/pn62/misc.c +++ /dev/null @@ -1,219 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include "pn62.h" - -typedef struct { - pci_dev_t devno; - volatile u32 *csr; - -} i2155x_t; - -static i2155x_t i2155x = { 0, NULL }; - -static struct pci_device_id i2155x_ids[] = { - { 0x1011, 0x0046 }, /* i21554 */ - { 0x8086, 0xb555 } /* i21555 */ -}; - -int i2155x_init(void) -{ - pci_dev_t devno; - u32 val; - int i; - - /* - * Find the Intel bridge. - */ - if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) { - printf("Error: Intel bridge 2155x not found!\n"); - return -1; - } - i2155x.devno = devno; - - /* - * Get auto-configured base address for CSR access. - */ - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val); - if (val & PCI_BASE_ADDRESS_SPACE_IO) { - val &= PCI_BASE_ADDRESS_IO_MASK; - i2155x.csr = (volatile u32 *)(_IO_BASE + val); - } else { - val &= PCI_BASE_ADDRESS_MEM_MASK; - i2155x.csr = (volatile u32 *)val; - } - - /* - * Translate downstream memory 2 (bar3) to base of shared memory. - */ - i2155x_set_bar_base(3, PN62_SMEM_DEFAULT); - - /* - * Enable memory space, I/O space and bus master bits - * in both Primary and Secondary command registers. - */ - val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO; - pci_write_config_word(devno, 0x44, val); - pci_write_config_word(devno, 0x04, val); - - /* - * Clear scratchpad registers. - */ - for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) { - i2155x_write_scrapad(i, 0x0); - } - - /* - * Set interrupt line for Linux. - */ - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3); - - return 0; -} - -/* - * Access the Scratchpad registers 0..7 of the Intel bridge. - */ -void i2155x_write_scrapad(int idx, u32 val) -{ - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) - out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val); - else - printf("i2155x_write_scrapad: invalid index\n"); -} - -u32 i2155x_read_scrapad(int idx) -{ - if (idx >= 0 && idx < I2155X_SCRAPAD_MAX) - return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx); - else - printf("i2155x_read_scrapad: invalid index\n"); - return -1; -} - -void i2155x_set_bar_base(int bar, u32 base) -{ - if (bar >= 2 && bar <= 4) { - pci_write_config_dword(i2155x.devno, - I2155X_BAR2_BASE + (bar - 2) * 4, - base); - } -} - -/* - * Read Vital Product Data (VPD) from the Serial EPROM attached - * to the Intel bridge. - */ -int i2155x_read_vpd(int offset, int size, unsigned char *data) -{ - int i, n; - u16 val16; - - for (i = 0; i < size; i++) { - pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR, - offset + i - I2155X_VPD_START); - for (n = 10000; n > 0; n--) { - pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16); - if ((val16 & 0x8000) != 0) /* wait for completion */ - break; - udelay(100); - } - if (n == 0) { - printf("i2155x_read_vpd: TIMEOUT\n"); - return -1; - } - - pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]); - } - - return i; -} - -static struct pci_device_id am79c95x_ids [] = { - { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE }, - { } -}; - - -/* - * Initialize the AMD ethernet controllers. - */ -int am79c95x_init(void) -{ - pci_dev_t devno; - int i; - - /* - * Set interrupt line for Linux. - */ - for (i = 0; i < 2; i++) { - if ((devno = pci_find_devices(am79c95x_ids, i)) < 0) - break; - pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i); - } - if (i < 2) - printf("Error: Only %d AMD Ethernet Controller found!\n", i); - - return 0; -} - - -void set_led(unsigned int number, unsigned int function) -{ - volatile u8 *addr; - - if ((number >= 0) && (number < PN62_LED_MAX) && - (function >= 0) && (function <= LED_LAST_FUNCTION)) { - addr = (volatile u8 *)(PN62_LED_BASE + number * 8); - out_8(addr, function&0xff); - } -} - -/* - * Show fatal error indicated by Kinght Rider(tm) effect - * in LEDS 0-7. LEDS 8-11 contain 4 bit error code. - * Note: this function will not terminate. - */ -void fatal_error(unsigned int error_code) -{ - int i, d; - - for (i = 0; i < 12; i++) { - set_led(i, LED_0); - } - - /* - * Write error code. - */ - set_led(8, (error_code & 0x01) ? LED_1 : LED_0); - set_led(9, (error_code & 0x02) ? LED_1 : LED_0); - set_led(10, (error_code & 0x04) ? LED_1 : LED_0); - set_led(11, (error_code & 0x08) ? LED_1 : LED_0); - - /* - * Yay - Knight Rider effect! - */ - while(1) { - unsigned int delay = 2000; - - for (i = 0; i < 8; i++) { - set_led(i, LED_1); - for (d = 0; d < delay; d++); - set_led(i, LED_0); - } - - for (i = 7; i > 0; i--) { - set_led(i, LED_1); - for (d = 0; d < delay; d++); - set_led(i, LED_0); - } - } -} diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c deleted file mode 100644 index 81829dd75f..0000000000 --- a/board/pn62/pn62.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#include "pn62.h" - -DECLARE_GLOBAL_DATA_PTR; - -static int get_serial_number (char *string, int size); -static void get_mac_address(int id, u8 *mac); - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int phase) -{ - /* - * Show phases of the bootm command on the front panel - * LEDs and the scratchpad register #3 as well. We use - * blinking LEDs for logical "1". - */ - if (phase > 0) { - set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0); - set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0); - set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0); - set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0); - } - i2155x_write_scrapad (BOOT_STATUS, phase); - if (phase < 0) - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); -} -#endif - -void show_startup_phase (int phase) -{ - /* - * Show the phase of U-Boot startup on the front panel - * LEDs and the scratchpad register #3 as well. - */ - if (phase > 0) { - set_led (8, (phase & 0x1) ? LED_1 : LED_0); - set_led (9, (phase & 0x2) ? LED_1 : LED_0); - set_led (10, (phase & 0x4) ? LED_1 : LED_0); - set_led (11, (phase & 0x8) ? LED_1 : LED_0); - } - i2155x_write_scrapad (BOOT_STATUS, phase); - if (phase < 0) - i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR); -} - -int checkboard (void) -{ - show_startup_phase (1); - puts ("Board: PN62\n"); - return 0; -} - -phys_size_t initdram (int board_type) -{ - long size; - long new_bank0_end; - long mear1; - long emear1; - - show_startup_phase (2); - - size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE); - - new_bank0_end = size - 1; - mear1 = mpc824x_mpc107_getreg (MEAR1); - emear1 = mpc824x_mpc107_getreg (EMEAR1); - mear1 = (mear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT); - emear1 = (emear1 & 0xFFFFFF00) | - ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT); - mpc824x_mpc107_setreg (MEAR1, mear1); - mpc824x_mpc107_setreg (EMEAR1, emear1); - - return (size); -} - -/* - * Initialize PCI Devices. We rely on auto-configuration. - */ -#ifndef CONFIG_PCI_PNP -#error "CONFIG_PCI_PNP is not defined, please correct!" -#endif - -struct pci_controller hose = { -}; - -void pci_init_board (void) -{ - show_startup_phase (4); - pci_mpc824x_init (&hose); - - show_startup_phase (5); - i2155x_init (); - show_startup_phase (6); - am79c95x_init (); - show_startup_phase (7); -} - -int misc_init_r (void) -{ - char str[20]; - u8 mac[6]; - - show_startup_phase (8); - /* - * Get serial number and ethernet addresses if not already defined - * and update the board info structure and the environment. - */ - if (getenv ("serial#") == NULL && - get_serial_number (str, strlen (str)) > 0) { - setenv ("serial#", str); - } - show_startup_phase (9); - - if (!eth_getenv_enetaddr("ethaddr", mac)) { - get_mac_address(0, mac); - eth_setenv_enetaddr("ethaddr", mac); - } - show_startup_phase (10); - -#ifdef CONFIG_HAS_ETH1 - if (!eth_getenv_enetaddr("eth1addr", mac)) { - get_mac_address(1, mac); - eth_setenv_enetaddr("eth1addr", mac); - } -#endif /* CONFIG_HAS_ETH1 */ - show_startup_phase (11); - - /* Tell everybody that U-Boot is up and runnig */ - i2155x_write_scrapad (0, 0x12345678); - return (0); -} - -static int get_serial_number (char *string, int size) -{ - int i; - char c; - - if (size < I2155X_VPD_SN_SIZE) - size = I2155X_VPD_SN_SIZE; - for (i = 0; i < (size - 1); i++) { - i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c); - if (c == '\0') - break; - string[i] = c; - } - string[i] = '\0'; /* make sure it's terminated */ - - return i; -} - -static void get_mac_address(int id, u8 *mac) -{ - i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac); -} - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h deleted file mode 100644 index 10290c3142..0000000000 --- a/board/pn62/pn62.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2002 Wolfgang Grandegger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PN62_H_ -#define _PN62_H_ - -/* - * Definitions for the Intel Bridge 21554 or 21555. - */ -#define I2155X_VPD_ADDR 0xe6 -#define I2155X_VPD_DATA 0xe8 - -#define I2155X_VPD_START 0x80 -#define I2155X_VPD_SN_START 0x80 -#define I2155X_VPD_SN_SIZE 0x10 -#define I2155X_VPD_MAC0_START 0x90 -#define I2155X_VPD_MAC1_START 0x96 - -#define I2155X_SCRAPAD_ADDR 0xa8 -#define I2155X_SCRAPAD_MAX 8 - -#define I2155X_BAR2_BASE 0x98 -#define I2155X_BAR3_BASE 0x9c -#define I2155X_BAR4_BASE 0xa0 - -#define I2155X_BAR2_SETUP 0xb0 -#define I2155X_BAR3_SETUP 0xb4 -#define I2155X_BAR4_SETUP 0xb8 - -/* - * Interrupt request numbers - */ -#define PN62_IRQ_HOST 0x0 -#define PN62_IRQ_PLX9054 0x1 -#define PN62_IRQ_ETH0 0x2 -#define PN62_IRQ_ETH1 0x3 -#define PN62_IRQ_COM1 0x4 -#define PN62_IRQ_COM2 0x4 - -/* - * Miscellaneous definitons. - */ -#define PN62_SMEM_DEFAULT 0x1f00000 - -/* - * Definitions for boot protocol using Scratchpad registers. - */ -#define BOOT_DONE 0 -#define BOOT_DONE_CLEAR 0x00dead00 -#define BOOT_DONE_ERROR 0xbad0dead -#define BOOT_DONE_U_BOOT 0x12345678 -#define BOOT_DONE_LINUX 0x87654321 -#define BOOT_CMD 1 -#define BOOT_CMD_MOVE 0x1 -#define BOOT_CMD_BOOT 0x2 -#define BOOT_DATA 2 -#define BOOT_PROTO 3 -#define BOOT_PROTO_READY 0x23456789 -#define BOOT_PROTO_CLEAR 0x00000000 -#define BOOT_STATUS 4 - -/* - * LED Definitions: - */ -#define PN62_LED_BASE 0xff800300 -#define PN62_LED_MAX 12 - -/* - * LED0 - 7 mounted on top of board, D1 - D8 - * LED8 - 11 upper four LEDs on the front panel of the board. - */ -#define LED_0 0x00 /* OFF */ -#define LED_1 0x01 /* ON */ -#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */ -#define LED_nSLOW_CLOCK 0x03 /* inverse of above */ -#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */ -#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */ - -/* - * LED's currently setup in AMD79C973 device as the following: - * LED0 100Mbit - * LED1 LNKSE - * LED2 TX Activity - * LED3 RX Activity - */ -#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */ -#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */ -#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */ -#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */ -#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */ -#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */ -#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */ -#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */ -#define LED_STROBE0 0x10 /* Processor Strobe 0 */ -#define LED_STROBE1 0x11 /* Processor Strobe 1 */ -#define LED_STROBE2 0x12 /* Processor Strobe 2 */ -#define LED_STROBE3 0x13 /* Processor Strobe 3 */ -#define LED_STROBE4 0x14 /* Processor Strobe 4 */ -#define LED_STROBE5 0x15 /* Processor Strobe 5 */ -#define LED_STROBE6 0x16 /* Processor Strobe 6 */ -#define LED_STROBE7 0x17 /* Processor Strobe 7 */ -#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */ -#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */ -#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */ -#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */ -#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */ -#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */ -#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */ -#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */ -#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */ -#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */ -#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */ -#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */ -#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */ -#define LED_UART0_CS 0x25 /* UART 0 Chip Select */ -#define LED_UART1_CS 0x26 /* UART 1 Chip Select */ -#define LED_SRAM_CS 0x27 /* SRAM Chip Select */ -#define LED_SRAM_WR 0x28 /* SRAM WR Signal */ -#define LED_SRAM_RD 0x29 /* SRAM RD Signal */ -#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */ -#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */ -#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */ -#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */ -#define LED_LAST_FUNCTION LED_HOST_INT /* last function */ - -/* - * Forward declarations - */ -int i2155x_init (void); -void i2155x_write_scrapad(int idx, u32 val); -u32 i2155x_read_scrapad (int idx); -void i2155x_set_bar_base (int bar, u32 addr); -int i2155x_read_vpd (int offset, int size, unsigned char *data); - -int am79c95x_init (void); - -void set_led (unsigned int number, unsigned int function); -void fatal_error (unsigned int error_code); -void show_startup_phase (int phase); - - -#endif /* _PN62_H_ */ diff --git a/boards.cfg b/boards.cfg index 7ee63ee3c0..caba64e432 100644 --- a/boards.cfg +++ b/boards.cfg @@ -632,7 +632,6 @@ Active powerpc mpc824x - - hidden_dragon Active powerpc mpc824x - - linkstation linkstation_HGLAN linkstation:HGLAN=1 Guennadi Liakhovetski Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson Active powerpc mpc824x - - mvblue MVBLUE - - -Active powerpc mpc824x - - pn62 PN62 - Wolfgang Grandegger Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson Active powerpc mpc824x - etin - debris - Sangmoon Kim diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 8ed09c7103..c3182e4d90 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger pdnb3 arm ixp - 2013-09-24 Stefan Roese scpu arm ixp - 2013-09-24 Stefan Roese omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 5b248bee43..71a3110712 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -291,16 +291,6 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) /* Switch pcnet to 32bit mode */ pcnet_write_bcr(dev, 20, 2); -#ifdef CONFIG_PN62 - /* Setup LED registers */ - val = pcnet_read_bcr(dev, 2) | 0x1000; - pcnet_write_bcr(dev, 2, val); /* enable LEDPE */ - pcnet_write_bcr(dev, 4, 0x5080); /* 100MBit */ - pcnet_write_bcr(dev, 5, 0x40c0); /* LNKSE */ - pcnet_write_bcr(dev, 6, 0x4090); /* TX Activity */ - pcnet_write_bcr(dev, 7, 0x4084); /* RX Activity */ -#endif - /* Set/reset autoselect bit */ val = pcnet_read_bcr(dev, 2) & ~2; val |= 2; diff --git a/include/configs/PN62.h b/include/configs/PN62.h deleted file mode 100644 index 2a82f94b65..0000000000 --- a/include/configs/PN62.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC824X 1 -#define CONFIG_MPC8240 1 -#define CONFIG_PN62 1 - -#define CONFIG_SYS_TEXT_BASE 0xFFF00000 - -#define CONFIG_CONS_INDEX 1 - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_PCI -#define CONFIG_CMD_BSP - -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_SOURCE - - -#define CONFIG_BAUDRATE 19200 /* console baudrate */ - -#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */ - -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - -#define CONFIG_SERVERIP 10.0.0.201 -#define CONFIG_IPADDR 10.0.0.200 -#define CONFIG_ROOTPATH "/opt/eldk/ppc_82xx" -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_BOOTARGS -#if 0 -/* Boot Linux with NFS root filesystem */ -#define CONFIG_BOOTCOMMAND \ - "setenv verify y;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ - "loadp 100000; bootm" - /* "tftpboot 100000 uImage; bootm" */ -#else -/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */ -#define CONFIG_BOOTCOMMAND \ - "setenv verify n;" \ - "setenv bootargs console=ttyS0,19200 mem=31M quiet " \ - "root=/dev/ram rw " \ - "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \ - "loadp 200000; bootm" -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ - -#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */ - -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */ - -#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -/* - * PCI stuff - */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCI_PNP /* we need Plug 'n Play */ -#if 0 -#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */ -#endif - -/* - * Networking stuff - */ - -#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */ -#define CONFIG_PCNET_79C973 - -#define _IO_BASE 0xfe000000 /* points to PCI I/O space */ - - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - -#undef CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_MONITOR_LEN 0x00030000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - - -#define CONFIG_SYS_NO_FLASH 1 /* There is no FLASH memory */ - -#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */ - -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */ - -/* - * Serial port configuration - */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_NS16550_CLK 1843200 - -#define CONFIG_SYS_NS16550_COM1 0xff800008 -#define CONFIG_SYS_NS16550_COM2 0xff800000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3 - -#define CONFIG_SYS_EUMB_ADDR 0xFCE00000 - -/* MCCR1 */ -#define CONFIG_SYS_ROMNAL 3 /* rom/flash next access time */ -#define CONFIG_SYS_ROMFAL 7 /* rom/flash access time */ - -/* MCCR2 */ -#define CONFIG_SYS_ASRISE 6 /* ASRISE in clocks */ -#define CONFIG_SYS_ASFALL 12 /* ASFALL in clocks */ -#define CONFIG_SYS_REFINT 5600 /* REFINT in clocks */ - -/* MCCR3 */ -#define CONFIG_SYS_BSTOPRE 0x3cf /* Burst To Precharge */ -#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */ -#define CONFIG_SYS_RDLAT 3 /* data latency from read command */ - -/* MCCR4 */ -#define CONFIG_SYS_PRETOACT 1 /* Precharge to activate interval */ -#define CONFIG_SYS_ACTTOPRE 3 /* Activate to Precharge interval */ -#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */ -#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */ -#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE Wrap type */ -#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */ -#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 - -/* Memory bank settings: - * - * only bits 20-29 are actually used from these vales to set the - * start/qend address the upper two bits will be 0, and the lower 20 - * bits will be set to 0x00000 for a start address, or 0xfffff for an - * end address - */ -#define CONFIG_SYS_BANK0_START 0x00000000 -#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) -#define CONFIG_SYS_BANK0_ENABLE 1 -#define CONFIG_SYS_BANK1_START 0x00000000 -#define CONFIG_SYS_BANK1_END 0x00000000 -#define CONFIG_SYS_BANK1_ENABLE 0 -#define CONFIG_SYS_BANK2_START 0x00000000 -#define CONFIG_SYS_BANK2_END 0x00000000 -#define CONFIG_SYS_BANK2_ENABLE 0 -#define CONFIG_SYS_BANK3_START 0x00000000 -#define CONFIG_SYS_BANK3_END 0x00000000 -#define CONFIG_SYS_BANK3_ENABLE 0 -#define CONFIG_SYS_BANK4_START 0x00000000 -#define CONFIG_SYS_BANK4_END 0x00000000 -#define CONFIG_SYS_BANK4_ENABLE 0 -#define CONFIG_SYS_BANK5_START 0x00000000 -#define CONFIG_SYS_BANK5_END 0x00000000 -#define CONFIG_SYS_BANK5_ENABLE 0 -#define CONFIG_SYS_BANK6_START 0x00000000 -#define CONFIG_SYS_BANK6_END 0x00000000 -#define CONFIG_SYS_BANK6_ENABLE 0 -#define CONFIG_SYS_BANK7_START 0x00000000 -#define CONFIG_SYS_BANK7_END 0x00000000 -#define CONFIG_SYS_BANK7_ENABLE 0 - -/* - * Memory bank enable bitmask, specifying which of the banks defined above - * are actually present. MSB is for bank #7, LSB is for bank #0. - */ -#define CONFIG_SYS_BANK_ENABLE 0x01 - -#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */ - /* see 8240 book for bit definitions */ -#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */ - /* currently accessed page in memory */ - /* see 8240 book for details */ - -/* SDRAM 0 - 256MB */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) - -/* PCI memory space */ -#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -/* Config addrs, etc */ -#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#endif /* __CONFIG_H */ -- cgit v1.2.1 From e2788afe672d06d4ee92220c4d7d39a83b4f90ee Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Tue, 22 Oct 2013 22:27:20 +0200 Subject: ARM: bcm2835: add missing mbox overscan response field Add the missing "right" field to struct bcm2835_mbox_tag_overscan. Signed-off-by: Andre Heider Acked-by: Stephen Warren Acked-by: Albert ARIBAUD --- arch/arm/include/asm/arch-bcm2835/mbox.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index 24abe57959..6b806ec57f 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -350,6 +350,7 @@ struct bcm2835_mbox_tag_overscan { u32 top; u32 bottom; u32 left; + u32 right; } resp; } body; }; -- cgit v1.2.1 From cefa47171276509fee89d8084da15409285e481b Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Sat, 9 Nov 2013 11:00:09 +0100 Subject: lcd: allow overriding lcd_get_size() Remove the redundant lcd_line_length initialisation which sneaked in when an earlier version of the patch of commit 6d330719 has been rebased. Some lcd drivers need to setup lcd_line_length not from the panel_info parameters but by different means. Make the lcd_get_size() weak to allow setting lcd_line_length in a driver specific way. Signed-off-by: Anatolij Gustschin Cc: Stephen Warren --- common/lcd.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index 5dd7948121..56bf067fb5 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -386,8 +386,13 @@ static void test_pattern(void) /************************************************************************/ /* ** GENERIC Initialization Routines */ /************************************************************************/ - -int lcd_get_size(int *line_length) +/* + * With most lcd drivers the line length is set up + * by calculating it from panel_info parameters. Some + * drivers need to calculate the line length differently, + * so make the function weak to allow overriding it. + */ +__weak int lcd_get_size(int *line_length) { *line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; return *line_length * panel_info.vl_row; @@ -495,7 +500,6 @@ static int lcd_init(void *lcdbase) debug("[LCD] Using LCD frambuffer at %p\n", lcd_base); lcd_get_size(&lcd_line_length); - lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; lcd_is_enabled = 1; lcd_clear(); lcd_enable(); -- cgit v1.2.1 From 44376eff256da60625f99c1f3559c290f148fc1c Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Sat, 9 Nov 2013 11:07:53 +0100 Subject: video: bcm2835: respect the pitch value Depending on the firmware's video options [1] the active SDTV or HDTV mode can yield a framebuffer with noncontiguous horizontal lines, giving a messed up display, for both, u-boot and the loaded kernel. Fix this by setting lcd_line_length to the pitch value of the configured framebuffer. [1] http://elinux.org/RPiconfig#Video_mode_options Signed-off-by: Andre Heider Cc: Stephen Warren Signed-off-by: Anatolij Gustschin Acked-by: Stephen Warren --- drivers/video/bcm2835.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c index 58a616317a..1f18231ac6 100644 --- a/drivers/video/bcm2835.c +++ b/drivers/video/bcm2835.c @@ -14,6 +14,8 @@ DECLARE_GLOBAL_DATA_PTR; /* Global variables that lcd.c expects to exist */ vidinfo_t panel_info; +static u32 bcm2835_pitch; + struct msg_query { struct bcm2835_mbox_hdr hdr; struct bcm2835_mbox_tag_physical_w_h physical_w_h; @@ -30,6 +32,7 @@ struct msg_setup { struct bcm2835_mbox_tag_virtual_offset virtual_offset; struct bcm2835_mbox_tag_overscan overscan; struct bcm2835_mbox_tag_allocate_buffer allocate_buffer; + struct bcm2835_mbox_tag_pitch pitch; u32 end_tag; }; @@ -80,6 +83,7 @@ void lcd_ctrl_init(void *lcdbase) msg_setup->overscan.body.req.right = 0; BCM2835_MBOX_INIT_TAG(&msg_setup->allocate_buffer, ALLOCATE_BUFFER); msg_setup->allocate_buffer.body.req.alignment = 0x100; + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_setup->pitch, GET_PITCH); ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_setup->hdr); if (ret) { @@ -90,6 +94,7 @@ void lcd_ctrl_init(void *lcdbase) w = msg_setup->physical_w_h.body.resp.width; h = msg_setup->physical_w_h.body.resp.height; + bcm2835_pitch = msg_setup->pitch.body.resp.pitch; debug("bcm2835: Final resolution is %d x %d\n", w, h); @@ -103,3 +108,9 @@ void lcd_ctrl_init(void *lcdbase) void lcd_enable(void) { } + +int lcd_get_size(int *line_length) +{ + *line_length = bcm2835_pitch; + return *line_length * panel_info.vl_row; +} -- cgit v1.2.1 From 54a759c880a11a6dd93704f0adba40139b595e87 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 16 Oct 2013 17:23:24 +0300 Subject: spi: omap3: remove semicolon from #define Remove unnecessary semicolon from #define SPI_WAIT_TIMEOUT Cc: Tom Rini Cc: Jagannadha Sutradharudu Teki Cc: Igor Grinberg Cc: Gerhard Sittig Signed-off-by: Nikita Kiryanov --- drivers/spi/omap3_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index e80be8eaac..116276c000 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -21,7 +21,7 @@ #include "omap3_spi.h" #define WORD_LEN 8 -#define SPI_WAIT_TIMEOUT 3000000; +#define SPI_WAIT_TIMEOUT 3000000 static void spi_reset(struct omap3_spi_slave *ds) { -- cgit v1.2.1 From 5753d09b1064a669e3be8f27e0f1fd008b96934a Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 16 Oct 2013 17:23:25 +0300 Subject: spi: omap3: add support for more word lengths Current implementation only supports 8 bit word lengths, even though omap3 can handle anything between 4 and 32. Update the spi interface to support changing the SPI word length, and implement it in omap3_spi driver to support the full range of possible word lengths. This implementation is backwards compatible by defaulting to the old behavior of 8 bit word lengths. Also, it required a change to the omap3_spi non static I/O functions, but since they are not used anywhere else, no collateral changes are required. Cc: Tom Rini Cc: Jagannadha Sutradharudu Teki Cc: Igor Grinberg Signed-off-by: Nikita Kiryanov --- drivers/spi/omap3_spi.c | 69 +++++++++++++++++++++++++++++++++++-------------- drivers/spi/omap3_spi.h | 8 +++--- drivers/spi/spi.c | 13 ++++++++++ include/spi.h | 16 ++++++++++++ 4 files changed, 82 insertions(+), 24 deletions(-) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 116276c000..a3ad056473 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -20,7 +20,6 @@ #include #include "omap3_spi.h" -#define WORD_LEN 8 #define SPI_WAIT_TIMEOUT 3000000 static void spi_reset(struct omap3_spi_slave *ds) @@ -185,7 +184,7 @@ int spi_claim_bus(struct spi_slave *slave) /* wordlength */ conf &= ~OMAP3_MCSPI_CHCONF_WL_MASK; - conf |= (WORD_LEN - 1) << 7; + conf |= (ds->slave.wordlen - 1) << 7; /* set chipselect polarity; manage with FORCE */ if (!(ds->mode & SPI_CS_HIGH)) @@ -223,7 +222,7 @@ void spi_release_bus(struct spi_slave *slave) spi_reset(ds); } -int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, +int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp, unsigned long flags) { struct omap3_spi_slave *ds = to_omap3_spi(slave); @@ -234,7 +233,8 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, /* Enable the channel */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); - chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); + chconf |= (ds->slave.wordlen - 1) << 7; chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY; chconf |= OMAP3_MCSPI_CHCONF_FORCE; omap3_spi_write_chconf(ds,chconf); @@ -250,7 +250,13 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, } } /* Write the data */ - writel(txp[i], &ds->regs->channel[ds->slave.cs].tx); + unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx; + if (ds->slave.wordlen > 16) + writel(((u32 *)txp)[i], tx); + else if (ds->slave.wordlen > 8) + writel(((u16 *)txp)[i], tx); + else + writel(((u8 *)txp)[i], tx); } /* wait to finish of transfer */ @@ -268,7 +274,7 @@ int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, return 0; } -int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, +int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp, unsigned long flags) { struct omap3_spi_slave *ds = to_omap3_spi(slave); @@ -279,7 +285,8 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, /* Enable the channel */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); - chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); + chconf |= (ds->slave.wordlen - 1) << 7; chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY; chconf |= OMAP3_MCSPI_CHCONF_FORCE; omap3_spi_write_chconf(ds,chconf); @@ -302,7 +309,13 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); /* Read the data */ - rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx); + unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx; + if (ds->slave.wordlen > 16) + ((u32 *)rxp)[i] = readl(rx); + else if (ds->slave.wordlen > 8) + ((u16 *)rxp)[i] = (u16)readl(rx); + else + ((u8 *)rxp)[i] = (u8)readl(rx); } if (flags & SPI_XFER_END) { @@ -314,8 +327,8 @@ int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, } /*McSPI Transmit Receive Mode*/ -int omap3_spi_txrx(struct spi_slave *slave, - unsigned int len, const u8 *txp, u8 *rxp, unsigned long flags) +int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, + const void *txp, void *rxp, unsigned long flags) { struct omap3_spi_slave *ds = to_omap3_spi(slave); int timeout = SPI_WAIT_TIMEOUT; @@ -327,7 +340,8 @@ int omap3_spi_txrx(struct spi_slave *slave, omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_EN); /*set TRANSMIT-RECEIVE Mode*/ - chconf &= ~OMAP3_MCSPI_CHCONF_TRM_MASK; + chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK); + chconf |= (ds->slave.wordlen - 1) << 7; chconf |= OMAP3_MCSPI_CHCONF_FORCE; omap3_spi_write_chconf(ds,chconf); @@ -344,7 +358,13 @@ int omap3_spi_txrx(struct spi_slave *slave, } } /* Write the data */ - writel(txp[i], &ds->regs->channel[ds->slave.cs].tx); + unsigned int *tx = &ds->regs->channel[ds->slave.cs].tx; + if (ds->slave.wordlen > 16) + writel(((u32 *)txp)[i], tx); + else if (ds->slave.wordlen > 8) + writel(((u16 *)txp)[i], tx); + else + writel(((u8 *)txp)[i], tx); /*Read: wait for RX containing data (RXS == 1)*/ while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) & @@ -356,7 +376,13 @@ int omap3_spi_txrx(struct spi_slave *slave, } } /* Read the data */ - rxp[i] = readl(&ds->regs->channel[ds->slave.cs].rx); + unsigned int *rx = &ds->regs->channel[ds->slave.cs].rx; + if (ds->slave.wordlen > 16) + ((u32 *)rxp)[i] = readl(rx); + else if (ds->slave.wordlen > 8) + ((u16 *)rxp)[i] = (u16)readl(rx); + else + ((u8 *)rxp)[i] = (u8)readl(rx); } /* Disable the channel */ omap3_spi_set_enable(ds,OMAP3_MCSPI_CHCTRL_DIS); @@ -375,14 +401,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, { struct omap3_spi_slave *ds = to_omap3_spi(slave); unsigned int len; - const u8 *txp = dout; - u8 *rxp = din; int ret = -1; - if (bitlen % 8) + if (ds->slave.wordlen < 4 || ds->slave.wordlen > 32) { + printf("omap3_spi: invalid wordlen %d\n", ds->slave.wordlen); + return -1; + } + + if (bitlen % ds->slave.wordlen) return -1; - len = bitlen / 8; + len = bitlen / ds->slave.wordlen; if (bitlen == 0) { /* only change CS */ int chconf = readl(&ds->regs->channel[ds->slave.cs].chconf); @@ -400,11 +429,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, ret = 0; } else { if (dout != NULL && din != NULL) - ret = omap3_spi_txrx(slave, len, txp, rxp, flags); + ret = omap3_spi_txrx(slave, len, dout, din, flags); else if (dout != NULL) - ret = omap3_spi_write(slave, len, txp, flags); + ret = omap3_spi_write(slave, len, dout, flags); else if (din != NULL) - ret = omap3_spi_read(slave, len, rxp, flags); + ret = omap3_spi_read(slave, len, din, flags); } return ret; } diff --git a/drivers/spi/omap3_spi.h b/drivers/spi/omap3_spi.h index 01537b6246..ab7cd84448 100644 --- a/drivers/spi/omap3_spi.h +++ b/drivers/spi/omap3_spi.h @@ -99,11 +99,11 @@ static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave) return container_of(slave, struct omap3_spi_slave, slave); } -int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp, - u8 *rxp, unsigned long flags); -int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp, +int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const void *txp, + void *rxp, unsigned long flags); +int omap3_spi_write(struct spi_slave *slave, unsigned int len, const void *txp, unsigned long flags); -int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp, +int omap3_spi_read(struct spi_slave *slave, unsigned int len, void *rxp, unsigned long flags); #endif /* _OMAP3_SPI_H_ */ diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index ea39d1a1ee..b76a26cef0 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -8,6 +8,18 @@ #include #include +int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen) +{ + if (wordlen == 0 || wordlen > 32) { + printf("spi: invalid wordlen %d\n", wordlen); + return -1; + } + + slave->wordlen = wordlen; + + return 0; +} + void *spi_do_alloc_slave(int offset, int size, unsigned int bus, unsigned int cs) { @@ -20,6 +32,7 @@ void *spi_do_alloc_slave(int offset, int size, unsigned int bus, slave = (struct spi_slave *)(ptr + offset); slave->bus = bus; slave->cs = cs; + slave->wordlen = SPI_DEFAULT_WORDLEN; } return ptr; diff --git a/include/spi.h b/include/spi.h index ad9248bee0..67da75cb59 100644 --- a/include/spi.h +++ b/include/spi.h @@ -33,6 +33,8 @@ /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec +#define SPI_DEFAULT_WORDLEN 8 + /** * struct spi_slave - Representation of a SPI slave * @@ -40,6 +42,7 @@ * * @bus: ID of the bus that the slave is attached to. * @cs: ID of the chip select connected to the slave. + * @wordlen: Size of SPI word in number of bits * @max_write_size: If non-zero, the maximum number of bytes which can * be written at once, excluding command bytes. * @memory_map: Address of read-only SPI flash access. @@ -47,6 +50,7 @@ struct spi_slave { unsigned int bus; unsigned int cs; + unsigned int wordlen; unsigned int max_write_size; void *memory_map; }; @@ -152,6 +156,18 @@ int spi_claim_bus(struct spi_slave *slave); */ void spi_release_bus(struct spi_slave *slave); +/** + * Set the word length for SPI transactions + * + * Set the word length (number of bits per word) for SPI transactions. + * + * @slave: The SPI slave + * @wordlen: The number of bits in a word + * + * Returns: 0 on success, -1 on failure. + */ +int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen); + /** * SPI transfer * -- cgit v1.2.1 From 4700219dce2b6b5163207fbbd9b57a2e1b03582d Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 16 Oct 2013 17:23:26 +0300 Subject: spi: define SPI_XFER_ONCE The flag combination "SPI_XFER_BEGIN | SPI_XFER_END" is a common use case of spi_xfer, and it can easily cause an already long line (spi_xfer takes 5 parameters) to go over the 80 character limit. define SPI_XFER_ONCE to be a shorter version of the above flag combination. Cc: Tom Rini Cc: Jagannadha Sutradharudu Teki Cc: Igor Grinberg Signed-off-by: Nikita Kiryanov --- include/spi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/spi.h b/include/spi.h index 67da75cb59..e2563c99f2 100644 --- a/include/spi.h +++ b/include/spi.h @@ -29,6 +29,7 @@ #define SPI_XFER_END 0x02 /* Deassert CS after transfer */ #define SPI_XFER_MMAP 0x08 /* Memory Mapped start */ #define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */ +#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) /* Header byte that marks the start of the message */ #define SPI_PREAMBLE_END_BYTE 0xec -- cgit v1.2.1 From f1a74918e1d3d9988525c12b8af2eebc1910ccf7 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 16 Oct 2013 17:23:27 +0300 Subject: lcd: add DataImage SCF0403x LCD panel support Add SPI-based driver for DataImage SCF0403852GGU04 and SCF0403526GGU20 LCD panels. Cc: Tom Rini Cc: Anatolij Gustschin Cc: Igor Grinberg Signed-off-by: Nikita Kiryanov Acked-by: Anatolij Gustschin Signed-off-by: Anatolij Gustschin --- drivers/video/Makefile | 1 + drivers/video/scf0403_lcd.c | 296 ++++++++++++++++++++++++++++++++++++++++++++ include/scf0403_lcd.h | 11 ++ 3 files changed, 308 insertions(+) create mode 100644 drivers/video/scf0403_lcd.c create mode 100644 include/scf0403_lcd.h diff --git a/drivers/video/Makefile b/drivers/video/Makefile index fed1c9c957..a7f54698ac 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o obj-$(CONFIG_L5F31188) += l5f31188.o obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o +obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_S6E8AX0) += s6e8ax0.o obj-$(CONFIG_S6E63D6) += s6e63d6.o obj-$(CONFIG_LD9040) += ld9040.o diff --git a/drivers/video/scf0403_lcd.c b/drivers/video/scf0403_lcd.c new file mode 100644 index 0000000000..2bc8bcae8a --- /dev/null +++ b/drivers/video/scf0403_lcd.c @@ -0,0 +1,296 @@ +/* + * scf0403.c -- support for DataImage SCF0403 LCD + * + * Copyright (c) 2013 Adapted from Linux driver: + * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved. + * Copyright (c) 2012 CompuLab, Ltd + * Dmitry Lifshitz + * Ilya Ledvich + * Inspired by Alberto Panizzo & + * Marek Vasut work in l4f00242t03.c + * + * U-Boot port: Nikita Kiryanov + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct scf0403_cmd { + u16 cmd; + u16 *params; + int count; +}; + +struct scf0403_initseq_entry { + struct scf0403_cmd cmd; + int delay_ms; +}; + +struct scf0403_priv { + struct spi_slave *spi; + unsigned int reset_gpio; + u32 rddid; + struct scf0403_initseq_entry *init_seq; + int seq_size; +}; + +struct scf0403_priv priv; + +#define SCF0403852GGU04_ID 0x000080 + +/* SCF0403526GGU20 model commands parameters */ +static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06}; +static u16 spiinttype_params_sn20[] = {0x60}; +static u16 bc_params_sn20[] = { + 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B, + 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40, +}; +static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67}; +static u16 be_params_sn20[] = { + 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22, +}; +static u16 vcom_params_sn20[] = {0x74}; +static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00}; +static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00}; +static u16 lvglvolt_params_sn20[] = {0x08}; +static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20}; +static u16 dispfunc_params_sn20[] = {0xa0}; +static u16 dvddvolt_params_sn20[] = {0x74}; +static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00}; +static u16 panelres_params_sn20[] = {0x82}; +static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13}; +static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28}; +static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20}; +static u16 memaccess_params_sn20[] = {0x00}; +static u16 pixfmt_params_sn20[] = {0x66}; +static u16 pgamma_params_sn20[] = { + 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04, + 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10, +}; +static u16 ngamma_params_sn20[] = { + 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03, + 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00, +}; +static u16 tearing_params_sn20[] = {0x00}; + +/* SCF0403852GGU04 model commands parameters */ +static u16 memaccess_params_sn04[] = {0x08}; +static u16 pixfmt_params_sn04[] = {0x66}; +static u16 modectl_params_sn04[] = {0x01}; +static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04}; +static u16 vcom_params_sn04[] = {0x00, 0x6A}; +static u16 pgamma_params_sn04[] = { + 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c, + 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f, +}; +static u16 ngamma_params_sn04[] = { + 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05, + 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00, +}; +static u16 dispinv_params_sn04[] = {0x02}; + +/* Common commands */ +static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0}; +static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0}; + +/* SCF0403852GGU04 init sequence */ +static struct scf0403_initseq_entry scf0403_initseq_sn04[] = { + {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0}, + {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0}, + {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0}, + {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0}, + {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0}, + {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20}, + {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0}, + {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100}, +}; + +/* SCF0403526GGU20 init sequence */ +static struct scf0403_initseq_entry scf0403_initseq_sn20[] = { + {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0}, + {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0}, + {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0}, + {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0}, + {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0}, + {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0}, + {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0}, + {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0}, + {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0}, + {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0}, + {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0}, + {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0}, + {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0}, + {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0}, + {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0}, + {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0}, + {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0}, + {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0}, + {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0}, + {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0}, + {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0}, + {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0}, +}; + +static void scf0403_gpio_reset(unsigned int gpio) +{ + if (!gpio_is_valid(gpio)) + return; + + gpio_set_value(gpio, 1); + mdelay(100); + gpio_set_value(gpio, 0); + mdelay(40); + gpio_set_value(gpio, 1); + mdelay(100); +} + +static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid) +{ + int error = 0; + u8 ids_buf = 0x00; + u16 dummy_buf = 0x00; + u16 cmd = 0x04; + + error = spi_set_wordlen(spi, 9); + if (error) + return error; + + /* Here 9 bits required to transmit a command */ + error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE); + if (error) + return error; + + /* + * Here 8 + 1 bits required to arrange extra clock cycle + * before the first data bit. + * According to the datasheet - first parameter is the dummy data. + */ + error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE); + if (error) + return error; + + error = spi_set_wordlen(spi, 8); + if (error) + return error; + + /* Read rest of the data */ + error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE); + if (error) + return error; + + *rddid = ids_buf; + + return 0; +} + +static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd) +{ + int i, error; + u32 command = cmd->cmd; + u32 msg; + + error = spi_set_wordlen(spi, 9); + if (error) + return error; + + error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE); + if (error) + return error; + + for (i = 0; i < cmd->count; i++) { + msg = (cmd->params[i] | 0x100); + error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE); + if (error) + return error; + } + + return 0; +} + +static void scf0403_lcd_init(struct scf0403_priv *priv) +{ + int i; + + /* reset LCD */ + scf0403_gpio_reset(priv->reset_gpio); + + for (i = 0; i < priv->seq_size; i++) { + if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0) + puts("SPI transfer failed\n"); + + mdelay(priv->init_seq[i].delay_ms); + } +} + +static int scf0403_request_reset_gpio(unsigned gpio) +{ + int err = gpio_request(gpio, "lcd reset"); + + if (err) + return err; + + err = gpio_direction_output(gpio, 0); + if (err) + gpio_free(gpio); + + return err; +} + +int scf0403_init(int reset_gpio) +{ + int error; + + if (gpio_is_valid(reset_gpio)) { + error = scf0403_request_reset_gpio(reset_gpio); + if (error) { + printf("Failed requesting reset GPIO%d: %d\n", + reset_gpio, error); + return error; + } + } + + priv.reset_gpio = reset_gpio; + priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0); + error = spi_claim_bus(priv.spi); + if (error) + goto bus_claim_fail; + + /* reset LCD */ + scf0403_gpio_reset(reset_gpio); + + error = scf0403_spi_read_rddid(priv.spi, &priv.rddid); + if (error) { + puts("IDs read failed\n"); + goto readid_fail; + } + + if (priv.rddid == SCF0403852GGU04_ID) { + priv.init_seq = scf0403_initseq_sn04; + priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04); + } else { + priv.init_seq = scf0403_initseq_sn20; + priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20); + } + + scf0403_lcd_init(&priv); + + /* Start operation */ + scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison); + mdelay(100); + scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout); + spi_release_bus(priv.spi); + + return 0; + +readid_fail: + spi_release_bus(priv.spi); +bus_claim_fail: + if (gpio_is_valid(priv.reset_gpio)) + gpio_free(priv.reset_gpio); + + return error; +} diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h new file mode 100644 index 0000000000..d71896bbda --- /dev/null +++ b/include/scf0403_lcd.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2013, Compulab Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef SCF0403_LCD_H_ +#define SCF0403_LCD_H_ + +int scf0403_init(int reset_gpio); + +#endif -- cgit v1.2.1 From f109a6e73e6bf177eabedfa5fb622ed4809e145c Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 16 Oct 2013 17:23:28 +0300 Subject: omap3_dss: define DSS_ONOFF Add DSS_ONOFF to polarity defines Cc: Tom Rini Cc: Anatolij Gustschin Cc: Igor Grinberg Signed-off-by: Nikita Kiryanov Acked-by: Igor Grinberg Acked-by: Anatolij Gustschin --- arch/arm/include/asm/arch-omap3/dss.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h index ae0babf17c..8bf6b4895f 100644 --- a/arch/arm/include/asm/arch-omap3/dss.h +++ b/arch/arm/include/asm/arch-omap3/dss.h @@ -178,10 +178,11 @@ struct venc_regs { #define LCD_INTERFACE_24_BIT 3 /* Polarity */ -#define DSS_IVS (1 << 12) -#define DSS_IHS (1 << 13) -#define DSS_IPC (1 << 14) -#define DSS_IEO (1 << 15) +#define DSS_IVS (1 << 12) +#define DSS_IHS (1 << 13) +#define DSS_IPC (1 << 14) +#define DSS_IEO (1 << 15) +#define DSS_ONOFF (1 << 17) /* GFX format */ #define GFXFORMAT_BITMAP1 (0x0 << 1) -- cgit v1.2.1 From 63c4f17b2f8017d22241522a48c765073b8791b0 Mon Sep 17 00:00:00 2001 From: Nikita Kiryanov Date: Wed, 16 Oct 2013 17:23:29 +0300 Subject: cm_t35: use scf0403 driver Use scf0403 driver to add scf0403x LCD support for cm-t35 and cm-t3730 boards. Signed-off-by: Nikita Kiryanov Acked-by: Igor Grinberg --- board/compulab/cm_t35/cm_t35.c | 12 +++++++++ board/compulab/common/omap3_display.c | 46 +++++++++++++++++++++++++++++++++-- include/configs/cm_t35.h | 3 +++ 3 files changed, 59 insertions(+), 2 deletions(-) diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index b9a996594f..9f2937a978 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -268,6 +268,9 @@ static void cm_t3x_set_common_muxconf(void) /* DVI enable */ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/ + /* DataImage backlight */ + MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ + /* CM-T3x Ethernet */ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/ MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/ @@ -374,6 +377,15 @@ static void cm_t3x_set_common_muxconf(void) MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/ + + /* SPI */ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/ + MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/ + + /* display controls */ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/ } static void cm_t35_set_muxconf(void) diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c index ead821eeb7..61707f5b90 100644 --- a/board/compulab/common/omap3_display.c +++ b/board/compulab/common/omap3_display.c @@ -14,6 +14,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -22,6 +23,7 @@ enum display_type { NONE, DVI, DVI_CUSTOM, + DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */ }; #define CMAP_ADDR 0x80100000 @@ -119,6 +121,18 @@ static const struct panel_config preset_dvi_1280X1024 = { .gfx_format = GFXFORMAT_RGB16, }; +static const struct panel_config preset_dataimage_480X800 = { + .lcd_size = PANEL_LCD_SIZE(480, 800), + .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2), + .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3), + .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF, + .divisor = 10 | (1 << 10), + .data_lines = LCD_INTERFACE_18_BIT, + .panel_type = ACTIVE_DISPLAY, + .load_mode = 2, + .gfx_format = GFXFORMAT_RGB16, +}; + /* * set_resolution_params() * @@ -146,6 +160,13 @@ static enum display_type set_dvi_preset(const struct panel_config preset, return DVI; } +static enum display_type set_dataimage_preset(const struct panel_config preset, + int x_res, int y_res) +{ + set_preset(preset, x_res, y_res); + return DATA_IMAGE; +} + /* * parse_mode() - parse the mode parameter of custom lcd settings * @@ -369,6 +390,8 @@ static enum display_type env_parse_displaytype(char *displaytype) return set_dvi_preset(preset_dvi_1280X960, 1280, 960); else if (!strncmp(displaytype, "dvi1280x1024", 12)) return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024); + else if (!strncmp(displaytype, "dataimage480x800", 16)) + return set_dataimage_preset(preset_dataimage_480X800, 480, 800); return NONE; } @@ -401,12 +424,31 @@ void lcd_ctrl_init(void *lcdbase) clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); } +#ifdef CONFIG_SCF0403_LCD +static void scf0403_enable(void) +{ + gpio_direction_output(58, 1); + scf0403_init(157); +} +#else +static inline void scf0403_enable(void) {} +#endif + void lcd_enable(void) { - if (lcd_def == DVI || lcd_def == DVI_CUSTOM) { + switch (lcd_def) { + case NONE: + return; + case DVI: + case DVI_CUSTOM: gpio_direction_output(54, 0); /* Turn on DVI */ - omap3_dss_enable(); + break; + case DATA_IMAGE: + scf0403_enable(); + break; } + + omap3_dss_enable(); } void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {} diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 516ef7f301..a6c63cb493 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -325,5 +325,8 @@ #define CONFIG_SPLASH_SCREEN #define CONFIG_CMD_BMP #define CONFIG_BMP_16BPP +#define CONFIG_SCF0403_LCD + +#define CONFIG_OMAP3_SPI #endif /* __CONFIG_H */ -- cgit v1.2.1 From 2035d77d790044f389a18c0e6baa05e86d4b32a0 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 29 Oct 2013 13:33:51 +0900 Subject: i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework This updates to new I2C framwwork on sh_i2c. And this also updates boards(kzm9g and ecovec) that using sh_i2c. Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Nobuhiro Iwamatsu --- README | 18 +++ board/kmc/kzm9g/kzm9g.c | 1 - board/renesas/ecovec/ecovec.c | 3 +- drivers/i2c/Makefile | 2 +- drivers/i2c/sh_i2c.c | 294 +++++++++++++++++++----------------------- include/configs/ecovec.h | 15 +-- include/configs/kzm9g.h | 31 ++--- 7 files changed, 174 insertions(+), 190 deletions(-) diff --git a/README b/README index a70475fb05..9c6d058ef0 100644 --- a/README +++ b/README @@ -2040,6 +2040,24 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3 - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses + - drivers/i2c/sh_i2c.c: + - activate this driver with CONFIG_SYS_I2C_SH + - This driver adds from 2 to 5 i2c buses + + - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0 + - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0 + - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1 + - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1 + - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2 + - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2 + - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3 + - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 + - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 + - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 + - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5 + - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 + - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses + additional defines: CONFIG_SYS_NUM_I2C_BUSES diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index b669ffefec..ea36fa4e19 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -289,7 +289,6 @@ void adjust_core_voltage(void) { u8 data; - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); data = 0x35; i2c_set_bus_num(0); i2c_write(0x40, 3, 1, &data, 1); diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c index e2d365a187..fb4acf3641 100644 --- a/board/renesas/ecovec/ecovec.c +++ b/board/renesas/ecovec/ecovec.c @@ -57,8 +57,7 @@ int board_late_init(void) outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */ + i2c_set_bus_num(1); /* Use I2C 1 */ /* Read MAC address */ i2c_read(0x50, 0x10, 0, mac, 6); diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 5280bb3fe3..0899b6e5ac 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_U8500_I2C) += u8500_i2c.o -obj-$(CONFIG_SH_I2C) += sh_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o @@ -26,6 +25,7 @@ obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o +obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 808202c299..cc19100750 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -6,6 +6,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -22,8 +23,6 @@ struct sh_i2c { }; #undef ureg -static struct sh_i2c *base; - /* ICCR */ #define SH_I2C_ICCR_ICE (1 << 7) #define SH_I2C_ICCR_RACK (1 << 6) @@ -43,202 +42,165 @@ static struct sh_i2c *base; #define SH_I2C_ICIC_ICCHB8 (1 << 6) #endif +static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = { + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0, +#ifdef CONFIG_SYS_I2C_SH_BASE1 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE2 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE3 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3, +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE4 + (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4, +#endif +}; + static u16 iccl, icch; #define IRQ_WAIT 1000 -static void irq_dte(struct sh_i2c *base) +static void sh_irq_dte(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (SH_IC_DTE & readb(&base->icsr)) + for (i = 0; i < IRQ_WAIT; i++) { + if (SH_IC_DTE & readb(&dev->icsr)) break; udelay(10); } } -static int irq_dte_with_tack(struct sh_i2c *base) +static int sh_irq_dte_with_tack(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (SH_IC_DTE & readb(&base->icsr)) + for (i = 0; i < IRQ_WAIT; i++) { + if (SH_IC_DTE & readb(&dev->icsr)) break; - if (SH_IC_TACK & readb(&base->icsr)) + if (SH_IC_TACK & readb(&dev->icsr)) return -1; udelay(10); } return 0; } -static void irq_busy(struct sh_i2c *base) +static void sh_irq_busy(struct sh_i2c *dev) { int i; - for (i = 0 ; i < IRQ_WAIT ; i++) { - if (!(SH_IC_BUSY & readb(&base->icsr))) + for (i = 0; i < IRQ_WAIT; i++) { + if (!(SH_IC_BUSY & readb(&dev->icsr))) break; udelay(10); } } -static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) +static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop) { u8 icic = SH_IC_TACK; - clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); - setbits_8(&base->iccr, SH_I2C_ICCR_ICE); + debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n", + __func__, chip, addr, iccl, icch); + clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); + setbits_8(&dev->iccr, SH_I2C_ICCR_ICE); - writeb(iccl & 0xff, &base->iccl); - writeb(icch & 0xff, &base->icch); + writeb(iccl & 0xff, &dev->iccl); + writeb(icch & 0xff, &dev->icch); #ifdef CONFIG_SH_I2C_8BIT if (iccl > 0xff) icic |= SH_I2C_ICIC_ICCLB8; if (icch > 0xff) icic |= SH_I2C_ICIC_ICCHB8; #endif - writeb(icic, &base->icic); + writeb(icic, &dev->icic); - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); - irq_dte(base); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); + sh_irq_dte(dev); - clrbits_8(&base->icsr, SH_IC_TACK); - writeb(id << 1, &base->icdr); - if (irq_dte_with_tack(base) != 0) + clrbits_8(&dev->icsr, SH_IC_TACK); + writeb(chip << 1, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) return -1; - writeb(reg, &base->icdr); + writeb(addr, &dev->icdr); if (stop) - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr); - if (irq_dte_with_tack(base) != 0) + if (sh_irq_dte_with_tack(dev) != 0) return -1; return 0; } -static void i2c_finish(struct sh_i2c *base) +static void sh_i2c_finish(struct sh_i2c *dev) { - writeb(0, &base->icsr); - clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); + writeb(0, &dev->icsr); + clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); } -static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) +static int +sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val) { int ret = -1; - if (i2c_set_addr(base, id, reg, 0) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) goto exit0; udelay(10); - writeb(val, &base->icdr); - if (irq_dte_with_tack(base) != 0) + writeb(val, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); - if (irq_dte_with_tack(base) != 0) + writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - irq_busy(base); + sh_irq_busy(dev); ret = 0; + exit0: - i2c_finish(base); + sh_i2c_finish(dev); return ret; } -static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) +static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr) { int ret = -1; #if defined(CONFIG_SH73A0) - if (i2c_set_addr(base, id, reg, 0) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) goto exit0; #else - if (i2c_set_addr(base, id, reg, 1) != 0) + if (sh_i2c_set_addr(dev, chip, addr, 1) != 0) goto exit0; udelay(100); #endif - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); - irq_dte(base); + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); + sh_irq_dte(dev); - writeb(id << 1 | 0x01, &base->icdr); - if (irq_dte_with_tack(base) != 0) + writeb(chip << 1 | 0x01, &dev->icdr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); - if (irq_dte_with_tack(base) != 0) + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr); + if (sh_irq_dte_with_tack(dev) != 0) goto exit0; - ret = readb(&base->icdr) & 0xff; + ret = readb(&dev->icdr) & 0xff; + + writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr); + readb(&dev->icdr); /* Dummy read */ + sh_irq_busy(dev); - writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); - readb(&base->icdr); /* Dummy read */ - irq_busy(base); exit0: - i2c_finish(base); + sh_i2c_finish(dev); return ret; } -#ifdef CONFIG_I2C_MULTI_BUS -static unsigned int current_bus; - -/** - * i2c_set_bus_num - change active I2C bus - * @bus: bus index, zero based - * @returns: 0 on success, non-0 on failure - */ -int i2c_set_bus_num(unsigned int bus) -{ - if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { - printf("Bad bus: %d\n", bus); - return -1; - } - - switch (bus) { - case 0: - base = (void *)CONFIG_SH_I2C_BASE0; - break; - case 1: - base = (void *)CONFIG_SH_I2C_BASE1; - break; -#ifdef CONFIG_SH_I2C_BASE2 - case 2: - base = (void *)CONFIG_SH_I2C_BASE2; - break; -#endif -#ifdef CONFIG_SH_I2C_BASE3 - case 3: - base = (void *)CONFIG_SH_I2C_BASE3; - break; -#endif -#ifdef CONFIG_SH_I2C_BASE4 - case 4: - base = (void *)CONFIG_SH_I2C_BASE4; - break; -#endif - default: - return -1; - } - current_bus = bus; - - return 0; -} - -/** - * i2c_get_bus_num - returns index of active I2C bus - */ -unsigned int i2c_get_bus_num(void) -{ - return current_bus; -} -#endif - -#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ - ((clk / rate) * (t_low / t_low + t_high)) -#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ - ((clk / rate) * (t_high / t_low + t_high)) - -void i2c_init(int speed, int slaveaddr) +static void +sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { int num, denom, tmp; @@ -246,11 +208,6 @@ void i2c_init(int speed, int slaveaddr) if (!(gd->flags & GD_FLG_RELOC)) return; -#ifdef CONFIG_I2C_MULTI_BUS - current_bus = 0; -#endif - base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; - /* * Calculate the value for iccl. From the data sheet: * iccl = (p-clock / transfer-rate) * (L / (L + H)) @@ -272,67 +229,78 @@ void i2c_init(int speed, int slaveaddr) icch = (u16)((num/denom) + 1); else icch = (u16)(num/denom); + + debug("clock: %d, speed %d, iccl: %x, icch: %x\n", + CONFIG_SH_I2C_CLOCK, speed, iccl, icch); } -/* - * i2c_read: - Read multiple bytes from an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be read - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to write the data - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) +static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint addr, int alen, u8 *data, int len) { - int ret; - int i = 0; - for (i = 0 ; i < len ; i++) { - ret = i2c_raw_read(base, chip, addr + i); + int ret, i; + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + + for (i = 0; i < len; i++) { + ret = sh_i2c_raw_read(dev, chip, addr + i); if (ret < 0) return -1; - buffer[i] = ret & 0xff; + + data[i] = ret & 0xff; + debug("%s: data[%d]: %02x\n", __func__, i, data[i]); } + return 0; } -/* - * i2c_write: - Write multiple bytes to an i2c device - * - * The higher level routines take into account that this function is only - * called with len < page length of the device (see configuration file) - * - * @chip: address of the chip which is to be written - * @addr: i2c data address within the chip - * @alen: length of the i2c data address (1..2 bytes) - * @buffer: where to find the data to be written - * @len: how much byte do we want to read - * @return: 0 in case of success - */ -int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) +static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, + int alen, u8 *data, int len) { - int i = 0; - for (i = 0; i < len ; i++) - if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0) + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + int i; + + for (i = 0; i < len; i++) { + debug("%s: data[%d]: %02x\n", __func__, i, data[i]); + if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0) return -1; + } return 0; } -/* - * i2c_probe: - Test if a chip answers for a given i2c address - * - * @chip: address of the chip which is searched for - * @return: 0 if a chip was found, -1 otherwhise - */ -int i2c_probe(u8 chip) +static int +sh_i2c_probe(struct i2c_adapter *adap, u8 dev) { - int ret; + return sh_i2c_read(adap, dev, 0, 0, NULL, 0); +} - ret = i2c_set_addr(base, chip, 0, 1); - i2c_finish(base); - return ret; +static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) +{ + struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; + + sh_i2c_finish(dev); + sh_i2c_init(adap, speed, 0); + + return 0; } + +/* + * Register RCAR i2c adapters + */ +U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) +#ifdef CONFIG_SYS_I2C_SH_BASE1 +U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE2 +U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE3 +U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) +#endif +#ifdef CONFIG_SYS_I2C_SH_BASE4 +U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) +#endif diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 335e9cdffa..3483cf1f58 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -58,18 +58,17 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_SH_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_SYS_MAX_I2C_BUS 2 -#define CONFIG_SYS_I2C_MODULE 1 -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH #define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2 +#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000 +#define CONFIG_SYS_I2C_SH_SPEED0 100000 +#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000 +#define CONFIG_SYS_I2C_SH_SPEED1 100000 #define CONFIG_SH_I2C_DATA_HIGH 4 #define CONFIG_SH_I2C_DATA_LOW 5 #define CONFIG_SH_I2C_CLOCK 41666666 -#define CONFIG_SH_I2C_BASE0 0xA4470000 -#define CONFIG_SH_I2C_BASE1 0xA4750000 /* Ether */ #define CONFIG_SH_ETHER 1 diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 1afd487932..f75de5e603 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -139,21 +139,22 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_SH_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 +#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 +#define CONFIG_SYS_I2C_SH_SPEED0 100000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 +#define CONFIG_SYS_I2C_SH_SPEED1 100000 +#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 +#define CONFIG_SYS_I2C_SH_SPEED2 100000 +#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 +#define CONFIG_SYS_I2C_SH_SPEED3 100000 +#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 +#define CONFIG_SYS_I2C_SH_SPEED4 100000 #define CONFIG_SH_I2C_8BIT -#define CONFIG_HARD_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (5) -#define CONFIG_SYS_I2C_MODULE -#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE (0x7F) -#define CONFIG_SH_I2C_DATA_HIGH (4) -#define CONFIG_SH_I2C_DATA_LOW (5) -#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ -#define CONFIG_SH_I2C_BASE0 (0xE6820000) -#define CONFIG_SH_I2C_BASE1 (0xE6822000) -#define CONFIG_SH_I2C_BASE2 (0xE6824000) -#define CONFIG_SH_I2C_BASE3 (0xE6826000) -#define CONFIG_SH_I2C_BASE4 (0xE6828000) +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ #endif /* __KZM9G_H */ -- cgit v1.2.1 From 124913556c4b99909f40b4bf4ceaefe2b555d6f8 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 4 Nov 2013 14:29:12 +0100 Subject: i2c: mxs_i2c: Squash endless loop The endless waiting for a bit to be set can cause a hang, add a timeout so we prevent such situation. A testcase for such a hang is below. The testcase assumes a device to be present at address 0x50 and a device to NOT be present at address 0x42 . Also note that the "sleep 1" induced delays are imperative for this bug to manifest . i2c read 0x42 0x0.2 0x10 0x42000000 ; sleep 1 ; \ i2c read 0x50 0x0.2 0x10 0x42000000 ; sleep 1 ; \ i2c read 0x42 0x0.2 0x10 0x42000000 The expected result of the above command is: Error reading the chip. Error reading the chip. While without this patch, we observe a hang in the last read from 0x42 precisely when waiting for this bit to be set. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Heiko Schocher Cc: Stefano Babic --- drivers/i2c/mxs_i2c.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c index 46106b7712..a298c95e14 100644 --- a/drivers/i2c/mxs_i2c.c +++ b/drivers/i2c/mxs_i2c.c @@ -150,6 +150,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; uint32_t tmp = 0; + int timeout = MXS_I2C_MAX_TIMEOUT; int ret; int i; @@ -169,9 +170,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) for (i = 0; i < len; i++) { if (!(i & 3)) { - while (readl(&i2c_regs->hw_i2c_queuestat) & - I2C_QUEUESTAT_RD_QUEUE_EMPTY) - ; + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY)) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed receiving data!\n"); + return -ETIMEDOUT; + } + tmp = readl(&i2c_regs->hw_i2c_queuedata); } buffer[i] = tmp & 0xff; -- cgit v1.2.1 From 6789e84ecaa8f45d053084e08c381284a04abff7 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 22 Oct 2013 11:03:18 +0200 Subject: i2c, omap24xx: convert driver to new mutlibus/mutliadapter framework MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - add omap24xx driver to new multibus/multiadpater support - adapted all config files, which uses this driver Tested on the am335x based siemens boards rut, dxr2 and pxm2 posted here: http://patchwork.ozlabs.org/patch/263211/ Signed-off-by: Heiko Schocher Tested-by: Tom Rini Cc: Lars Poeschel Cc: Steve Sakoman Cc: Thomas Weber Cc: Tom Rix Cc: Grazvydas Ignotas Cc: Enric Balletbo i Serra Cc: Luca Ceresoli Cc: Igor Grinberg Cc: Ilya Yanok Cc: Stefano Babic Cc: Nishanth Menon Cc: Pali Rohár Cc: Peter Barada Cc: Nagendra T S Cc: Michael Jones Cc: Raphael Assenat Acked-by: Igor Grinberg Acked-by: Stefano Babic --- README | 13 ++ arch/arm/cpu/armv7/omap-common/clocks-common.c | 3 +- arch/arm/cpu/armv7/omap-common/u-boot-spl.lds | 4 + arch/arm/cpu/armv7/omap3/board.c | 2 +- arch/arm/cpu/armv7/omap3/clock.c | 2 +- arch/arm/include/asm/arch-am33xx/i2c.h | 6 +- board/compulab/cm_t35/cm_t35.c | 2 +- board/compulab/common/Makefile | 2 +- board/compulab/common/eeprom.h | 2 +- board/logicpd/am3517evm/am3517evm.c | 4 +- board/overo/overo.c | 2 +- board/phytec/pcm051/board.c | 4 +- board/siemens/common/board.c | 4 +- board/ti/am335x/board.c | 2 +- board/ti/am3517crane/am3517crane.c | 4 +- board/ti/evm/evm.c | 4 +- drivers/i2c/Makefile | 4 +- drivers/i2c/omap24xx_i2c.c | 172 ++++++++++++++++--------- include/configs/am335x_evm.h | 1 - include/configs/am3517_crane.h | 8 +- include/configs/am3517_evm.h | 8 +- include/configs/cm_t35.h | 8 +- include/configs/devkit8000.h | 8 +- include/configs/dig297.h | 8 +- include/configs/mcx.h | 8 +- include/configs/nokia_rx51.h | 8 +- include/configs/omap3_beagle.h | 9 +- include/configs/omap3_evm_common.h | 9 +- include/configs/omap3_igep00x0.h | 8 +- include/configs/omap3_logic.h | 10 +- include/configs/omap3_mvblx.h | 9 +- include/configs/omap3_overo.h | 9 +- include/configs/omap3_pandora.h | 8 +- include/configs/omap3_sdp3430.h | 8 +- include/configs/omap3_zoom1.h | 8 +- include/configs/omap3_zoom2.h | 8 +- include/configs/pcm051.h | 9 +- include/configs/siemens-am33x-common.h | 9 +- include/configs/tam3517-common.h | 11 +- include/configs/ti_armv7_common.h | 9 +- include/configs/tricorder.h | 10 +- 41 files changed, 239 insertions(+), 188 deletions(-) diff --git a/README b/README index 9c6d058ef0..53e56bb187 100644 --- a/README +++ b/README @@ -2058,6 +2058,19 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 - CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses + - drivers/i2c/omap24xx_i2c.c + - activate this driver with CONFIG_SYS_I2C_OMAP24XX + - CONFIG_SYS_OMAP24_I2C_SPEED speed channel 0 + - CONFIG_SYS_OMAP24_I2C_SLAVE slave addr channel 0 + - CONFIG_SYS_OMAP24_I2C_SPEED1 speed channel 1 + - CONFIG_SYS_OMAP24_I2C_SLAVE1 slave addr channel 1 + - CONFIG_SYS_OMAP24_I2C_SPEED2 speed channel 2 + - CONFIG_SYS_OMAP24_I2C_SLAVE2 slave addr channel 2 + - CONFIG_SYS_OMAP24_I2C_SPEED3 speed channel 3 + - CONFIG_SYS_OMAP24_I2C_SLAVE3 slave addr channel 3 + - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 + - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 + additional defines: CONFIG_SYS_NUM_I2C_BUSES diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index bb77b5ca3e..dfa3760dfc 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -779,7 +779,8 @@ void gpi2c_init(void) static int gpi2c = 1; if (gpi2c) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE); gpi2c = 0; } } diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 5e93b343e6..989083c808 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -32,6 +32,10 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } >.sram . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 7d1f8d9d2c..29228160c3 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -98,7 +98,7 @@ void spl_board_init(void) gpmc_init(); #endif #ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif } #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c index 9f989ff860..14fc7e8e81 100644 --- a/arch/arm/cpu/armv7/omap3/clock.c +++ b/arch/arm/cpu/armv7/omap3/clock.c @@ -708,7 +708,7 @@ void per_clocks_enable(void) sr32(&prcm_base->iclken_per, 17, 1, 1); #endif -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX /* Turn on all 3 I2C clocks */ sr32(&prcm_base->fclken1_core, 15, 3, 0x7); sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */ diff --git a/arch/arm/include/asm/arch-am33xx/i2c.h b/arch/arm/include/asm/arch-am33xx/i2c.h index 8bfa53f41b..8642c8f872 100644 --- a/arch/arm/include/asm/arch-am33xx/i2c.h +++ b/arch/arm/include/asm/arch-am33xx/i2c.h @@ -4,8 +4,8 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _I2C_H_ -#define _I2C_H_ +#ifndef _I2C_AM33XX_H_ +#define _I2C_AM33XX_H_ #define I2C_BASE1 0x44E0B000 #define I2C_BASE2 0x4802A000 @@ -62,4 +62,4 @@ struct i2c { #define I2C_IP_CLK 48000000 #define I2C_INTERNAL_SAMPLING_CLK 12000000 -#endif /* _I2C_H_ */ +#endif /* _I2C_AM33XX_H_ */ diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 9f2937a978..bc8e0cad94 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -482,7 +482,7 @@ static void setup_net_chip_gmpc(void) &ctrl_base->gpmc_nadv_ale); } -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX /* * Routine: reset_net_chip * Description: reset the Ethernet controller via TPS65930 GPIO diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index 831be2e0e7..6d7d06815c 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -6,5 +6,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o +obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o obj-$(CONFIG_LCD) += omap3_display.o diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h index cf8c302b2e..e87162930d 100644 --- a/board/compulab/common/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -10,7 +10,7 @@ #ifndef _EEPROM_ #define _EEPROM_ -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX int cl_eeprom_read_mac_addr(uchar *buf); u32 cl_eeprom_get_board_rev(void); #else diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index b6c68da7a8..1569905460 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -98,8 +98,8 @@ static void am3517_evm_musb_init(void) */ int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif dieid_num_r(); diff --git a/board/overo/overo.c b/board/overo/overo.c index aace42a8be..9ac35d2f4e 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -92,7 +92,7 @@ int get_board_revision(void) { int revision; -#ifdef CONFIG_DRIVER_OMAP34XX_I2C +#ifdef CONFIG_SYS_I2C_OMAP34XX unsigned char data; /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index dafb1eb8e6..034886ad5d 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -91,7 +91,7 @@ void set_mux_conf_regs(void) { /* Initalize the board header */ enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); enable_board_pin_mux(); } @@ -108,7 +108,7 @@ void sdram_init(void) */ int board_init(void) { - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c index 6279c3281c..32d2ee4de9 100644 --- a/board/siemens/common/board.c +++ b/board/siemens/common/board.c @@ -42,7 +42,7 @@ void set_mux_conf_regs(void) { /* Initalize the board header */ enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_set_bus_num(0); if (read_eeprom() < 0) puts("Could not get board ID.\n"); @@ -67,7 +67,7 @@ int board_init(void) #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif /* defined(CONFIG_HW_WATCHDOG) */ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_set_bus_num(0); if (read_eeprom() < 0) puts("Could not get board ID.\n"); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57fedab340..8edd21b119 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -397,7 +397,7 @@ const struct dpll_params *get_dpll_ddr_params(void) struct am335x_baseboard_id header; enable_i2c0_pin_mux(); - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index 5eb97ff378..a649697257 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -43,8 +43,8 @@ int board_init(void) */ int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif dieid_num_r(); diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index c71c218529..81dd081d76 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -146,8 +146,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) int misc_init_r(void) { -#ifdef CONFIG_DRIVER_OMAP34XX_I2C - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#ifdef CONFIG_SYS_I2C_OMAP34XX + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); #endif #if defined(CONFIG_CMD_NET) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 0899b6e5ac..298b17b365 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -12,8 +12,6 @@ obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_I2C_MXS) += mxs_i2c.o obj-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o -obj-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o -obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o @@ -23,6 +21,8 @@ obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o +obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o +obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index ef38d71725..3d38c035b6 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -35,6 +35,7 @@ */ #include +#include #include #include @@ -48,22 +49,14 @@ DECLARE_GLOBAL_DATA_PTR; /* Absolutely safe for status update at 100 kHz I2C: */ #define I2C_WAIT 200 -static int wait_for_bb(void); -static u16 wait_for_event(void); -static void flush_fifo(void); +static int wait_for_bb(struct i2c_adapter *adap); +static struct i2c *omap24_get_base(struct i2c_adapter *adap); +static u16 wait_for_event(struct i2c_adapter *adap); +static void flush_fifo(struct i2c_adapter *adap); -/* - * For SPL boot some boards need i2c before SDRAM is initialised so force - * variables to live in SRAM - */ -static struct i2c __attribute__((section (".data"))) *i2c_base = - (struct i2c *)I2C_DEFAULT_BASE; -static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = - { [0 ... (I2C_BUS_MAX-1)] = 0 }; -static unsigned int __attribute__((section (".data"))) current_bus = 0; - -void i2c_init(int speed, int slaveadd) +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { + struct i2c *i2c_base = omap24_get_base(adap); int psc, fsscll, fssclh; int hsscll = 0, hssclh = 0; u32 scll, sclh; @@ -163,16 +156,15 @@ void i2c_init(int speed, int slaveadd) I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); - - if (gd->flags & GD_FLG_RELOC) - bus_initialized[current_bus] = 1; } -static void flush_fifo(void) -{ u16 stat; +static void flush_fifo(struct i2c_adapter *adap) +{ + struct i2c *i2c_base = omap24_get_base(adap); + u16 stat; /* note: if you try and read data when its not there or ready * you get a bus error @@ -192,8 +184,9 @@ static void flush_fifo(void) * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ -int i2c_probe(uchar chip) +static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) { + struct i2c *i2c_base = omap24_get_base(adap); u16 status; int res = 1; /* default = fail */ @@ -201,7 +194,7 @@ int i2c_probe(uchar chip) return res; /* Wait until bus is free */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return res; /* No data transfer, slave addr only */ @@ -212,7 +205,7 @@ int i2c_probe(uchar chip) writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); - status = wait_for_event(); + status = wait_for_event(adap); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* @@ -223,7 +216,7 @@ int i2c_probe(uchar chip) */ if (status == I2C_STAT_XRDY) printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto pr_exit; } @@ -239,7 +232,7 @@ int i2c_probe(uchar chip) I2C_CON_STP, &i2c_base->con); /* STP */ } pr_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); return res; @@ -258,8 +251,10 @@ pr_exit: * or that do not need a register address at all (such as some clock * distributors). */ -int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { + struct i2c *i2c_base = omap24_get_base(adap); int i2c_error = 0; u16 status; @@ -287,7 +282,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Wait until bus not busy */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return 1; /* Zero, one or two bytes reg address (offset) */ @@ -308,12 +303,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) #endif /* Send register offset */ while (1) { - status = wait_for_event(); + status = wait_for_event(adap); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto rd_exit; } if (status == 0 || status & I2C_STAT_NACK) { @@ -348,7 +343,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) /* Receive data */ while (1) { - status = wait_for_event(); + status = wait_for_event(adap); /* * Try to identify bus that is not padconf'd for I2C. This * state could be left over from previous transactions if @@ -357,7 +352,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto rd_exit; } if (status == 0 || status & I2C_STAT_NACK) { @@ -375,15 +370,17 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } rd_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); return i2c_error; } /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ -int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) { + struct i2c *i2c_base = omap24_get_base(adap); int i; u16 status; int i2c_error = 0; @@ -415,7 +412,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Wait until bus not busy */ - if (wait_for_bb()) + if (wait_for_bb(adap)) return 1; /* Start address phase - will write regoffset + len bytes data */ @@ -428,12 +425,12 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) while (alen) { /* Must write reg offset (one or two bytes) */ - status = wait_for_event(); + status = wait_for_event(adap); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", - current_bus, status); + adap->hwadapnr, status); goto wr_exit; } if (status == 0 || status & I2C_STAT_NACK) { @@ -455,7 +452,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } /* Address phase is over, now write data */ for (i = 0; i < len; i++) { - status = wait_for_event(); + status = wait_for_event(adap); if (status == 0 || status & I2C_STAT_NACK) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", @@ -474,7 +471,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) } wr_exit: - flush_fifo(); + flush_fifo(adap); writew(0xFFFF, &i2c_base->stat); writew(0, &i2c_base->cnt); return i2c_error; @@ -484,8 +481,9 @@ wr_exit: * Wait for the bus to be free by checking the Bus Busy (BB) * bit to become clear */ -static int wait_for_bb(void) +static int wait_for_bb(struct i2c_adapter *adap) { + struct i2c *i2c_base = omap24_get_base(adap); int timeout = I2C_TIMEOUT; u16 stat; @@ -514,8 +512,9 @@ static int wait_for_bb(void) * Wait for the I2C controller to complete current action * and update status */ -static u16 wait_for_event(void) +static u16 wait_for_event(struct i2c_adapter *adap) { + struct i2c *i2c_base = omap24_get_base(adap); u16 status; int timeout = I2C_TIMEOUT; @@ -540,7 +539,7 @@ static u16 wait_for_event(void) * not been configured for I2C, and/or pull-ups are missing. */ printf("Check if pads/pull-ups of bus %d are properly configured\n", - current_bus); + adap->hwadapnr); writew(0xFFFF, &i2c_base->stat); status = 0; } @@ -548,48 +547,93 @@ static u16 wait_for_event(void) return status; } -int i2c_set_bus_num(unsigned int bus) +static struct i2c *omap24_get_base(struct i2c_adapter *adap) { - if (bus >= I2C_BUS_MAX) { - printf("Bad bus: %x\n", bus); - return -1; - } - - switch (bus) { - default: - bus = 0; /* Fall through */ + switch (adap->hwadapnr) { case 0: - i2c_base = (struct i2c *)I2C_BASE1; + return (struct i2c *)I2C_BASE1; break; case 1: - i2c_base = (struct i2c *)I2C_BASE2; + return (struct i2c *)I2C_BASE2; break; #if (I2C_BUS_MAX > 2) case 2: - i2c_base = (struct i2c *)I2C_BASE3; + return (struct i2c *)I2C_BASE3; break; #if (I2C_BUS_MAX > 3) case 3: - i2c_base = (struct i2c *)I2C_BASE4; + return (struct i2c *)I2C_BASE4; break; #if (I2C_BUS_MAX > 4) case 4: - i2c_base = (struct i2c *)I2C_BASE5; + return (struct i2c *)I2C_BASE5; break; #endif #endif #endif + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + break; } + return NULL; +} - current_bus = bus; +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) +#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) +#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif - if (!bus_initialized[current_bus]) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED, + CONFIG_SYS_OMAP24_I2C_SLAVE, + 0) +U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED1, + CONFIG_SYS_OMAP24_I2C_SLAVE1, + 1) +#if (I2C_BUS_MAX > 2) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) +#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) +#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif - return 0; -} +U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED2, + CONFIG_SYS_OMAP24_I2C_SLAVE2, + 2) +#if (I2C_BUS_MAX > 3) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) +#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) +#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif -int i2c_get_bus_num(void) -{ - return (int) current_bus; -} +U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED3, + CONFIG_SYS_OMAP24_I2C_SLAVE3, + 3) +#if (I2C_BUS_MAX > 4) +#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) +#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED +#endif +#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) +#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE +#endif + +U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, + omap24_i2c_read, omap24_i2c_write, NULL, + CONFIG_SYS_OMAP24_I2C_SPEED4, + CONFIG_SYS_OMAP24_I2C_SLAVE4, + 4) +#endif +#endif +#endif diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c2ba7e35d8..f35ed6fba0 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -183,7 +183,6 @@ #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ #define CONFIG_BAUDRATE 115200 -/* I2C Configuration */ #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index c5e67bf87d..6fd3fb9045 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -142,10 +142,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 5ff65c6d58..7e9c55edf1 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -136,10 +136,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index a6c63cb493..f4ecd0ddbe 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -141,10 +141,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_I2C_MULTI_BUS diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 8343891cb8..474a5687a9 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -90,10 +90,10 @@ #define CONFIG_DOS_PARTITION 1 /* I2C */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* TWL4030 */ #define CONFIG_TWL4030_POWER 1 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index c19c4c7549..5049afca7a 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -123,10 +123,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 4619dfb3e4..a2f7cf711d 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -137,10 +137,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* RTC */ #define CONFIG_RTC_DS1337 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 4332779d25..e0c0fac8e1 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -157,10 +157,10 @@ #undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ #define CONFIG_OMAP3_SPI -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 47d9902088..bba39d4286 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -161,11 +161,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_VIDEO_OMAP3 /* DSS Support */ /* diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 3eae28884c..43616e2b02 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -87,11 +87,10 @@ /* * I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_OMAP34XX_I2C - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * PISMO support diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index ac36ac6950..75d7d70d29 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -124,10 +124,10 @@ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_OMAP34XX +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 /* * TWL4030 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0c096f429f..bedd6f9cb3 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -118,12 +118,10 @@ /* * I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_OMAP34XX_I2C - -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 45da2e00b2..8d11010f84 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -128,11 +128,10 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_FPGA -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 46416946c7..84b4aeee2a 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -98,11 +98,10 @@ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP34XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 3cce0de48d..eacdfaaa53 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -111,10 +111,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 697a3f386c..6f1304dc94 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -114,10 +114,10 @@ /* * I2C for power management setup */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* OMITTED: single 1 Gbit MT29F1G NAND flash */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 8591f98a8a..1dd53fa133 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -118,10 +118,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index cb8c7ec6f0..f749740815 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -138,10 +138,10 @@ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 4970b13e96..6f41ee7718 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -172,11 +172,10 @@ /* I2C Configuration */ #define CONFIG_I2C #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX #define CONFIG_CMD_EEPROM #define CONFIG_ENV_EEPROM_IS_ON_I2C #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 9eb0a04da6..745e3bea58 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -131,11 +131,10 @@ /* I2C Configuration */ #define CONFIG_I2C #define CONFIG_CMD_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C - +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED OMAP_I2C_STANDARD +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX /* Defines for SPL */ #define CONFIG_SPL diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 683bc54a2c..6112c1b7a6 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -117,14 +117,13 @@ #undef CONFIG_CMD_IMLS #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 400000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_DRIVER_OMAP34XX_I2C - /* * Board NAND Info. @@ -369,7 +368,7 @@ struct tam3517_module_info { #define TAM3517_READ_EEPROM(info, ret) \ do { \ - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); \ + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \ if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \ (void *)info, sizeof(*info))) \ ret = 1; \ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 84269ad262..99b60fcf61 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -59,12 +59,11 @@ /* I2C IP block */ #define CONFIG_I2C -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_DRIVER_OMAP24XX_I2C #define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX /* MMC/SD IP block */ #define CONFIG_MMC diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index d57394e550..afd870762b 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -98,11 +98,11 @@ #define CONFIG_DOS_PARTITION /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX + /* EEPROM */ #define CONFIG_SYS_I2C_MULTI_EEPROMS -- cgit v1.2.1 From 0bdffe71fddeaa46768a39305797e4512dee0f15 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 8 Nov 2013 07:30:53 +0100 Subject: i2c, zynq: convert zynq i2c driver to new multibus/multiadapter framework - add zync i2c driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher Cc: Joe Hershberger Cc: Michal Simek --- README | 5 +++++ drivers/i2c/Makefile | 2 +- drivers/i2c/zynq_i2c.c | 29 ++++++++++++++++------------- include/configs/zynq.h | 8 ++++---- 4 files changed, 26 insertions(+), 18 deletions(-) diff --git a/README b/README index 53e56bb187..c97ff0af0b 100644 --- a/README +++ b/README @@ -2071,6 +2071,11 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_OMAP24_I2C_SPEED4 speed channel 4 - CONFIG_SYS_OMAP24_I2C_SLAVE4 slave addr channel 4 + - drivers/i2c/zynq_i2c.c + - activate this driver with CONFIG_SYS_I2C_ZYNQ + - set CONFIG_SYS_I2C_ZYNQ_SPEED for speed setting + - set CONFIG_SYS_I2C_ZYNQ_SLAVE for slave addr + additional defines: CONFIG_SYS_NUM_I2C_BUSES diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 298b17b365..9dd90947d3 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -28,4 +28,4 @@ obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o -obj-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o +obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index ce2d23f725..70a9aeafd5 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -74,7 +74,8 @@ static struct zynq_i2c_registers *zynq_i2c = (struct zynq_i2c_registers *)ZYNQ_I2C_BASE; /* I2C init called by cmd_i2c when doing 'i2c reset'. */ -void i2c_init(int requested_speed, int slaveadd) +static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, + int slaveadd) { /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | @@ -151,7 +152,7 @@ static u32 zynq_i2c_wait(u32 mask) * I2C probe called by cmd_i2c when doing 'i2c probe'. * Begin read, nak data byte, end. */ -int i2c_probe(u8 dev) +static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) { /* Attempt to read a byte */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | @@ -170,7 +171,8 @@ int i2c_probe(u8 dev) * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c * Begin write, send address byte(s), begin read, receive data bytes, end. */ -int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) { u32 status; u32 i = 0; @@ -235,7 +237,8 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c * Begin write, send address byte(s), send data bytes, end. */ -int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, + int alen, u8 *data, int length) { u8 *cur_data = data; @@ -275,16 +278,16 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) return 0; } -int i2c_set_bus_num(unsigned int bus) +static unsigned int zynq_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int speed) { - /* Only support bus 0 */ - if (bus > 0) - return -1; - return 0; -} + if (speed != 1000000) + return -EINVAL; -unsigned int i2c_get_bus_num(void) -{ - /* Only support bus 0 */ return 0; } + +U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, + zynq_i2c_write, zynq_i2c_set_bus_speed, + CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, + 0) diff --git a/include/configs/zynq.h b/include/configs/zynq.h index 4c6e6e8f6a..82ec826f73 100644 --- a/include/configs/zynq.h +++ b/include/configs/zynq.h @@ -60,10 +60,10 @@ /* I2C */ #if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) # define CONFIG_CMD_I2C -# define CONFIG_ZYNQ_I2C -# define CONFIG_HARD_I2C -# define CONFIG_SYS_I2C_SPEED 100000 -# define CONFIG_SYS_I2C_SLAVE 1 +# define CONFIG_SYS_I2C +# define CONFIG_SYS_I2C_ZYNQ +# define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 #endif #if defined(CONFIG_ZYNQ_DCC) -- cgit v1.2.1 From 85bb251b393470c6d2a91b8f0f92b9f3fda856ca Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 8 Nov 2013 08:33:22 +0100 Subject: i2c, omap1510: remove i2c driver remove omap1510 i2c driver, as there is no board which uses it Signed-off-by: Heiko Schocher Cc: Tom Rini Cc: Jian Zhang --- drivers/i2c/Makefile | 1 - drivers/i2c/omap1510_i2c.c | 277 --------------------------------------------- 2 files changed, 278 deletions(-) delete mode 100644 drivers/i2c/omap1510_i2c.c diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 9dd90947d3..553b519cca 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_DW_I2C) += designware_i2c.o obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_I2C_MXS) += mxs_i2c.o -obj-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o diff --git a/drivers/i2c/omap1510_i2c.c b/drivers/i2c/omap1510_i2c.c deleted file mode 100644 index f91ee8884a..0000000000 --- a/drivers/i2c/omap1510_i2c.c +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Basic I2C functions - * - * Copyright (c) 2003 Texas Instruments - * - * This package is free software; you can redistribute it and/or - * modify it under the terms of the license found in the file - * named COPYING that should have accompanied this file. - * - * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED - * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. - * - * Author: Jian Zhang jzhang@ti.com, Texas Instruments - * - * Copyright (c) 2003 Wolfgang Denk, wd@denx.de - * Rewritten to fit into the current U-Boot framework - * - */ - -#include - -static void wait_for_bb (void); -static u16 wait_for_pin (void); - -void i2c_init (int speed, int slaveadd) -{ - u16 scl; - - if (inw (I2C_CON) & I2C_CON_EN) { - outw (0, I2C_CON); - udelay (5000); - } - - /* 12MHz I2C module clock */ - outw (0, I2C_PSC); - outw (I2C_CON_EN, I2C_CON); - outw (0, I2C_SYSTEST); - /* have to enable intrrupts or OMAP i2c module doesn't work */ - outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); - scl = (12000000 / 2) / speed - 6; - outw (scl, I2C_SCLL); - outw (scl, I2C_SCLH); - /* own address */ - outw (slaveadd, I2C_OA); - outw (0, I2C_CNT); - udelay (1000); -} - -static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) -{ - int i2c_error = 0; - u16 status; - - /* wait until bus not busy */ - wait_for_bb (); - - /* one byte only */ - outw (1, I2C_CNT); - /* set slave address */ - outw (devaddr, I2C_SA); - /* no stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); - - status = wait_for_pin (); - - if (status & I2C_STAT_XRDY) { - /* Important: have to use byte access */ - *(volatile u8 *) (I2C_DATA) = regoffset; - udelay (20000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { - i2c_error = 1; - } - } else { - i2c_error = 1; - } - - if (!i2c_error) { - /* free bus, otherwise we can't use a combined transction */ - outw (0, I2C_CON); - while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (10000); - /* Have to clear pending interrupt to clear I2C_STAT */ - inw (I2C_IV); - } - - wait_for_bb (); - /* set slave address */ - outw (devaddr, I2C_SA); - /* read one byte from slave */ - outw (1, I2C_CNT); - /* need stop bit here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); - - status = wait_for_pin (); - if (status & I2C_STAT_RRDY) { - *value = inw (I2C_DATA); - udelay (20000); - } else { - i2c_error = 1; - } - - if (!i2c_error) { - outw (I2C_CON_EN, I2C_CON); - while (inw (I2C_STAT) - || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (10000); - inw (I2C_IV); - } - } - } - - return i2c_error; -} - -static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) -{ - int i2c_error = 0; - u16 status; - - /* wait until bus not busy */ - wait_for_bb (); - - /* two bytes */ - outw (2, I2C_CNT); - /* set slave address */ - outw (devaddr, I2C_SA); - /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); - - /* wait until state change */ - status = wait_for_pin (); - - if (status & I2C_STAT_XRDY) { - /* send out two bytes */ - outw ((value << 8) + regoffset, I2C_DATA); - /* must have enough delay to allow BB bit to go low */ - udelay (30000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { - i2c_error = 1; - } - } else { - i2c_error = 1; - } - - if (!i2c_error) { - outw (I2C_CON_EN, I2C_CON); - while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { - udelay (1000); - /* have to read to clear intrrupt */ - inw (I2C_IV); - } - } - - return i2c_error; -} - -int i2c_probe (uchar chip) -{ - int res = 1; - - if (chip == inw (I2C_OA)) { - return res; - } - - /* wait until bus not busy */ - wait_for_bb (); - - /* try to read one byte */ - outw (1, I2C_CNT); - /* set slave address */ - outw (chip, I2C_SA); - /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); - /* enough delay for the NACK bit set */ - udelay (2000); - if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { - res = 0; - } else { - outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); - udelay (20); - wait_for_bb (); - } - - return res; -} - -int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - int i; - - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf ("I2C read: address out of range\n"); - return 1; - } - - for (i = 0; i < len; i++) { - if (i2c_read_byte (chip, addr + i, &buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; - } - } - - return 0; -} - -int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) -{ - int i; - - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf ("I2C read: address out of range\n"); - return 1; - } - - for (i = 0; i < len; i++) { - if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; - } - } - - return 0; -} - -static void wait_for_bb (void) -{ - int timeout = 10; - - while ((inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - inw (I2C_IV); - udelay (1000); - } - - if (timeout <= 0) { - printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - inw (I2C_STAT)); - } -} - -static u16 wait_for_pin (void) -{ - u16 status, iv; - int timeout = 10; - - do { - udelay (1000); - status = inw (I2C_STAT); - iv = inw (I2C_IV); - } while (!iv && - !(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); - - if (timeout <= 0) { - printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - inw (I2C_STAT)); - } - - return status; -} -- cgit v1.2.1 From a2e0a45d2e1e258cbe9bd3dbbe7bc7cacbf7a84e Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Thu, 7 Nov 2013 17:51:43 +0400 Subject: cmd_eeprom: fix i2c_{read|write} usage if env is in I2C EEPROM Data "offset" is not used directly in case of I2C EEPROM. Istead it is split into "block number" and "offset within mentioned block". Which are "addr[0]" and "addr[1]" respectively. Signed-off-by: Alexey Brodkin Cc: Jean-Christophe PLAGNIOL-VILLARD cc: Peter Tyser Cc: Heiko Schocher Cc: Wolfgang Denk Cc: Stefan Roese Cc: Mischa Jonker --- common/cmd_eeprom.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_eeprom.c b/common/cmd_eeprom.c index ef694d8f87..02539c40a0 100644 --- a/common/cmd_eeprom.c +++ b/common/cmd_eeprom.c @@ -161,7 +161,7 @@ int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt #if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C) spi_read (addr, alen, buffer, len); #else - if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_read (addr[0], addr[1], alen-1, buffer, len) != 0) rcode = 1; #endif buffer += len; @@ -339,7 +339,7 @@ int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cn /* Write is enabled ... now write eeprom value. */ #endif - if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0) + if (i2c_write (addr[0], addr[1], alen-1, buffer, len) != 0) rcode = 1; #endif -- cgit v1.2.1 From 8b7c87253960aac0b670e606d8dbe2f64b1e5652 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Thu, 7 Nov 2013 17:52:18 +0400 Subject: designware_i2c: disable i2c controller during target address setup As it is stated in DesignWare I2C databook: writes to IC_TAR (0x4) register succeed only when IC_ENABLE[0] is set to 0. Signed-off-by: Alexey Brodkin Cc: Tom Rini cc: Armando Visconti Cc: Stefan Roese Cc: Albert ARIBAUD Cc: Heiko Schocher Cc: Vipin KUMAR Cc: Tom Rix Cc: Mischa Jonker --- drivers/i2c/designware_i2c.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c2f06627d3..c5c6015e99 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -151,7 +151,19 @@ void i2c_init(int speed, int slaveadd) */ static void i2c_setaddress(unsigned int i2c_addr) { + unsigned int enbl; + + /* Disable i2c */ + enbl = readl(&i2c_regs_p->ic_enable); + enbl &= ~IC_ENABLE_0B; + writel(enbl, &i2c_regs_p->ic_enable); + writel(i2c_addr, &i2c_regs_p->ic_tar); + + /* Enable i2c */ + enbl = readl(&i2c_regs_p->ic_enable); + enbl |= IC_ENABLE_0B; + writel(enbl, &i2c_regs_p->ic_enable); } /* -- cgit v1.2.1 From f9de54e9b09b4836fb3cda9d98a6dfba367b9734 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Thu, 7 Nov 2013 17:52:33 +0400 Subject: designware_i2c: remove 10msec delay in i2c_xfer_finish This delay applies to any data transfer on I2C bus. For example 1kB data read with per-byte access (which happens if environment is stored in I2C EEPROM) takes more than 10 seconds. Moreover data bus driver has to care about bus state and data transfer, but not about internal states of attached devices. Signed-off-by: Alexey Brodkin Cc: Tom Rini cc: Armando Visconti Cc: Stefan Roese Cc: Albert ARIBAUD Cc: Heiko Schocher Cc: Vipin KUMAR Cc: Tom Rix Cc: Mischa Jonker --- drivers/i2c/designware_i2c.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c5c6015e99..cb2ac04b60 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -249,9 +249,6 @@ static int i2c_xfer_finish(void) i2c_flush_rxfifo(); - /* Wait for read/write operation to complete on actual memory */ - udelay(10000); - return 0; } -- cgit v1.2.1 From 439fbe75a0185b3b6ede9c665f2117a1a30f64f9 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 1 Oct 2013 13:56:43 +0530 Subject: powerpc/t1040: enable PBL tool for T1040 Use a default RCW of protocol 0x66. A PBI configure file which uses CPC as 256KB SRAM. It can be used by PBL tool on T1040 to build a pbl boot image. Signed-off-by: Prabhakar Kushwaha --- board/freescale/t1040qds/t1040_pbi.cfg | 27 +++++++++++++++++++++++++++ board/freescale/t1040qds/t1040_rcw.cfg | 7 +++++++ include/configs/T1040QDS.h | 2 ++ 3 files changed, 36 insertions(+) create mode 100644 board/freescale/t1040qds/t1040_pbi.cfg create mode 100644 board/freescale/t1040qds/t1040_rcw.cfg diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg new file mode 100644 index 0000000000..624398a25d --- /dev/null +++ b/board/freescale/t1040qds/t1040_pbi.cfg @@ -0,0 +1,27 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 512KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cf0 00000000 +09000cf4 fffc0000 +09000cf8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg new file mode 100644 index 0000000000..0d0dfa5a46 --- /dev/null +++ b/board/freescale/t1040qds/t1040_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0a10000c 0c000000 00000000 00000000 +66000002 00000000 fc027000 01000000 +00000000 00000000 00000000 00030810 +00000000 03fc500f 00000000 00000000 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 2738242c54..7c6bec8f76 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -32,6 +32,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg #endif /* High Level Configuration Options */ -- cgit v1.2.1 From 62af7615eb8e05bb29ecc44210f24317a51fcd94 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 11 Oct 2013 23:02:38 +0800 Subject: powerpc/p1010rdb: update readme for p1010rdb-pa and p1010rdb-pb - Remove duplicate doc/README.p1010rdb - Rename README to README.P1010RDB-PA - Add new README.P1010RDB-PB P1010RDB-PB is a variation of previous P1010RDB-PA board. Signed-off-by: Shengzhou Liu --- board/freescale/p1010rdb/README | 208 ---------------------------- board/freescale/p1010rdb/README.P1010RDB-PA | 208 ++++++++++++++++++++++++++++ board/freescale/p1010rdb/README.P1010RDB-PB | 188 +++++++++++++++++++++++++ doc/README.p1010rdb | 198 -------------------------- 4 files changed, 396 insertions(+), 406 deletions(-) delete mode 100644 board/freescale/p1010rdb/README create mode 100644 board/freescale/p1010rdb/README.P1010RDB-PA create mode 100644 board/freescale/p1010rdb/README.P1010RDB-PB delete mode 100644 doc/README.p1010rdb diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README deleted file mode 100644 index 7f18aaa1b2..0000000000 --- a/board/freescale/p1010rdb/README +++ /dev/null @@ -1,208 +0,0 @@ -Overview -========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB board features are as follows: -Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5” 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port via an external ULPI PHY to micro-AB connector - - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector - - FlexCAN ports: - - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - RJ45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM interface. - SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to POTS -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) - - -Physical Memory Map on P1010RDB -=============================== -Address Start Address End Memory type Attributes -0x0000_0000 0x3fff_ffff DDR 1G Cacheable -0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable -0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable -0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable -0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable -0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable -0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 -0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash -Note: 1 stands for 'on', 0 stands for 'off' - - -Setting of hwconfig -=================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn u-boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -================== -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn u-boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - -Build and burn u-boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -Please contact your local field applications engineer or sales representative -to obtain related documents, such as P1010-RDB User Guide for details. diff --git a/board/freescale/p1010rdb/README.P1010RDB-PA b/board/freescale/p1010rdb/README.P1010RDB-PA new file mode 100644 index 0000000000..158a1b3152 --- /dev/null +++ b/board/freescale/p1010rdb/README.P1010RDB-PA @@ -0,0 +1,208 @@ +Overview +========= +The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), +that addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB board features are as follows: +Memory subsystem: + - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32 Mbyte NOR flash single-chip memory + - 32 Mbyte NAND flash memory + - 256 Kbit M24256 I2C EEPROM + - 16 Mbyte SPI memory + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - PCIe: + - Lane0: x1 mini-PCIe slot + - Lane1: x1 PCIe standard slot + - SATA: + - 1 internal SATA connector to 2.5” 160G SATA2 HDD + - 1 eSATA connector to rear panel + - 10/100/1000 BaseT Ethernet ports: + - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO + - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 + - USB 2.0 port: + - x1 USB2.0 port via an external ULPI PHY to micro-AB connector + - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector + - FlexCAN ports: + - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B) + interface; + - DUART interface: + - DUART interface: supports two UARTs up to 115200 bps for + console display + - RJ45 connectors are used for these 2 UART ports. + - TDM + - 2 FXS ports connected via an external SLIC to the TDM interface. + SLIC is controllled via SPI. + - 1 FXO port connected via a relay to FXS for switchover to POTS +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging +IEEE Std. 1588 signals for test and measurement +Real-time clock on I2C bus +POR + - support critical POR setting changed via switch on board +PCB + - 6-layer routing (4-layer signals, 2-layer power and ground) + + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +Settings of DIP-switch +====================== + SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash + SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash + SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash +Note: 1 stands for 'on', 0 stands for 'off' + + +Setting of hwconfig +=================== +If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or +"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: +setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" +By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection +is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM +instead of to CAN/UART1. + + +Build and burn u-boot to NOR flash +================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NOR + +2. Burn u-boot.bin into NOR flash + => tftp $loadaddr $uboot + => protect off eff80000 +$filesize + => erase eff80000 +$filesize + => cp.b $loadaddr eff80000 $filesize + +3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. + + +Alternate NOR bank +================== +1. Burn u-boot.bin into alternate NOR bank + => tftp $loadaddr $uboot + => protect off eef80000 +$filesize + => erase eef80000 +$filesize + => cp.b $loadaddr eef80000 $filesize + +2. Switch to alternate NOR bank + => mw.b ffb00009 1 + => reset + or set SW1[8]= ON + +SW1[8]= OFF: Upper bank used for booting start +SW1[8]= ON: Lower bank used for booting start +CPLD NOR bank selection register address 0xFFB00009 Bit[0]: +0 - boot from upper 4 sectors +1 - boot from lower 4 sectors + + +Build and burn u-boot to NAND flash +=================================== +1. Build u-boot.bin image + export ARCH=powerpc + export CROSS_COMPILE=/your_path/powerpc-linux-gnu- + make P1010RDB_NAND + +2. Burn u-boot-nand.bin into NAND flash + => tftp $loadaddr $uboot-nand + => nand erase 0 $filesize + => nand write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. + + +Build and burn u-boot to SPI flash +================================== +1. Build u-boot-spi.bin image + make P1010RDB_SPIFLASH_config; make + Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb + Download u-boot.bin to linux and you can find some config files + under /usr/share such as config_xx.dat. Do below command: + boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ + u-boot-spi.bin + to generate u-boot-spi.bin. + +2. Burn u-boot-spi.bin into SPI flash + => tftp $loadaddr $uboot-spi + => sf erase 0 100000 + => sf write $loadaddr 0 $filesize + +3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. + + +CPLD POR setting registers +========================== +1. Set POR switch selection register (addr 0xFFB00011) to 0. +2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with + proper values. + If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 + switch command by I2C. +3. Send reset command. + After reset, the new POR setting will be implemented. + +Two examples are given in below: +Switch from NOR to NAND boot with default frequency: + => i2c dev 0 + => i2c mw 18 1 f9 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00017 1 + => reset +Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): + => i2c dev 0 + => i2c mw 18 1 f1 + => i2c mw 18 3 f0 + => mw.b ffb00011 0 + => mw.b ffb00014 2 + => mw.b ffb00015 5 + => mw.b ffb00016 3 + => mw.b ffb00017 f + => reset + + +Boot Linux from network using TFTP on P1010RDB +============================================== +Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +For more details, please refer to P1010RDB User Guide and access website +www.freescale.com diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB new file mode 100644 index 0000000000..cf459b339e --- /dev/null +++ b/board/freescale/p1010rdb/README.P1010RDB-PB @@ -0,0 +1,188 @@ +Overview +========= +The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC. +P1010RDB-PB is a variation of previous P1010RDB-PA board. + +The P1010 is a cost-effective, low-power, highly integrated host processor +based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that +addresses the requirements of several routing, gateways, storage, consumer, +and industrial applications. Applications of interest include the main CPUs and +I/O processors in network attached storage (NAS), the voice over IP (VoIP) +router/gateway, and wireless LAN (WLAN) and industrial controllers. + +The P1010RDB-PB board features are as following: +Memory subsystem: + - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus) + - 32M bytes NOR flash single-chip memory + - 2G bytes NAND flash memory + - 16M bytes SPI memory + - 256K bit M24256 I2C EEPROM + - I2C Board EEPROM 128x8 bit memory + - SD/MMC connector to interface with the SD memory card +Interfaces: + - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII) + - PCIe 2.0: two x1 mini-PCIe slots + - SATA 2.0: two SATA interfaces + - USB 2.0: one USB interface + - FlexCAN: two FlexCAN interfaces (revision 2.0B) + - UART: one USB-to-Serial interface + - TDM: 2 FXS ports connected via an external SLIC to the TDM interface. + 1 FXO port connected via a relay to FXS for switchover to POTS + +Board connectors: + - Mini-ITX power supply connector + - JTAG/COP for debugging + +POR: support critical POR setting changed via switch on board +PCB: 6-layer routing (4-layer signals, 2-layer power and ground) + +Physical Memory Map on P1010RDB +=============================== +Address Start Address End Memory type Attributes +0x0000_0000 0x3fff_ffff DDR 1G Cacheable +0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable +0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable +0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable +0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable +0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable +0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0 +0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + + +Serial Port Configuration on P1010RDB +===================================== +Configure the serial port of the attached computer with the following values: + -Data rate: 115200 bps + -Number of data bits: 8 + -Parity: None + -Number of Stop bits: 1 + -Flow Control: Hardware/None + + +P1010RDB-PB default DIP-switch settings +======================================= +SW1[1:8]= 10101010 +SW2[1:8]= 11011000 +SW3[1:8]= 10010000 +SW4[1:4]= 1010 +SW5[1:8]= 11111010 + + +P1010RDB-PB boot mode settings via DIP-switch +============================================= +SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot +SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot +SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot +SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot +Note: 1 stands for 'on', 0 stands for 'off' + + +Switch P1010RDB-PB boot mode via software without setting DIP-switch +==================================================================== +=> run boot_bank0 (boot from NOR bank0) +=> run boot_bank1 (boot from NOR bank1) +=> run boot_nand (boot from NAND flash) +=> run boot_spi (boot from SPI flash) +=> run boot_sd (boot from SD card) + + +Frequency combination support on P1010RDB-PB +============================================= +SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s) +0101 1 1010 0 800 400 800 +1001 1 1010 0 800 400 667 +1010 1 1100 0 667 333 667 +1000 0 1010 0 533 266 667 +0101 1 1010 1 1000 400 800 +1001 1 1010 1 1000 400 667 + + +Setting of pin mux +================== +Since pins multiplexing, TDM and CAN are muxed with SPI flash. +SDHC is muxed with IFC. IFC and SPI flash are enabled by default. + +To enable TDM: +=> setenv hwconfig fsl_p1010mux:tdm_can=tdm +=> save;reset + +To enable FlexCAN: +=> setenv hwconfig fsl_p1010mux:tdm_can=can +=> save;reset + +To enable SDHC in case of NOR/NAND/SPI boot + a) For temporary use case in runtime without reboot system + run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. + + b) For long-term use case + set 'esdhc' in hwconfig and save it. + +To enable IFC in case of SD boot + a) For temporary use case in runtime without reboot system + run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. + + b) For long-term use case + set 'ifc' in hwconfig and save it. + + +Build images for different boot mode +==================================== +First setup cross compile environment on build host + $ export ARCH=powerpc + $ export CROSS_COMPILE=/powerpc-linux-gnu- + +1. For NOR boot + $ make P1010RDB-PB_NOR + +2. For NAND boot + $ make P1010RDB-PB_NAND + +3. For SPI boot + $ make P1010RDB-PB_SPIFLASH + +4. For SD boot + $ make P1010RDB-PB_SDCARD + + +Steps to program images to flash for different boot mode +======================================================== +1. NOR boot + => tftp 1000000 u-boot.bin + For bank0 + => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize + set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + + For bank1 + => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize + set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board + +2. NAND boot + => tftp 1000000 u-boot-nand.bin + => nand erase 0 $filesize; nand write $loadaddr 0 $filesize + Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board + +3. SPI boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin + 2) => tftp 1000000 u-boot-spi-combined.bin + 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000 + set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board + +4. SD boot + 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin + 2) => tftp 1000000 u-boot-sd-combined.bin + 3) => mux sdhc + 4) => mmc write 1000000 0 1050 + set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board + + +Boot Linux from network using TFTP on P1010RDB-PB +================================================= +Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path. + => tftp 1000000 uImage + => tftp 2000000 p1010rdb.dtb + => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb + => bootm 1000000 3000000 2000000 + + +For more details, please refer to P1010RDB-PB User Guide and access website +www.freescale.com and Freescale QorIQ SDK Infocenter document. diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb deleted file mode 100644 index 6b2b5ff3fb..0000000000 --- a/doc/README.p1010rdb +++ /dev/null @@ -1,198 +0,0 @@ -Overview -========= -The P1010RDB is a Freescale reference design board that hosts the P1010 SoC. - -The P1010 is a cost-effective, low-power, highly integrated host processor -based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz), -that addresses the requirements of several routing, gateways, storage, consumer, -and industrial applications. Applications of interest include the main CPUs and -I/O processors in network attached storage (NAS), the voice over IP (VoIP) -router/gateway, and wireless LAN (WLAN) and industrial controllers. - -The P1010RDB board features are as follows: -Memory subsystem: - - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) - - 32 Mbyte NOR flash single-chip memory - - 32 Mbyte NAND flash memory - - 256 Kbit M24256 I2C EEPROM - - 16 Mbyte SPI memory - - I2C Board EEPROM 128x8 bit memory - - SD/MMC connector to interface with the SD memory card -Interfaces: - - PCIe: - - Lane0: x1 mini-PCIe slot - - Lane1: x1 PCIe standard slot - - SATA: - - 1 internal SATA connector to 2.5" 160G SATA2 HDD - - 1 eSATA connector to rear panel - - 10/100/1000 BaseT Ethernet ports: - - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO - - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221 - - USB 2.0 port: - - x1 USB2.0 port: via an ULPI PHY to micro-AB connector - - x1 USB2.0 poort via an internal PHY to micro-AB connector - - FlexCAN ports: - - x2 DB-9 female connectors for FlexCAN bus(revision 2.0B) - interface; - - DUART interface: - - DUART interface: supports two UARTs up to 115200 bps for - console display - - J45 connectors are used for these 2 UART ports. - - TDM - - 2 FXS ports connected via an external SLIC to the TDM - interface. SLIC is controllled via SPI. - - 1 FXO port connected via a relay to FXS for switchover to - POTS -Board connectors: - - Mini-ITX power supply connector - - JTAG/COP for debugging -IEEE Std. 1588 signals for test and measurement -Real-time clock on I2C bus -POR - - support critical POR setting changed via switch on board -PCB - - 6-layer routing (4-layer signals, 2-layer power and ground) - - -Serial Port Configuration on P1010RDB -===================================== -Configure the serial port of the attached computer with the following values: - -Data rate: 115200 bps - -Number of data bits: 8 - -Parity: None - -Number of Stop bits: 1 - -Flow Control: Hardware/None - - -Settings of DIP-switch -====================== - SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash - SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash - SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash -Note: 1 stands for 'on', 0 stands for 'off' - - -Setting of hwconfig -=================== -If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or -"fsl_p1010mux:tdm_can=tdm" explicitly in u-booot prompt as below for example: -setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi" -By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection -is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM -instead of to CAN/UART1. - - -Build and burn u-boot to NOR flash -================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NOR - -2. Burn u-boot.bin into NOR flash - => tftp $loadaddr $uboot - => protect off eff80000 +$filesize - => erase eff80000 +$filesize - => cp.b $loadaddr eff80000 $filesize - -3. Check SW4[1:4]= 1111 and SW6[4]=0, then power on. - - -Alternate NOR bank -============================ -1. Burn u-boot.bin into alternate NOR bank - => tftp $loadaddr $uboot - => protect off eef80000 +$filesize - => erase eef80000 +$filesize - => cp.b $loadaddr eef80000 $filesize - -2. Switch to alternate NOR bank - => mw.b ffb00009 1 - => reset - or set SW1[8]= ON - -SW1[8]= OFF: Upper bank used for booting start -SW1[8]= ON: Lower bank used for booting start -CPLD NOR bank selection register address 0xFFB00009 Bit[0]: -0 - boot from upper 4 sectors -1 - boot from lower 4 sectors - - -Build and burn u-boot to NAND flash -=================================== -1. Build u-boot.bin image - export ARCH=powerpc - export CROSS_COMPILE=/your_path/powerpc-linux-gnu- - make P1010RDB_NAND - -2. Burn u-boot-nand.bin into NAND flash - => tftp $loadaddr $uboot-nand - => nand erase 0 $filesize - => nand write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on. - - - -Build and burn u-boot to SPI flash -================================== -1. Build u-boot-spi.bin image - make P1010RDB_SPIFLASH_config; make - Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb - Download u-boot.bin to linux and you can find some config files - under /usr/share such as config_xx.dat. Do below command: - boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \ - u-boot-spi.bin - to generate u-boot-spi.bin. - -2. Burn u-boot-spi.bin into SPI flash - => tftp $loadaddr $uboot-spi - => sf erase 0 100000 - => sf write $loadaddr 0 $filesize - -3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on. - - - -CPLD POR setting registers -========================== -1. Set POR switch selection register (addr 0xFFB00011) to 0. -2. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with - proper values. - If change boot ROM location to NOR or NAND flash, need write the IFC_CS0 - switch command by I2C. -3. Send reset command. - After reset, the new POR setting will be implemented. - -Two examples are given in below: -Switch from NOR to NAND boot with default frequency: - => i2c dev 0 - => i2c mw 18 1 f9 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00017 1 - => reset -Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz): - => i2c dev 0 - => i2c mw 18 1 f1 - => i2c mw 18 3 f0 - => mw.b ffb00011 0 - => mw.b ffb00014 2 - => mw.b ffb00015 5 - => mw.b ffb00016 3 - => mw.b ffb00017 f - => reset - - -Boot Linux from network using TFTP on P1010RDB -============================================== -Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area. - => tftp 1000000 uImage - => tftp 2000000 p1010rdb.dtb - => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb - => bootm 1000000 3000000 2000000 - - -Please contact your local field applications engineer or sales representative -to obtain related documents, such as P1010-RDB User Guide for details. -- cgit v1.2.1 From 2967af6816a2b5b549a3377edf41781a51d00003 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 18 Oct 2013 12:30:21 +0530 Subject: powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain [York Sun: fixed Makefiles] Acked-by: York Sun --- arch/powerpc/cpu/mpc85xx/Makefile | 10 ++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 3 ++- arch/powerpc/include/asm/immap_85xx.h | 3 ++- drivers/net/fm/Makefile | 3 +++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 50ddb5040e..a34014f305 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -70,6 +70,9 @@ obj-$(CONFIG_PPC_B4860) += ddr-gen3.o obj-$(CONFIG_BSC9131) += ddr-gen3.o obj-$(CONFIG_BSC9132) += ddr-gen3.o obj-$(CONFIG_PPC_T1040) += ddr-gen3.o +obj-$(CONFIG_PPC_T1042) += ddr-gen3.o +obj-$(CONFIG_PPC_T1020) += ddr-gen3.o +obj-$(CONFIG_PPC_T1022) += ddr-gen3.o obj-$(CONFIG_CPM2) += ether_fcc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o @@ -89,6 +92,10 @@ obj-$(CONFIG_PPC_T4160) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o +obj-$(CONFIG_PPC_T1042) += t1040_ids.o +obj-$(CONFIG_PPC_T1020) += t1040_ids.o +obj-$(CONFIG_PPC_T1022) += t1040_ids.o + obj-$(CONFIG_QE) += qe_io.o obj-$(CONFIG_CPM2) += serial_scc.o @@ -128,6 +135,9 @@ obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o obj-$(CONFIG_PPC_T1040) += t1040_serdes.o +obj-$(CONFIG_PPC_T1042) += t1040_serdes.o +obj-$(CONFIG_PPC_T1020) += t1040_serdes.o +obj-$(CONFIG_PPC_T1022) += t1040_serdes.o obj-y += cpu.o obj-y += cpu_init.o diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 4cc12ee70f..d4cd27dd00 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -674,7 +674,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #endif -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 060e0d769b..3e76c5419b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1847,7 +1847,8 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 -#elif defined(CONFIG_PPC_T1040) +#elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ +defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index bec86c16c1..2efba7693e 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -26,6 +26,9 @@ obj-$(CONFIG_PPC_P4080) += p4080.o obj-$(CONFIG_PPC_P5020) += p5020.o obj-$(CONFIG_PPC_P5040) += p5040.o obj-$(CONFIG_PPC_T1040) += t1040.o +obj-$(CONFIG_PPC_T1042) += t1040.o +obj-$(CONFIG_PPC_T1020) += t1040.o +obj-$(CONFIG_PPC_T1022) += t1040.o obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o -- cgit v1.2.1 From 062ef1a662ee5b3292805d8fe458f1baead21281 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 18 Oct 2013 17:19:06 +0530 Subject: powerpc/t104xrdb: Add T1040RDB board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T1040RDB is Freescale Reference Design Board supporting the T1040 QorIQ Power Architecture™ processor. T1040RDB board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: - PCI - SGMII - QSGMII - SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha Signed-off-by: Priyanka Jain [York Sun: fixed Makefile] Acked-by: York Sun --- board/freescale/t104xrdb/Makefile | 12 + board/freescale/t104xrdb/README | 162 +++++++++ board/freescale/t104xrdb/ddr.c | 132 +++++++ board/freescale/t104xrdb/ddr.h | 76 ++++ board/freescale/t104xrdb/law.c | 32 ++ board/freescale/t104xrdb/pci.c | 23 ++ board/freescale/t104xrdb/t104xrdb.c | 93 +++++ board/freescale/t104xrdb/t104xrdb.h | 13 + board/freescale/t104xrdb/tlb.c | 107 ++++++ boards.cfg | 1 + include/configs/T1040RDB.h | 690 ++++++++++++++++++++++++++++++++++++ 11 files changed, 1341 insertions(+) create mode 100644 board/freescale/t104xrdb/Makefile create mode 100644 board/freescale/t104xrdb/README create mode 100644 board/freescale/t104xrdb/ddr.c create mode 100644 board/freescale/t104xrdb/ddr.h create mode 100644 board/freescale/t104xrdb/law.c create mode 100644 board/freescale/t104xrdb/pci.c create mode 100644 board/freescale/t104xrdb/t104xrdb.c create mode 100644 board/freescale/t104xrdb/t104xrdb.h create mode 100644 board/freescale/t104xrdb/tlb.c create mode 100644 include/configs/T1040RDB.h diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile new file mode 100644 index 0000000000..76c0c94b0e --- /dev/null +++ b/board/freescale/t104xrdb/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + + +obj-y += t104xrdb.o +obj-y += ddr.o +obj-$(CONFIG_PCI) += pci.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README new file mode 100644 index 0000000000..e8848ee7f0 --- /dev/null +++ b/board/freescale/t104xrdb/README @@ -0,0 +1,162 @@ +Overview +-------- +The T1040RDB is a Freescale reference board that hosts the T1040 SoC +(and variants). Variants inclued T1042 presonality of T1040, in which +case T1040RDB can also be called T1042RDB. + +T1040 SoC Overview +------------------ +The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA +processor cores with high-performance data path acceleration architecture +and network peripheral interfaces required for networking & telecommunications. + +The T1040/T1042 SoC includes the following function and features: + + - Four e5500 cores, each with a private 256 KB L2 cache + - 256 KB shared L3 CoreNet platform cache (CPC) + - Interconnect CoreNet platform + - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration + for the following functions: + - Packet parsing, classification, and distribution + - Queue management for scheduling, packet sequencing, and congestion + management + - Cryptography Acceleration (SEC 5.0) + - RegEx Pattern Matching Acceleration (PME 2.2) + - IEEE Std 1588 support + - Hardware buffer management for buffer allocation and deallocation + - Ethernet interfaces + - Integrated 8-port Gigabit Ethernet switch (T1040 only) + - Four 1 Gbps Ethernet controllers + - Two RGMII interfaces or one RGMII and one MII interfaces + - High speed peripheral interfaces + - Four PCI Express 2.0 controllers running at up to 5 GHz + - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation + - Upto two QSGMII interface + - Upto six SGMII interface supporting 1000 Mbps + - One SGMII interface supporting upto 2500 Mbps + - Additional peripheral interfaces + - Two USB 2.0 controllers with integrated PHY + - SD/eSDHC/eMMC + - eSPI controller + - Four I2C controllers + - Four UARTs + - Four GPIO controllers + - Integrated flash controller (IFC) + - LCD and HDMI interface (DIU) with 12 bit dual data rate + - TDM interface + - Multicore programmable interrupt controller (PIC) + - Two 8-channel DMA engines + - Single source clocking implementation + - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) + +T1040 SoC Personalities +------------------------- + +T1022 Personality: +T1022 is a reduced personality of T1040 with less core/clusters. + +T1042 Personality: +T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit +Ethernet switch. Rest of the blocks are same as T1040 + + +T1040RDB board Overview +------------------------- + - SERDES Connections, 8 lanes information: + 1: None + 2: SGMII + 3: QSGMII + 4: QSGMII + 5: PCIe1 x1 slot + 6: mini PCIe connector + 7: mini PCIe connector + 8: SATA connector + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. + - IFC/Local Bus + - NAND flash: 1GB 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Two on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, “DDRCLK”) + - SERDES clocks + - Power Supplies + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - SDHC/SDXC connector + - SPI + - On-board 64MB SPI flash + - Other IO + - Two Serial ports + - Four I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB +0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB +0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB +0x0_0000_0000 0x0_ffff_ffff DDR 2GB + + +NOR Flash memory Map +--------------------- + Start End Definition Size +0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB +0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB +0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB +0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB +0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB +0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB +0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB +0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB +0xE8000000 0xE801FFFF RCW (current bank) 128KB + + +Various Software configurations/environment variables/commands +-------------------------------------------------------------- +The below commands apply to the board + +1. U-boot environment variable hwconfig + The default hwconfig is: + hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: + dr_mode=host,phy_type=utmi + Note: For USB gadget set "dr_mode=peripheral" + +2. FMAN Ucode versions + fsl_fman_ucode_t1040.bin + +3. Switching to alternate bank + Commands for switching to alternate bank. + + 1. To change from vbank0 to vbank4 + => qixis_reset altbank (it will boot using vbank4) + + 2.To change from vbank4 to vbank0 + => qixis reset (it will boot using vbank0) diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c new file mode 100644 index 0000000000..8f58dd6832 --- /dev/null +++ b/board/freescale/t104xrdb/ddr.c @@ -0,0 +1,132 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "RAW timing DDR"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 1) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found\n"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * rtt and rtt_wr override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h new file mode 100644 index 0000000000..9276b596ac --- /dev/null +++ b/board/freescale/t104xrdb/ddr.h @@ -0,0 +1,76 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 2147483648u, + .capacity = 4294967296u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 1, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, /* ECC */ + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1071, + .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ + .taa_ps = 13910, + .twr_ps = 15000, + .trcd_ps = 13910, + .trrd_ps = 6000, + .trp_ps = 13910, + .tras_ps = 34000, + .trc_ps = 48910, + .trfc_ps = 260000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 35000, +}; + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0}, + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; +#endif diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c new file mode 100644 index 0000000000..2362d4324b --- /dev/null +++ b/board/freescale/t104xrdb/law.c @@ -0,0 +1,32 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_CPLD_BASE_PHYS + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c new file mode 100644 index 0000000000..c53e3b76a4 --- /dev/null +++ b/board/freescale/t104xrdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c new file mode 100644 index 0000000000..6e29d64107 --- /dev/null +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -0,0 +1,93 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "t104xrdb.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + + printf("Board: %sRDB\n", cpu->name); + return 0; +} + +int board_early_init_r(void) +{ +#ifdef CONFIG_SYS_FLASH_BASE + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); +#endif + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); +#endif +} diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h new file mode 100644 index 0000000000..e7cc0c7b5e --- /dev/null +++ b/board/freescale/t104xrdb/t104xrdb.h @@ -0,0 +1,13 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T104x_RDB_H__ +#define __T104x_RDB_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c new file mode 100644 index 0000000000..84f97a41e3 --- /dev/null +++ b/board/freescale/t104xrdb/tlb.c @@ -0,0 +1,107 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the + * SRAM is at 0xfffc0000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 5, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef CONFIG_SYS_CPLD_BASE + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_256K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index caba64e432..725b1e6c8f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -963,6 +963,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi +Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h new file mode 100644 index 0000000000..620387fcd0 --- /dev/null +++ b/include/configs/T1040RDB.h @@ -0,0 +1,690 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * T1040 RDB board configuration file + */ +#define CONFIG_T104xRDB +#define CONFIG_T1040RDB +#define CONFIG_PHYS_64BIT + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ + +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1105) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif +#else /* CONFIG_SYS_NO_FLASH */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR 0x70 +#define I2C_MUX_CH_DEFAULT 0x8 + + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t1040rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t1040rdb/t1040rdb.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#endif + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 0d7ba2ea4372ba12a5a7e27d4adb127c3268c7e1 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 18 Oct 2013 17:19:23 +0530 Subject: powerpc/t104xrdb: Add T1042RDB_PI board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T1042RDB_PI is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture™ processor. T1042 is a reduced personality of T1040 SoC without Integrated 8-port Gigabit. The board is designed with low power features targeted for Printing Image Market. T1042RDB_PI is similar to T1040RDB board with few differences like it has video interface, supports T1042 personality T1042RDB_PI board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Two on-board RGMII 10/100/1G ethernet ports. - SERDES Connections, 8 lanes supporting: — PCI — SATA 2.0 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Video - DIU supports video at up to 1280x1024x32bpp - HDMI connector - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Device connected: EEPROM, thermal monitor, VID controller, RTC - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha Signed-off-by: Priyanka Jain --- board/freescale/t104xrdb/README | 38 +++ boards.cfg | 1 + include/configs/T1042RDB_PI.h | 694 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 733 insertions(+) create mode 100644 include/configs/T1042RDB_PI.h diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README index e8848ee7f0..2cd8219c84 100644 --- a/board/freescale/t104xrdb/README +++ b/board/freescale/t104xrdb/README @@ -4,6 +4,10 @@ The T1040RDB is a Freescale reference board that hosts the T1040 SoC (and variants). Variants inclued T1042 presonality of T1040, in which case T1040RDB can also be called T1042RDB. +The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC. +(a personality of T1040 SoC). The board is similar to T1040RDB but is +designed specially with low power features targeted for Printing Image Market. + T1040 SoC Overview ------------------ The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA @@ -97,6 +101,40 @@ T1040RDB board Overview - Two Serial ports - Four I2C ports +T1042RDB_PI board Overview +------------------------- + - SERDES Connections, 8 lanes information: + 1, 2, 3, 4 : PCIe x4 slot + 5: mini PCIe connector + 6: mini PCIe connector + 7: NA + 8: SATA connector + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types. + - IFC/Local Bus + - NAND flash: 1GB 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Two on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, “DDRCLK”) + - SERDES clocks + - Video + - DIU supports video at up to 1280x1024x32bpp + - Power Supplies + - USB + - Supports two USB 2.0 ports with integrated PHYs + - Two type A ports with 5V@1.5A per port. + - SDHC + - SDHC/SDXC connector + - SPI + - On-board 64MB SPI flash + - Other IO + - Two Serial ports + - Four I2C ports + Memory map ----------- The addresses in brackets are physical addresses. diff --git a/boards.cfg b/boards.cfg index 725b1e6c8f..e742746281 100644 --- a/boards.cfg +++ b/boards.cfg @@ -964,6 +964,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h new file mode 100644 index 0000000000..4b023f9e84 --- /dev/null +++ b/include/configs/T1042RDB_PI.h @@ -0,0 +1,694 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * T1042RDB_PI board configuration file + */ +#define CONFIG_T104xRDB +#define CONFIG_T1042RDB_PI +#define CONFIG_PHYS_64BIT + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ + +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1105) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif +#else /* CONFIG_SYS_NO_FLASH */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BACKSIDE_L2_CACHE +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x51 + +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe8000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_NOR_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +/* CPLD on IFC */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR 0x70 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/*DVI encoder*/ +#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +#ifdef CONFIG_PCI +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#ifdef CONFIG_PCIE1 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#ifdef CONFIG_PCIE2 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#ifdef CONFIG_PCIE3 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif + +/* controller 4, Base address 203000 */ +#ifdef CONFIG_PCIE4 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#endif + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From 4e2e0df94d606531927e411123ae5ce3d2aed49c Mon Sep 17 00:00:00 2001 From: ramneek mehresh Date: Sat, 19 Oct 2013 19:33:04 +0530 Subject: powerpc/83xx: Define USB1 and USB2 base addr for MPC834x Define base addresse for both MPH(USB1) and DR(USB2) controllers for MPC834x socs Signed-off-by: Ramneek Mehresh --- arch/powerpc/include/asm/immap_83xx.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 3c86ff66fd..289f7cac52 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -763,6 +763,7 @@ typedef struct immap { u8 res7[0xC0000]; } immap_t; +#ifndef CONFIG_MPC834x #ifdef CONFIG_HAS_FSL_MPH_USB #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 /* use the MPH controller */ #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0 @@ -770,6 +771,10 @@ typedef struct immap { #define CONFIG_SYS_MPC83xx_USB1_OFFSET 0 #define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 /* use the DR controller */ #endif +#else +#define CONFIG_SYS_MPC83xx_USB1_OFFSET 0x22000 +#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000 +#endif #elif defined(CONFIG_MPC8313) typedef struct immap { -- cgit v1.2.1 From b4125a235e2c4a490765292a95b47008036a4e0d Mon Sep 17 00:00:00 2001 From: Laurentiu TUDOR Date: Wed, 23 Oct 2013 15:20:16 +0300 Subject: powerpc/t4240: set pcie liodn in the correct register The liodn for the T4240's PCIE controller is no longer set through a register in the guts register block but with one in the PCIE register block itself. Use the already existing SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor Cc: Scott Wood Cc: York Sun --- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 54c1cfd2c1..f181315134 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -86,10 +86,10 @@ struct liodn_id_table liodn_tbl[] = { SET_SATA_LIODN(1, 555), SET_SATA_LIODN(2, 556), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), - SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), SET_DMA_LIODN(1, 147), SET_DMA_LIODN(2, 227), -- cgit v1.2.1 From 8f9fe660fcf99af47dc0a28b80cd4e34d403f7c5 Mon Sep 17 00:00:00 2001 From: Laurentiu TUDOR Date: Wed, 23 Oct 2013 15:20:27 +0300 Subject: powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor Cc: Scott Wood Cc: York Sun --- arch/powerpc/cpu/mpc85xx/liodn.c | 25 +++++++++++++++++++++---- arch/powerpc/include/asm/immap_85xx.h | 4 +++- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 4b00da9f75..19e130e87f 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) #endif #define CONFIG_SYS_MAX_PCI_EPS 8 -#define CONFIG_SYS_PCI_EP_LIODN_START 256 -static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) +static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, + int ep_liodn_start) { int off, pci_idx = 0, pci_cnt = 0, i, rc; const uint32_t *base_liodn; @@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat) continue; } for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++) - liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START + + liodn_offs[i + 1] = ep_liodn_start + i * pci_cnt + pci_idx - *base_liodn; rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list", liodn_offs, sizeof(liodn_offs)); @@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob) fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); #endif - fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4"); + ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR; + int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0; + + if (pci_ver >= 0x0204) { + if (pci_ver >= 0x0300) + liodn_base = 1024; + else + liodn_base = 256; + } + + if (liodn_base) { + char compat[32]; + + sprintf(compat, "fsl,qoriq-pcie-v%d.%d", + (pci_ver & 0xff00) >> 8, pci_ver & 0xff); + fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base); + fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base); + } } diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 3e76c5419b..631261857e 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -282,7 +282,9 @@ typedef struct ccsr_pcix { u32 int_ack; /* PCIX IRQ Acknowledge */ u8 res000c[52]; u32 liodn_base; /* PCIX LIODN base register */ - u8 res0044[3004]; + u8 res0044[2996]; + u32 ipver1; /* PCIX IP block revision register 1 */ + u32 ipver2; /* PCIX IP block revision register 2 */ u32 potar0; /* PCIX Outbound Transaction Addr 0 */ u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ -- cgit v1.2.1 From 51abee64eee0186634858d1e6f91a65969c90125 Mon Sep 17 00:00:00 2001 From: Laurentiu TUDOR Date: Wed, 23 Oct 2013 15:20:45 +0300 Subject: powerpc/85xx: fix broken cpu "clock-frequency" property When indexing freqProcessor[] we use the first value in the cpu's "reg" property, which on new e6500 cores IDs the threads. But freqProcessor[] should be indexed with a core index so, when fixing "the clock-frequency" cpu node property, access the freqProcessor[] with the core index derived from the "reg' property. If we don't do this, last half of the "cpu" nodes will have broken "clock-frequency" values. Signed-off-by: Laurentiu Tudor Cc: York Sun --- arch/powerpc/cpu/mpc85xx/fdt.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 2ccd9c7b95..33bc900167 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -586,6 +586,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) { int off; int val; + int len; sys_info_t sysinfo; /* delete crypto node if not on an E-processor */ @@ -615,8 +616,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) get_sys_info(&sysinfo); off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); while (off != -FDT_ERR_NOTFOUND) { - u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); - val = cpu_to_fdt32(sysinfo.freq_processor[*reg]); + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len); + val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]); fdt_setprop(blob, off, "clock-frequency", &val, 4); off = fdt_node_offset_by_prop_value(blob, off, "device_type", "cpu", 4); -- cgit v1.2.1 From 7604a3f920031aa6f3426eedf44494b69ae291e1 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 28 Aug 2013 14:54:26 +0000 Subject: MTD: atmel_nand: support for software BCH ECC Add possible to use software BCH ECC for atmel nand driver Signed-off-by: Bo Shen --- drivers/mtd/nand/atmel_nand.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index da83f06e47..10011c6a8f 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -1178,7 +1178,11 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) mtd->priv = nand; nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr; +#ifdef CONFIG_NAND_ECC_BCH + nand->ecc.mode = NAND_ECC_SOFT_BCH; +#else nand->ecc.mode = NAND_ECC_SOFT; +#endif #ifdef CONFIG_SYS_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif -- cgit v1.2.1 From ed5ac34a33821809ddee6307aa6dc80aeb0245a7 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 3 Oct 2013 11:35:35 +0530 Subject: driver/mtd/ifc: Read Status while programming NAND flash as per controller description, "While programming a NAND flash, status read should never skipped. Because it may happen that a new command is issued to the NAND Flash, even when the device has not yet finished processing the previous request. This may result in unpredictable behaviour." IFC controller never polls for R/B signal after command send. It just return control to software. This behaviour may not occur with NAND flash access. because new commands are sent after polling R/B signal. But it may happen in scenario where GPCM-ASIC and NAND flash device are working simultaneously. Update the controller driver to take care of this requirement Signed-off-by: Prabhakar Kushwaha --- drivers/mtd/nand/fsl_ifc_nand.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 98a09c0641..1d18815b2b 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -428,20 +428,27 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (mtd->writesize > 512) { nand_fcr0 = (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT); + (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | + (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); out_be32(&ifc->ifc_nand.nand_fir0, (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0); + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_RDSTAT << + IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); } else { nand_fcr0 = ((NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_SEQIN << - IFC_NAND_FCR0_CMD2_SHIFT)); + IFC_NAND_FCR0_CMD2_SHIFT) | + (NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD3_SHIFT)); out_be32(&ifc->ifc_nand.nand_fir0, (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | @@ -450,7 +457,11 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT)); + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_RDSTAT << + IFC_NAND_FIR1_OP7_SHIFT) | + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); if (column >= mtd->writesize) nand_fcr0 |= -- cgit v1.2.1 From 10473d0490a08cc1bc7748e710dc562a64206c30 Mon Sep 17 00:00:00 2001 From: Gabor Juhos Date: Tue, 12 Nov 2013 16:47:32 +0100 Subject: malta: use unmapped flash base address The physical base address of the NOR flash is 0x1e000000 on the Malta boards. The hardware also maps the first 4MiB of the flash into the 0x1fc00000-0x1fffffff range. Currently, U-Boot uses the mapped address to access the flash, which does not work in recent qemu versions. Since commit a427338b222b43197c2776cbc996936df0302f51 (mips_malta: correct reading MIPS revision at 0x1fc00010) writing to the mapped address space causes a CPU exception. Due to the exception, U-Boot hangs during boot when it tries to detect the CFI flash chip. Use the correct physical address for the MALTA_FLASH_BASE constant to fix the problem. In order to avoid relocation problems, also update the CONFIG_SYS_{TEXT,MONITOR}_BASE constants. The change makes it possible to start U-Boot on a Malta board emulated with Qemu 1.6.1 and 1.7.0-rc0. It also works on older versions (tested with 1.1.1, 1.2.2, 1.4.2, 1.5.3). Signed-off-by: Gabor Juhos Signed-off-by: Daniel Schwierzeck Cc: Paul Burton --- arch/mips/include/asm/malta.h | 2 +- include/configs/malta.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index 9b1100bc49..bd9043d51c 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -44,7 +44,7 @@ #define MALTA_RESET_BASE 0x1f000500 #define GORESET 0x42 -#define MALTA_FLASH_BASE 0x1fc00000 +#define MALTA_FLASH_BASE 0x1e000000 #define MALTA_REVISION 0x1fc00010 #define MALTA_REVISION_CORID_SHF 10 diff --git a/include/configs/malta.h b/include/configs/malta.h index 4098e724fe..458c33a586 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -40,8 +40,8 @@ /* * Memory map */ -#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_TEXT_BASE 0xbe000000 /* Rom version */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ #define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) -- cgit v1.2.1 From 5e995c00f60596d6e8a6d4ceb9a544cedc1bc838 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 15 Nov 2013 12:20:33 -0500 Subject: TI:omap: Update u-boot-spl.lds for i2c multibus/multiadapter update In 6789e84 we update u-boot-spl.lds for OMAP to ensure we include adapter information, as we use i2c during SPL. However, the regex used also means we included commands that may have been built. On omap5_uevm this leads to a failure as we include the command from the do_tca642x command, and fail to link. The fix is to restrict our regex to only the i2c list parts. Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/u-boot-spl.lds | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 989083c808..02aa129733 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -34,8 +34,9 @@ SECTIONS . = ALIGN(4); .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); + KEEP(*(SORT(.u_boot_list*_i2c_*))); } >.sram + . = ALIGN(4); __image_copy_end = .; _end = .; -- cgit v1.2.1 From e63510d1cb56387885f94f065fdacdf45195ffec Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 09:49:36 +0900 Subject: configs: clean up unused macro CONFIG_L2_OFF Since commit c2dd0d455 and 45bf05854 introduced the new cache maintainance framework to ARM, CONFIG_L2_OFF has not been used at all. Signed-off-by: Masahiro Yamada --- include/configs/highbank.h | 1 - include/configs/kzm9g.h | 1 - include/configs/mx51_efikamx.h | 1 - include/configs/origen.h | 2 -- include/configs/smdkv310.h | 3 --- include/configs/snowball.h | 1 - include/configs/socfpga_cyclone5.h | 1 - include/configs/u8500_href.h | 1 - 8 files changed, 11 deletions(-) diff --git a/include/configs/highbank.h b/include/configs/highbank.h index b86eb430a1..7dbee3cdb9 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -8,7 +8,6 @@ #define __CONFIG_H #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_L2_OFF #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index f75de5e603..f183279ba8 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -22,7 +22,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_L2_OFF #define CONFIG_OF_LIBFDT #include diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h index 8a44ef5a74..0f2a4ef973 100644 --- a/include/configs/mx51_efikamx.h +++ b/include/configs/mx51_efikamx.h @@ -29,7 +29,6 @@ #define CONFIG_SYS_TEXT_BASE 0x97800000 -#define CONFIG_L2_OFF #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF diff --git a/include/configs/origen.h b/include/configs/origen.h index bad34b3e71..f46b833b53 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -22,8 +22,6 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F -/* Keep L2 Cache Disabled */ -#define CONFIG_L2_OFF 1 #define CONFIG_SYS_DCACHE_OFF 1 #define CONFIG_SYS_SDRAM_BASE 0x40000000 diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index e2e8efe58c..1388f49986 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -25,9 +25,6 @@ /* Mach Type */ #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 -/* Keep L2 Cache Disabled */ -#define CONFIG_L2_OFF 1 - #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 00d6fa5e89..9a069f3cdb 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -23,7 +23,6 @@ * (easy to change) */ #define CONFIG_U8500 -#define CONFIG_L2_OFF #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 980636c93b..608578ad2c 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -16,7 +16,6 @@ #define CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 -#define CONFIG_L2_OFF #define CONFIG_SYS_DCACHE_OFF #undef CONFIG_USE_IRQ diff --git a/include/configs/u8500_href.h b/include/configs/u8500_href.h index 45d33a6896..629299d107 100644 --- a/include/configs/u8500_href.h +++ b/include/configs/u8500_href.h @@ -12,7 +12,6 @@ * (easy to change) */ #define CONFIG_U8500 -#define CONFIG_L2_OFF #define CONFIG_SYS_MEMTEST_START 0x00000000 #define CONFIG_SYS_MEMTEST_END 0x1FFFFFFF -- cgit v1.2.1 From 0298793dd9f84f4b290d582e2293627298bd20a4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 10:30:20 +0900 Subject: board: cogent: include header files in a more natural way Signed-off-by: Masahiro Yamada --- board/cogent/config.mk | 12 ------------ board/cogent/dipsw.c | 2 +- board/cogent/flash.c | 2 +- board/cogent/lcd.c | 2 +- board/cogent/mb.c | 10 +++++----- board/cogent/serial.c | 2 +- 6 files changed, 9 insertions(+), 21 deletions(-) delete mode 100644 board/cogent/config.mk diff --git a/board/cogent/config.mk b/board/cogent/config.mk deleted file mode 100644 index 1452d46a9f..0000000000 --- a/board/cogent/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Cogent Modular Architecture -# - -PLATFORM_CPPFLAGS += -I$(TOPDIR) diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c index d2027c9758..ecfbc25981 100644 --- a/board/cogent/dipsw.c +++ b/board/cogent/dipsw.c @@ -1,5 +1,5 @@ #include -#include +#include "dipsw.h" unsigned char dipsw_raw(void) diff --git a/board/cogent/flash.c b/board/cogent/flash.c index d4ae4d0a3c..1da8f10a1f 100644 --- a/board/cogent/flash.c +++ b/board/cogent/flash.c @@ -6,7 +6,7 @@ */ #include -#include +#include "flash.h" #include flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c index 76f5ad103f..8e90f9853a 100644 --- a/board/cogent/lcd.c +++ b/board/cogent/lcd.c @@ -48,7 +48,7 @@ #include #include -#include +#include "lcd.h" static char lines[2][LCD_LINE_LENGTH+1]; static int curline; diff --git a/board/cogent/mb.c b/board/cogent/mb.c index 603f1235a4..3eea47d3e8 100644 --- a/board/cogent/mb.c +++ b/board/cogent/mb.c @@ -6,11 +6,11 @@ */ #include -#include -#include -#include -#include -#include +#include "dipsw.h" +#include "lcd.h" +#include "rtc.h" +#include "par.h" +#include "pci.h" /* ------------------------------------------------------------------------- */ diff --git a/board/cogent/serial.c b/board/cogent/serial.c index 20631d162d..f0d6b22cfd 100644 --- a/board/cogent/serial.c +++ b/board/cogent/serial.c @@ -4,7 +4,7 @@ */ #include -#include +#include "serial.h" #include #include -- cgit v1.2.1 From 477fe65832e0251e5a077aa15a3a7b97660db4f4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 12:11:12 +0900 Subject: nios2: remove unnecessary header include path Signed-off-by: Masahiro Yamada Cc: Thomas Chou --- board/altera/nios2-generic/config.mk | 4 ---- board/psyent/pci5441/config.mk | 1 - board/psyent/pk1c20/config.mk | 1 - 3 files changed, 6 deletions(-) diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk index f9f317c440..a673525195 100644 --- a/board/altera/nios2-generic/config.mk +++ b/board/altera/nios2-generic/config.mk @@ -5,11 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# we get text_base from board config header, so do not use this -#CONFIG_SYS_TEXT_BASE = do-not-use-me - PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk index 00ff743c96..776fa8ab40 100644 --- a/board/psyent/pci5441/config.mk +++ b/board/psyent/pci5441/config.mk @@ -8,7 +8,6 @@ CONFIG_SYS_TEXT_BASE = 0x018e0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk index 7b0810a302..83cfadc113 100644 --- a/board/psyent/pk1c20/config.mk +++ b/board/psyent/pk1c20/config.mk @@ -8,7 +8,6 @@ CONFIG_SYS_TEXT_BASE = 0x01fc0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul -PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG -- cgit v1.2.1 From 5f9cc8e6387a5ba8962e8466c8bcbb8c07caf845 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 12:15:58 +0900 Subject: cosmetic: README.scrapyard: Add eNET board Commit 7e8c53d7 removed eNET board but missed to add eNET to README.scrapyard. This commit adds it for the record. Signed-off-by: Masahiro Yamada Cc: Simon Glass Cc: Graeme Russ Acked-by: Simon Glass --- doc/README.scrapyard | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/README.scrapyard b/doc/README.scrapyard index c3182e4d90..f045f433f6 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -103,3 +103,4 @@ CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuc PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk omap2420h4 arm omap24xx - 2013-06-04 Richard Woodruff +eNET x86 x86 7e8c53d 2013-02-14 Graeme Russ -- cgit v1.2.1 From 13b213b47de472f29dfe03f71989892d8ffb5881 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 12:45:40 +0900 Subject: examples: remove the remainders of dead board Commit 309a292e deleted OXC board, but missed to remove the standalone example specific to OXC board. eepro100_eeprom.c has been an orphan file for a long term. Signed-off-by: Masahiro Yamada --- examples/standalone/Makefile | 4 +- examples/standalone/eepro100_eeprom.c | 214 ---------------------------------- 2 files changed, 1 insertion(+), 217 deletions(-) delete mode 100644 examples/standalone/eepro100_eeprom.c diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 4afedea065..93469217ef 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -8,7 +8,6 @@ include $(TOPDIR)/config.mk ELF-$(ARCH) := -ELF-$(BOARD) := ELF-$(CPU) := ELF-y := hello_world @@ -20,14 +19,13 @@ ELF-mpc5xxx += interrupt ELF-mpc8xx += test_burst timer ELF-mpc8260 += mem_to_mem_idma2intr ELF-ppc += sched -ELF-oxc += eepro100_eeprom # # Some versions of make do not handle trailing white spaces properly; # leading to build failures. The problem was found with GNU Make 3.80. # Using 'strip' as a workaround for the problem. # -ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU))) +ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(CPU))) SREC := $(addsuffix .srec,$(ELF)) BIN := $(addsuffix .bin,$(ELF)) diff --git a/examples/standalone/eepro100_eeprom.c b/examples/standalone/eepro100_eeprom.c deleted file mode 100644 index 3c7f380977..0000000000 --- a/examples/standalone/eepro100_eeprom.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright 1998-2001 by Donald Becker. - * This software may be used and distributed according to the terms of - * the GNU General Public License (GPL), incorporated herein by reference. - * Contact the author for use under other terms. - * - * This program must be compiled with "-O"! - * See the bottom of this file for the suggested compile-command. - * - * The author may be reached as becker@scyld.com, or C/O - * Scyld Computing Corporation - * 410 Severn Ave., Suite 210 - * Annapolis MD 21403 - * - * Common-sense licensing statement: Using any portion of this program in - * your own program means that you must give credit to the original author - * and release the resulting code under the GPL. - */ - -/* avoid unnecessary memcpy function */ -#define _PPC_STRING_H_ - -#include -#include - -static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr); - -int eepro100_eeprom(int argc, char * const argv[]) -{ - int ret = 0; - - unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 }; - unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 }; - - app_startup(argv); - -#if defined(CONFIG_OXC) - ret |= reset_eeprom(0x80000000, hwaddr1); - ret |= reset_eeprom(0x81000000, hwaddr2); -#endif - - return ret; -} - -/* Default EEPROM for i82559 */ -static unsigned short default_eeprom[64] = { - 0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, - 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff -}; - -static unsigned short eeprom[256]; - -static int eeprom_size = 64; -static int eeprom_addr_size = 6; - -static int debug = 0; - -static inline unsigned short swap16(unsigned short x) -{ - return (((x & 0xff) << 8) | ((x & 0xff00) >> 8)); -} - -static inline void outw(short data, long addr) -{ - *(volatile short *)(addr) = swap16(data); -} - -static inline short inw(long addr) -{ - return swap16(*(volatile short *)(addr)); -} - -void *memcpy(void *dst, const void *src, unsigned int len) -{ - char *ret = dst; - while (len-- > 0) { - *ret++ = *((char *)src); - src++; - } - return (void *)ret; -} - -/* The EEPROM commands include the alway-set leading bit. */ -#define EE_WRITE_CMD (5) -#define EE_READ_CMD (6) -#define EE_ERASE_CMD (7) - -/* Serial EEPROM section. */ -#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */ -#define EE_CS 0x02 /* EEPROM chip select. */ -#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ -#define EE_DATA_READ 0x08 /* EEPROM chip data out. */ -#define EE_ENB (0x4800 | EE_CS) -#define EE_WRITE_0 0x4802 -#define EE_WRITE_1 0x4806 -#define EE_OFFSET 14 - -/* Delay between EEPROM clock transitions. */ -#define eeprom_delay(ee_addr) inw(ee_addr) - -/* Wait for the EEPROM to finish the previous operation. */ -static int eeprom_busy_poll(long ee_ioaddr) -{ - int i; - outw(EE_ENB, ee_ioaddr); - for (i = 0; i < 10000; i++) /* Typical 2000 ticks */ - if (inw(ee_ioaddr) & EE_DATA_READ) - break; - return i; -} - -/* This executes a generic EEPROM command, typically a write or write enable. - It returns the data output from the EEPROM, and thus may also be used for - reads. */ -static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len) -{ - unsigned retval = 0; - long ee_addr = ioaddr + EE_OFFSET; - - if (debug > 1) - printf(" EEPROM op 0x%x: ", cmd); - - outw(EE_ENB | EE_SHIFT_CLK, ee_addr); - - /* Shift the command bits out. */ - do { - short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0; - outw(dataval, ee_addr); - eeprom_delay(ee_addr); - if (debug > 2) - printf("%X", inw(ee_addr) & 15); - outw(dataval | EE_SHIFT_CLK, ee_addr); - eeprom_delay(ee_addr); - retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0); - } while (--cmd_len >= 0); -#if 0 - outw(EE_ENB, ee_addr); -#endif - /* Terminate the EEPROM access. */ - outw(EE_ENB & ~EE_CS, ee_addr); - if (debug > 1) - printf(" EEPROM result is 0x%5.5x.\n", retval); - return retval; -} - -static int read_eeprom(long ioaddr, int location, int addr_len) -{ - return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location) - << 16 , 3 + addr_len + 16) & 0xffff; -} - -static void write_eeprom(long ioaddr, int index, int value, int addr_len) -{ - long ee_ioaddr = ioaddr + EE_OFFSET; - int i; - - /* Poll for previous op finished. */ - eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */ - /* Enable programming modes. */ - do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len); - /* Do the actual write. */ - do_eeprom_cmd(ioaddr, - (((EE_WRITE_CMD< Date: Mon, 11 Nov 2013 14:13:33 +0900 Subject: board: Do not add -DCONFIG_SYS_TEXT_BASE in board config.mk Board config.mk do not need to add -DCONFIG_SYS_TEXT_BASE to CPPFLAGS because the top level config.mk does instead. Signed-off-by: Masahiro Yamada --- board/freescale/m52277evb/config.mk | 11 ----------- board/freescale/m5235evb/config.mk | 12 ------------ board/freescale/m54451evb/config.mk | 11 ----------- board/freescale/m54455evb/config.mk | 11 ----------- board/gaisler/gr_cpci_ax2000/config.mk | 3 +-- board/gaisler/gr_ep2s60/config.mk | 3 +-- board/gaisler/gr_xc3s_1500/config.mk | 3 +-- board/gaisler/grsim/config.mk | 3 +-- board/gaisler/grsim_leon2/config.mk | 3 +-- 9 files changed, 5 insertions(+), 55 deletions(-) delete mode 100644 board/freescale/m52277evb/config.mk delete mode 100644 board/freescale/m5235evb/config.mk delete mode 100644 board/freescale/m54451evb/config.mk delete mode 100644 board/freescale/m54455evb/config.mk diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk deleted file mode 100644 index 0ffb0a204b..0000000000 --- a/board/freescale/m52277evb/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk deleted file mode 100644 index 9ab4582bf8..0000000000 --- a/board/freescale/m5235evb/config.mk +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/ -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m54451evb/config.mk b/board/freescale/m54451evb/config.mk deleted file mode 100644 index 0ffb0a204b..0000000000 --- a/board/freescale/m54451evb/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk deleted file mode 100644 index 0ffb0a204b..0000000000 --- a/board/freescale/m54455evb/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn -# -# SPDX-License-Identifier: GPL-2.0+ -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk index e9c60286ce..309c879489 100644 --- a/board/gaisler/gr_cpci_ax2000/config.mk +++ b/board/gaisler/gr_cpci_ax2000/config.mk @@ -18,5 +18,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN SDRAM #CONFIG_SYS_TEXT_BASE = 0x60000000 -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk index 6c31a17f8c..d57efae158 100644 --- a/board/gaisler/gr_ep2s60/config.mk +++ b/board/gaisler/gr_ep2s60/config.mk @@ -16,5 +16,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN SDRAM #CONFIG_SYS_TEXT_BASE = 0x40000000 -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk index 3b59cca5e6..e87320be99 100644 --- a/board/gaisler/gr_xc3s_1500/config.mk +++ b/board/gaisler/gr_xc3s_1500/config.mk @@ -15,5 +15,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk index d98ed54c07..df26f82c9c 100644 --- a/board/gaisler/grsim/config.mk +++ b/board/gaisler/grsim/config.mk @@ -15,5 +15,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # U-BOOT IN RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk index 59e4e31690..99f9a68725 100644 --- a/board/gaisler/grsim_leon2/config.mk +++ b/board/gaisler/grsim_leon2/config.mk @@ -15,5 +15,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000 # RUN U-BOOT FROM RAM #CONFIG_SYS_TEXT_BASE = 0x40000000 -PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \ - -I$(TOPDIR)/board +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board -- cgit v1.2.1 From 3fdf5c8e94e7a2a62f98ea8f0ad1a84d18eccfbf Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:49 +0900 Subject: Makefile: abolish COBJS, SOBJS, etc. The support for COBJS, COBJS-y, SOBJS, SOBJS-y, GLCOBJS, GLSOBJS from scripts/Makefile.build. Going forward we need to use Kbuild style consistently. Signed-off-by: Masahiro Yamada --- scripts/Makefile.build | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 2ef7341f37..805c3c3e3a 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -10,10 +10,6 @@ SRCS := include Makefile -# Backward compatible: obj-y is preferable -COBJS := $(sort $(COBJS) $(COBJS-y)) -SOBJS := $(sort $(SOBJS) $(SOBJS-y)) - # Going forward use the following obj-y := $(sort $(obj-y)) extra-y := $(sort $(extra-y)) @@ -24,11 +20,11 @@ obj-y := $(patsubst %/, %/built-in.o, $(obj-y)) subdir-obj-y := $(filter %/built-in.o, $(obj-y)) subdir-obj-y := $(addprefix $(obj),$(subdir-obj-y)) -SRCS += $(COBJS:.o=.c) $(SOBJS:.o=.S) \ - $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S)) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y)) +SRCS += $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \ + $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S)) +OBJS := $(addprefix $(obj),$(obj-y)) -LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y)) +LGOBJS := $(addprefix $(obj),$(sort $(lib-y))) all: $(LIB) $(addprefix $(obj),$(extra-y)) -- cgit v1.2.1 From 1b2226e0ceebf01e192715b77b96dbe9e9f75a4b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:50 +0900 Subject: Makefile: specifiy an explicite object name rather than $(BOARD).o Signed-off-by: Masahiro Yamada --- board/freescale/t1040qds/Makefile | 2 +- board/keymile/kmp204x/Makefile | 2 +- board/ti/beagle/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index a2dba6ff1c..93af9eb6a0 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -4,7 +4,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += $(BOARD).o +obj-y += t1040qds.o obj-y += ddr.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile index 64eb37c9d7..c318e08a59 100644 --- a/board/keymile/kmp204x/Makefile +++ b/board/keymile/kmp204x/Makefile @@ -12,5 +12,5 @@ ifneq ($(OBJTREE),$(SRCTREE)) $(shell mkdir -p $(obj)../common) endif -obj-y := $(BOARD).o ddr.o eth.o tlb.o pci.o law.o \ +obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \ ../common/common.o ../common/ivm.o diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile index 9f55e8f358..7a858be5e4 100644 --- a/board/ti/beagle/Makefile +++ b/board/ti/beagle/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := $(BOARD).o +obj-y := beagle.o obj-$(CONFIG_STATUS_LED) += led.o -- cgit v1.2.1 From 7b6af41ef342199e4967735ea17424b42ed742d2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:51 +0900 Subject: drivers: descend into sub directories only when it is necessary - Descend into drivers/fpga/ only when CONFIG_FPGA=y - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y Signed-off-by: Masahiro Yamada --- drivers/Makefile | 4 ++-- drivers/bios_emulator/Makefile | 2 +- drivers/fpga/Makefile | 2 -- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/Makefile b/drivers/Makefile index 9cec2ba6fe..95a4b80724 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,8 +1,8 @@ -obj-y += bios_emulator/ +obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ obj-y += crypto/ -obj-y += fpga/ +obj-$(CONFIG_FPGA) += fpga/ obj-y += hwmon/ obj-y += misc/ obj-y += pcmcia/ diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index dd42e0f766..9aa8ea9020 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -2,7 +2,7 @@ X86DIR = x86emu $(shell mkdir -p $(obj)$(X86DIR)) -obj-$(CONFIG_BIOSEMU) = atibios.o biosemu.o besys.o bios.o \ +obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/decode.o \ $(X86DIR)/ops2.o \ $(X86DIR)/ops.o \ diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 4fcdf40fd0..dfb2e7fc76 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -5,7 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_FPGA obj-y += fpga.o obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o @@ -19,4 +18,3 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o endif -endif -- cgit v1.2.1 From 164922bd7c383a2c82739f8b080b2e0da801ec0d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:52 +0900 Subject: lib: descend into sub directories only when it is necessary Signed-off-by: Masahiro Yamada --- Makefile | 8 ++++---- lib/lzma/Makefile | 2 +- lib/lzo/Makefile | 2 +- lib/rsa/Makefile | 4 +--- lib/zlib/Makefile | 2 +- 5 files changed, 8 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index 1f499c5ec8..e12f1807f4 100644 --- a/Makefile +++ b/Makefile @@ -232,10 +232,10 @@ OBJS := $(addprefix $(obj),$(OBJS)) HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n) LIBS-y += lib/libgeneric.o -LIBS-y += lib/rsa/librsa.o -LIBS-y += lib/lzma/liblzma.o -LIBS-y += lib/lzo/liblzo.o -LIBS-y += lib/zlib/libz.o +LIBS-$(CONFIG_RSA) += lib/rsa/librsa.o +LIBS-$(CONFIG_LZMA) += lib/lzma/liblzma.o +LIBS-$(CONFIG_LZO) += lib/lzo/liblzo.o +LIBS-$(CONFIG_ZLIB) += lib/zlib/libz.o LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o LIBS-y += $(CPUDIR)/lib$(CPU).o diff --git a/lib/lzma/Makefile b/lib/lzma/Makefile index 25c6797fb6..f8eda06c9f 100644 --- a/lib/lzma/Makefile +++ b/lib/lzma/Makefile @@ -10,4 +10,4 @@ CFLAGS += -D_LZMA_PROB32 -obj-$(CONFIG_LZMA) += LzmaDec.o LzmaTools.o +obj-y += LzmaDec.o LzmaTools.o diff --git a/lib/lzo/Makefile b/lib/lzo/Makefile index dd853eae23..2936544abc 100644 --- a/lib/lzo/Makefile +++ b/lib/lzo/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_LZO) += lzo1x_decompress.o +obj-y += lzo1x_decompress.o diff --git a/lib/rsa/Makefile b/lib/rsa/Makefile index 693c745514..164ab39964 100644 --- a/lib/rsa/Makefile +++ b/lib/rsa/Makefile @@ -7,6 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_FIT_SIGNATURE -obj-$(CONFIG_RSA) += rsa-verify.o -endif +obj-$(CONFIG_FIT_SIGNATURE) += rsa-verify.o diff --git a/lib/zlib/Makefile b/lib/zlib/Makefile index 1e9e04d991..2fba95f438 100644 --- a/lib/zlib/Makefile +++ b/lib/zlib/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ZLIB) += zlib.o +obj-y += zlib.o -- cgit v1.2.1 From 36cf0a845c869c514a6cc20a953c53a086251d2f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:53 +0900 Subject: drivers: tpm: clean up unused code Signed-off-by: Masahiro Yamada --- drivers/tpm/Makefile | 2 - drivers/tpm/tis_i2c.c | 185 -------------------------------------------------- 2 files changed, 187 deletions(-) delete mode 100644 drivers/tpm/tis_i2c.c diff --git a/drivers/tpm/Makefile b/drivers/tpm/Makefile index 4b8cbecaf9..2f2353f809 100644 --- a/drivers/tpm/Makefile +++ b/drivers/tpm/Makefile @@ -3,8 +3,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)slb9635_i2c) - # TODO: Merge tpm_tis_lpc.c with tpm.c obj-$(CONFIG_TPM_ATMEL_TWI) += tpm_atmel_twi.o obj-$(CONFIG_TPM_TIS_I2C) += tpm.o diff --git a/drivers/tpm/tis_i2c.c b/drivers/tpm/tis_i2c.c deleted file mode 100644 index 22554e1456..0000000000 --- a/drivers/tpm/tis_i2c.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include -#include -#include -#include -#include "slb9635_i2c/tpm.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* TPM configuration */ -struct tpm { - int i2c_bus; - int slave_addr; - char inited; - int old_bus; -} tpm; - - -static int tpm_select(void) -{ - int ret; - - tpm.old_bus = i2c_get_bus_num(); - if (tpm.old_bus != tpm.i2c_bus) { - ret = i2c_set_bus_num(tpm.i2c_bus); - if (ret) { - debug("%s: Fail to set i2c bus %d\n", __func__, - tpm.i2c_bus); - return -1; - } - } - return 0; -} - -static int tpm_deselect(void) -{ - int ret; - - if (tpm.old_bus != i2c_get_bus_num()) { - ret = i2c_set_bus_num(tpm.old_bus); - if (ret) { - debug("%s: Fail to restore i2c bus %d\n", - __func__, tpm.old_bus); - return -1; - } - } - tpm.old_bus = -1; - return 0; -} - -/** - * Decode TPM configuration. - * - * @param dev Returns a configuration of TPM device - * @return 0 if ok, -1 on error - */ -static int tpm_decode_config(struct tpm *dev) -{ -#ifdef CONFIG_OF_CONTROL - const void *blob = gd->fdt_blob; - int node, parent; - int i2c_bus; - - node = fdtdec_next_compatible(blob, 0, COMPAT_INFINEON_SLB9635_TPM); - if (node < 0) { - node = fdtdec_next_compatible(blob, 0, - COMPAT_INFINEON_SLB9645_TPM); - } - if (node < 0) { - debug("%s: Node not found\n", __func__); - return -1; - } - parent = fdt_parent_offset(blob, node); - if (parent < 0) { - debug("%s: Cannot find node parent\n", __func__); - return -1; - } - i2c_bus = i2c_get_bus_num_fdt(parent); - if (i2c_bus < 0) - return -1; - dev->i2c_bus = i2c_bus; - dev->slave_addr = fdtdec_get_addr(blob, node, "reg"); -#else - dev->i2c_bus = CONFIG_INFINEON_TPM_I2C_BUS; - dev->slave_addr = CONFIG_INFINEON_TPM_I2C_ADDR; -#endif - return 0; -} - -int tis_init(void) -{ - if (tpm.inited) - return 0; - - if (tpm_decode_config(&tpm)) - return -1; - - if (tpm_select()) - return -1; - - /* - * Probe TPM twice; the first probing might fail because TPM is asleep, - * and the probing can wake up TPM. - */ - if (i2c_probe(tpm.slave_addr) && i2c_probe(tpm.slave_addr)) { - debug("%s: fail to probe i2c addr 0x%x\n", __func__, - tpm.slave_addr); - return -1; - } - - tpm_deselect(); - - tpm.inited = 1; - - return 0; -} - -int tis_open(void) -{ - int rc; - - if (!tpm.inited) - return -1; - - if (tpm_select()) - return -1; - - rc = tpm_open(tpm.slave_addr); - - tpm_deselect(); - - return rc; -} - -int tis_close(void) -{ - if (!tpm.inited) - return -1; - - if (tpm_select()) - return -1; - - tpm_close(); - - tpm_deselect(); - - return 0; -} - -int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, - uint8_t *recvbuf, size_t *rbuf_len) -{ - int len; - uint8_t buf[4096]; - - if (!tpm.inited) - return -1; - - if (sizeof(buf) < sbuf_size) - return -1; - - memcpy(buf, sendbuf, sbuf_size); - - if (tpm_select()) - return -1; - - len = tpm_transmit(buf, sbuf_size); - - tpm_deselect(); - - if (len < 10) { - *rbuf_len = 0; - return -1; - } - - memcpy(recvbuf, buf, len); - *rbuf_len = len; - - return 0; -} -- cgit v1.2.1 From e5c5301f1444ea454d17a368bb5138e0f3a59247 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:54 +0900 Subject: Makefile: make directories by Makefile.build Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc512x/Makefile | 2 -- arch/powerpc/cpu/mpc824x/Makefile | 4 ---- board/LaCie/edminiv2/Makefile | 4 ---- board/LaCie/net2big_v2/Makefile | 4 ---- board/LaCie/netspace_v2/Makefile | 4 ---- board/LaCie/wireless_space/Makefile | 4 ---- board/Marvell/db64360/Makefile | 4 ---- board/Marvell/db64460/Makefile | 4 ---- board/altera/nios2-generic/Makefile | 4 ---- board/avionic-design/medcom-wide/Makefile | 2 -- board/avionic-design/plutux/Makefile | 2 -- board/avionic-design/tec/Makefile | 2 -- board/compal/paz00/Makefile | 2 -- board/compulab/trimslice/Makefile | 2 -- board/emk/top5200/Makefile | 4 ---- board/emk/top860/Makefile | 3 --- board/esd/adciop/Makefile | 4 ---- board/esd/apc405/Makefile | 4 ---- board/esd/ar405/Makefile | 4 ---- board/esd/ash405/Makefile | 4 ---- board/esd/cms700/Makefile | 4 ---- board/esd/cpci2dp/Makefile | 4 ---- board/esd/cpci405/Makefile | 4 ---- board/esd/cpci5200/Makefile | 4 ---- board/esd/cpci750/Makefile | 4 ---- board/esd/cpciiser4/Makefile | 4 ---- board/esd/dasa_sim/Makefile | 4 ---- board/esd/dp405/Makefile | 4 ---- board/esd/du405/Makefile | 4 ---- board/esd/hh405/Makefile | 4 ---- board/esd/hub405/Makefile | 4 ---- board/esd/ocrtc/Makefile | 4 ---- board/esd/pci405/Makefile | 4 ---- board/esd/pf5200/Makefile | 4 ---- board/esd/plu405/Makefile | 4 ---- board/esd/pmc405/Makefile | 4 ---- board/esd/pmc405de/Makefile | 4 ---- board/esd/pmc440/Makefile | 4 ---- board/esd/voh405/Makefile | 4 ---- board/esd/vom405/Makefile | 4 ---- board/esd/wuh405/Makefile | 4 ---- board/keymile/km82xx/Makefile | 3 --- board/keymile/km83xx/Makefile | 4 ---- board/keymile/km_arm/Makefile | 4 ---- board/keymile/kmp204x/Makefile | 4 ---- board/kup/kup4k/Makefile | 4 ---- board/kup/kup4x/Makefile | 4 ---- board/mpl/mip405/Makefile | 4 ---- board/mpl/pati/Makefile | 4 ---- board/mpl/pip405/Makefile | 4 ---- board/mpl/vcma9/Makefile | 4 ---- board/nvidia/beaver/Makefile | 2 -- board/nvidia/ventana/Makefile | 2 -- board/prodrive/p3mx/Makefile | 4 ---- board/psyent/pci5441/Makefile | 4 ---- board/psyent/pk1c20/Makefile | 4 ---- board/sandburst/karef/Makefile | 4 ---- board/sandburst/metrobox/Makefile | 4 ---- board/siemens/dxr2/Makefile | 4 ---- board/siemens/pxm2/Makefile | 4 ---- board/siemens/rut/Makefile | 4 ---- board/toradex/colibri_t20_iris/Makefile | 3 --- board/tqc/tqm8260/Makefile | 4 ---- board/tqc/tqm8272/Makefile | 4 ---- board/xilinx/ppc405-generic/Makefile | 4 ---- board/xilinx/ppc440-generic/Makefile | 4 ---- drivers/bios_emulator/Makefile | 2 -- scripts/Makefile.build | 7 +++++++ 68 files changed, 7 insertions(+), 247 deletions(-) diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index f770350dc2..a4934ef78a 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -4,8 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(OBJTREE)/board/freescale/common) - extra-y = start.o obj-y := cpu.o obj-y += traps.o diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile index 67b0d1713c..194fadd0c0 100644 --- a/arch/powerpc/cpu/mpc824x/Makefile +++ b/arch/powerpc/cpu/mpc824x/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)drivers/epic $(obj)drivers/i2c) -endif - extra-y = start.o obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \ drivers/epic/epic1.o drivers/i2c/i2c.o pci.o diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile index 7ca06f5a79..035f6865d9 100644 --- a/board/LaCie/edminiv2/Makefile +++ b/board/LaCie/edminiv2/Makefile @@ -9,8 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := edminiv2.o ../common/common.o diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile index 4fa08c5138..f3074af256 100644 --- a/board/LaCie/net2big_v2/Makefile +++ b/board/LaCie/net2big_v2/Makefile @@ -9,10 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := net2big_v2.o ../common/common.o ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),) obj-y += ../common/cpld-gpio-bus.o diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile index e5357e4bc3..47778d8472 100644 --- a/board/LaCie/netspace_v2/Makefile +++ b/board/LaCie/netspace_v2/Makefile @@ -9,8 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := netspace_v2.o ../common/common.o diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile index 11c535e99a..90a84f4892 100644 --- a/board/LaCie/wireless_space/Makefile +++ b/board/LaCie/wireless_space/Makefile @@ -9,8 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := wireless_space.o ../common/common.o diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile index aad4776b88..aefe0a789a 100644 --- a/board/Marvell/db64360/Makefile +++ b/board/Marvell/db64360/Makefile @@ -8,10 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ sdram_init.o ../common/intel_flash.o ../common/misc.o diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile index ea9e57086e..a970f9afde 100644 --- a/board/Marvell/db64460/Makefile +++ b/board/Marvell/db64460/Makefile @@ -8,10 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y += db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \ mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \ sdram_init.o ../common/intel_flash.o ../common/misc.o diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile index 84c7bff80f..84690fe04d 100644 --- a/board/altera/nios2-generic/Makefile +++ b/board/altera/nios2-generic/Makefile @@ -6,10 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := nios2-generic.o obj-$(CONFIG_CMD_IDE) += ../common/cfide.o obj-$(CONFIG_EPLED) += ../common/epled.o diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile index 6c4ab643ef..87e19123b0 100644 --- a/board/avionic-design/medcom-wide/Makefile +++ b/board/avionic-design/medcom-wide/Makefile @@ -7,8 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - obj-y := ../common/tamonten.o include ../../nvidia/common/common.mk diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index 6c4ab643ef..87e19123b0 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -7,8 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - obj-y := ../common/tamonten.o include ../../nvidia/common/common.mk diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index 6c4ab643ef..87e19123b0 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -7,8 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common) - obj-y := ../common/tamonten.o include ../../nvidia/common/common.mk diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index 824cd2ea1f..b2d3b6b4b2 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -14,8 +14,6 @@ # more details. # -$(shell mkdir -p $(obj)../../nvidia/common) - obj-y := paz00.o include ../../nvidia/common/common.mk diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index 0818673cbd..f3bd00dbf1 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../../nvidia/common) - obj-y := trimslice.o include ../../nvidia/common/common.mk diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile index 0930d484fb..b455c26e17 100644 --- a/board/emk/top5200/Makefile +++ b/board/emk/top5200/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile index b2645f6347..0401639ce3 100644 --- a/board/emk/top860/Makefile +++ b/board/emk/top860/Makefile @@ -5,7 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif obj-y = top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile index a096e44418..d0e264de92 100644 --- a/board/esd/adciop/Makefile +++ b/board/esd/adciop/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = adciop.o flash.o ../common/misc.o ../common/pci.o diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile index c6ab1a5e21..ada8bfd3d3 100644 --- a/board/esd/apc405/Makefile +++ b/board/esd/apc405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = apc405.o \ ../common/misc.o \ ../common/auto_update.o diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile index 2d16313e8d..dd54f546a6 100644 --- a/board/esd/ar405/Makefile +++ b/board/esd/ar405/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = ar405.o flash.o ../common/misc.o diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile index 4c866ee0aa..aab8de44bc 100644 --- a/board/esd/ash405/Makefile +++ b/board/esd/ash405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = ash405.o flash.o \ ../common/misc.o \ ../common/esd405ep_nand.o \ diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile index 8cfe3baf79..2bf50066c4 100644 --- a/board/esd/cms700/Makefile +++ b/board/esd/cms700/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif - # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile index 1d1502071e..ce2c6dd912 100644 --- a/board/esd/cpci2dp/Makefile +++ b/board/esd/cpci2dp/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile index 1af7e9454d..b140571796 100644 --- a/board/esd/cpci405/Makefile +++ b/board/esd/cpci405/Makefile @@ -5,9 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = cpci405.o flash.o ../common/misc.o ../common/auto_update.o obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile index fb6c0e20e4..8421f54869 100644 --- a/board/esd/cpci5200/Makefile +++ b/board/esd/cpci5200/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# ifneq ($(OBJTREE),$(SRCTREE)) -# $(shell mkdir -p $(obj)../common/xilinx_jtag) -# endif - # Objects for Xilinx JTAG programming (CPLD) # CPLD = ../common/xilinx_jtag/lenval.o \ # ../common/xilinx_jtag/micro.o \ diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile index 8b3dc33704..a3300c9f4a 100644 --- a/board/esd/cpci750/Makefile +++ b/board/esd/cpci750/Makefile @@ -8,10 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../Marvell/common) -endif - obj-y = misc.o obj-y += cpci750.o serial.o ../../Marvell/common/memory.o pci.o \ mv_eth.o mpsc.o i2c.o \ diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile index 4d3c34ae42..b8d6bea6dc 100644 --- a/board/esd/cpciiser4/Makefile +++ b/board/esd/cpciiser4/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = cpciiser4.o flash.o ../common/misc.o diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile index f0a5a8f09b..eb9f5f86d0 100644 --- a/board/esd/dasa_sim/Makefile +++ b/board/esd/dasa_sim/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = dasa_sim.o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile index 6809c673ce..cfcfb66a15 100644 --- a/board/esd/dp405/Makefile +++ b/board/esd/dp405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif - # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile index 12ce41a9a8..7914eab355 100644 --- a/board/esd/du405/Makefile +++ b/board/esd/du405/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = du405.o flash.o ../common/misc.o diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile index 0507f1b4dd..fba21a3ae2 100644 --- a/board/esd/hh405/Makefile +++ b/board/esd/hh405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = hh405.o flash.o \ ../common/misc.o \ ../common/esd405ep_nand.o \ diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile index 5447a959c0..99e18b567f 100644 --- a/board/esd/hub405/Makefile +++ b/board/esd/hub405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = hub405.o flash.o \ ../common/misc.o \ ../common/esd405ep_nand.o \ diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile index 0d9a6fdc43..44b7d5d072 100644 --- a/board/esd/ocrtc/Makefile +++ b/board/esd/ocrtc/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile index 2f8706bd6e..9e659c796c 100644 --- a/board/esd/pci405/Makefile +++ b/board/esd/pci405/Makefile @@ -5,9 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o obj-y += writeibm.o diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile index a9d20c90b1..a54289c073 100644 --- a/board/esd/pf5200/Makefile +++ b/board/esd/pf5200/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -# ifneq ($(OBJTREE),$(SRCTREE)) -# $(shell mkdir -p $(obj)../common/xilinx_jtag) -# endif - # Objects for Xilinx JTAG programming (CPLD) # CPLD = ../common/xilinx_jtag/lenval.o \ # ../common/xilinx_jtag/micro.o \ diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile index 45b962f69a..6ffae677b1 100644 --- a/board/esd/plu405/Makefile +++ b/board/esd/plu405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = plu405.o flash.o \ ../common/misc.o \ ../common/esd405ep_nand.o \ diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile index f4aa1c9eea..ad98207f3e 100644 --- a/board/esd/pmc405/Makefile +++ b/board/esd/pmc405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif - # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile index 7d5b273c0f..b3f6dcd1e7 100644 --- a/board/esd/pmc405de/Makefile +++ b/board/esd/pmc405de/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = pmc405de.o obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o obj-y += ../common/cmd_loadpci.o diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile index b1318c7429..708e9d138e 100644 --- a/board/esd/pmc440/Makefile +++ b/board/esd/pmc440/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \ ../common/cmd_loadpci.o extra-y += init.o diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile index 8fcfa37dc0..3d82399ed1 100644 --- a/board/esd/voh405/Makefile +++ b/board/esd/voh405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = voh405.o flash.o \ ../common/misc.o \ ../common/esd405ep_nand.o \ diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile index c8a4a4e4c7..7cf5c0224c 100644 --- a/board/esd/vom405/Makefile +++ b/board/esd/vom405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common/xilinx_jtag) -endif - # Objects for Xilinx JTAG programming (CPLD) CPLD = ../common/xilinx_jtag/lenval.o \ ../common/xilinx_jtag/micro.o \ diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile index 046ebad301..b9beeffc57 100644 --- a/board/esd/wuh405/Makefile +++ b/board/esd/wuh405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = wuh405.o flash.o \ ../common/misc.o \ ../common/esd405ep_nand.o \ diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile index b44582fbea..20f193ab1d 100644 --- a/board/keymile/km82xx/Makefile +++ b/board/keymile/km82xx/Makefile @@ -5,7 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif obj-y := km82xx.o ../common/common.o ../common/ivm.o diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile index 7bdddf3bc3..6c3268853e 100644 --- a/board/keymile/km83xx/Makefile +++ b/board/keymile/km83xx/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile index 32eaa9357f..a17d8d963a 100644 --- a/board/keymile/km_arm/Makefile +++ b/board/keymile/km_arm/Makefile @@ -6,10 +6,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := km_arm.o ../common/common.o ../common/ivm.o ifdef CONFIG_KM_FPGA_CONFIG diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile index c318e08a59..3e69ee2f15 100644 --- a/board/keymile/kmp204x/Makefile +++ b/board/keymile/kmp204x/Makefile @@ -8,9 +8,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \ ../common/common.o ../common/ivm.o diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile index b3ad86ce18..c896fcd64d 100644 --- a/board/kup/kup4k/Makefile +++ b/board/kup/kup4k/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = kup4k.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile index 05a1afc3a9..6945943d09 100644 --- a/board/kup/kup4x/Makefile +++ b/board/kup/kup4x/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = kup4x.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile index 509eb591b3..5bcf130501 100644 --- a/board/mpl/mip405/Makefile +++ b/board/mpl/mip405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = mip405.o cmd_mip405.o \ ../common/pci.o \ ../common/usb_uhci.o \ diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile index 67381c108a..9822082612 100644 --- a/board/mpl/pati/Makefile +++ b/board/mpl/pati/Makefile @@ -5,9 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := pati.o cmd_pati.o \ ../common/common_util.o diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile index 3d73cc3f8d..0a3d059e9c 100644 --- a/board/mpl/pip405/Makefile +++ b/board/mpl/pip405/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y = pip405.o cmd_pip405.o \ ../common/pci.o \ ../common/isa.o \ diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index e0e96691c5..175a19fa36 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := ../common/common_util.o obj-y += vcma9.o cmd_vcma9.o diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile index f828f52c25..1f7c31d64b 100644 --- a/board/nvidia/beaver/Makefile +++ b/board/nvidia/beaver/Makefile @@ -14,6 +14,4 @@ # along with this program. If not, see . # -$(shell mkdir -p $(obj)../cardhu) - obj-y = ../cardhu/cardhu.o diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile index 7265cfcccc..f67044f2cf 100644 --- a/board/nvidia/ventana/Makefile +++ b/board/nvidia/ventana/Makefile @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../seaboard) - obj-y = ../seaboard/seaboard.o diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile index 43caffbc22..6ddda2296d 100644 --- a/board/prodrive/p3mx/Makefile +++ b/board/prodrive/p3mx/Makefile @@ -5,10 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../Marvell/common) -endif - obj-y = misc.o obj-y += p3mx.o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \ ../../Marvell/common/i2c.o ../../Marvell/common/memory.o diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile index 9a66cfdfe8..364f163e4f 100644 --- a/board/psyent/pci5441/Makefile +++ b/board/psyent/pci5441/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := pci5441.o ../common/AMDLV065D.o diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile index 286db94aef..5450f93ac3 100644 --- a/board/psyent/pk1c20/Makefile +++ b/board/psyent/pk1c20/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - obj-y := pk1c20.o led.o ../common/AMDLV065D.o diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile index 05c818791c..f890008be2 100644 --- a/board/sandburst/karef/Makefile +++ b/board/sandburst/karef/Makefile @@ -9,10 +9,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - # TBS: add for debugging purposes BUILDUSER := $(shell whoami) FORCEBUILD := $(shell rm -f karef.o) diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile index 76dfffc9c7..37d91a51a3 100644 --- a/board/sandburst/metrobox/Makefile +++ b/board/sandburst/metrobox/Makefile @@ -8,10 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - # TBS: add for debugging purposes BUILDUSER := $(shell whoami) FORCEBUILD := $(shell rm -f metrobox.o) diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile index 5129c6e3b1..f15993216b 100644 --- a/board/siemens/dxr2/Makefile +++ b/board/siemens/dxr2/Makefile @@ -11,10 +11,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - ifdef CONFIG_SPL_BUILD obj-y := mux.o endif diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile index 5129c6e3b1..f15993216b 100644 --- a/board/siemens/pxm2/Makefile +++ b/board/siemens/pxm2/Makefile @@ -11,10 +11,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - ifdef CONFIG_SPL_BUILD obj-y := mux.o endif diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile index 5129c6e3b1..f15993216b 100644 --- a/board/siemens/rut/Makefile +++ b/board/siemens/rut/Makefile @@ -11,10 +11,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -endif - ifdef CONFIG_SPL_BUILD obj-y := mux.o endif diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile index 7ca3fe596f..ebeac70ea1 100644 --- a/board/toradex/colibri_t20_iris/Makefile +++ b/board/toradex/colibri_t20_iris/Makefile @@ -4,9 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -$(shell mkdir -p $(obj)../../nvidia/common) -$(shell mkdir -p $(obj)../colibri_t20-common) - obj-y := ../../nvidia/common/board.o obj-y += ../colibri_t20-common/colibri_t20-common.o obj-y += colibri_t20_iris.o diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile index dc4a528083..6b8573d9ab 100644 --- a/board/tqc/tqm8260/Makefile +++ b/board/tqc/tqm8260/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../tqm8xx/) -endif - obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile index 09af765f05..8bf02414e3 100644 --- a/board/tqc/tqm8272/Makefile +++ b/board/tqc/tqm8272/Makefile @@ -5,8 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../tqm8xx/) -endif - obj-y = tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile index 1562f1775e..c9da870657 100644 --- a/board/xilinx/ppc405-generic/Makefile +++ b/board/xilinx/ppc405-generic/Makefile @@ -9,8 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../xilinx/ppc405-generic) -endif - obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile index b2227c58a5..0acd95d6e4 100644 --- a/board/xilinx/ppc440-generic/Makefile +++ b/board/xilinx/ppc440-generic/Makefile @@ -9,9 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../../xilinx/ppc440-generic) -endif - obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o extra-y += ../../xilinx/ppc440-generic/init.o diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 9aa8ea9020..6f74fdc230 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -1,7 +1,5 @@ X86DIR = x86emu -$(shell mkdir -p $(obj)$(X86DIR)) - obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/decode.o \ $(X86DIR)/ops2.o \ diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 805c3c3e3a..e3354aaa3f 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -24,6 +24,13 @@ SRCS += $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \ $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S)) OBJS := $(addprefix $(obj),$(obj-y)) +# $(obj-dirs) is a list of directories that contain object files +obj-dirs := $(dir $(OBJS)) + +# Create directories for object files if directory does not exist +# Needed when obj-y := dir/file.o syntax is used +_dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d))) + LGOBJS := $(addprefix $(obj),$(sort $(lib-y))) all: $(LIB) $(addprefix $(obj),$(extra-y)) -- cgit v1.2.1 From 08e39a8434ff22d3851c1f9326b0e9afa5de0bee Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:55 +0900 Subject: Makefile: merge $(LIBBOARD) into $(LIBS) We do not need to handle $(LIBBOARD) and $(LIBS) separately. Signed-off-by: Masahiro Yamada --- Makefile | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index e12f1807f4..419278aad0 100644 --- a/Makefile +++ b/Makefile @@ -306,12 +306,11 @@ endif LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o +LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o + LIBS := $(addprefix $(obj),$(sort $(LIBS-y))) .PHONY : $(LIBS) -LIBBOARD = board/$(BOARDDIR)/lib$(BOARD).o -LIBBOARD := $(addprefix $(obj),$(LIBBOARD)) - # Add GCC lib ifdef USE_PRIVATE_LIBGCC ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") @@ -335,7 +334,7 @@ LDPPFLAGS += \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') __OBJS := $(subst $(obj),,$(OBJS)) -__LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) +__LIBS := $(subst $(obj),,$(LIBS)) ######################################################################### ######################################################################### @@ -549,7 +548,7 @@ GEN_UBOOT = \ endif $(obj)u-boot: depend \ - $(SUBDIR_TOOLS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds + $(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds $(GEN_UBOOT) ifeq ($(CONFIG_KALLSYMS),y) smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \ @@ -566,10 +565,6 @@ $(LIBS): depend $(SUBDIR_TOOLS) $(MAKE) $(build) $(dir $(subst $(obj),,$@)) mv $(dir $@)built-in.o $@ -$(LIBBOARD): depend $(LIBS) - $(MAKE) $(build) $(dir $(subst $(obj),,$@)) - mv $(dir $@)built-in.o $@ - $(SUBDIRS): depend $(MAKE) -C $@ all -- cgit v1.2.1 From c54ecaa965211c3f34004031b3574c069402dc8e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:56 +0900 Subject: powerpc: move mpc8xxx entry under arch/powerpc/cpu/ Signed-off-by: Masahiro Yamada --- Makefile | 9 +-------- arch/powerpc/cpu/Makefile | 3 +++ arch/powerpc/cpu/mpc8xxx/Makefile | 6 ++++++ spl/Makefile | 13 +------------ 4 files changed, 11 insertions(+), 20 deletions(-) create mode 100644 arch/powerpc/cpu/Makefile diff --git a/Makefile b/Makefile index 419278aad0..3a8ea6750e 100644 --- a/Makefile +++ b/Makefile @@ -273,18 +273,10 @@ LIBS-y += drivers/power/libpower.o \ LIBS-y += drivers/spi/libspi.o ifeq ($(CPU),mpc83xx) LIBS-y += drivers/qe/libqe.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o endif ifeq ($(CPU),mpc85xx) LIBS-y += drivers/qe/libqe.o LIBS-y += drivers/net/fm/libfm.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif -ifeq ($(CPU),mpc86xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o endif LIBS-y += drivers/serial/libserial.o LIBS-y += drivers/usb/eth/libusb_eth.o @@ -305,6 +297,7 @@ LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o +LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/libcpu.o LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o diff --git a/arch/powerpc/cpu/Makefile b/arch/powerpc/cpu/Makefile new file mode 100644 index 0000000000..d630abe1da --- /dev/null +++ b/arch/powerpc/cpu/Makefile @@ -0,0 +1,3 @@ +ifneq ($(filter mpc83xx mpc85xx mpc86xx,$(CPU)),) +obj-y += mpc8xxx/ +endif diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 395fed16b6..1d083bf354 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -31,3 +31,9 @@ obj-$(CONFIG_SYS_SRIO) += srio.o obj-$(CONFIG_FSL_LAW) += law.o endif + +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/ +else +obj-y += ddr/ +endif diff --git a/spl/Makefile b/spl/Makefile index cbd3d27849..0ac0c3c42e 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -57,18 +57,6 @@ endif LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o LIBS-y += $(CPUDIR)/lib$(CPU).o -ifeq ($(CPU),mpc83xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif -ifeq ($(CPU),mpc85xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -ifdef CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -LIBS-y += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o -endif -endif -ifeq ($(CPU),mpc86xx) -LIBS-y += arch/powerpc/cpu/mpc8xxx/lib8xxx.o -endif ifdef SOC LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o @@ -106,6 +94,7 @@ LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o +LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/libcpu.o ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o -- cgit v1.2.1 From 4c76b552313f3a12a38789afa828c6a7e9e71d7a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:57 +0900 Subject: drivers/qe: move the entry to drivers/Makefile Signed-off-by: Masahiro Yamada --- Makefile | 4 ---- drivers/Makefile | 1 + drivers/qe/Makefile | 4 ++-- 3 files changed, 3 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 3a8ea6750e..0e9609f69c 100644 --- a/Makefile +++ b/Makefile @@ -271,11 +271,7 @@ LIBS-y += drivers/power/libpower.o \ drivers/power/pmic/libpmic.o \ drivers/power/battery/libbattery.o LIBS-y += drivers/spi/libspi.o -ifeq ($(CPU),mpc83xx) -LIBS-y += drivers/qe/libqe.o -endif ifeq ($(CPU),mpc85xx) -LIBS-y += drivers/qe/libqe.o LIBS-y += drivers/net/fm/libfm.o endif LIBS-y += drivers/serial/libserial.o diff --git a/drivers/Makefile b/drivers/Makefile index 95a4b80724..5d03f37a18 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -13,3 +13,4 @@ obj-y += tpm/ obj-y += twserial/ obj-y += video/ obj-y += watchdog/ +obj-$(CONFIG_QE) += qe/ diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile index b8c15f8e1f..7f1bd06922 100644 --- a/drivers/qe/Makefile +++ b/drivers/qe/Makefile @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(and $(CONFIG_QE),$(CONFIG_OF_LIBFDT)) += fdt.o -obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o +obj-y := qe.o uccf.o uec.o uec_phy.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o -- cgit v1.2.1 From fc9ac3565a80d571def4f2eae4ad10c4ed90cbb2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:58 +0900 Subject: drivers/net/fm: descend only when CONFIG_FMAN_ENET=y CONFIG_FMAN_ENET is defined only for CPU mpc85xx. We do not need to filter by CPU mpc85xx. Signed-off-by: Masahiro Yamada --- Makefile | 4 +--- drivers/net/fm/Makefile | 2 -- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 0e9609f69c..5cdfc6dfea 100644 --- a/Makefile +++ b/Makefile @@ -271,9 +271,7 @@ LIBS-y += drivers/power/libpower.o \ drivers/power/pmic/libpmic.o \ drivers/power/battery/libbattery.o LIBS-y += drivers/spi/libspi.o -ifeq ($(CPU),mpc85xx) -LIBS-y += drivers/net/fm/libfm.o -endif +LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/libfm.o LIBS-y += drivers/serial/libserial.o LIBS-y += drivers/usb/eth/libusb_eth.o LIBS-y += drivers/usb/gadget/libusb_gadget.o diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 2efba7693e..d0fd7fccee 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -4,7 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_FMAN_ENET obj-y += dtsec.o obj-y += eth.o obj-y += fm.o @@ -33,4 +32,3 @@ obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o -endif -- cgit v1.2.1 From fdd91faef9148fd5a52467a91f79934ee4e7f2bd Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:35:59 +0900 Subject: drivers/net/npe: descend only when CONFIG_IXP4XX_NPE=y CONFIG_IXP4XX_NPE is defined only for CPU ixp. It is not necessary to filter by CPU ixp. Signed-off-by: Masahiro Yamada --- Makefile | 4 +--- drivers/net/npe/Makefile | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 5cdfc6dfea..4724f4171c 100644 --- a/Makefile +++ b/Makefile @@ -242,9 +242,7 @@ LIBS-y += $(CPUDIR)/lib$(CPU).o ifdef SOC LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o endif -ifeq ($(CPU),ixp) -LIBS-y += drivers/net/npe/libnpe.o -endif +LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/libnpe.o LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o LIBS-y += fs/libfs.o \ diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile index 7fa5ea635f..e36c0bbd69 100644 --- a/drivers/net/npe/Makefile +++ b/drivers/net/npe/Makefile @@ -10,7 +10,7 @@ CFLAGS += $(LOCAL_CFLAGS) CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend HOSTCFLAGS += $(LOCAL_CFLAGS) -obj-$(CONFIG_IXP4XX_NPE) := npe.o \ +obj-y := npe.o \ miiphy.o \ IxOsalBufferMgt.o \ IxOsalIoMem.o \ -- cgit v1.2.1 From e2906a5943f6a1a9e0d7ea2c71e605b88ee17ef0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:00 +0900 Subject: Makefile: rename all libraries to built-in.o Signed-off-by: Masahiro Yamada --- Makefile | 112 ++++++++++++++--------------- arch/microblaze/cpu/u-boot.lds | 2 +- board/LEOX/elpt860/u-boot.lds | 8 +-- board/actux1/u-boot.lds | 8 +-- board/actux2/u-boot.lds | 8 +-- board/actux3/u-boot.lds | 8 +-- board/davinci/da8xxevm/u-boot-spl-hawk.lds | 4 +- board/dvlhost/u-boot.lds | 8 +-- board/esteem192e/u-boot.lds | 4 +- board/freescale/m52277evb/u-boot.lds | 4 +- board/freescale/m53017evb/u-boot.lds | 6 +- board/freescale/mx31ads/u-boot.lds | 10 +-- board/genietv/u-boot.lds | 10 +-- board/hermes/u-boot.lds | 2 +- board/matrix_vision/mvsmr/u-boot.lds | 2 +- board/mvblue/u-boot.lds | 12 ++-- board/rbc823/u-boot.lds | 8 +-- board/spd8xx/u-boot.lds | 4 +- board/svm_sc8xx/u-boot.lds | 10 +-- board/ti/am335x/u-boot.lds | 2 +- board/tqc/tqm8xx/u-boot.lds | 14 ++-- board/vpac270/u-boot-spl.lds | 4 +- include/configs/bct-brettl2.h | 4 +- include/configs/bf533-stamp.h | 4 +- include/configs/bf537-pnav.h | 4 +- include/configs/bf537-stamp.h | 4 +- include/configs/bf538f-ezkit.h | 4 +- include/configs/cm-bf537e.h | 4 +- include/configs/cm-bf537u.h | 4 +- include/configs/dnp5370.h | 4 +- include/configs/ibf-dsp561.h | 4 +- include/configs/tcm-bf537.h | 4 +- spl/Makefile | 73 +++++++++---------- 33 files changed, 182 insertions(+), 181 deletions(-) diff --git a/Makefile b/Makefile index 4724f4171c..1389ee773e 100644 --- a/Makefile +++ b/Makefile @@ -231,68 +231,69 @@ OBJS := $(addprefix $(obj),$(OBJS)) HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n) -LIBS-y += lib/libgeneric.o -LIBS-$(CONFIG_RSA) += lib/rsa/librsa.o -LIBS-$(CONFIG_LZMA) += lib/lzma/liblzma.o -LIBS-$(CONFIG_LZO) += lib/lzo/liblzo.o -LIBS-$(CONFIG_ZLIB) += lib/zlib/libz.o -LIBS-$(CONFIG_TIZEN) += lib/tizen/libtizen.o -LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o -LIBS-y += $(CPUDIR)/lib$(CPU).o +LIBS-y += lib/ +LIBS-$(CONFIG_RSA) += lib/rsa/ +LIBS-$(CONFIG_LZMA) += lib/lzma/ +LIBS-$(CONFIG_LZO) += lib/lzo/ +LIBS-$(CONFIG_ZLIB) += lib/zlib/ +LIBS-$(CONFIG_TIZEN) += lib/tizen/ +LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ +LIBS-y += $(CPUDIR)/ ifdef SOC -LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o -endif -LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/libnpe.o -LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o -LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o -LIBS-y += fs/libfs.o \ - fs/fat/libfat.o -LIBS-y += net/libnet.o -LIBS-y += disk/libdisk.o -LIBS-y += drivers/libdrivers.o -LIBS-y += drivers/dma/libdma.o -LIBS-y += drivers/gpio/libgpio.o -LIBS-y += drivers/i2c/libi2c.o -LIBS-y += drivers/input/libinput.o -LIBS-y += drivers/mmc/libmmc.o -LIBS-y += drivers/mtd/libmtd.o -LIBS-y += drivers/mtd/nand/libnand.o -LIBS-y += drivers/mtd/onenand/libonenand.o -LIBS-y += drivers/mtd/ubi/libubi.o -LIBS-y += drivers/mtd/spi/libspi_flash.o -LIBS-y += drivers/net/libnet.o -LIBS-y += drivers/net/phy/libphy.o -LIBS-y += drivers/pci/libpci.o -LIBS-y += drivers/power/libpower.o \ - drivers/power/fuel_gauge/libfuel_gauge.o \ - drivers/power/mfd/libmfd.o \ - drivers/power/pmic/libpmic.o \ - drivers/power/battery/libbattery.o -LIBS-y += drivers/spi/libspi.o -LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/libfm.o -LIBS-y += drivers/serial/libserial.o -LIBS-y += drivers/usb/eth/libusb_eth.o -LIBS-y += drivers/usb/gadget/libusb_gadget.o -LIBS-y += drivers/usb/host/libusb_host.o -LIBS-y += drivers/usb/musb/libusb_musb.o -LIBS-y += drivers/usb/musb-new/libusb_musb-new.o -LIBS-y += drivers/usb/phy/libusb_phy.o -LIBS-y += drivers/usb/ulpi/libusb_ulpi.o -LIBS-y += common/libcommon.o -LIBS-y += lib/libfdt/libfdt.o -LIBS-y += api/libapi.o -LIBS-y += post/libpost.o -LIBS-y += test/libtest.o +LIBS-y += $(CPUDIR)/$(SOC)/ +endif +LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/ +LIBS-$(CONFIG_OF_EMBED) += dts/ +LIBS-y += arch/$(ARCH)/lib/ +LIBS-y += fs/ \ + fs/fat/ +LIBS-y += net/ +LIBS-y += disk/ +LIBS-y += drivers/ +LIBS-y += drivers/dma/ +LIBS-y += drivers/gpio/ +LIBS-y += drivers/i2c/ +LIBS-y += drivers/input/ +LIBS-y += drivers/mmc/ +LIBS-y += drivers/mtd/ +LIBS-y += drivers/mtd/nand/ +LIBS-y += drivers/mtd/onenand/ +LIBS-y += drivers/mtd/ubi/ +LIBS-y += drivers/mtd/spi/ +LIBS-y += drivers/net/ +LIBS-y += drivers/net/phy/ +LIBS-y += drivers/pci/ +LIBS-y += drivers/power/ \ + drivers/power/fuel_gauge/ \ + drivers/power/mfd/ \ + drivers/power/pmic/ \ + drivers/power/battery/ +LIBS-y += drivers/spi/ +LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/ +LIBS-y += drivers/serial/ +LIBS-y += drivers/usb/eth/ +LIBS-y += drivers/usb/gadget/ +LIBS-y += drivers/usb/host/ +LIBS-y += drivers/usb/musb/ +LIBS-y += drivers/usb/musb-new/ +LIBS-y += drivers/usb/phy/ +LIBS-y += drivers/usb/ulpi/ +LIBS-y += common/ +LIBS-y += lib/libfdt/ +LIBS-y += api/ +LIBS-y += post/ +LIBS-y += test/ ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) -LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o +LIBS-y += arch/$(ARCH)/imx-common/ endif -LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o -LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/libcpu.o +LIBS-$(CONFIG_ARM) += arch/arm/cpu/ +LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/ -LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o +LIBS-y += board/$(BOARDDIR)/ +LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y)) LIBS := $(addprefix $(obj),$(sort $(LIBS-y))) .PHONY : $(LIBS) @@ -548,7 +549,6 @@ $(OBJS): $(LIBS): depend $(SUBDIR_TOOLS) $(MAKE) $(build) $(dir $(subst $(obj),,$@)) - mv $(dir $@)built-in.o $@ $(SUBDIRS): depend $(MAKE) -C $@ all diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds index 3e6204de32..fdad20753d 100644 --- a/arch/microblaze/cpu/u-boot.lds +++ b/arch/microblaze/cpu/u-boot.lds @@ -30,7 +30,7 @@ SECTIONS { __data_start = .; #ifdef CONFIG_OF_EMBED - dts/libdts.o (.data) + dts/built-in.o (.data) #endif *(.data) __data_end = .; diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index b30b667eb9..c5e57ec03b 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -30,10 +30,10 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - common/libcommon.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - board/LEOX/elpt860/libelpt860.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) + common/built-in.o (.text*) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) + board/LEOX/elpt860/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) . = env_offset; common/env_embedded.o (.text*) diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index a656fa99d1..b0f09f592e 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -16,10 +16,10 @@ SECTIONS .text : { *(.__image_copy_start) arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/actux1/libactux1.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/input/libinput.o(.text*) + net/built-in.o(.text*) + board/actux1/built-in.o(.text*) + arch/arm/cpu/ixp/built-in.o(.text*) + drivers/input/built-in.o(.text*) . = env_offset; common/env_embedded.o(.ppcenv) diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 7a1717640a..d84934e1f8 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -16,10 +16,10 @@ SECTIONS .text : { *(.__image_copy_start) arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/actux2/libactux2.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/input/libinput.o(.text*) + net/built-in.o(.text*) + board/actux2/built-in.o(.text*) + arch/arm/cpu/ixp/built-in.o(.text*) + drivers/input/built-in.o(.text*) . = env_offset; common/env_embedded.o(.ppcenv) diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index aadfdd2f57..30c204b646 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -16,10 +16,10 @@ SECTIONS .text : { *(.__image_copy_start) arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/actux3/libactux3.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/input/libinput.o(.text*) + net/built-in.o(.text*) + board/actux3/built-in.o(.text*) + arch/arm/cpu/ixp/built-in.o(.text*) + drivers/input/built-in.o(.text*) . = env_offset; common/env_embedded.o(.ppcenv) diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index e43130aa67..d49c314490 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -19,8 +19,8 @@ SECTIONS .text : { arch/arm/cpu/arm926ejs/start.o (.text*) - arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*) - drivers/mtd/nand/libnand.o (.text*) + arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*) + drivers/mtd/nand/built-in.o (.text*) *(.text*) } diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 40c9c8038b..0035a0bf07 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -16,10 +16,10 @@ SECTIONS .text : { *(.__image_copy_start) arch/arm/cpu/ixp/start.o(.text*) - net/libnet.o(.text*) - board/dvlhost/libdvlhost.o(.text*) - arch/arm/cpu/ixp/libixp.o(.text*) - drivers/serial/libserial.o(.text*) + net/built-in.o(.text*) + board/dvlhost/built-in.o(.text*) + arch/arm/cpu/ixp/built-in.o(.text*) + drivers/serial/built-in.o(.text*) . = env_offset; common/env_embedded.o(.ppcenv) diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 87642d6b40..59a86bfdc0 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -18,8 +18,8 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - net/libnet.o (.text*) - board/esteem192e/libesteem192e.o (.text*) + net/built-in.o (.text*) + board/esteem192e/built-in.o (.text*) . = env_offset; common/env_embedded.o (.text*) diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index f3337a3845..70121d9248 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -13,8 +13,8 @@ SECTIONS .text : { arch/m68k/cpu/mcf5227x/start.o (.text*) - arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*) - arch/m68k/lib/libm68k.o (.text*) + arch/m68k/cpu/mcf5227x/built-in.o (.text*) + arch/m68k/lib/built-in.o (.text*) *(.text*) } diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index ef21299ea9..de8d09bf66 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -12,9 +12,9 @@ SECTIONS /* Read-only sections, merged into text segment: */ .text : { - arch/m68k/cpu/mcf532x/start.o (.text*) - arch/m68k/cpu/mcf532x/libmcf532x.o (.text*) - arch/m68k/lib/libm68k.o (.text*) + arch/m68k/cpu/mcf532x/start.o (.text*) + arch/m68k/cpu/mcf532x/built-in.o (.text*) + arch/m68k/lib/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.text*) diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 3acc4ca548..8d5cc9101a 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -22,11 +22,11 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/arm/cpu/arm1136/start.o (.text*) - board/freescale/mx31ads/libmx31ads.o (.text*) - arch/arm/lib/libarm.o (.text*) - net/libnet.o (.text*) - drivers/mtd/libmtd.o (.text*) + arch/arm/cpu/arm1136/start.o (.text*) + board/freescale/mx31ads/built-in.o (.text*) + arch/arm/lib/built-in.o (.text*) + net/built-in.o (.text*) + drivers/mtd/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o(.text*) diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index e217f06819..70ab702fd9 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -18,11 +18,11 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - board/genietv/libgenietv.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) + lib/built-in.o (.text*) + net/built-in.o (.text*) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) + board/genietv/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) *(.text.do_load_serial*) *(.text.do_mem_*) *(.text.do_bootm*) diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index 9419f83a70..0309860391 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -17,7 +17,7 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - board/hermes/libhermes.o (.text*) + board/hermes/built-in.o (.text*) . = env_offset; common/env_embedded.o (.text*) diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 08ce014aac..e885b7c160 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -18,7 +18,7 @@ SECTIONS /* the first two sectors (=8KB) of our S29GL flash chip */ arch/powerpc/cpu/mpc5xxx/start.o (.text*) arch/powerpc/cpu/mpc5xxx/traps.o (.text*) - board/matrix_vision/common/libmatrix_vision.o (.text*) + board/matrix_vision/common/built-in.o (.text*) /* This is only needed to force failure if size of above code will ever */ /* increase and grow into reserved space. */ diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds index 121354bfeb..5034a9675a 100644 --- a/board/mvblue/u-boot.lds +++ b/board/mvblue/u-boot.lds @@ -14,12 +14,12 @@ SECTIONS .text : { arch/powerpc/cpu/mpc824x/start.o (.text*) - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - drivers/pci/libpci.o (.text*) - arch/powerpc/cpu/mpc824x/libmpc824x.o (.text*) - board/mvblue/libmvblue.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) + lib/built-in.o (.text*) + net/built-in.o (.text*) + drivers/pci/built-in.o (.text*) + arch/powerpc/cpu/mpc824x/built-in.o (.text*) + board/mvblue/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv*) diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index 191f9eb837..7676cf43b1 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -19,10 +19,10 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) + lib/built-in.o (.text*) + net/built-in.o (.text*) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) . = env_offset; common/env_embedded.o (.text*) diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index 2a68934c32..463af7eaa4 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -18,8 +18,8 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) + net/built-in.o (.text*) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) *(.text.v*printf) . = DEFINED(env_offset) ? env_offset : .; diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 49226251b2..df564e9395 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -17,11 +17,11 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - lib/libgeneric.o (.text*) - net/libnet.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - board/svm_sc8xx/libsvm_sc8xx.o (.text*) + lib/built-in.o (.text*) + net/built-in.o (.text*) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) + board/svm_sc8xx/built-in.o (.text*) *(.text.*printf) *(.text.do_mem_*) *(.text.flash*) diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index a173f620ef..e77a501f56 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -35,7 +35,7 @@ SECTIONS { *(.__image_copy_start) CPUDIR/start.o (.text*) - board/ti/am335x/libam335x.o (.text*) + board/ti/am335x/built-in.o (.text*) *(.text*) } diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index cbfc94f57e..b77ae56c51 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -18,13 +18,13 @@ SECTIONS arch/powerpc/cpu/mpc8xx/start.o (.text*) arch/powerpc/cpu/mpc8xx/traps.o (.text*) - arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*) - arch/powerpc/lib/libpowerpc.o (.text*) - board/tqc/tqm8xx/libtqm8xx.o (.text*) - disk/libdisk.o (.text*) - drivers/net/libnet.o (.text*) - drivers/libdrivers.o (.text.pcmcia_on) - drivers/libdrivers.o (.text.pcmcia_hardware_enable) + arch/powerpc/cpu/mpc8xx/built-in.o (.text*) + arch/powerpc/lib/built-in.o (.text*) + board/tqc/tqm8xx/built-in.o (.text*) + disk/built-in.o (.text*) + drivers/net/built-in.o (.text*) + drivers/built-in.o (.text.pcmcia_on) + drivers/built-in.o (.text.pcmcia_hardware_enable) . = DEFINED(env_offset) ? env_offset : .; common/env_embedded.o (.ppcenv*) diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 7eac4975ba..c9b50e9f4d 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -20,8 +20,8 @@ SECTIONS .text.0 : { arch/arm/cpu/pxa/start.o (.text*) - board/vpac270/libvpac270.o (.text*) - drivers/mtd/onenand/libonenand.o (.text*) + board/vpac270/built-in.o (.text*) + drivers/mtd/onenand/built-in.o (.text*) } diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index ce09c2e138..5b09b45b56 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -111,8 +111,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 7144c6319f..a22c868422 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -155,8 +155,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 62bd3bf085..3aa3d50a89 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -111,8 +111,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 25cebf880f..02945bee79 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -118,8 +118,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 77822e792f..ffb0caf947 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -115,8 +115,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 77f47d9457..8f10eba467 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -112,8 +112,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 55e61d674f..a1c8e8a856 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -110,8 +110,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h index f2f41028eb..d0e72e3e13 100644 --- a/include/configs/dnp5370.h +++ b/include/configs/dnp5370.h @@ -85,8 +85,8 @@ #define ENV_IS_EMBEDDED #define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h index 5291755121..ac5ca9af37 100644 --- a/include/configs/ibf-dsp561.h +++ b/include/configs/ibf-dsp561.h @@ -95,8 +95,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 2adb071ddb..627836a7e8 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -112,8 +112,8 @@ * it linked after the configuration sector. */ # define LDS_BOARD_TEXT \ - arch/blackfin/lib/libblackfin.o (.text*); \ - arch/blackfin/cpu/libblackfin.o (.text*); \ + arch/blackfin/lib/built-in.o (.text*); \ + arch/blackfin/cpu/built-in.o (.text*); \ . = DEFINED(env_offset) ? env_offset : .; \ common/env_embedded.o (.text*); #endif diff --git a/spl/Makefile b/spl/Makefile index 0ac0c3c42e..29354f920c 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -54,52 +54,54 @@ ifeq ($(CPU),mpc85xx) START += $(START_PATH)/resetvec.o endif -LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o +LIBS-y += arch/$(ARCH)/lib/ -LIBS-y += $(CPUDIR)/lib$(CPU).o +LIBS-y += $(CPUDIR)/ ifdef SOC -LIBS-y += $(CPUDIR)/$(SOC)/lib$(SOC).o -endif -LIBS-y += board/$(BOARDDIR)/lib$(BOARD).o -LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/lib$(VENDOR).o - -LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/libspl.o -LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/libcommon.o -LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/libdisk.o -LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/libi2c.o -LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/libgpio.o -LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/libmmc.o -LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/libserial.o -LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/libspi_flash.o -LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/libspi.o -LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/libfat.o -LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/libgeneric.o -LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/libpower.o \ - drivers/power/pmic/libpmic.o -LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/libnand.o -LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/libonenand.o -LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/libdma.o -LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/memory.o -LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o -LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o -LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o -LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/libphy.o -LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o -LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o -LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o +LIBS-y += $(CPUDIR)/$(SOC)/ +endif +LIBS-y += board/$(BOARDDIR)/ +LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ + +LIBS-$(CONFIG_SPL_FRAMEWORK) += common/spl/ +LIBS-$(CONFIG_SPL_LIBCOMMON_SUPPORT) += common/ +LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ +LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/ +LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/ +LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ +LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ +LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ +LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/ +LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/ +LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ +LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \ + drivers/power/pmic/ +LIBS-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/ +LIBS-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/ +LIBS-$(CONFIG_SPL_DMA_SUPPORT) += drivers/dma/ +LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ +LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/ +LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/ +LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/ +LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/ +LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/ +LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/ +LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/ ifneq (,$(CONFIG_MX23)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35)) -LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o +LIBS-y += arch/$(ARCH)/imx-common/ endif -LIBS-$(CONFIG_ARM) += arch/arm/cpu/libcpu.o -LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/libcpu.o +LIBS-$(CONFIG_ARM) += arch/arm/cpu/ +LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/ ifneq ($(CONFIG_MX23)$(CONFIG_MX35),) -LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o +LIBS-y += arch/$(ARCH)/imx-common/ endif +LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y)) + # Add GCC lib ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o @@ -184,7 +186,6 @@ $(START): $(LIBS): depend $(MAKE) $(build) $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) - mv $(dir $@)built-in.o $@ $(obj)u-boot-spl.lds: $(LDSCRIPT) depend $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ -- cgit v1.2.1 From bc8bb6ec0af8e7a14e9a50057504263e7127aa73 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:01 +0900 Subject: Makefile: refactor a little Signed-off-by: Masahiro Yamada --- Makefile | 4 +--- spl/Makefile | 3 +-- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index 1389ee773e..e28878bf8d 100644 --- a/Makefile +++ b/Makefile @@ -65,11 +65,9 @@ endif # the object files are placed in the source directory. # -ifdef O ifeq ("$(origin O)", "command line") BUILD_DIR := $(O) endif -endif # Call a source code checker (by default, "sparse") as part of the # C compilation. @@ -614,7 +612,7 @@ SYSTEM_MAP = \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ LC_ALL=C sort $(obj)System.map: $(obj)u-boot - @$(call SYSTEM_MAP,$<) > $(obj)System.map + @$(call SYSTEM_MAP,$<) > $@ checkthumb: @if test $(call cc-version) -lt 0404; then \ diff --git a/spl/Makefile b/spl/Makefile index 29354f920c..5bc75b4bce 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -166,8 +166,7 @@ all: $(ALL-y) ifdef CONFIG_SAMSUNG $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin - $(OBJTREE)/tools/mk$(BOARD)spl \ - $(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin + $(OBJTREE)/tools/mk$(BOARD)spl $< $@ endif $(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) -- cgit v1.2.1 From 74307f206cb8bc2f6a3a283154c8d4151337f965 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:02 +0900 Subject: config.mk: delete unnecessary lines SPL_BIN is already defined in spl/Makefile and it is used only in spl/Makefile. Signed-off-by: Masahiro Yamada --- config.mk | 6 ------ 1 file changed, 6 deletions(-) diff --git a/config.mk b/config.mk index 344138759c..206de203cc 100644 --- a/config.mk +++ b/config.mk @@ -13,12 +13,6 @@ SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ export SHELL -ifeq ($(CONFIG_TPL_BUILD),y) -SPL_BIN := u-boot-tpl -else -SPL_BIN := u-boot-spl -endif - ifeq ($(CURDIR),$(SRCTREE)) dir := else -- cgit v1.2.1 From e2e1f3ca391b7ad8bbe4407b2edf5ee2778892c5 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:03 +0900 Subject: tools: Makefile: delete redundant lines HOSTOS is defined and exported at the top Makefile. Signed-off-by: Masahiro Yamada --- tools/gdb/Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/tools/gdb/Makefile b/tools/gdb/Makefile index dee91fccc0..dd98fb65c0 100644 --- a/tools/gdb/Makefile +++ b/tools/gdb/Makefile @@ -23,8 +23,6 @@ BINS := $(addprefix $(obj),$(BINS)) # HOSTCPPFLAGS = -I$(BFD_ROOT_DIR)/include -HOSTOS := $(shell uname -s | sed -e 's/\([Cc][Yy][Gg][Ww][Ii][Nn]\).*/cygwin/') - ifeq ($(HOSTOS),cygwin) all: -- cgit v1.2.1 From 88afda1682537e434469dc26d7ff53a242f6d73e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:04 +0900 Subject: Makefile: delete unused lines Signed-off-by: Masahiro Yamada --- Makefile | 6 ------ 1 file changed, 6 deletions(-) diff --git a/Makefile b/Makefile index e28878bf8d..5ad2bd733e 100644 --- a/Makefile +++ b/Makefile @@ -784,12 +784,6 @@ sinclude $(obj).boards.depend $(obj).boards.depend: boards.cfg @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@ -# -# Functions to generate common board directory names -# -lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/') -ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/') - ######################################################################### ######################################################################### -- cgit v1.2.1 From c64c5aa56ab0225a57d52152e76b6d17f751ae83 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:05 +0900 Subject: powerpc: mpc83xx: delete unused rules Signed-off-by: Masahiro Yamada --- arch/powerpc/cpu/mpc83xx/Makefile | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index b7142f0dff..a501a3bce0 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -48,11 +48,5 @@ obj-$(CONFIG_FSL_DDR2) += law.o endif # not minimal -$(obj)ddr-gen1.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c - $(obj)ddr-gen2.c: ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c - -$(obj)ddr-gen3.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c -- cgit v1.2.1 From 5cdee2d41ad4a1a351d50dc7af6d7ff3db549006 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:06 +0900 Subject: powerpc: mpc83xx: Do not create a symbolic link to ddr-gen2.c Signed-off-by: Masahiro Yamada --- Makefile | 1 - arch/powerpc/cpu/mpc83xx/Makefile | 6 +----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 5ad2bd733e..4f5a1acf78 100644 --- a/Makefile +++ b/Makefile @@ -861,7 +861,6 @@ clobber: tidy @rm -f $(obj)SPL @rm -f $(obj)tools/xway-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c - @rm -f $(obj)arch/powerpc/cpu/mpc83xx/ddr-gen?.c @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @rm -fr $(obj)include/generated @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index a501a3bce0..d3f7001478 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -39,14 +39,10 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += cache.o ifdef CONFIG_FSL_DDR2 -obj-$(CONFIG_MPC8349) += ddr-gen2.o -SRCS += $(obj)ddr-gen2.c +obj-$(CONFIG_MPC8349) += ../mpc85xx/ddr-gen2.o else obj-y += spd_sdram.o endif obj-$(CONFIG_FSL_DDR2) += law.o endif # not minimal - -$(obj)ddr-gen2.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c -- cgit v1.2.1 From 0a3656a42e1ffb574568459f7b1ec27ed354f258 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:07 +0900 Subject: powerpc: mpc824x: Do not create a symbolic link to bedbug_603e.c Signed-off-by: Masahiro Yamada --- Makefile | 1 - arch/powerpc/cpu/mpc824x/.gitignore | 1 - arch/powerpc/cpu/mpc824x/Makefile | 6 +----- 3 files changed, 1 insertion(+), 7 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc824x/.gitignore diff --git a/Makefile b/Makefile index 4f5a1acf78..c04917f60d 100644 --- a/Makefile +++ b/Makefile @@ -860,7 +860,6 @@ clobber: tidy @rm -f $(obj)MLO MLO.byteswap @rm -f $(obj)SPL @rm -f $(obj)tools/xway-swap-bytes - @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm @rm -fr $(obj)include/generated @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f diff --git a/arch/powerpc/cpu/mpc824x/.gitignore b/arch/powerpc/cpu/mpc824x/.gitignore deleted file mode 100644 index 2d79931e96..0000000000 --- a/arch/powerpc/cpu/mpc824x/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/bedbug_603e.c diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile index 194fadd0c0..2c8be92571 100644 --- a/arch/powerpc/cpu/mpc824x/Makefile +++ b/arch/powerpc/cpu/mpc824x/Makefile @@ -8,8 +8,4 @@ extra-y = start.o obj-y = traps.o cpu.o cpu_init.o interrupts.o speed.o \ drivers/epic/epic1.o drivers/i2c/i2c.o pci.o -obj-y += bedbug_603e.o - -SRCS += $(obj)bedbug_603e.c -$(obj)bedbug_603e.c: - ln -sf $(src)../mpc8260/bedbug_603e.c $(obj)bedbug_603e.c +obj-y += ../mpc8260/bedbug_603e.o -- cgit v1.2.1 From a52f90f074a84880f8cb13e060e9ca5f3c7d9c2f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:08 +0900 Subject: arm: rmobile: Do not create a symbolic link to sh timer Signed-off-by: Masahiro Yamada Cc: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/Makefile | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index 8f4cf3a195..5e296c4208 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -15,10 +15,4 @@ obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o obj-$(CONFIG_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o obj-$(CONFIG_SH73A0) += pfc-sh73a0.o -obj-$(CONFIG_TMU_TIMER) += sh_timer.o - -SRCS += $(obj)sh_timer.c -# from arch/sh/lib/ directory -$(obj)sh_timer.c: - @rm -f $(obj)sh_timer.c - ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c +obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o -- cgit v1.2.1 From 57c3e5fcf2cbc791d9507c8b8c09df1ef21c043a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:09 +0900 Subject: Makefile: move fs/fat/ entry to drivers/Makefile Signed-off-by: Masahiro Yamada Cc: Simon Glass Acked-by: Simon Glass --- Makefile | 3 +-- fs/Makefile | 5 +++++ spl/Makefile | 2 +- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index c04917f60d..b8713a4935 100644 --- a/Makefile +++ b/Makefile @@ -243,8 +243,7 @@ endif LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/ LIBS-$(CONFIG_OF_EMBED) += dts/ LIBS-y += arch/$(ARCH)/lib/ -LIBS-y += fs/ \ - fs/fat/ +LIBS-y += fs/ LIBS-y += net/ LIBS-y += disk/ LIBS-y += drivers/ diff --git a/fs/Makefile b/fs/Makefile index bdcd74631d..ee01a7d4a1 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -6,11 +6,15 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/ +else obj-y += fs.o obj-y += cbfs/ obj-y += cramfs/ obj-y += ext4/ +obj-y += fat/ obj-y += fdos/ obj-y += jffs2/ obj-y += reiserfs/ @@ -18,3 +22,4 @@ obj-y += sandbox/ obj-y += ubifs/ obj-y += yaffs2/ obj-y += zfs/ +endif diff --git a/spl/Makefile b/spl/Makefile index 5bc75b4bce..29d7818df5 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -73,7 +73,7 @@ LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/ -LIBS-$(CONFIG_SPL_FAT_SUPPORT) += fs/fat/ +LIBS-y += fs/ LIBS-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ LIBS-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ \ drivers/power/pmic/ -- cgit v1.2.1 From 4678d742567e282d9e0f786441f59102e8d3553e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 11 Nov 2013 14:36:10 +0900 Subject: fs: descend into sub directories when it is necessary Signed-off-by: Masahiro Yamada --- fs/Makefile | 20 ++++++++++---------- fs/cbfs/Makefile | 2 +- fs/cramfs/Makefile | 4 ++-- fs/ext4/Makefile | 2 +- fs/fdos/Makefile | 2 +- fs/jffs2/Makefile | 2 -- fs/reiserfs/Makefile | 2 +- fs/sandbox/Makefile | 2 +- fs/ubifs/Makefile | 8 ++++---- fs/yaffs2/Makefile | 2 +- fs/zfs/Makefile | 2 +- 11 files changed, 23 insertions(+), 25 deletions(-) diff --git a/fs/Makefile b/fs/Makefile index ee01a7d4a1..34dc0351ed 100644 --- a/fs/Makefile +++ b/fs/Makefile @@ -11,15 +11,15 @@ obj-$(CONFIG_SPL_FAT_SUPPORT) += fat/ else obj-y += fs.o -obj-y += cbfs/ -obj-y += cramfs/ -obj-y += ext4/ +obj-$(CONFIG_CMD_CBFS) += cbfs/ +obj-$(CONFIG_CMD_CRAMFS) += cramfs/ +obj-$(CONFIG_FS_EXT4) += ext4/ obj-y += fat/ -obj-y += fdos/ -obj-y += jffs2/ -obj-y += reiserfs/ -obj-y += sandbox/ -obj-y += ubifs/ -obj-y += yaffs2/ -obj-y += zfs/ +obj-$(CONFIG_CMD_FDOS) += fdos/ +obj-$(CONFIG_CMD_JFFS2) += jffs2/ +obj-$(CONFIG_CMD_REISER) += reiserfs/ +obj-$(CONFIG_SANDBOX) += sandbox/ +obj-$(CONFIG_CMD_UBIFS) += ubifs/ +obj-$(CONFIG_YAFFS2) += yaffs2/ +obj-$(CONFIG_CMD_ZFS) += zfs/ endif diff --git a/fs/cbfs/Makefile b/fs/cbfs/Makefile index 6f33d2813d..a106e05dd8 100644 --- a/fs/cbfs/Makefile +++ b/fs/cbfs/Makefile @@ -3,4 +3,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CMD_CBFS) := cbfs.o +obj-y := cbfs.o diff --git a/fs/cramfs/Makefile b/fs/cramfs/Makefile index e2b2c7366c..12d73a375e 100644 --- a/fs/cramfs/Makefile +++ b/fs/cramfs/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CMD_CRAMFS) := cramfs.o -obj-$(CONFIG_CMD_CRAMFS) += uncompress.o +obj-y := cramfs.o +obj-y += uncompress.o diff --git a/fs/ext4/Makefile b/fs/ext4/Makefile index 0f5d3995cb..8d15bdad67 100644 --- a/fs/ext4/Makefile +++ b/fs/ext4/Makefile @@ -9,5 +9,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_FS_EXT4) := ext4fs.o ext4_common.o dev.o +obj-y := ext4fs.o ext4_common.o dev.o obj-$(CONFIG_EXT4_WRITE) += ext4_write.o ext4_journal.o crc16.o diff --git a/fs/fdos/Makefile b/fs/fdos/Makefile index 95480af3e4..2f8b5addd6 100644 --- a/fs/fdos/Makefile +++ b/fs/fdos/Makefile @@ -10,4 +10,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CMD_FDOS) := fat.o vfat.o dev.o fdos.o fs.o subdir.o +obj-y := fat.o vfat.o dev.o fdos.o fs.o subdir.o diff --git a/fs/jffs2/Makefile b/fs/jffs2/Makefile index 02e481f3ce..4cb0600cf9 100644 --- a/fs/jffs2/Makefile +++ b/fs/jffs2/Makefile @@ -5,11 +5,9 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifdef CONFIG_CMD_JFFS2 obj-$(CONFIG_JFFS2_LZO) += compr_lzo.o obj-y += compr_rtime.o obj-y += compr_rubin.o obj-y += compr_zlib.o obj-y += jffs2_1pass.o obj-y += mini_inflate.o -endif diff --git a/fs/reiserfs/Makefile b/fs/reiserfs/Makefile index 55f70b1a94..5a692f0ee7 100644 --- a/fs/reiserfs/Makefile +++ b/fs/reiserfs/Makefile @@ -9,4 +9,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CMD_REISER) := reiserfs.o dev.o mode_string.o +obj-y := reiserfs.o dev.o mode_string.o diff --git a/fs/sandbox/Makefile b/fs/sandbox/Makefile index faa7c16ba0..ca238f6d7d 100644 --- a/fs/sandbox/Makefile +++ b/fs/sandbox/Makefile @@ -10,4 +10,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_SANDBOX) := sandboxfs.o +obj-y := sandboxfs.o diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile index 47d5a8fb0a..389b0e37e7 100644 --- a/fs/ubifs/Makefile +++ b/fs/ubifs/Makefile @@ -9,10 +9,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CMD_UBIFS) := ubifs.o io.o super.o sb.o master.o lpt.o -obj-$(CONFIG_CMD_UBIFS) += lpt_commit.o scan.o lprops.o -obj-$(CONFIG_CMD_UBIFS) += tnc.o tnc_misc.o debug.o crc16.o budget.o -obj-$(CONFIG_CMD_UBIFS) += log.o orphan.o recovery.o replay.o +obj-y := ubifs.o io.o super.o sb.o master.o lpt.o +obj-y += lpt_commit.o scan.o lprops.o +obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o +obj-y += log.o orphan.o recovery.o replay.o # SEE README.arm-unaligned-accesses $(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile index 077af7834e..d811287ddb 100644 --- a/fs/yaffs2/Makefile +++ b/fs/yaffs2/Makefile @@ -16,7 +16,7 @@ # # $Id: Makefile,v 1.15 2007/07/18 19:40:38 charles Exp $ -obj-$(CONFIG_YAFFS2) := \ +obj-y := \ yaffs_allocator.o yaffs_attribs.o yaffs_bitmap.o yaffs_uboot_glue.o\ yaffs_checkptrw.o yaffs_ecc.o yaffs_error.o \ yaffsfs.o yaffs_guts.o yaffs_nameval.o yaffs_nand.o\ diff --git a/fs/zfs/Makefile b/fs/zfs/Makefile index 7090416b87..fa58b7fcde 100644 --- a/fs/zfs/Makefile +++ b/fs/zfs/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_CMD_ZFS) := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o +obj-y := dev.o zfs.o zfs_fletcher.o zfs_sha256.o zfs_lzjb.o -- cgit v1.2.1 From 68ec9c85a9d334c7598b4972af037de05c034f8d Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 4 Oct 2013 13:47:58 +0530 Subject: mtd: move & update nand_ecclayout structure (plus board changes) nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Changes from Prabhabkar's version (squashed into one patch to preserve bisectability): - Added _LARGE to MTD_MAX_*_ENTRIES This makes the names match current Linux source, and resolves a conflict between http://patchwork.ozlabs.org/patch/280488/ and http://patchwork.ozlabs.org/patch/284513/ The former was posted first and is closer to matching Linux, but unlike Linux it does not add _LARGE to the names. The second adds _LARGE to one of the names, and depends on it in a subsequent patch (http://patchwork.ozlabs.org/patch/284512/). - Made max oobfree/eccpos configurable, and used this on tricorder, alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build for me without doing so, due to a size increase). On tricorder SPL, this saves 2576 bytes (and makes the SPL build again) versus the new default of 640 eccpos and 32 oobfree, and saves 336 bytes versus the old default of 128 eccpos and 8 oobfree. Signed-off-by: Prabhakar Kushwaha CC: Vipin Kumar [scottwood@freescale.com: changes as described above] Signed-off-by: Scott Wood Cc: Thomas Weber Cc: Matthias Fuchs Cc: Stefan Roese Cc: York Sun Cc: Tom Rini Reviewed-by: Stefan Roese --- doc/README.nand | 10 ++++++++++ drivers/mtd/onenand/onenand_base.c | 15 ++++++++++----- include/configs/ASH405.h | 2 ++ include/configs/MPC8572DS.h | 2 ++ include/configs/T4240QDS.h | 2 ++ include/configs/alpr.h | 2 ++ include/configs/tricorder.h | 2 ++ include/linux/mtd/mtd.h | 23 +++++++++++++++++++++++ include/mtd/mtd-abi.h | 12 ------------ 9 files changed, 53 insertions(+), 17 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index 913e9b50b8..3a507b6c81 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -104,6 +104,16 @@ Configuration Options: CONFIG_SYS_MAX_NAND_DEVICE The maximum number of NAND devices you want to support. + CONFIG_SYS_NAND_MAX_ECCPOS + If specified, overrides the maximum number of ECC bytes + supported. Useful for reducing image size, especially with SPL. + This must be at least 48 if nand_base.c is used. + + CONFIG_SYS_NAND_MAX_OOBFREE + If specified, overrides the maximum number of free OOB regions + supported. Useful for reducing image size, especially with SPL. + This must be at least 2 if nand_base.c is used. + CONFIG_SYS_NAND_MAX_CHIPS The maximum number of NAND chips per device to be supported. diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 067f8ef184..979e4af7c5 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -761,7 +761,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, uint8_t *oob_buf = this->oob_buf; free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { if (readcol >= lastgap) readcol += free->offset - lastgap; if (readend >= lastgap) @@ -770,7 +771,8 @@ static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, } this->read_bufferram(mtd, 0, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { int free_end = free->offset + free->length; if (free->offset < readend && free_end > readcol) { int st = max_t(int,free->offset,readcol); @@ -1356,7 +1358,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, unsigned int i; free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { if (writecol >= lastgap) writecol += free->offset - lastgap; if (writeend >= lastgap) @@ -1364,7 +1367,8 @@ static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, lastgap = free->offset + free->length; } free = this->ecclayout->oobfree; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && free->length; + i++, free++) { int free_end = free->offset + free->length; if (free->offset < writeend && free_end > writecol) { int st = max_t(int,free->offset,writecol); @@ -2750,7 +2754,8 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) * the out of band area */ this->ecclayout->oobavail = 0; - for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && + + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES_LARGE && this->ecclayout->oobfree[i].length; i++) this->ecclayout->oobavail += this->ecclayout->oobfree[i].length; diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9460be3b59..2f5340723d 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -143,6 +143,8 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /*----------------------------------------------------------------------- * PCI stuff diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c7511449ea..9ad94021e4 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -322,6 +322,8 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_MAX_OOBFREE 5 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /* NAND boot: 4K NAND loader config */ #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 3777ccb835..c96df54d99 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -229,6 +229,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 #if defined(CONFIG_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 2bf1986e3a..61fdebac3f 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -324,6 +324,8 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } #define CONFIG_SYS_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index d57394e550..590eab7e48 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -140,6 +140,8 @@ /* devices */ #define CONFIG_NAND_OMAP_BCH8 #define CONFIG_BCH +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 /* commands to include */ #include diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 6f44abdc16..a65b681551 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -96,6 +96,29 @@ struct mtd_oob_ops { uint8_t *oobbuf; }; +#ifdef CONFIG_SYS_NAND_MAX_OOBFREE +#define MTD_MAX_OOBFREE_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_OOBFREE +#else +#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 +#endif + +#ifdef CONFIG_SYS_NAND_MAX_ECCPOS +#define MTD_MAX_ECCPOS_ENTRIES_LARGE CONFIG_SYS_NAND_MAX_ECCPOS +#else +#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640 +#endif + +/* + * ECC layout control structure. Exported to userspace for + * diagnosis and to allow creation of raw images + */ +struct nand_ecclayout { + uint32_t eccbytes; + uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; + uint32_t oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE]; +}; + struct mtd_info { u_char type; u_int32_t flags; diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index d51c1abd18..ac3c298760 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -155,18 +155,6 @@ struct nand_oobfree { uint32_t length; }; -#define MTD_MAX_OOBFREE_ENTRIES 8 -/* - * ECC layout control structure. Exported to userspace for - * diagnosis and to allow creation of raw images - */ -struct nand_ecclayout { - uint32_t eccbytes; - uint32_t eccpos[128]; - uint32_t oobavail; - struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; -}; - /** * struct mtd_ecc_stats - error correction stats * -- cgit v1.2.1 From 71220f80e7489b7fc1766f573ae89c64db2419ce Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 4 Oct 2013 10:05:36 +0530 Subject: mtd/ifc: Add support of 8K page size NAND flash Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha CC: Liu Po --- arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 24 ++++++++++++ arch/powerpc/include/asm/fsl_ifc.h | 2 + drivers/mtd/nand/fsl_ifc_nand.c | 78 ++++++++++++++++++++++++++++++++++++++ drivers/mtd/nand/fsl_ifc_spl.c | 7 +++- 4 files changed, 109 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c index 2d0fb433bc..64a52258a0 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c @@ -33,6 +33,9 @@ void init_early_memctl_regs(void) #ifndef CONFIG_A003399_NOR_WORKAROUND #ifdef CONFIG_SYS_CSPR0_EXT set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); +#endif +#ifdef CONFIG_SYS_CSOR0_EXT + set_ifc_csor_ext(IFC_CS0, CONFIG_SYS_CSOR0_EXT); #endif set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); @@ -43,6 +46,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR1_EXT set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); #endif +#ifdef CONFIG_SYS_CSOR1_EXT + set_ifc_csor_ext(IFC_CS1, CONFIG_SYS_CSOR1_EXT); +#endif #if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); @@ -57,6 +63,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR2_EXT set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); #endif +#ifdef CONFIG_SYS_CSOR2_EXT + set_ifc_csor_ext(IFC_CS2, CONFIG_SYS_CSOR2_EXT); +#endif #if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); @@ -71,6 +80,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR3_EXT set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); #endif +#ifdef CONFIG_SYS_CSOR3_EXT + set_ifc_csor_ext(IFC_CS3, CONFIG_SYS_CSOR3_EXT); +#endif #if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); @@ -85,6 +97,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR4_EXT set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); #endif +#ifdef CONFIG_SYS_CSOR4_EXT + set_ifc_csor_ext(IFC_CS4, CONFIG_SYS_CSOR4_EXT); +#endif #if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); @@ -99,6 +114,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR5_EXT set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); #endif +#ifdef CONFIG_SYS_CSOR5_EXT + set_ifc_csor_ext(IFC_CS5, CONFIG_SYS_CSOR5_EXT); +#endif #if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); @@ -113,6 +131,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR6_EXT set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); #endif +#ifdef CONFIG_SYS_CSOR6_EXT + set_ifc_csor_ext(IFC_CS6, CONFIG_SYS_CSOR6_EXT); +#endif #if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); @@ -127,6 +148,9 @@ void init_early_memctl_regs(void) #ifdef CONFIG_SYS_CSPR7_EXT set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); #endif +#ifdef CONFIG_SYS_CSOR7_EXT + set_ifc_csor_ext(IFC_CS7, CONFIG_SYS_CSOR7_EXT); +#endif #if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h index a945e4b2d4..182b1a6333 100644 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ b/arch/powerpc/include/asm/fsl_ifc.h @@ -77,6 +77,7 @@ #define CSOR_NAND_PGS_512 0x00000000 #define CSOR_NAND_PGS_2K 0x00080000 #define CSOR_NAND_PGS_4K 0x00100000 +#define CSOR_NAND_PGS_8K 0x00180000 /* Spare region Size */ #define CSOR_NAND_SPRZ_MASK 0x0000E000 #define CSOR_NAND_SPRZ_SHIFT 13 @@ -86,6 +87,7 @@ #define CSOR_NAND_SPRZ_210 0x00006000 #define CSOR_NAND_SPRZ_218 0x00008000 #define CSOR_NAND_SPRZ_224 0x0000A000 +#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000 /* Pages Per Block */ #define CSOR_NAND_PB_MASK 0x00000700 #define CSOR_NAND_PB_SHIFT 8 diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 1d18815b2b..49b63af85d 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -125,6 +125,69 @@ static struct nand_ecclayout oob_4096_ecc8 = { .oobfree = { {2, 6}, {136, 82} }, }; +/* 8192-byte page size with 4-bit ECC */ +static struct nand_ecclayout oob_8192_ecc4 = { + .eccbytes = 128, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + }, + .oobfree = { {2, 6}, {136, 208} }, +}; + +/* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */ +static struct nand_ecclayout oob_8192_ecc8 = { + .eccbytes = 256, + .eccpos = { + 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 94, 95, + 96, 97, 98, 99, 100, 101, 102, 103, + 104, 105, 106, 107, 108, 109, 110, 111, + 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, + 128, 129, 130, 131, 132, 133, 134, 135, + 136, 137, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 149, 150, 151, + 152, 153, 154, 155, 156, 157, 158, 159, + 160, 161, 162, 163, 164, 165, 166, 167, + 168, 169, 170, 171, 172, 173, 174, 175, + 176, 177, 178, 179, 180, 181, 182, 183, + 184, 185, 186, 187, 188, 189, 190, 191, + 192, 193, 194, 195, 196, 197, 198, 199, + 200, 201, 202, 203, 204, 205, 206, 207, + 208, 209, 210, 211, 212, 213, 214, 215, + 216, 217, 218, 219, 220, 221, 222, 223, + 224, 225, 226, 227, 228, 229, 230, 231, + 232, 233, 234, 235, 236, 237, 238, 239, + 240, 241, 242, 243, 244, 245, 246, 247, + 248, 249, 250, 251, 252, 253, 254, 255, + 256, 257, 258, 259, 260, 261, 262, 263, + }, + .oobfree = { {2, 6}, {264, 80} }, +}; /* * Generic flash bbt descriptors @@ -913,6 +976,21 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) priv->bufnum_mask = 1; break; + case CSOR_NAND_PGS_8K: + if ((csor & CSOR_NAND_ECC_MODE_MASK) == + CSOR_NAND_ECC_MODE_4) { + layout = &oob_8192_ecc4; + nand->ecc.strength = 4; + } else { + layout = &oob_8192_ecc8; + nand->ecc.strength = 8; + nand->ecc.bytes = 16; + } + + priv->bufnum_mask = 0; + break; + + default: printf("ifc nand: bad csor %#x: bad page size\n", csor); return -ENODEV; diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d4622653fa..9fa5ccbc56 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -112,10 +112,13 @@ static void nand_load(unsigned int offs, int uboot_size, uchar *dst) port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8; - if (csor & CSOR_NAND_PGS_4K) { + if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) { + page_size = 8192; + bufnum_mask = 0x0; + } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) { page_size = 4096; bufnum_mask = 0x1; - } else if (csor & CSOR_NAND_PGS_2K) { + } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) { page_size = 2048; bufnum_mask = 0x3; } else { -- cgit v1.2.1 From affd520f8ce506eab96e66ad525c4807871e2981 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Fri, 4 Oct 2013 10:05:50 +0530 Subject: board/c29xpcie: Add support of 8K page size NAND flash Defines constants required to support 8K page size NAND flash. Signed-off-by: Prabhakar Kushwaha --- include/configs/C29XPCIE.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 08156c531d..bb15745372 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -191,13 +191,14 @@ | CSPR_MSEL_NAND \ | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ + | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ + | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0c) | \ FTIM0_NAND_TWCHT(0x08) | \ @@ -224,6 +225,7 @@ #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -- cgit v1.2.1 From 16dddef6050471f47c84b6c929ae3c4bc9c0fb46 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Fri, 18 Oct 2013 17:46:31 +0800 Subject: mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flash increase the delay to 75us to support the 8k bytes page nand flash Signed-off-by: Josh Wu --- drivers/mtd/nand/atmel_nand.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 10011c6a8f..1d8c860f1a 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -827,6 +827,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, switch (mtd->writesize) { case 2048: case 4096: + case 8192: host->pmecc_degree = (sector_size == 512) ? PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14; host->pmecc_cw_len = (1 << host->pmecc_degree) - 1; @@ -840,6 +841,13 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, nand->ecc.steps = 1; nand->ecc.bytes = host->pmecc_bytes_per_sector * host->pmecc_sector_number; + + if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) { + dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n", + MTD_MAX_ECCPOS_ENTRIES_LARGE); + return -EINVAL; + } + if (nand->ecc.bytes > mtd->oobsize - 2) { printk(KERN_ERR "No room for ECC bytes\n"); return -EINVAL; @@ -1190,7 +1198,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr) #ifdef CONFIG_SYS_NAND_READY_PIN nand->dev_ready = at91_nand_ready; #endif - nand->chip_delay = 20; + nand->chip_delay = 75; ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); if (ret) -- cgit v1.2.1 From d02a60a16e40b185a9eb5ad3bc038584fd7264c2 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Fri, 18 Oct 2013 17:46:32 +0800 Subject: sama5d3xek: support larger than 4G nand flash Signed-off-by: Josh Wu --- board/atmel/sama5d3xek/sama5d3xek.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index b0965ef211..83fd63f541 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -131,7 +131,8 @@ static void sama5d3xek_lcd_hw_init(void) void lcd_show_board_info(void) { - ulong dram_size, nand_size; + ulong dram_size; + uint64_t nand_size; int i; char temp[32]; @@ -150,7 +151,7 @@ void lcd_show_board_info(void) for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i].size; #endif - lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + lcd_printf("%ld MB SDRAM, %lld MB NAND\n", dram_size >> 20, nand_size >> 20); } #endif /* CONFIG_LCD_INFO */ -- cgit v1.2.1 From c55cc573eaf1ba7318b1b692c673a28b99f5195c Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Fri, 18 Oct 2013 17:46:33 +0800 Subject: mtd: atmel_nand: don't print bit correction message in driver Since for some MLC nand, bit errors happened too often. Just disable it to avoid noise Signed-off-by: Josh Wu --- drivers/mtd/nand/atmel_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 1d8c860f1a..92547432ac 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -452,7 +452,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, *(buf + byte_pos) ^= (1 << bit_pos); pos = sector_num * host->pmecc_sector_size + byte_pos; - printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", + dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", pos, bit_pos, err_byte, *(buf + byte_pos)); } else { /* Bit flip in OOB area */ @@ -462,7 +462,7 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc, ecc[tmp] ^= (1 << bit_pos); pos = tmp + nand_chip->ecc.layout->eccpos[0]; - printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", + dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n", pos, bit_pos, err_byte, ecc[tmp]); } -- cgit v1.2.1 From c0dc3dec697e930d290145e127a86ff31f7c2dde Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Fri, 18 Oct 2013 17:46:34 +0800 Subject: mtd: atmel_nand: use dev_xxx instead of printk Signed-off-by: Josh Wu --- drivers/mtd/nand/atmel_nand.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 92547432ac..16b7df0f72 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -412,7 +412,7 @@ static int pmecc_err_location(struct mtd_info *mtd) } if (!timeout) { - printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n"); + dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n"); return -1; } @@ -500,7 +500,7 @@ normal_check: err_nbr = pmecc_err_location(mtd); if (err_nbr == -1) { - printk(KERN_ERR "PMECC: Too many errors\n"); + dev_err(host->dev, "PMECC: Too many errors\n"); mtd->ecc_stats.failed++; return -EIO; } else { @@ -544,7 +544,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd, } if (!timeout) { - printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n"); + dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n"); return -1; } @@ -584,7 +584,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd, } if (!timeout) { - printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n"); + dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n"); goto out; } @@ -849,7 +849,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, } if (nand->ecc.bytes > mtd->oobsize - 2) { - printk(KERN_ERR "No room for ECC bytes\n"); + dev_err(host->dev, "No room for ECC bytes\n"); return -EINVAL; } pmecc_config_ecc_layout(&atmel_pmecc_oobinfo, @@ -860,7 +860,7 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, case 512: case 1024: /* TODO */ - printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n"); + dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n"); default: /* page size not handled by HW ECC */ /* switching back to soft ECC */ @@ -1043,7 +1043,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, /* it doesn't seems to be a freshly * erased block. * We can't correct so many errors */ - printk(KERN_WARNING "atmel_nand : multiple errors detected." + dev_warn(host->dev, "atmel_nand : multiple errors detected." " Unable to correct.\n"); return -EIO; } @@ -1053,12 +1053,12 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, /* there's nothing much to do here. * the bit error is on the ECC itself. */ - printk(KERN_WARNING "atmel_nand : one bit error on ECC code." + dev_warn(host->dev, "atmel_nand : one bit error on ECC code." " Nothing to correct\n"); return 0; } - printk(KERN_WARNING "atmel_nand : one bit error on data." + dev_warn(host->dev, "atmel_nand : one bit error on data." " (word offset in the page :" " 0x%x bit offset : 0x%x)\n", ecc_word, ecc_bit); @@ -1070,7 +1070,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat, /* 8 bits words */ dat[ecc_word] ^= (1 << ecc_bit); } - printk(KERN_WARNING "atmel_nand : error corrected\n"); + dev_warn(host->dev, "atmel_nand : error corrected\n"); return 1; } @@ -1226,6 +1226,6 @@ void board_nand_init(void) int i; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) if (atmel_nand_chip_init(i, base_addr[i])) - printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip", + dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip", i); } -- cgit v1.2.1 From beba5f04f2215c81016fbfb727257ea6667aca85 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 18 Nov 2013 19:02:59 +0530 Subject: mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform. Signed-off-by: Pekon Gupta --- arch/arm/cpu/armv7/am33xx/Makefile | 1 - arch/arm/cpu/armv7/am33xx/elm.c | 196 --------------------------------- arch/arm/include/asm/arch-am33xx/elm.h | 77 ------------- arch/arm/include/asm/omap_elm.h | 77 +++++++++++++ doc/README.nand | 19 ++++ drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/omap_elm.c | 196 +++++++++++++++++++++++++++++++++ drivers/mtd/nand/omap_gpmc.c | 2 +- include/configs/am335x_evm.h | 2 + include/configs/am335x_igep0033.h | 1 + include/configs/siemens-am33x-common.h | 1 + 11 files changed, 298 insertions(+), 275 deletions(-) delete mode 100644 arch/arm/cpu/armv7/am33xx/elm.c delete mode 100644 arch/arm/include/asm/arch-am33xx/elm.h create mode 100644 arch/arm/include/asm/omap_elm.h create mode 100644 drivers/mtd/nand/omap_elm.c diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 966fcab71b..5566310d94 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -19,4 +19,3 @@ obj-y += ddr.o obj-y += emif4.o obj-y += board.o obj-y += mux.o -obj-$(CONFIG_NAND_OMAP_GPMC) += elm.o diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c deleted file mode 100644 index 8f1d6afdd3..0000000000 --- a/arch/arm/cpu/armv7/am33xx/elm.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2010-2011 Texas Instruments, - * Mansoor Ahamed - * - * BCH Error Location Module (ELM) support. - * - * NOTE: - * 1. Supports only continuous mode. Dont see need for page mode in uboot - * 2. Supports only syndrome polynomial 0. i.e. poly local variable is - * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial - * sets in uboot - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#define ELM_DEFAULT_POLY (0) - -struct elm *elm_cfg; - -/** - * elm_load_syndromes - Load BCH syndromes based on nibble selection - * @syndrome: BCH syndrome - * @nibbles: - * @poly: Syndrome Polynomial set to use - * - * Load BCH syndromes based on nibble selection - */ -static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) -{ - u32 *ptr; - u32 val; - - /* reg 0 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0]; - val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | - (syndrome[3] << 24); - writel(val, ptr); - /* reg 1 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1]; - val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | - (syndrome[7] << 24); - writel(val, ptr); - - /* BCH 8-bit with 26 nibbles (4*8=32) */ - if (nibbles > 13) { - /* reg 2 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; - val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | - (syndrome[11] << 24); - writel(val, ptr); - /* reg 3 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3]; - val = syndrome[12] | (syndrome[13] << 8) | - (syndrome[14] << 16) | (syndrome[15] << 24); - writel(val, ptr); - } - - /* BCH 16-bit with 52 nibbles (7*8=56) */ - if (nibbles > 26) { - /* reg 4 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; - val = syndrome[16] | (syndrome[17] << 8) | - (syndrome[18] << 16) | (syndrome[19] << 24); - writel(val, ptr); - - /* reg 5 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5]; - val = syndrome[20] | (syndrome[21] << 8) | - (syndrome[22] << 16) | (syndrome[23] << 24); - writel(val, ptr); - - /* reg 6 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]; - val = syndrome[24] | (syndrome[25] << 8) | - (syndrome[26] << 16) | (syndrome[27] << 24); - writel(val, ptr); - } -} - -/** - * elm_check_errors - Check for BCH errors and return error locations - * @syndrome: BCH syndrome - * @nibbles: - * @error_count: Returns number of errrors in the syndrome - * @error_locations: Returns error locations (in decimal) in this array - * - * Check the provided syndrome for BCH errors and return error count - * and locations in the array passed. Returns -1 if error is not correctable, - * else returns 0 - */ -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, - u32 *error_locations) -{ - u8 poly = ELM_DEFAULT_POLY; - s8 i; - u32 location_status; - - elm_load_syndromes(syndrome, nibbles, poly); - - /* start processing */ - writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) - | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), - &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); - - /* wait for processing to complete */ - while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1) - ; - /* clear status */ - writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), - &elm_cfg->irqstatus); - - /* check if correctable */ - location_status = readl(&elm_cfg->error_location[poly].location_status); - if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) - return -1; - - /* get error count */ - *error_count = readl(&elm_cfg->error_location[poly].location_status) & - ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; - - for (i = 0; i < *error_count; i++) { - error_locations[i] = - readl(&elm_cfg->error_location[poly].error_location_x[i]); - } - - return 0; -} - - -/** - * elm_config - Configure ELM module - * @level: 4 / 8 / 16 bit BCH - * - * Configure ELM module based on BCH level. - * Set mode as continuous mode. - * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used. - * Also, the mode is set only for syndrome 0 - */ -int elm_config(enum bch_level level) -{ - u32 val; - u8 poly = ELM_DEFAULT_POLY; - u32 buffer_size = 0x7FF; - - /* config size and level */ - val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK; - val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) & - ELM_LOCATION_CONFIG_ECC_SIZE_MASK); - writel(val, &elm_cfg->location_config); - - /* config continous mode */ - /* enable interrupt generation for syndrome polynomial set */ - writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), - &elm_cfg->irqenable); - /* set continuous mode for the syndrome polynomial set */ - writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), - &elm_cfg->page_ctrl); - - return 0; -} - -/** - * elm_reset - Do a soft reset of ELM - * - * Perform a soft reset of ELM and return after reset is done. - */ -void elm_reset(void) -{ - /* initiate reset */ - writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), - &elm_cfg->sysconfig); - - /* wait for reset complete and normal operation */ - while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != - ELM_SYSSTATUS_RESETDONE) - ; -} - -/** - * elm_init - Initialize ELM module - * - * Initialize ELM support. Currently it does only base address init - * and ELM reset. - */ -void elm_init(void) -{ - elm_cfg = (struct elm *)ELM_BASE; - elm_reset(); -} diff --git a/arch/arm/include/asm/arch-am33xx/elm.h b/arch/arm/include/asm/arch-am33xx/elm.h deleted file mode 100644 index 45454eaf0f..0000000000 --- a/arch/arm/include/asm/arch-am33xx/elm.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2010-2011 Texas Instruments, - * Mansoor Ahamed - * - * Derived from work done by Rohit Choraria for omap3 - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_ELM_H -#define __ASM_ARCH_ELM_H -/* - * ELM Module Registers - */ - -/* ELM registers bit fields */ -#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) -#define ELM_SYSCONFIG_SOFTRESET (0x2) -#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) -#define ELM_SYSSTATUS_RESETDONE (0x1) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) -#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) -#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) -#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) - -#ifndef __ASSEMBLY__ - -enum bch_level { - BCH_4_BIT = 0, - BCH_8_BIT, - BCH_16_BIT -}; - - -/* BCH syndrome registers */ -struct syndrome { - u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ - u8 res1[36]; /* 0x41c */ -}; - -/* BCH error status & location register */ -struct location { - u32 location_status; /* 0x800 */ - u8 res1[124]; /* 0x804 */ - u32 error_location_x[16]; /* 0x880.... */ - u8 res2[64]; /* 0x8c0 */ -}; - -/* BCH ELM register map - do not try to allocate memmory for this structure. - * We have used plenty of reserved variables to fill the slots in the ELM - * register memory map. - * Directly initialize the struct pointer to ELM base address. - */ -struct elm { - u32 rev; /* 0x000 */ - u8 res1[12]; /* 0x004 */ - u32 sysconfig; /* 0x010 */ - u32 sysstatus; /* 0x014 */ - u32 irqstatus; /* 0x018 */ - u32 irqenable; /* 0x01c */ - u32 location_config; /* 0x020 */ - u8 res2[92]; /* 0x024 */ - u32 page_ctrl; /* 0x080 */ - u8 res3[892]; /* 0x084 */ - struct syndrome syndrome_fragments[8]; /* 0x400 */ - u8 res4[512]; /* 0x600 */ - struct location error_location[8]; /* 0x800 */ -}; - -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, - u32 *error_locations); -int elm_config(enum bch_level level); -void elm_reset(void); -void elm_init(void); -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_ELM_H */ diff --git a/arch/arm/include/asm/omap_elm.h b/arch/arm/include/asm/omap_elm.h new file mode 100644 index 0000000000..45454eaf0f --- /dev/null +++ b/arch/arm/include/asm/omap_elm.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, + * Mansoor Ahamed + * + * Derived from work done by Rohit Choraria for omap3 + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_ELM_H +#define __ASM_ARCH_ELM_H +/* + * ELM Module Registers + */ + +/* ELM registers bit fields */ +#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) +#define ELM_SYSCONFIG_SOFTRESET (0x2) +#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) +#define ELM_SYSSTATUS_RESETDONE (0x1) +#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) +#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) +#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) +#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) +#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) +#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) + +#ifndef __ASSEMBLY__ + +enum bch_level { + BCH_4_BIT = 0, + BCH_8_BIT, + BCH_16_BIT +}; + + +/* BCH syndrome registers */ +struct syndrome { + u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ + u8 res1[36]; /* 0x41c */ +}; + +/* BCH error status & location register */ +struct location { + u32 location_status; /* 0x800 */ + u8 res1[124]; /* 0x804 */ + u32 error_location_x[16]; /* 0x880.... */ + u8 res2[64]; /* 0x8c0 */ +}; + +/* BCH ELM register map - do not try to allocate memmory for this structure. + * We have used plenty of reserved variables to fill the slots in the ELM + * register memory map. + * Directly initialize the struct pointer to ELM base address. + */ +struct elm { + u32 rev; /* 0x000 */ + u8 res1[12]; /* 0x004 */ + u32 sysconfig; /* 0x010 */ + u32 sysstatus; /* 0x014 */ + u32 irqstatus; /* 0x018 */ + u32 irqenable; /* 0x01c */ + u32 location_config; /* 0x020 */ + u8 res2[92]; /* 0x024 */ + u32 page_ctrl; /* 0x080 */ + u8 res3[892]; /* 0x084 */ + struct syndrome syndrome_fragments[8]; /* 0x400 */ + u8 res4[512]; /* 0x600 */ + struct location error_location[8]; /* 0x800 */ +}; + +int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, + u32 *error_locations); +int elm_config(enum bch_level level); +void elm_reset(void); +void elm_init(void); +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_ELM_H */ diff --git a/doc/README.nand b/doc/README.nand index 3a507b6c81..ce7ea5e1e9 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -179,6 +179,25 @@ Configuration Options: Please convert your driver even if you don't need the extra flexibility, so that one day we can eliminate the old mechanism. + +Platform specific options +========================= + CONFIG_NAND_OMAP_GPMC + Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms. + GPMC controller is used for parallel NAND flash devices, and can + do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8 + and BCH16 ECC algorithms. + + CONFIG_NAND_OMAP_ELM + Enables omap_elm.c driver for OMAPx and AMxxxx platforms. + ELM controller is used for ECC error detection (not ECC calculation) + of BCH4, BCH8 and BCH16 ECC algorithms. + Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, + thus such SoC platforms need to depend on software library for ECC error + detection. However ECC calculation on such plaforms would still be + done by GPMC controller. + + NOTE: ===== diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index eb1eafaf06..e145cd1842 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_DOCG4) += docg4.o diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c new file mode 100644 index 0000000000..2aa7807f3e --- /dev/null +++ b/drivers/mtd/nand/omap_elm.c @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, + * Mansoor Ahamed + * + * BCH Error Location Module (ELM) support. + * + * NOTE: + * 1. Supports only continuous mode. Dont see need for page mode in uboot + * 2. Supports only syndrome polynomial 0. i.e. poly local variable is + * always set to ELM_DEFAULT_POLY. Dont see need for other polynomial + * sets in uboot + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define ELM_DEFAULT_POLY (0) + +struct elm *elm_cfg; + +/** + * elm_load_syndromes - Load BCH syndromes based on nibble selection + * @syndrome: BCH syndrome + * @nibbles: + * @poly: Syndrome Polynomial set to use + * + * Load BCH syndromes based on nibble selection + */ +static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) +{ + u32 *ptr; + u32 val; + + /* reg 0 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0]; + val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | + (syndrome[3] << 24); + writel(val, ptr); + /* reg 1 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1]; + val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | + (syndrome[7] << 24); + writel(val, ptr); + + /* BCH 8-bit with 26 nibbles (4*8=32) */ + if (nibbles > 13) { + /* reg 2 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; + val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | + (syndrome[11] << 24); + writel(val, ptr); + /* reg 3 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3]; + val = syndrome[12] | (syndrome[13] << 8) | + (syndrome[14] << 16) | (syndrome[15] << 24); + writel(val, ptr); + } + + /* BCH 16-bit with 52 nibbles (7*8=56) */ + if (nibbles > 26) { + /* reg 4 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; + val = syndrome[16] | (syndrome[17] << 8) | + (syndrome[18] << 16) | (syndrome[19] << 24); + writel(val, ptr); + + /* reg 5 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5]; + val = syndrome[20] | (syndrome[21] << 8) | + (syndrome[22] << 16) | (syndrome[23] << 24); + writel(val, ptr); + + /* reg 6 */ + ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]; + val = syndrome[24] | (syndrome[25] << 8) | + (syndrome[26] << 16) | (syndrome[27] << 24); + writel(val, ptr); + } +} + +/** + * elm_check_errors - Check for BCH errors and return error locations + * @syndrome: BCH syndrome + * @nibbles: + * @error_count: Returns number of errrors in the syndrome + * @error_locations: Returns error locations (in decimal) in this array + * + * Check the provided syndrome for BCH errors and return error count + * and locations in the array passed. Returns -1 if error is not correctable, + * else returns 0 + */ +int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, + u32 *error_locations) +{ + u8 poly = ELM_DEFAULT_POLY; + s8 i; + u32 location_status; + + elm_load_syndromes(syndrome, nibbles, poly); + + /* start processing */ + writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) + | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), + &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); + + /* wait for processing to complete */ + while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1) + ; + /* clear status */ + writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), + &elm_cfg->irqstatus); + + /* check if correctable */ + location_status = readl(&elm_cfg->error_location[poly].location_status); + if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) + return -1; + + /* get error count */ + *error_count = readl(&elm_cfg->error_location[poly].location_status) & + ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; + + for (i = 0; i < *error_count; i++) { + error_locations[i] = + readl(&elm_cfg->error_location[poly].error_location_x[i]); + } + + return 0; +} + + +/** + * elm_config - Configure ELM module + * @level: 4 / 8 / 16 bit BCH + * + * Configure ELM module based on BCH level. + * Set mode as continuous mode. + * Currently we are using only syndrome 0 and syndromes 1 to 6 are not used. + * Also, the mode is set only for syndrome 0 + */ +int elm_config(enum bch_level level) +{ + u32 val; + u8 poly = ELM_DEFAULT_POLY; + u32 buffer_size = 0x7FF; + + /* config size and level */ + val = (u32)(level) & ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK; + val |= ((buffer_size << ELM_LOCATION_CONFIG_ECC_SIZE_POS) & + ELM_LOCATION_CONFIG_ECC_SIZE_MASK); + writel(val, &elm_cfg->location_config); + + /* config continous mode */ + /* enable interrupt generation for syndrome polynomial set */ + writel((readl(&elm_cfg->irqenable) | (0x1 << poly)), + &elm_cfg->irqenable); + /* set continuous mode for the syndrome polynomial set */ + writel((readl(&elm_cfg->page_ctrl) & ~(0x1 << poly)), + &elm_cfg->page_ctrl); + + return 0; +} + +/** + * elm_reset - Do a soft reset of ELM + * + * Perform a soft reset of ELM and return after reset is done. + */ +void elm_reset(void) +{ + /* initiate reset */ + writel((readl(&elm_cfg->sysconfig) | ELM_SYSCONFIG_SOFTRESET), + &elm_cfg->sysconfig); + + /* wait for reset complete and normal operation */ + while ((readl(&elm_cfg->sysstatus) & ELM_SYSSTATUS_RESETDONE) != + ELM_SYSSTATUS_RESETDONE) + ; +} + +/** + * elm_init - Initialize ELM module + * + * Initialize ELM support. Currently it does only base address init + * and ELM reset. + */ +void elm_init(void) +{ + elm_cfg = (struct elm *)ELM_BASE; + elm_reset(); +} diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index ec1787f224..c8288597a4 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -16,7 +16,7 @@ #include #include #ifdef CONFIG_AM33XX -#include +#include #endif static uint8_t cs; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c2ba7e35d8..73d8b4dfba 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -221,6 +221,8 @@ #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #ifdef CONFIG_NAND +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ CONFIG_SYS_NAND_PAGE_SIZE) diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 2c69d4e30c..88ced7311f 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -187,6 +187,7 @@ /* NAND support */ #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 9eb0a04da6..f3b41975cf 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -431,6 +431,7 @@ "\0" #define CONFIG_NAND_OMAP_GPMC +#define CONFIG_NAND_OMAP_ELM #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ -- cgit v1.2.1 From d016dc42cedbf6102e100fa9ecb58462edfb14f8 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 18 Nov 2013 19:03:00 +0530 Subject: mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours +-----------------------------------+-----------------+-----------------+ |ECC Scheme | ECC Calculation | Error Detection | +-----------------------------------+-----------------+-----------------+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +-----------------------------------+-----------------+-----------------+ Current implementation limits the BCH8_CODE_HW only for AM33xx device family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM. This patch - removes CONFIG_AM33xx Thus this driver can be reused by all devices having ELM h/w engine. - adds omap_select_ecc_scheme() A common function to handle ecc-scheme related configurations. This can be used both during device-probe and via user-space u-boot commads to change ecc-scheme. During device probe ecc-scheme is selected based on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8 - enables CONFIG_BCH S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW is enabled by CONFIG_BCH. - enables CONFIG_SYS_NAND_ONFI_DETECTION for auto-detection of ONFI compliant NAND devices - updates following README doc doc/README.nand board/ti/am335x/README doc/README.omap3 Signed-off-by: Pekon Gupta [scottwood@freescale.com: fixed unused variable warning] Signed-off-by: Scott Wood --- arch/arm/include/asm/omap_gpmc.h | 16 ++ doc/README.nand | 11 ++ drivers/mtd/nand/omap_gpmc.c | 326 ++++++++++++++++++++++++--------------- 3 files changed, 228 insertions(+), 125 deletions(-) diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h index dd40cb6c16..d4143ecd80 100644 --- a/arch/arm/include/asm/omap_gpmc.h +++ b/arch/arm/include/asm/omap_gpmc.h @@ -68,4 +68,20 @@ } #endif +enum omap_ecc { + /* 1-bit ECC calculation by Software, Error detection by Software */ + OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ + /* 1-bit ECC calculation by GPMC, Error detection by Software */ + /* ECC layout compatible to legacy ROMCODE. */ + OMAP_ECC_HAM1_CODE_HW, + /* 4-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, + /* 4-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH4_CODE_HW, + /* 8-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + /* 8-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH8_CODE_HW, +}; + #endif /* __ASM_OMAP_GPMC_H */ diff --git a/doc/README.nand b/doc/README.nand index ce7ea5e1e9..487548fcb8 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -180,6 +180,17 @@ Configuration Options: flexibility, so that one day we can eliminate the old mechanism. + CONFIG_SYS_NAND_ONFI_DETECTION + Enables detection of ONFI compliant devices during probe. + And fetching device parameters flashed on device, by parsing + ONFI parameter page. + + CONFIG_BCH + Enables software based BCH ECC algorithm present in lib/bch.c + This is used by SoC platforms which do not have built-in ELM + hardware engine required for BCH ECC correction. + + Platform specific options ========================= CONFIG_NAND_OMAP_GPMC diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index c8288597a4..e6b289dec8 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -15,15 +15,13 @@ #include #include #include -#ifdef CONFIG_AM33XX #include -#endif + +#define BADBLOCK_MARKER_LENGTH 2 +#define SECTOR_BYTES 512 static uint8_t cs; -static __maybe_unused struct nand_ecclayout hw_nand_oob = - GPMC_NAND_HW_ECC_LAYOUT; -static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob = - GPMC_NAND_HW_BCH8_ECC_LAYOUT; +static __maybe_unused struct nand_ecclayout omap_ecclayout; /* * omap_nand_hwcontrol - Set the address pointers corretly for the @@ -233,6 +231,7 @@ struct nand_bch_priv { uint8_t type; uint8_t nibbles; struct bch_control *control; + enum omap_ecc ecc_scheme; }; /* bch types */ @@ -274,17 +273,15 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) { uint32_t val; uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; -#ifdef CONFIG_AM33XX uint32_t unused_length = 0; -#endif uint32_t wr_mode = BCH_WRAPMODE_6; struct nand_bch_priv *bch = chip->priv; /* Clear the ecc result registers, select ecc reg as 1 */ writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); -#ifdef CONFIG_AM33XX - wr_mode = BCH_WRAPMODE_1; + if (bch->ecc_scheme == OMAP_ECC_BCH8_CODE_HW) { + wr_mode = BCH_WRAPMODE_1; switch (bch->nibbles) { case ECC_BCH4_NIBBLES: @@ -320,7 +317,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) val |= (unused_length << 22); break; } -#else + } else { /* * This ecc_size_config setting is for BCH sw library. * @@ -333,7 +330,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) */ val = (32 << 22) | (0 << 12); -#endif + } /* ecc size configuration */ writel(val, &gpmc_cfg->ecc_size_config); @@ -376,9 +373,9 @@ static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) } /* - * BCH8 support (needs ELM and thus AM33xx-only) + * BCH support using ELM module */ -#ifdef CONFIG_AM33XX +#ifdef CONFIG_NAND_OMAP_ELM /* * omap_read_bch8_result - Read BCH result for BCH8 level * @@ -631,20 +628,20 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, } return 0; } -#endif /* CONFIG_AM33XX */ +#endif /* CONFIG_NAND_OMAP_ELM */ /* * OMAP3 BCH8 support (with BCH library) */ -#ifdef CONFIG_NAND_OMAP_BCH8 +#ifdef CONFIG_BCH /* - * omap_calculate_ecc_bch - Read BCH ECC result + * omap_calculate_ecc_bch_sw - Read BCH ECC result * * @mtd: MTD device structure * @dat: The pointer to data on which ecc is computed (unused here) * @ecc: The ECC output buffer */ -static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, +static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc) { int ret = 0; @@ -689,13 +686,13 @@ static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, } /** - * omap_correct_data_bch - Decode received data and correct errors + * omap_correct_data_bch_sw - Decode received data and correct errors * @mtd: MTD device structure * @data: page data * @read_ecc: ecc read from nand flash * @calc_ecc: ecc read from HW ECC registers */ -static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, +static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, u_char *read_ecc, u_char *calc_ecc) { int i, count; @@ -752,7 +749,150 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) chip_priv->control = NULL; } } -#endif /* CONFIG_NAND_OMAP_BCH8 */ +#endif /* CONFIG_BCH */ + +/** + * omap_select_ecc_scheme - configures driver for particular ecc-scheme + * @nand: NAND chip device structure + * @ecc_scheme: ecc scheme to configure + * @pagesize: number of main-area bytes per page of NAND device + * @oobsize: number of OOB/spare bytes per page of NAND device + */ +static int omap_select_ecc_scheme(struct nand_chip *nand, + enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { + struct nand_bch_priv *bch = nand->priv; + struct nand_ecclayout *ecclayout = nand->ecc.layout; + int eccsteps = pagesize / SECTOR_BYTES; + int i; + + switch (ecc_scheme) { + case OMAP_ECC_HAM1_CODE_SW: + debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); + /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are + * initialized in nand_scan_tail(), so just set ecc.mode */ + bch_priv.control = NULL; + bch_priv.type = 0; + nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = NULL; + nand->ecc.size = pagesize; + bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW; + break; + + case OMAP_ECC_HAM1_CODE_HW: + debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + bch_priv.control = NULL; + bch_priv.type = 0; + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 1; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 3; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW; + break; + + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: +#ifdef CONFIG_BCH + debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (13 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* check if BCH S/W library can be used for error detection */ + bch_priv.control = init_bch(13, 8, 0x201b); + if (!bch_priv.control) { + printf("nand: error: could not init_bch()\n"); + return -ENODEV; + } + bch_priv.type = ECC_BCH8; + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 8; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 13; + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch_sw; + nand->ecc.calculate = omap_calculate_ecc_bch_sw; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; + for (i = 1; i < ecclayout->eccbytes; i++) { + if (i % nand->ecc.bytes) + ecclayout->eccpos[i] = + ecclayout->eccpos[i - 1] + 1; + else + ecclayout->eccpos[i] = + ecclayout->eccpos[i - 1] + 2; + } + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + omap_hwecc_init_bch(nand, NAND_ECC_READ); + bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; + break; +#else + printf("nand: error: CONFIG_BCH required for ECC\n"); + return -EINVAL; +#endif + + case OMAP_ECC_BCH8_CODE_HW: +#ifdef CONFIG_NAND_OMAP_ELM + debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n"); + /* check ecc-scheme requirements before updating ecc info */ + if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { + printf("nand: error: insufficient OOB: require=%d\n", ( + (14 * eccsteps) + BADBLOCK_MARKER_LENGTH)); + return -EINVAL; + } + /* intialize ELM for ECC error detection */ + elm_init(); + bch_priv.type = ECC_BCH8; + /* populate ecc specific fields */ + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.strength = 8; + nand->ecc.size = SECTOR_BYTES; + nand->ecc.bytes = 14; + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + nand->ecc.read_page = omap_read_page_bch; + /* define ecc-layout */ + ecclayout->eccbytes = nand->ecc.bytes * eccsteps; + for (i = 0; i < ecclayout->eccbytes; i++) + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; + ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - + BADBLOCK_MARKER_LENGTH; + bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW; + break; +#else + printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); + return -EINVAL; +#endif + + default: + debug("nand: error: ecc scheme not enabled or supported\n"); + return -EINVAL; + } + return 0; +} #ifndef CONFIG_SPL_BUILD /* @@ -763,77 +903,45 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) * @eccstrength - the number of bits that could be corrected * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) */ -void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) +int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) { struct nand_chip *nand; struct mtd_info *mtd; + int err = 0; if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[nand_curr_device].name) { - printf("Error: Can't switch ecc, no devices available\n"); - return; + printf("nand: error: no NAND devices found\n"); + return -ENODEV; } mtd = &nand_info[nand_curr_device]; nand = mtd->priv; - nand->options |= NAND_OWN_BUFFERS; - - /* Reset ecc interface */ - nand->ecc.mode = NAND_ECC_NONE; - nand->ecc.read_page = NULL; - nand->ecc.write_page = NULL; - nand->ecc.read_oob = NULL; - nand->ecc.write_oob = NULL; - nand->ecc.hwctl = NULL; - nand->ecc.correct = NULL; - nand->ecc.calculate = NULL; - nand->ecc.strength = eccstrength; - /* Setup the ecc configurations again */ if (hardware) { if (eccstrength == 1) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - omap_hwecc_init(nand); - printf("1-bit hamming HW ECC selected\n"); - } -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) - else if (eccstrength == 8) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; - nand->ecc.size = 512; -#ifdef CONFIG_AM33XX - nand->ecc.bytes = 14; - nand->ecc.read_page = omap_read_page_bch; -#else - nand->ecc.bytes = 13; -#endif - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; - omap_hwecc_init_bch(nand, NAND_ECC_READ); - printf("8-bit BCH HW ECC selected\n"); + err = omap_select_ecc_scheme(nand, + OMAP_ECC_HAM1_CODE_HW, + mtd->writesize, mtd->oobsize); + } else if (eccstrength == 8) { + err = omap_select_ecc_scheme(nand, + OMAP_ECC_BCH8_CODE_HW, + mtd->writesize, mtd->oobsize); + } else { + printf("nand: error: unsupported ECC scheme\n"); + return -EINVAL; } -#endif } else { - nand->ecc.mode = NAND_ECC_SOFT; - /* Use mtd default settings */ - nand->ecc.layout = NULL; - nand->ecc.size = 0; - printf("SW ECC selected\n"); + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + mtd->writesize, mtd->oobsize); } /* Update NAND handling after ECC mode switch */ - nand_scan_tail(mtd); - - nand->options &= ~NAND_OWN_BUFFERS; + if (!err) + err = nand_scan_tail(mtd); + return err; } #endif /* CONFIG_SPL_BUILD */ @@ -856,7 +964,7 @@ int board_nand_init(struct nand_chip *nand) { int32_t gpmc_config = 0; cs = 0; - + int err = 0; /* * xloader/Uboot's gpmc configuration would have configured GPMC for * nand type of memory. The following logic scans and latches on to the @@ -873,7 +981,7 @@ int board_nand_init(struct nand_chip *nand) cs++; } if (cs >= GPMC_MAX_CS) { - printf("NAND: Unable to find NAND settings in " + printf("nand: error: Unable to find NAND settings in " "GPMC Configuration - quitting\n"); return -ENODEV; } @@ -885,64 +993,32 @@ int board_nand_init(struct nand_chip *nand) nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; - - nand->cmd_ctrl = omap_nand_hwcontrol; - nand->options = NAND_NO_PADDING | NAND_CACHEPRG; + nand->priv = &bch_priv; + nand->cmd_ctrl = omap_nand_hwcontrol; + nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; /* If we are 16 bit dev, our gpmc config tells us that */ if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) nand->options |= NAND_BUSWIDTH_16; nand->chip_delay = 100; - -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) -#ifdef CONFIG_AM33XX - /* AM33xx uses the ELM */ - /* required in case of BCH */ - elm_init(); -#else - /* - * Whereas other OMAP based SoC do not have the ELM, they use the BCH - * SW library. - */ - bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */); - if (!bch_priv.control) { - puts("Could not init_bch()\n"); - return -ENODEV; - } -#endif - /* BCH info that will be correct for SPL or overridden otherwise. */ - nand->priv = &bch_priv; -#endif - - /* Default ECC mode */ -#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; - nand->ecc.strength = 8; - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; -#ifdef CONFIG_AM33XX - nand->ecc.read_page = omap_read_page_bch; -#endif - omap_hwecc_init_bch(nand, NAND_ECC_READ); -#else -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) - nand->ecc.mode = NAND_ECC_SOFT; + nand->ecc.layout = &omap_ecclayout; + + /* select ECC scheme */ +#if defined(CONFIG_NAND_OMAP_ELM) + err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); +#elif defined(CONFIG_NAND_OMAP_BCH8) + err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); +#elif !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, + 0, 0); #else - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - nand->ecc.strength = 1; - omap_hwecc_init(nand); -#endif + err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_HW, + CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); #endif + if (err) + return err; #ifdef CONFIG_SPL_BUILD if (nand->options & NAND_BUSWIDTH_16) -- cgit v1.2.1 From 3f719069c884284b2457448a7afe32b02bd4f782 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 18 Nov 2013 19:03:01 +0530 Subject: mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed CONFIG_xx used for selecting NAND ecc-schemes. This patch aims at solving following issues. 1) Currently ecc-scheme is tied to SoC platform, which prevents user to select other ecc-schemes also supported in hardware. like; - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW). - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware supports BCH16 ecc-scheme also. 2) Different platforms use different CONFIG_xx to select ecc-schemes, which adds confusion for user while migrating platforms. - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only 8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW) whereas ELM hardware engine supports other ecc-schemes also like; BCH4, and BCH16 (in future). - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW). - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency on SoC platform and NAND driver. And user can select ecc-scheme independently foreach board. However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand) Signed-off-by: Pekon Gupta --- doc/README.nand | 23 +++++++++++++++++++++++ doc/README.omap3 | 3 +-- drivers/mtd/nand/omap_gpmc.c | 13 ++++--------- include/configs/am335x_evm.h | 3 ++- include/configs/am335x_igep0033.h | 1 + include/configs/am3517_crane.h | 1 + include/configs/am3517_evm.h | 1 + include/configs/devkit8000.h | 1 + include/configs/mcx.h | 2 +- include/configs/omap3_beagle.h | 1 + include/configs/omap3_evm.h | 1 + include/configs/omap3_evm_quick_nand.h | 1 + include/configs/omap3_igep00x0.h | 1 + include/configs/omap3_overo.h | 1 + include/configs/siemens-am33x-common.h | 1 + include/configs/tam3517-common.h | 2 +- include/configs/tricorder.h | 2 +- 17 files changed, 43 insertions(+), 15 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index 487548fcb8..b91f1985d1 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -208,6 +208,29 @@ Platform specific options detection. However ECC calculation on such plaforms would still be done by GPMC controller. + CONFIG_NAND_OMAP_ECCSCHEME + On OMAP platforms, this CONFIG specifies NAND ECC scheme. + It can take following values: + OMAP_ECC_HAM1_CODE_SW + 1-bit Hamming code using software lib. + (for legacy devices only) + OMAP_ECC_HAM1_CODE_HW + 1-bit Hamming code using GPMC hardware. + (for legacy devices only) + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW + 4-bit BCH code (unsupported) + OMAP_ECC_BCH4_CODE_HW + 4-bit BCH code (unsupported) + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + 8-bit BCH code with + - ecc calculation using GPMC hardware engine, + - error detection using software library. + - requires CONFIG_BCH to enable software BCH library + (For legacy device which do not have ELM h/w engine) + OMAP_ECC_BCH8_CODE_HW + 8-bit BCH code with + - ecc calculation using GPMC hardware engine, + - error detection using ELM hardware engine. NOTE: ===== diff --git a/doc/README.omap3 b/doc/README.omap3 index 1fbe79db37..a62c357405 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -161,8 +161,7 @@ BCH8 To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH -to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted -syndrom generation to your board config. +and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW. The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8 implementation for OMAP3 works for you so the u-boot version should also. When you require the SPL to read with BCH8 there are two more configs to diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index e6b289dec8..5e7e6b3375 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -1004,18 +1004,13 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.layout = &omap_ecclayout; /* select ECC scheme */ -#if defined(CONFIG_NAND_OMAP_ELM) - err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW, +#if defined(CONFIG_NAND_OMAP_ECCSCHEME) + err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); -#elif defined(CONFIG_NAND_OMAP_BCH8) - err = omap_select_ecc_scheme(nand, OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, - CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); -#elif !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) +#else + /* pagesize and oobsize are not required to configure sw ecc-scheme */ err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, 0, 0); -#else - err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_HW, - CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); #endif if (err) return err; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 73d8b4dfba..1d5916753d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -240,7 +240,8 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 - +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 88ced7311f..115d1b37c9 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -264,6 +264,7 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index c5e67bf87d..b24ef54143 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -340,6 +340,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 5ff65c6d58..f13fd7001c 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -334,6 +334,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 8343891cb8..13315dc4b6 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -327,6 +327,7 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 4619dfb3e4..56102f5712 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -353,7 +353,6 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT @@ -395,6 +394,7 @@ 56, 57, 58, 59, 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 47d9902088..8b68635668 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -432,6 +432,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 3ace8bb6e5..b7638fb8a6 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -107,6 +107,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 9ecd70d55b..4427e88b7e 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -86,6 +86,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index ac36ac6950..cdaa9ba9a4 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -362,6 +362,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 46416946c7..00d7c6cebc 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -325,6 +325,7 @@ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index f3b41975cf..e3944782f6 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -196,6 +196,7 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 14 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_ECCSTEPS 4 #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 683bc54a2c..48698b57da 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -225,7 +225,6 @@ #define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_CONSOLE #define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_NAND_SOFTECC #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */ #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -262,6 +261,7 @@ 56, 57, 58, 59, 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 590eab7e48..3ca1fd0e65 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -138,7 +138,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_NAND_OMAP_BCH8 #define CONFIG_BCH #define CONFIG_SYS_NAND_MAX_OOBFREE 2 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 @@ -376,6 +375,7 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -- cgit v1.2.1 From 2c17e6d1d996a1b8b9325de15f253a13d5877dee Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Mon, 18 Nov 2013 19:03:02 +0530 Subject: am335x: fix GPMC config for NAND and NOR SPL boot GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot. Signed-off-by: Pekon Gupta --- arch/arm/cpu/armv7/am33xx/mem.c | 52 +++++++++++++++++++--------------- arch/arm/include/asm/arch-am33xx/mem.h | 5 ---- board/ti/am335x/board.c | 14 +-------- 3 files changed, 30 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index b6eb46678f..56c9e7dbce 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -22,17 +22,6 @@ struct gpmc *gpmc_cfg; -#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif - void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) @@ -61,11 +50,34 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; - -#ifdef CONFIG_CMD_NAND - const u32 *gpmc_config = NULL; - u32 base = 0; +#if defined(CONFIG_NOR) +/* configure GPMC for NOR */ + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 size = GPMC_SIZE_16M; + u32 base = CONFIG_SYS_FLASH_BASE; +#elif defined(CONFIG_NAND) +/* configure GPMC for NAND */ + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_256M; + u32 base = CONFIG_SYS_NAND_BASE; +#else + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; u32 size = 0; + u32 base = 0; #endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); @@ -81,12 +93,6 @@ void gpmc_init(void) */ writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000); - -#ifdef CONFIG_CMD_NAND - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index 983ea28dc0..e7e8c58b00 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -68,9 +68,4 @@ #define PISMO2_NAND_CS0 7 #define PISMO2_NAND_CS1 8 -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE -#define PISMO1_NAND_SIZE GPMC_SIZE_256M - #endif /* endif _MEM_H_ */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57fedab340..0299dd6486 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -481,26 +481,14 @@ void sdram_init(void) */ int board_init(void) { -#ifdef CONFIG_NOR - const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; -#endif - #if defined(CONFIG_HW_WATCHDOG) hw_watchdog_init(); #endif gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - +#if defined(CONFIG_NOR) || defined(CONFIG_NAND) gpmc_init(); - -#ifdef CONFIG_NOR - /* Reconfigure CS0 for NOR instead of NAND. */ - enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], - CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); #endif - return 0; } -- cgit v1.2.1 From 5c8fdd91dcc5c8f7da072d96df965e0399750e07 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Tue, 12 Nov 2013 11:14:41 +0100 Subject: patman: add Commit-notes tag and section Sometimes a commit should have notes enclosed with it rather than withing the cover letter -- possibly even because there is no cover letter. Add a 'Commit-notes' tag, similar to the 'Series-notes' one; lines between this tag and the next END line are inserted in the patch right after the '---' commit delimiter. Change-Id: I01e99ae125607dc6dec08f3be8a5a0b37f0a483d Signed-off-by: Albert ARIBAUD Signed-off-by: Simon Glass (Updated README) --- tools/patman/README | 10 +++++++++- tools/patman/commit.py | 2 ++ tools/patman/patchstream.py | 43 ++++++++++++++++++++++++++++++++++++------- 3 files changed, 47 insertions(+), 8 deletions(-) diff --git a/tools/patman/README b/tools/patman/README index e6d3070621..59f1776f54 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -180,6 +180,14 @@ END together and put after the cover letter. Can appear multiple times. +Commit-notes: +blah blah +blah blah +more blah blah +END + Similar, but for a single commit (patch). These notes will appear + immediately below the --- cut in the patch file. + Signed-off-by: Their Name A sign-off is added automatically to your patches (this is probably a bug). If you put this tag in your patches, it will @@ -227,7 +235,7 @@ TEST=... Change-Id: Review URL: Reviewed-on: - +Commit-xxxx: (except Commit-notes) Exercise for the reader: Try adding some tags to one of your current patch series and see how the patches turn out. diff --git a/tools/patman/commit.py b/tools/patman/commit.py index 900cfb3a5a..89cce7f88a 100644 --- a/tools/patman/commit.py +++ b/tools/patman/commit.py @@ -21,6 +21,7 @@ class Commit: changes: Dict containing a list of changes (single line strings). The dict is indexed by change version (an integer) cc_list: List of people to aliases/emails to cc on this commit + notes: List of lines in the commit (not series) notes """ def __init__(self, hash): self.hash = hash @@ -28,6 +29,7 @@ class Commit: self.tags = [] self.changes = {} self.cc_list = [] + self.notes = [] def AddChange(self, version, info): """Add a new change line to the change list for a version. diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index c2045230af..684204c63f 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -30,7 +30,10 @@ re_cover = re.compile('^Cover-letter:') re_cover_cc = re.compile('^Cover-letter-cc: *(.*)') # Patch series tag -re_series = re.compile('^Series-([a-z-]*): *(.*)') +re_series_tag = re.compile('^Series-([a-z-]*): *(.*)') + +# Commit series tag +re_commit_tag = re.compile('^Commit-([a-z-]*): *(.*)') # Commit tags that we want to collect and keep re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)') @@ -90,6 +93,20 @@ class PatchStream: if self.is_log: self.series.AddTag(self.commit, line, name, value) + def AddToCommit(self, line, name, value): + """Add a new Commit-xxx tag. + + When a Commit-xxx tag is detected, we come here to record it. + + Args: + line: Source line containing tag (useful for debug/error messages) + name: Tag name (part after 'Commit-') + value: Tag value (part after 'Commit-xxx: ') + """ + if name == 'notes': + self.in_section = 'commit-' + name + self.skip_blank = False + def CloseCommit(self): """Save the current commit into our commit list, and reset our state""" if self.commit and self.is_log: @@ -138,7 +155,8 @@ class PatchStream: line = line[4:] # Handle state transition and skipping blank lines - series_match = re_series.match(line) + series_tag_match = re_series_tag.match(line) + commit_tag_match = re_commit_tag.match(line) commit_match = re_commit.match(line) if self.is_log else None cover_cc_match = re_cover_cc.match(line) tag_match = None @@ -165,6 +183,9 @@ class PatchStream: elif self.in_section == 'notes': if self.is_log: self.series.notes += self.section + elif self.in_section == 'commit-notes': + if self.is_log: + self.commit.notes += self.section else: self.warn.append("Unknown section '%s'" % self.in_section) self.in_section = None @@ -178,7 +199,7 @@ class PatchStream: self.commit.subject = line # Detect the tags we want to remove, and skip blank lines - elif re_remove.match(line): + elif re_remove.match(line) and not commit_tag_match: self.skip_blank = True # TEST= should be the last thing in the commit, so remove @@ -211,9 +232,9 @@ class PatchStream: self.skip_blank = False # Detect Series-xxx tags - elif series_match: - name = series_match.group(1) - value = series_match.group(2) + elif series_tag_match: + name = series_tag_match.group(1) + value = series_tag_match.group(2) if name == 'changes': # value is the version number: e.g. 1, or 2 try: @@ -226,6 +247,14 @@ class PatchStream: self.AddToSeries(line, name, value) self.skip_blank = True + # Detect Commit-xxx tags + elif commit_tag_match: + name = commit_tag_match.group(1) + value = commit_tag_match.group(2) + if name == 'notes': + self.AddToCommit(line, name, value) + self.skip_blank = True + # Detect the start of a new commit elif commit_match: self.CloseCommit() @@ -276,7 +305,7 @@ class PatchStream: out = [] log = self.series.MakeChangeLog(self.commit) out += self.FormatTags(self.tags) - out += [line] + log + out += [line] + self.commit.notes + [''] + log elif self.found_test: if not re_allowed_after_test.match(line): self.lines_after_test += 1 -- cgit v1.2.1 From 61242ac5f92604621deef16a4362948bafc757e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Tue, 5 Nov 2013 10:37:09 +0100 Subject: buildman: fix README MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a trivial fix for c'n'p error. Signed-off-by: Andreas Bießmann Acked-by: Simon Glass --- tools/buildman/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/buildman/README b/tools/buildman/README index 090b653116..93cf28af38 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -643,7 +643,7 @@ snapper9260=${at91-boards} BUILD_TAG=442 snapper9g45=${at91-boards} BUILD_TAG=443 This will use 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9260 -and 'make ENABLE_AT91_TEST=1 BUILD_TAG=442' for snapper9g45. A special +and 'make ENABLE_AT91_TEST=1 BUILD_TAG=443' for snapper9g45. A special variable ${target} is available to access the target name (snapper9260 and snapper9g20 in this case). Variables are resolved recursively. -- cgit v1.2.1 From 8426d8b0899eb6a9845b3468662512a8da236241 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 10 Oct 2013 10:00:20 -0600 Subject: buildman: make board selector argument a regex A common use-case is to build all boards for a particular SoC. This can be achieved by: ./tools/buildman/buildman -b mainline_dev tegra20 However, when the SoC is a member of a family of SoCs, and each SoC has a different name, it would be even more useful to build all boards for every SoC in that family. This currently isn't possible since buildman's board selection command-line arguments are compared to board definitions using pure string equality. To enable this, compare using a regex match instead. This matches MAKEALL's handling of command-line arguments. This enables: (all Tegra) ./tools/buildman/buildman -b mainline_dev tegra (all Tegra) ./tools/buildman/buildman -b mainline_dev '^tegra.*$' (all Tegra20, Tegra30 boards, but not Tegra114) ./tools/buildman/buildman -b mainline_dev 'tegra[23]' Signed-off-by: Stephen Warren Acked-by: Simon Glass --- tools/buildman/README | 14 ++++++++++---- tools/buildman/board.py | 12 +++++++++++- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/tools/buildman/README b/tools/buildman/README index 93cf28af38..c30c1d4114 100644 --- a/tools/buildman/README +++ b/tools/buildman/README @@ -89,10 +89,16 @@ a few commits or boards, it will be pretty slow. As a tip, if you don't plan to use your machine for anything else, you can use -T to increase the number of threads beyond the default. -Buildman lets you build all boards, or a subset. Specify the subset using -the board name, architecture name, SOC name, or anything else in the -boards.cfg file. So 'at91' will build all AT91 boards (arm), powerpc will -build all PowerPC boards. +Buildman lets you build all boards, or a subset. Specify the subset by passing +command-line arguments that list the desired board name, architecture name, +SOC name, or anything else in the boards.cfg file. Multiple arguments are +allowed. Each argument will be interpreted as a regular expression, so +behaviour is a superset of exact or substring matching. Examples are: + +* 'tegra20' All boards with a Tegra20 SoC +* 'tegra' All boards with any Tegra Soc (Tegra20, Tegra30, Tegra114...) +* '^tegra[23]0$' All boards with either Tegra20 or Tegra30 SoC +* 'powerpc' All PowerPC boards Buildman does not store intermediate object files. It optionally copies the binary output into a directory when a build is successful. Size diff --git a/tools/buildman/board.py b/tools/buildman/board.py index 1d3db206bd..5172a473e3 100644 --- a/tools/buildman/board.py +++ b/tools/buildman/board.py @@ -3,6 +3,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +import re + class Board: """A particular board that we can build""" def __init__(self, status, arch, cpu, soc, vendor, board_name, target, options): @@ -135,14 +137,22 @@ class Boards: due to each argument, arranged by argument. """ result = {} + argres = {} for arg in args: result[arg] = 0 + argres[arg] = re.compile(arg) result['all'] = 0 for board in self._boards: if args: for arg in args: - if arg in board.props: + argre = argres[arg] + match = False + for prop in board.props: + match = argre.match(prop) + if match: + break + if match: if not board.build_it: board.build_it = True result[arg] += 1 -- cgit v1.2.1 From 2a54d1599f4c3a95b1d39db45888b49c36465af3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 19 May 2013 16:45:35 -0700 Subject: sandbox: Use uint64_t instead of u64 for time The uint64_t type is defined in linux/types.h, so is safer than u64, which is not actually a Linux type. Change-Id: Ifc9a369e6543250c49117b8d3cb3a676eee43e04 Signed-off-by: Simon Glass --- arch/sandbox/cpu/os.c | 3 ++- include/os.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index c2e5f57193..db66fd31f2 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -136,7 +137,7 @@ void os_usleep(unsigned long usec) usleep(usec); } -u64 __attribute__((no_instrument_function)) os_get_nsec(void) +uint64_t __attribute__((no_instrument_function)) os_get_nsec(void) { #if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK) struct timespec tp; diff --git a/include/os.h b/include/os.h index 8665f70edb..950433daa3 100644 --- a/include/os.h +++ b/include/os.h @@ -11,6 +11,8 @@ #ifndef __OS_H__ #define __OS_H__ +#include + struct sandbox_state; /** @@ -116,7 +118,7 @@ void os_usleep(unsigned long usec); * * \return A monotonic increasing time scaled in nano seconds */ -u64 os_get_nsec(void); +uint64_t os_get_nsec(void); /** * Parse arguments and update sandbox state. -- cgit v1.2.1 From cbe5cdfcd31633edce4ee78ebc008b922de571e3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 10 Nov 2013 10:26:48 -0700 Subject: sandbox: Use system headers first for sandbox's os.c This file must be compiled with system headers, even if U-Boot has headers of the same name. The existing solution for this is good enough for libfdt, but fails when we have headers like stdint.h in U-Boot. Use -idirafter instead of -I, and remove the -nostdinc and other things that we don't want for this file. The best way to do this is to keep a copy of the original flags, rather than trying to filter them later. Signed-off-by: Simon Glass --- arch/sandbox/cpu/Makefile | 6 ++++-- config.mk | 9 +++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 404ff6793f..58c2537762 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -10,5 +10,7 @@ obj-y := cpu.o os.o start.o state.o # os.c is build in the system environment, so needs standard includes -$(obj)os.o: ALL_CFLAGS := $(filter-out -nostdinc,$(ALL_CFLAGS)) -$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,$(CPPFLAGS)) +$(obj)os.o: ALL_CFLAGS := $(BASE_CPPFLAGS) \ + $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) +$(obj).depend.os: CPPFLAGS := $(BASE_CPPFLAGS) \ + $(patsubst %, -idirafter %, $(BASE_INCLUDE_DIRS)) diff --git a/config.mk b/config.mk index 206de203cc..d5b09a0095 100644 --- a/config.mk +++ b/config.mk @@ -250,11 +250,16 @@ Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file) endif endif +# Sandbox needs the base flags and includes, so keep them around +BASE_CPPFLAGS := $(CPPFLAGS) + ifneq ($(OBJTREE),$(SRCTREE)) -CPPFLAGS += -I$(OBJTREE)/include +BASE_INCLUDE_DIRS := $(OBJTREE)/include endif -CPPFLAGS += -I$(TOPDIR)/include -I$(SRCTREE)/arch/$(ARCH)/include +BASE_INCLUDE_DIRS += $(TOPDIR)/include $(SRCTREE)/arch/$(ARCH)/include + +CPPFLAGS += $(patsubst %, -I%, $(BASE_INCLUDE_DIRS)) CPPFLAGS += -fno-builtin -ffreestanding -nostdinc \ -isystem $(gccincdir) -pipe $(PLATFORM_CPPFLAGS) -- cgit v1.2.1 From 0eb2acee394b16dd734f5f48b2cbf2f22065d060 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 10 Nov 2013 10:26:53 -0700 Subject: sandbox: config: Don't use 64-bit physical memory Sandbox uses an emulated memory map which is quite small. We don't need the CONFIG_PHYS_64BIT option since we can address memory with a 32-bit offset into our ram_buf. Adjust the phys_addr_t and phys_size_t types accordingly. Signed-off-by: Simon Glass Signed-off-by: Simon Glass Reviewed-by: Hung-ying Tyan --- arch/sandbox/include/asm/types.h | 4 ++-- include/configs/sandbox.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h index 88c84bae7c..6d3eb1f3de 100644 --- a/arch/sandbox/include/asm/types.h +++ b/arch/sandbox/include/asm/types.h @@ -48,8 +48,8 @@ typedef unsigned long long u64; #define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG typedef unsigned long dma_addr_t; -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; +typedef u32 phys_addr_t; +typedef u32 phys_size_t; #endif /* __KERNEL__ */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 0884ad3a02..a4edc624bc 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -75,7 +75,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x00000000 #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) -#define CONFIG_PHYS_64BIT #define CONFIG_SYS_FDT_LOAD_ADDR 0x1000000 /* Size of our emulated memory */ -- cgit v1.2.1 From 370b6c5c4d764192399a220095a2dd1054314147 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 10 Nov 2013 10:26:54 -0700 Subject: sandbox: Correct data sizes and printf() strings in fdtdec.c There are a few wwrnings in this file when building for sandbox. Addresses coming from the device tree need to be treated as ulong as elsewhere in U-Boot and we must use map_sysmem() to convert to a pointer when needed. Signed-off-by: Simon Glass Signed-off-by: Simon Glass Reviewed-by: Hung-ying Tyan --- lib/fdtdec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 51fa868333..207314fa72 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -86,10 +86,10 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, size = (fdt_size_t *)((char *)cell + sizeof(fdt_addr_t)); *sizep = fdt_size_to_cpu(*size); - debug("addr=%p, size=%p\n", (void *)addr, - (void *)*sizep); + debug("addr=%08lx, size=%08x\n", + (ulong)addr, *sizep); } else { - debug("%p\n", (void *)addr); + debug("%08lx\n", (ulong)addr); } return addr; } @@ -611,7 +611,7 @@ int fdtdec_decode_region(const void *blob, int node, if (!cell || (len != sizeof(fdt_addr_t) * 2)) return -1; - *ptrp = (void *)fdt_addr_to_cpu(*cell); + *ptrp = map_sysmem(fdt_addr_to_cpu(*cell), *size); *size = fdt_size_to_cpu(cell[1]); debug("%s: size=%zx\n", __func__, *size); return 0; -- cgit v1.2.1 From ed072b96efd7a5de51cef01c3d4bed4db0e391f0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 7 Nov 2013 09:31:58 -0700 Subject: sandbox: Make map_to_sysmem() use a constant pointer Very often a constant pointer is passed to this function, so we should declare this, since map_to_sysmem() does not change the pointer. Signed-off-by: Simon Glass --- arch/sandbox/include/asm/io.h | 2 +- include/common.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 9ac6a5f00d..7956041171 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -38,6 +38,6 @@ static inline void unmap_sysmem(const void *vaddr) } /* Map from a pointer to our RAM buffer */ -phys_addr_t map_to_sysmem(void *ptr); +phys_addr_t map_to_sysmem(const void *ptr); #endif diff --git a/include/common.h b/include/common.h index 409515f498..8ca67f64fa 100644 --- a/include/common.h +++ b/include/common.h @@ -923,7 +923,7 @@ static inline void unmap_sysmem(const void *vaddr) { } -static inline phys_addr_t map_to_sysmem(void *ptr) +static inline phys_addr_t map_to_sysmem(const void *ptr) { return (phys_addr_t)(uintptr_t)ptr; } -- cgit v1.2.1 From f754f5dc6fe4b6cfbd28a9a6d9d08059d9312101 Mon Sep 17 00:00:00 2001 From: rockly Date: Sat, 3 Aug 2013 18:09:05 +0800 Subject: net: tftp: Make sure timeout will not effect wrap offset When the block 0 store to the memory of client and timeout at this moment. Because of no ACK packet, the server will send block 0 again, if this client reconnect to the server at this time, TftpBlockWrapOffset will become larger than it should be. Signed-off-by: Rockly Patch: 264417 --- net/tftp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/tftp.c b/net/tftp.c index 6d333d559c..2e06808d16 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -281,7 +281,7 @@ static void update_block_number(void) * number of 0 this means that there was a wrap * around of the (16 bit) counter. */ - if (TftpBlock == 0) { + if (TftpBlock == 0 && TftpLastBlock != 0) { TftpBlockWrap++; TftpBlockWrapOffset += TftpBlkSize * TFTP_SEQUENCE_SIZE; TftpTimeoutCount = 0; /* we've done well, reset thhe timeout */ -- cgit v1.2.1 From 626ee1e32eeb4fc89e0f406d6067ed6e71d8302f Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 8 Aug 2013 16:33:35 +0800 Subject: phylib: update atheros ar803x phy As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu --- drivers/net/phy/atheros.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 0f2dfd6126..7a1453ff3d 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -48,11 +48,11 @@ static struct phy_driver AR8021_driver = { }; static struct phy_driver AR8031_driver = { - .name = "AR8031", + .name = "AR8031/AR8033", .uid = 0x4dd074, .mask = 0xfffff0, .features = PHY_GBIT_FEATURES, - .config = genphy_config, + .config = ar8021_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; -- cgit v1.2.1 From 70672a29597c4ca4734f2d94bf1df7227b9c7604 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Fri, 8 Nov 2013 10:46:44 +0800 Subject: powerpc/p4080: enable support for PCIe SATA Signed-off-by: Shaohui Xie Acked-by: York Sun --- include/configs/P4080DS.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h index b0cd7d5c21..2f8900834d 100644 --- a/include/configs/P4080DS.h +++ b/include/configs/P4080DS.h @@ -17,6 +17,12 @@ #define CONFIG_MMC #define CONFIG_PCIE3 +#define CONFIG_CMD_SATA +#define CONFIG_SATA_SIL +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_LIBATA +#define CONFIG_LBA48 + #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ -- cgit v1.2.1 From f55a776cd03243aa575d3126996f11986e61a16b Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 14 Nov 2013 19:00:31 +0800 Subject: phy: introduce structure fixed-link fixed-link is used in kernel for PHY-less MAC, so introduce this structure that U-boot can use it to fixup dtb dynamically. Signed-off-by: Shaohui Xie --- include/phy.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/phy.h b/include/phy.h index f0f522a9c2..f86ffb9207 100644 --- a/include/phy.h +++ b/include/phy.h @@ -160,6 +160,14 @@ struct phy_device { u32 flags; }; +struct fixed_link { + int phy_id; + int duplex; + int link_speed; + int pause; + int asym_pause; +}; + static inline int phy_read(struct phy_device *phydev, int devad, int regnum) { struct mii_dev *bus = phydev->bus; -- cgit v1.2.1 From 57d33d4b4063ef731c35ba5b7b03e2e510c4ee65 Mon Sep 17 00:00:00 2001 From: Stephan Bauroth Date: Thu, 8 Aug 2013 13:44:41 +0200 Subject: net: trivial: Fix typos in mii field descriptions Signed-off-by: Stephan Bauroth Patch: 265707 --- common/cmd_mii.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/cmd_mii.c b/common/cmd_mii.c index d3dd6b1c9e..b82a7ce612 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -78,9 +78,9 @@ static const MII_field_desc_t reg_3_desc_tbl[] = { static const MII_field_desc_t reg_4_desc_tbl[] = { { 15, 15, 0x01, "next page able" }, - { 14, 14, 0x01, "reserved" }, + { 14, 14, 0x01, "(reserved)" }, { 13, 13, 0x01, "remote fault" }, - { 12, 12, 0x01, "reserved" }, + { 12, 12, 0x01, "(reserved)" }, { 11, 11, 0x01, "asymmetric pause" }, { 10, 10, 0x01, "pause enable" }, { 9, 9, 0x01, "100BASE-T4 able" }, -- cgit v1.2.1 From 0611c6017c9fc56a731ee5f8bbd91c7ee1a50849 Mon Sep 17 00:00:00 2001 From: Sascha Silbe Date: Sun, 11 Aug 2013 17:08:23 +0200 Subject: NET: mvgbe: avoid unused variable warning when used without phylib support Avoid a recently introduced unused variable warning for boards that use mvgbe but not phylib. Signed-off-by: Sascha Silbe Patch: 266334 --- drivers/net/mvgbe.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index 6c901d1eaa..0cd06b6a69 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -420,8 +420,9 @@ static int mvgbe_init(struct eth_device *dev) { struct mvgbe_device *dmvgbe = to_mvgbe(dev); struct mvgbe_registers *regs = dmvgbe->regs; -#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ - && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) +#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ + !defined(CONFIG_PHYLIB) && \ + defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) int i; #endif /* setup RX rings */ -- cgit v1.2.1 From 870cc23f07c725e6218a77b25314193ef6fbd1b4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Aug 2013 13:22:01 +0900 Subject: net: sh-eth: Change cache API of SH The cache API of SH was changed from dcache_wback_range to flush_dcache_range. sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range. Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/sh_eth.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index d5a83e0bf5..4cfd1e512a 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -25,9 +25,10 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif + #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK #define flush_cache_wback(addr, len) \ - dcache_wback_range((u32)addr, (u32)(addr + len - 1)) + flush_dcache_range((u32)addr, (u32)(addr + len - 1)) #else #define flush_cache_wback(...) #endif -- cgit v1.2.1 From f8b7507d41e9d2607e876b74f6ce79235f6bd618 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Aug 2013 13:22:02 +0900 Subject: net: sh-eth: Add control for padding size of packet descriptor sh-eth can change the alignment size of a packet descriptor according to BUS size. This patch adds this function. Signed-off-by: Hisashi Nakamura Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/sh_eth.c | 13 ++++++++----- drivers/net/sh_eth.h | 27 ++++++++++++++++++++++----- 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 4cfd1e512a..c0389299be 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -238,15 +238,17 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) * Allocate rx data buffers. They must be 32 bytes aligned and in * P2 area */ - port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31); + port_info->rx_buf_malloc = malloc( + NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1); if (!port_info->rx_buf_malloc) { printf(SHETHER_NAME ": malloc failed\n"); ret = -ENOMEM; goto err_buf_malloc; } - tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) & - ~(32 - 1)); + tmp_addr = (u32)(((int)port_info->rx_buf_malloc + + (RX_BUF_ALIGNE_SIZE - 1)) & + ~(RX_BUF_ALIGNE_SIZE - 1)); port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr); /* Initialize all descriptors */ @@ -352,8 +354,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) struct phy_device *phy; /* Configure e-dmac registers */ - sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, - EDMR); + sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | + (EMDR_DESC | EDMR_EL), EDMR); + sh_eth_write(eth, 0, EESIPR); sh_eth_write(eth, 0, TRSCER); sh_eth_write(eth, 0, TFTR); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 9ad800e427..35a1eee0d7 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -31,6 +31,11 @@ #define ADDR_TO_P2(addr) (addr) #endif /* defined(CONFIG_SH) */ +/* base padding size is 16 */ +#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 16 +#endif + /* Number of supported ports */ #define MAX_PORT_NUM 2 @@ -45,15 +50,16 @@ /* The size of the tx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define TX_DESC_PADDING 4 -#define TX_DESC_SIZE (12 + TX_DESC_PADDING) +#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */ +#define TX_DESC_SIZE (12 + TX_DESC_PADDING) /* Tx descriptor. We always use 3 bytes of padding */ struct tx_desc_s { volatile u32 td0; u32 td1; u32 td2; /* Buffer start */ - u32 padding; + u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ }; /* There is no limitation in the number of rx descriptors */ @@ -61,15 +67,18 @@ struct tx_desc_s { /* The size of the rx descriptor is determined by how much padding is used. 4, 20, or 52 bytes of padding can be used */ -#define RX_DESC_PADDING 4 +#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12) +/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */ #define RX_DESC_SIZE (12 + RX_DESC_PADDING) +/* aligned cache line size */ +#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32) /* Rx descriptor. We always use 4 bytes of padding */ struct rx_desc_s { volatile u32 rd0; volatile u32 rd1; u32 rd2; /* Buffer start */ - u32 padding; + u8 padding[TX_DESC_PADDING]; /* aligned cache line size */ }; struct sh_eth_info { @@ -320,6 +329,14 @@ enum DMAC_M_BIT { #endif }; +#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64 +# define EMDR_DESC EDMR_DL1 +#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32 +# define EMDR_DESC EDMR_DL0 +#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */ +# define EMDR_DESC 0 +#endif + /* RFLR */ #define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */ -- cgit v1.2.1 From 92f0713408859952cf82a9a4f368b2459cd1619f Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Aug 2013 13:22:03 +0900 Subject: net: sh-eth: Add invalidate cache control for rmobile (ARM SoC) The sh-eth of rmobile needs to use invalidate_cache* function. This patch adds invalidate_cache* function. Signed-off-by: Hisashi Nakamura Signed-off-by: Nobuhiro Iwamatsu Patch: 268948 --- drivers/net/sh_eth.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index c0389299be..6a78df0219 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -26,13 +26,30 @@ # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif -#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK -#define flush_cache_wback(addr, len) \ - flush_dcache_range((u32)addr, (u32)(addr + len - 1)) +#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) +#define flush_cache_wback(addr, len) \ + flush_dcache_range((u32)addr, (u32)(addr + len - 1)) #else #define flush_cache_wback(...) #endif +#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM) +#define invalidate_cache(addr, len) \ + { \ + u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \ + u32 start, end; \ + \ + start = (u32)addr; \ + end = start + len; \ + start &= ~(line_size - 1); \ + end = ((end + line_size - 1) & ~(line_size - 1)); \ + \ + invalidate_dcache_range(start, end); \ + } +#else +#define invalidate_cache(...) +#endif + #define TIMEOUT_CNT 1000 int sh_eth_send(struct eth_device *dev, void *packet, int len) @@ -70,8 +87,11 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len) /* Wait until packet is transmitted */ timeout = TIMEOUT_CNT; - while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--) + do { + invalidate_cache(port_info->tx_desc_cur, + sizeof(struct tx_desc_s)); udelay(100); + } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--); if (timeout < 0) { printf(SHETHER_NAME ": transmit timeout\n"); @@ -95,12 +115,14 @@ int sh_eth_recv(struct eth_device *dev) uchar *packet; /* Check if the rx descriptor is ready */ + invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { /* Check for errors */ if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { len = port_info->rx_desc_cur->rd1 & 0xffff; packet = (uchar *) ADDR_TO_P2(port_info->rx_desc_cur->rd2); + invalidate_cache(packet, len); NetReceive(packet, len); } @@ -109,7 +131,6 @@ int sh_eth_recv(struct eth_device *dev) port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; else port_info->rx_desc_cur->rd0 = RD_RACT; - /* Point to the next descriptor */ port_info->rx_desc_cur++; if (port_info->rx_desc_cur >= -- cgit v1.2.1 From 8707678cc420050285b7694292760c29d080192c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 22 Aug 2013 13:22:04 +0900 Subject: net: sh-eth: Add support R8A7790 R8A7790 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7790. Signed-off-by: Hisashi Nakamura Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/sh_eth.c | 5 ++++- drivers/net/sh_eth.h | 7 +++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 6a78df0219..9020752edd 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -4,6 +4,7 @@ * Copyright (C) 2008, 2011 Renesas Solutions Corp. * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu * Copyright (c) 2007 Carlos Munoz + * Copyright (C) 2013 Renesas Electronics Corporation * * SPDX-License-Identifier: GPL-2.0+ */ @@ -409,6 +410,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); +#elif defined(CONFIG_R8A7790) + sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); #endif /* Configure phy */ ret = sh_eth_phy_config(eth); @@ -432,7 +435,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) sh_eth_write(eth, 1, RTRATE); -#elif defined(CONFIG_CPU_SH7724) +#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) val = ECMR_RTM; #endif } else if (phy->speed == 10) { diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 35a1eee0d7..43b8ac9ce8 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -166,6 +166,7 @@ enum { TLFRCR, CERCR, CEECR, + RMIIMR, /* R8A7790 */ MAFCR, RTRATE, CSMR, @@ -272,6 +273,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { [RMCR] = 0x0058, [TFUCR] = 0x0064, [RFOCR] = 0x0068, + [RMIIMR] = 0x006C, [FCFTR] = 0x0070, [RPADIR] = 0x0078, [TRIMD] = 0x007c, @@ -299,6 +301,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7740) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xE9A00000 +#elif defined(CONFIG_R8A7790) +#define SH_ETH_TYPE_ETHER +#define BASE_IO_ADDR 0xEE700200 #endif /* @@ -502,6 +507,8 @@ enum FELIC_MODE_BIT { ECMR_PRM = 0x00000001, #ifdef CONFIG_CPU_SH7724 ECMR_RTM = 0x00000010, +#elif defined(CONFIG_R8A7790) + ECMR_RTM = 0x00000004, #endif }; -- cgit v1.2.1 From e97a78cfed113dfbf9a0db712624bca69065c3a1 Mon Sep 17 00:00:00 2001 From: Arpit Goel Date: Fri, 23 Aug 2013 20:18:05 +0530 Subject: net: phy/vitesse: Add support for VSC8514 phy module This patch adds support for VSC8514 PHY module which can be found on Freescale's T1040RDB boards. Signed-off-by: Arpit Goel Signed-off-by: Bhupesh Sharma --- drivers/net/phy/vitesse.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 5cf103e5a1..c555979661 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -49,6 +49,15 @@ #define MIIM_VSC8574_18G_QSGMII 0x80e0 #define MIIM_VSC8574_18G_CMDSTAT 0x8000 +/* Vitesse VSC8514 control register */ +#define MIIM_VSC8514_GENERAL18 0x12 +#define MIIM_VSC8514_GENERAL19 0x13 +#define MIIM_VSC8514_GENERAL23 0x17 + +/* Vitesse VSC8514 gerenal purpose register 18 */ +#define MIIM_VSC8514_18G_QSGMII 0x80e0 +#define MIIM_VSC8514_18G_CMDSTAT 0x8000 + /* CIS8201 */ static int vitesse_config(struct phy_device *phydev) { @@ -148,7 +157,7 @@ static int vsc8601_config(struct phy_device *phydev) static int vsc8574_config(struct phy_device *phydev) { u32 val; - /* configure regiser 19G for MAC */ + /* configure register 19G for MAC */ phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, PHY_EXT_PAGE_ACCESS_GENERAL); @@ -188,6 +197,53 @@ static int vsc8574_config(struct phy_device *phydev) return 0; } +static int vsc8514_config(struct phy_device *phydev) +{ + u32 val; + int timeout = 1000000; + + /* configure register to access 19G */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_GENERAL); + + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL19); + if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { + /* set bit 15:14 to '01' for QSGMII mode */ + val = (val & 0x3fff) | (1 << 14); + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_VSC8514_GENERAL19, val); + /* Enable 4 ports MAC QSGMII */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18, + MIIM_VSC8514_18G_QSGMII); + } else { + /*TODO Add SGMII functionality once spec sheet + * for VSC8514 defines complete functionality + */ + } + + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); + /* When bit 15 is cleared the command has completed */ + while ((val & MIIM_VSC8514_18G_CMDSTAT) && timeout--) + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL18); + + if (0 == timeout) { + printf("PHY 8514 config failed\n"); + return -1; + } + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + /* configure register to access 23 */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23); + /* set bits 10:8 to '000' */ + val = (val & 0xf8ff); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val); + + genphy_config_aneg(phydev); + + return 0; +} + static struct phy_driver VSC8211_driver = { .name = "Vitesse VSC8211", .uid = 0xfc4b0, @@ -238,6 +294,16 @@ static struct phy_driver VSC8574_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8514_driver = { + .name = "Vitesse VSC8514", + .uid = 0x70570, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8514_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + static struct phy_driver VSC8601_driver = { .name = "Vitesse VSC8601", .uid = 0x70420, @@ -298,6 +364,7 @@ int phy_vitesse_init(void) phy_register(&VSC8211_driver); phy_register(&VSC8221_driver); phy_register(&VSC8574_driver); + phy_register(&VSC8514_driver); phy_register(&VSC8662_driver); phy_register(&cis8201_driver); phy_register(&cis8204_driver); -- cgit v1.2.1 From 42205047674d7fc9e0aa747273fbc7dcfbac3183 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 1 Sep 2013 04:40:52 +0530 Subject: net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following method to determine which driver is to be loaded for a particular PHY module: list_for_each(entry, &phy_drivers) { drv = list_entry(entry, struct phy_driver, list); if ((drv->uid & drv->mask) == (phy_id & drv->mask)) return drv; } This means that a drv->mask of 0xfffff0 will return incorrect phy driver for the logic above, even if the drv->uid is anything other than something ending with a 0x0. For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then the phy driver selected will always be RTL8211B even though the underlying phy connected on the board is a 8211E module. This patch fixes this issue. Signed-off-by: Bhupesh Sharma --- drivers/net/phy/realtek.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index ddbbc35e27..a3ace68526 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -102,7 +102,7 @@ static int rtl8211x_startup(struct phy_device *phydev) static struct phy_driver RTL8211B_driver = { .name = "RealTek RTL8211B", .uid = 0x1cc910, - .mask = 0xfffff0, + .mask = 0xffffff, .features = PHY_GBIT_FEATURES, .config = &rtl8211x_config, .startup = &rtl8211x_startup, @@ -113,7 +113,7 @@ static struct phy_driver RTL8211B_driver = { static struct phy_driver RTL8211E_driver = { .name = "RealTek RTL8211E", .uid = 0x1cc915, - .mask = 0xfffff0, + .mask = 0xffffff, .features = PHY_GBIT_FEATURES, .config = &rtl8211x_config, .startup = &rtl8211x_startup, @@ -124,7 +124,7 @@ static struct phy_driver RTL8211E_driver = { static struct phy_driver RTL8211DN_driver = { .name = "RealTek RTL8211DN", .uid = 0x1cc914, - .mask = 0xfffff0, + .mask = 0xffffff, .features = PHY_GBIT_FEATURES, .config = &rtl8211x_config, .startup = &rtl8211x_startup, -- cgit v1.2.1 From 71817a16f1f0848b268ea627197e2b65cdc550ed Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 2 Sep 2013 15:42:28 +0200 Subject: phy: add missing constants for Micrel KSZ9031 Signed-off-by: Stefano Babic --- include/micrel.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/micrel.h b/include/micrel.h index e1c62d83cb..04c9ecf3bf 100644 --- a/include/micrel.h +++ b/include/micrel.h @@ -15,6 +15,11 @@ #define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000 #define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000 +#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4 +#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5 +#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6 +#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8 + struct phy_device; int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val); int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum); -- cgit v1.2.1 From e8194d58bd342631977d1e09d873784d145c7077 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 2 Sep 2013 15:42:29 +0200 Subject: net: fix mask for phy Micrel KSZ9031 Signed-off-by: Stefano Babic --- drivers/net/phy/micrel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index a7450f8326..f3e3054eff 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -174,7 +174,7 @@ int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr, static struct phy_driver ksz9031_driver = { .name = "Micrel ksz9031", .uid = 0x221620, - .mask = 0xfffffe, + .mask = 0xfffff0, .features = PHY_GBIT_FEATURES, .config = &genphy_config, .startup = &ksz90xx_startup, -- cgit v1.2.1 From b71841b978fc33f961383b255693a70a1dd64031 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 2 Sep 2013 15:42:30 +0200 Subject: net: add extended function to phy API Some phys (Micrel) has extended registers that must be accessed in a special way. Add pointers to the phy driver structure to allow to use these functions with mdio command. Signed-off-by: Stefano Babic --- include/phy.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/phy.h b/include/phy.h index f0f522a9c2..d3001f1381 100644 --- a/include/phy.h +++ b/include/phy.h @@ -125,6 +125,9 @@ struct phy_driver { /* Called when bringing down the controller */ int (*shutdown)(struct phy_device *phydev); + int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); + int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, + u16 val); struct list_head list; }; -- cgit v1.2.1 From 9ced16fefa35910b4d2cbc9c4688a037bda7f423 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 2 Sep 2013 15:42:31 +0200 Subject: net: add function to read/write extended registers in Micrel Phy Signed-off-by: Stefano Babic --- drivers/net/phy/micrel.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index f3e3054eff..5d7e3be52e 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -100,6 +100,19 @@ int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum) return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR); } + +static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr, + int regnum) +{ + return ksz9021_phy_extended_read(phydev, regnum); +} + +static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + return ksz9021_phy_extended_write(phydev, regnum, val); +} + /* Micrel ksz9021 */ static int ksz9021_config(struct phy_device *phydev) { @@ -131,6 +144,8 @@ static struct phy_driver ksz9021_driver = { .config = &ksz9021_config, .startup = &ksz90xx_startup, .shutdown = &genphy_shutdown, + .writeext = &ksz9021_phy_extwrite, + .readext = &ksz9021_phy_extread, }; #endif @@ -171,6 +186,21 @@ int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr, return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA); } +static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr, + int regnum) +{ + return ksz9031_phy_extended_read(phydev, devaddr, regnum, + MII_KSZ9031_MOD_DATA_NO_POST_INC); +}; + +static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + return ksz9031_phy_extended_write(phydev, devaddr, regnum, + MII_KSZ9031_MOD_DATA_POST_INC_RW, val); +}; + + static struct phy_driver ksz9031_driver = { .name = "Micrel ksz9031", .uid = 0x221620, @@ -179,6 +209,8 @@ static struct phy_driver ksz9031_driver = { .config = &genphy_config, .startup = &ksz90xx_startup, .shutdown = &genphy_shutdown, + .writeext = &ksz9031_phy_extwrite, + .readext = &ksz9031_phy_extread, }; int phy_micrel_init(void) -- cgit v1.2.1 From 26b807c4f8d95f7e1a9b16b5d0caebc6606d3dc6 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Mon, 2 Sep 2013 15:42:32 +0200 Subject: net: add support for extended registers to mdio command Some phys (Micrel) have additional registers that can be accessed using a special sequence. This patch allows to use standard "mdio" command to accesss these registers. Signed-off-by: Stefano Babic --- common/cmd_mdio.c | 75 +++++++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 59 insertions(+), 16 deletions(-) diff --git a/common/cmd_mdio.c b/common/cmd_mdio.c index 65a1f10a9f..fb13d05075 100644 --- a/common/cmd_mdio.c +++ b/common/cmd_mdio.c @@ -41,9 +41,11 @@ static int extract_range(char *input, int *plo, int *phi) return 0; } -static int mdio_write_ranges(struct mii_dev *bus, int addrlo, +static int mdio_write_ranges(struct phy_device *phydev, struct mii_dev *bus, + int addrlo, int addrhi, int devadlo, int devadhi, - int reglo, int reghi, unsigned short data) + int reglo, int reghi, unsigned short data, + int extended) { int addr, devad, reg; int err = 0; @@ -51,7 +53,12 @@ static int mdio_write_ranges(struct mii_dev *bus, int addrlo, for (addr = addrlo; addr <= addrhi; addr++) { for (devad = devadlo; devad <= devadhi; devad++) { for (reg = reglo; reg <= reghi; reg++) { - err = bus->write(bus, addr, devad, reg, data); + if (!extended) + err = bus->write(bus, addr, devad, + reg, data); + else + err = phydev->drv->writeext(phydev, + addr, devad, reg, data); if (err) goto err_out; @@ -63,9 +70,10 @@ err_out: return err; } -static int mdio_read_ranges(struct mii_dev *bus, int addrlo, +static int mdio_read_ranges(struct phy_device *phydev, struct mii_dev *bus, + int addrlo, int addrhi, int devadlo, int devadhi, - int reglo, int reghi) + int reglo, int reghi, int extended) { int addr, devad, reg; @@ -77,7 +85,12 @@ static int mdio_read_ranges(struct mii_dev *bus, int addrlo, for (reg = reglo; reg <= reghi; reg++) { int val; - val = bus->read(bus, addr, devad, reg); + if (!extended) + val = bus->read(bus, addr, devad, reg); + else + val = phydev->drv->readext(phydev, addr, + devad, reg); + if (val < 0) { printf("Error\n"); @@ -126,9 +139,10 @@ static int extract_reg_range(char *input, int *devadlo, int *devadhi, } static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus, + struct phy_device **phydev, int *addrlo, int *addrhi) { - struct phy_device *phydev; + struct phy_device *dev = *phydev; if ((argc < 1) || (argc > 2)) return -1; @@ -154,11 +168,11 @@ static int extract_phy_range(char *const argv[], int argc, struct mii_dev **bus, * device by the given name. If none are found, we call * extract_range() on the string, and see if it's an address range. */ - phydev = mdio_phydev_for_ethname(argv[0]); + dev = mdio_phydev_for_ethname(argv[0]); - if (phydev) { - *addrlo = *addrhi = phydev->addr; - *bus = phydev->bus; + if (dev) { + *addrlo = *addrhi = dev->addr; + *bus = dev->bus; return 0; } @@ -175,6 +189,8 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) unsigned short data; int pos = argc - 1; struct mii_dev *bus; + struct phy_device *phydev = NULL; + int extended = 0; if (argc < 2) return CMD_RET_USAGE; @@ -197,6 +213,29 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (flag & CMD_FLAG_REPEAT) op[0] = last_op[0]; + if (strlen(argv[1]) > 1) { + op[1] = argv[1][1]; + if (op[1] == 'x') { + phydev = mdio_phydev_for_ethname(argv[2]); + + if (phydev) { + addrlo = phydev->addr; + addrhi = addrlo; + bus = phydev->bus; + extended = 1; + } else { + return -1; + } + + if (!phydev->drv || + (!phydev->drv->writeext && (op[0] == 'w')) || + (!phydev->drv->readext && (op[0] == 'r'))) { + puts("PHY does not have extended functions\n"); + return -1; + } + } + } + switch (op[0]) { case 'w': if (pos > 1) @@ -210,7 +249,7 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) default: if (pos > 1) if (extract_phy_range(&(argv[2]), pos - 1, &bus, - &addrlo, &addrhi)) + &phydev, &addrlo, &addrhi)) return -1; break; @@ -227,13 +266,13 @@ static int do_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) switch (op[0]) { case 'w': - mdio_write_ranges(bus, addrlo, addrhi, devadlo, devadhi, - reglo, reghi, data); + mdio_write_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi, + reglo, reghi, data, extended); break; case 'r': - mdio_read_ranges(bus, addrlo, addrhi, devadlo, devadhi, - reglo, reghi); + mdio_read_ranges(phydev, bus, addrlo, addrhi, devadlo, devadhi, + reglo, reghi, extended); break; } @@ -262,6 +301,10 @@ U_BOOT_CMD( "read PHY's register at .\n" "mdio write [.] - " "write PHY's register at .\n" + "mdio rx [.] - " + "read PHY's extended register at .\n" + "mdio wx [.] - " + "write PHY's extended register at .\n" " may be:\n" " \n" " \n" -- cgit v1.2.1 From 7a36b9c1acb43c6be82b05c21cba1d0f14712d8c Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Sep 2013 16:03:41 +0200 Subject: net: rtl8169: Fix format string currticks() is defined as get_timer(0), which returns an unsigned long, so use %lu instead of %d to print the result. Signed-off-by: Thierry Reding Patch: 276473 --- drivers/net/rtl8169.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 13fa9c02fe..9dc10a5808 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -501,8 +501,8 @@ static int rtl_send(struct eth_device *dev, void *packet, int length) if (currticks() >= to) { #ifdef DEBUG_RTL8169_TX - puts ("tx timeout/error\n"); - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + puts("tx timeout/error\n"); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif ret = 0; } else { @@ -604,7 +604,7 @@ static void rtl8169_hw_start(struct eth_device *dev) RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); #ifdef DEBUG_RTL8169 - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif } @@ -642,7 +642,7 @@ static void rtl8169_init_ring(struct eth_device *dev) } #ifdef DEBUG_RTL8169 - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif } @@ -683,7 +683,7 @@ static int rtl_reset(struct eth_device *dev, bd_t *bis) txb[5] = dev->enetaddr[5]; #ifdef DEBUG_RTL8169 - printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); + printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif return 0; } -- cgit v1.2.1 From 65a6691ed3e3396c6aa8b8ca39b9e2631f37a974 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Sep 2013 16:03:44 +0200 Subject: net: rtl8169: Add support for RTL8168evl/8111evl This chip is compatible with other RTL8168 chips and can be found on the NVIDIA Cardhu and Beaver boards. Signed-off-by: Thierry Reding Patch: 276475 --- drivers/net/rtl8169.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 9dc10a5808..290c9887c0 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -246,6 +246,7 @@ static struct { {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, + {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, {"RTL-8101e", 0x34, 0xff7e1880,}, {"RTL-8100e", 0x32, 0xff7e1880,}, }; -- cgit v1.2.1 From dfcaa61c33e1fc5f737318cfdbcf7f7b49f237a3 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sun, 22 Sep 2013 09:55:49 +0200 Subject: net, phy: fix AR8031 phy_mask AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher Reported-by: Pavel Nakonechny Cc: Andy Fleming Cc: Joe Hershberger Patch: 276944 --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 7a1453ff3d..f225d93a36 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -50,7 +50,7 @@ static struct phy_driver AR8021_driver = { static struct phy_driver AR8031_driver = { .name = "AR8031/AR8033", .uid = 0x4dd074, - .mask = 0xfffff0, + .mask = 0xffffff, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, -- cgit v1.2.1 From 47ce8890486be72ce6b634c590a0c6baa2447084 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 24 Sep 2013 15:38:33 +0900 Subject: net: sh-eth: Add support R8A7791 R8A7791 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7791. Signed-off-by: Nobuhiro Iwamatsu CC: Nobuhiro Iwamatsu CC: Joe Hershberger --- drivers/net/sh_eth.c | 5 +++-- drivers/net/sh_eth.h | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 9020752edd..5e132f2b53 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -410,7 +410,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); #endif /* Configure phy */ @@ -435,7 +435,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) sh_eth_write(eth, 1, RTRATE); -#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) +#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ + defined(CONFIG_R8A7791) val = ECMR_RTM; #endif } else if (phy->speed == 10) { diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 43b8ac9ce8..8aa71098cb 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -301,7 +301,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7740) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xE9A00000 -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xEE700200 #endif @@ -507,7 +507,7 @@ enum FELIC_MODE_BIT { ECMR_PRM = 0x00000001, #ifdef CONFIG_CPU_SH7724 ECMR_RTM = 0x00000010, -#elif defined(CONFIG_R8A7790) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) ECMR_RTM = 0x00000004, #endif -- cgit v1.2.1 From 227ad7b2b6fab024fff6f60613b0e90c9e3a6724 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 25 Sep 2013 17:33:10 +0400 Subject: net: designware: Respect "bus mode" register contents on SW reset "bus mode" register contains lots of fields and some of them don't expect to be written with 0 (zero). So since we're only interested in resetting MAC (which is done with setting the least significant bit of this register with "0") I believe it's better to modify only 1 bit of the register. Signed-off-by: Alexey Brodkin Acked-by: Vipin Kumar Patch: 277864 --- drivers/net/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 8413d57767..22155b4d94 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -96,7 +96,7 @@ static int mac_reset(struct eth_device *dev) ulong start; int timeout = CONFIG_MACRESET_TIMEOUT; - writel(DMAMAC_SRST, &dma_p->busmode); + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); if (priv->interface != PHY_INTERFACE_MODE_RGMII) writel(MII_PORTSELECT, &mac_p->conf); -- cgit v1.2.1 From ed102be70f762afc39bda165ba57ea84dc9be39e Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 25 Sep 2013 19:27:48 +0400 Subject: net: designware: Fix alignment of buffer descriptors It's important that buffer descriptors are aligned in accordance to GMAC data bus width (32/64/128-bit). It's safe to align to 128-bit (16-bytes) for every bus width type. If buffer descriptor is improperly aligned GMAC discards lower bits of provided address and as a result reads from improper location that doesn't match expected fields. Commit ef76025a99247cdb8f927a2c9f15400678dfb599 "net: Multiple updates/enhancements to designware.c" introduced another structure member "link_printed" right before buffer descriptors while "padding" member was left untouched. This together with alignment of structure itself to 16-byte boundary forces buffer descriptoprs always to be 4-byte aligned that causes driver complete disfunction if GMAC bus width is 64 or 128-bit. Proposed change makes sure all buffer descriptors are 16-byte (128-bit) aligned. Signed-off-by: Alexey Brodkin Patch: 277902 --- drivers/net/designware.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/net/designware.h b/drivers/net/designware.h index e80002a0e4..5440c9215f 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -112,7 +112,7 @@ struct dmamacdescr { u32 dmamac_cntl; void *dmamac_addr; struct dmamacdescr *dmamac_next; -}; +} __aligned(16); /* * txrx_status definitions @@ -224,8 +224,7 @@ struct dw_eth_dev { u32 tx_currdescnum; u32 rx_currdescnum; u32 phy_configured; - int link_printed; - u32 padding; + u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -237,7 +236,7 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; -} __attribute__ ((aligned(8))); +}; /* Speed specific definitions */ #define SPEED_10M 1 -- cgit v1.2.1 From 9c4cffacec7b76299e74cb09e074a21fb6609dbe Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:39 +0300 Subject: net: Fix mcast function pointer prototype This fixes the following compiler warnings when activating CONFIG_MCAST_TFTP: tsec.c: In function 'tsec_mcast_addr': tsec.c:130:2: warning: passing argument 2 of 'ether_crc' makes pointer from integer without a cast [enabled by default] In file included from /work/u-boot-net/include/common.h:874:0, from tsec.c:15: /work/u-boot-net/include/net.h:189:5: note: expected 'const unsigned char *' but argument is of type 'u8' tsec.c: In function 'tsec_initialize': tsec.c:646:13: warning: assignment from incompatible pointer type [enabled by default] eth.c: In function 'eth_mcast_join': eth.c:358:2: warning: passing argument 2 of 'eth_current->mcast' makes integer from pointer without a cast [enabled by default] eth.c:358:2: note: expected 'u32' but argument is of type 'u8 *' In the eth_mcast_join() implementation, eth_current->mcast() takes a u8 pointer to the multicast mac address and not a ip address value as implied by its prototype. Fix parameter type mismatch for tsec_macst_addr() (tsec.c): ether_crc() takes a u8 pointer not a u8 value. mcast() is given a u8 pointer to the multicats mac address. Update parameter type for the rest of mcast() instances. Signed-off-by: Claudiu Manoil Patch: 278989 --- drivers/net/rtl8139.c | 2 +- drivers/net/tsec.c | 4 ++-- include/net.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index 4186699ff9..208ce5ccc4 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -188,7 +188,7 @@ static int rtl_transmit(struct eth_device *dev, void *packet, int length); static int rtl_poll(struct eth_device *dev); static void rtl_disable(struct eth_device *dev); #ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ -static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) +static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, u8 set) { return (0); } diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index f5e314b9ee..3428dd0cf9 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -120,14 +120,14 @@ static void tsec_configure_serdes(struct tsec_private *priv) * for PowerPC (tm) is usually the case) in the tregister holds * the entry. */ static int -tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set) +tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) { struct tsec_private *priv = privlist[1]; volatile tsec_t *regs = priv->regs; volatile u32 *reg_array, value; u8 result, whichbit, whichreg; - result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff); + result = (u8)((ether_crc(MAC_ADDR_LEN, mcast_mac) >> 24) & 0xff); whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ value = (1 << (31-whichbit)); diff --git a/include/net.h b/include/net.h index 5aedc17aa6..0802fad876 100644 --- a/include/net.h +++ b/include/net.h @@ -89,7 +89,7 @@ struct eth_device { int (*recv) (struct eth_device *); void (*halt) (struct eth_device *); #ifdef CONFIG_MCAST_TFTP - int (*mcast) (struct eth_device *, u32 ip, u8 set); + int (*mcast) (struct eth_device *, const u8 *enetaddr, u8 set); #endif int (*write_hwaddr) (struct eth_device *); struct eth_device *next; -- cgit v1.2.1 From 876d4515e38dfcec4346968caf6a0c9c8176ea0b Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:40 +0300 Subject: net: tsec: Fix and cleanup tsec_mcast_addr() There are several implementation issues for tsec_mcast_addr() addressed by this patch: * unmanaged, not portable r/w access to registers; fixed with setbits_be32()/ clrbits_be32() * use of volatile pointers * unnecessary forced cast to u8 for the ether_crc() result * removed redundant parens * corrected some comment slips Signed-off-by: Claudiu Manoil Patch: 279000 --- drivers/net/tsec.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 3428dd0cf9..9ffc801bc7 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -113,32 +113,31 @@ static void tsec_configure_serdes(struct tsec_private *priv) * result. * 2) Use the 8 most significant bits as a hash into a 256-entry * table. The table is controlled through 8 32-bit registers: - * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is - * gaddr7. This means that the 3 most significant bits in the + * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry + * 255. This means that the 3 most significant bits in the * hash index which gaddr register to use, and the 5 other bits * indicate which bit (assuming an IBM numbering scheme, which - * for PowerPC (tm) is usually the case) in the tregister holds + * for PowerPC (tm) is usually the case) in the register holds * the entry. */ static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) { struct tsec_private *priv = privlist[1]; - volatile tsec_t *regs = priv->regs; - volatile u32 *reg_array, value; - u8 result, whichbit, whichreg; + struct tsec __iomem *regs = priv->regs; + u32 result, value; + u8 whichbit, whichreg; - result = (u8)((ether_crc(MAC_ADDR_LEN, mcast_mac) >> 24) & 0xff); - whichbit = result & 0x1f; /* the 5 LSB = which bit to set */ - whichreg = result >> 5; /* the 3 MSB = which reg to set it in */ - value = (1 << (31-whichbit)); + result = ether_crc(MAC_ADDR_LEN, mcast_mac); + whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */ + whichreg = result >> 29; /* the 3 MSB = which reg to set it in */ - reg_array = &(regs->hash.gaddr0); + value = 1 << (31-whichbit); + + if (set) + setbits_be32(®s->hash.gaddr0 + whichreg, value); + else + clrbits_be32(®s->hash.gaddr0 + whichreg, value); - if (set) { - reg_array[whichreg] |= value; - } else { - reg_array[whichreg] &= ~value; - } return 0; } #endif /* Multicast TFTP ? */ -- cgit v1.2.1 From b200204e8e2a2eee081d576ed578d87b75813b46 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:41 +0300 Subject: net: tsec: Fix priv pointer in tsec_mcast_addr() Access to privlist[1] (hardcoded referece to the 2nd tsec's priv area) is neither correct nor does it make sense in the current context. Each tsec dev has access to its own priv instance only, and hence to its own set of group address registers (GADDR) to filter multicast addresses. This fix leads to removal of the unused (faulty) privlist[] and related global static vars. Note that mcast() can be called only after eth_device allocation and init, and hence after priv area allocation, so dev->priv is correctly initialized upon mcast() call. Signed-off-by: Claudiu Manoil Patch: 278990 --- drivers/net/tsec.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9ffc801bc7..9371ffa0da 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -33,11 +33,6 @@ typedef volatile struct rtxbd { rxbd8_t rxbd[PKTBUFSRX]; } RTXBD; -#define MAXCONTROLLERS (8) - -static struct tsec_private *privlist[MAXCONTROLLERS]; -static int num_tsecs = 0; - #ifdef __GNUC__ static RTXBD rtx __attribute__ ((aligned(8))); #else @@ -122,7 +117,7 @@ static void tsec_configure_serdes(struct tsec_private *priv) static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) { - struct tsec_private *priv = privlist[1]; + struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; u32 result, value; u8 whichbit, whichreg; @@ -625,7 +620,6 @@ static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info) if (NULL == priv) return 0; - privlist[num_tsecs++] = priv; priv->regs = tsec_info->regs; priv->phyregs_sgmii = tsec_info->miiregs_sgmii; -- cgit v1.2.1 From aec84bf6719f9efcc754acfb08b8ca866c8a5e95 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:42 +0300 Subject: net: tsec: Cleanup tsec regs init and fix __iomem warns Remove tsec_t typedef. Define macros as getters of tsec and mdio register memory regions, for consistent initialization of various 'regs' fields and also to manage overly long initialization lines. Use the __iomem address space marker to address sparse warnings in tsec.c where IO accessors are used, like: tsec.c:394:19: warning: incorrect type in argument 1 (different address spaces) tsec.c:394:19: expected unsigned int volatile [noderef] *addr tsec.c:394:19: got unsigned int * [...] Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. Signed-off-by: Claudiu Manoil --- drivers/net/tsec.c | 26 +++++++++++++------------- include/tsec.h | 39 +++++++++++++++++++++++++-------------- 2 files changed, 38 insertions(+), 27 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 9371ffa0da..adb6c123e5 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -5,7 +5,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004-2011 Freescale Semiconductor, Inc. + * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * author Andy Fleming * @@ -52,7 +52,7 @@ static struct tsec_info_struct tsec_info[] = { #endif #ifdef CONFIG_MPC85XX_FEC { - .regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000), + .regs = TSEC_GET_REGS(2, 0x2000), .devname = CONFIG_MPC85XX_FEC_NAME, .phyaddr = FEC_PHY_ADDR, .flags = FEC_FLAGS, @@ -141,7 +141,7 @@ tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set) * those we don't care about (unless zero is bad, in which case, * choose a more appropriate value) */ -static void init_registers(tsec_t *regs) +static void init_registers(struct tsec __iomem *regs) { /* Clear IEVENT */ out_be32(®s->ievent, IEVENT_INIT_CLEAR); @@ -188,7 +188,7 @@ static void init_registers(tsec_t *regs) */ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) { - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; u32 ecntrl, maccfg2; if (!phydev->link) { @@ -242,7 +242,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev) void redundant_init(struct eth_device *dev) { struct tsec_private *priv = dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; uint t, count = 0; int fail = 1; static const u8 pkt[] = { @@ -321,7 +321,7 @@ static void startup_tsec(struct eth_device *dev) { int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; /* reset the indices to zero */ rxIdx = 0; @@ -375,7 +375,7 @@ static int tsec_send(struct eth_device *dev, void *packet, int length) int i; int result = 0; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; /* Find an empty buffer descriptor */ for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { @@ -411,7 +411,7 @@ static int tsec_recv(struct eth_device *dev) { int length; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { @@ -447,7 +447,7 @@ static int tsec_recv(struct eth_device *dev) static void tsec_halt(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); @@ -473,7 +473,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) char tmpbuf[MAC_ADDR_LEN]; int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; int ret; /* Make sure the controller is stopped */ @@ -521,7 +521,7 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) static phy_interface_t tsec_get_interface(struct tsec_private *priv) { - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; u32 ecntrl; ecntrl = in_be32(®s->ecntrl); @@ -570,7 +570,7 @@ static int init_phy(struct eth_device *dev) { struct tsec_private *priv = (struct tsec_private *)dev->priv; struct phy_device *phydev; - tsec_t *regs = priv->regs; + struct tsec __iomem *regs = priv->regs; u32 supported = (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -677,7 +677,7 @@ int tsec_standard_init(bd_t *bis) { struct fsl_pq_mdio_info info; - info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + info.regs = TSEC_GET_MDIO_REGS_BASE(1); info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &info); diff --git a/include/tsec.h b/include/tsec.h index f0f3d4d59b..c30aafbc06 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming @@ -27,13 +27,26 @@ #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) +#define TSEC_GET_REGS(num, offset) \ + (struct tsec __iomem *)\ + (TSEC_BASE_ADDR + (((num) - 1) * (offset))) + +#define TSEC_GET_REGS_BASE(num) \ + TSEC_GET_REGS((num), TSEC_SIZE) + +#define TSEC_GET_MDIO_REGS(num, offset) \ + (struct tsec_mii_mng __iomem *)\ + (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset)) + +#define TSEC_GET_MDIO_REGS_BASE(num) \ + TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET) + #define DEFAULT_MII_NAME "FSL_MDIO" #define STD_TSEC_INFO(num) \ { \ - .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \ - + (num - 1) * TSEC_MDIO_OFFSET), \ + .regs = TSEC_GET_REGS_BASE(num), \ + .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ .flags = TSEC##num##_FLAGS, \ @@ -42,9 +55,8 @@ #define SET_STD_TSEC_INFO(x, num) \ { \ - x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \ - + (num - 1) * TSEC_MDIO_OFFSET); \ + x.regs = TSEC_GET_REGS_BASE(num); \ + x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ @@ -281,8 +293,7 @@ typedef struct tsec_hash_regs uint res2[24]; } tsec_hash_t; -typedef struct tsec -{ +struct tsec { /* General Control and Status Registers (0x2_n000) */ uint res000[4]; @@ -374,7 +385,7 @@ typedef struct tsec /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ uint resc00[256]; -} tsec_t; +}; #define TSEC_GIGABIT (1 << 0) @@ -383,8 +394,8 @@ typedef struct tsec #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ struct tsec_private { - tsec_t *regs; - struct tsec_mii_mng *phyregs_sgmii; + struct tsec __iomem *regs; + struct tsec_mii_mng __iomem *phyregs_sgmii; struct phy_device *phydev; phy_interface_t interface; struct mii_dev *bus; @@ -394,8 +405,8 @@ struct tsec_private { }; struct tsec_info_struct { - tsec_t *regs; - struct tsec_mii_mng *miiregs_sgmii; + struct tsec __iomem *regs; + struct tsec_mii_mng __iomem *miiregs_sgmii; char *devname; char *mii_devname; phy_interface_t interface; -- cgit v1.2.1 From 5be00a0164892eb695fefa41fb24258072ee2185 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:43 +0300 Subject: net: fsl_mdio: Fix warnings for __iomem pointers Add the __iomem address space marker for the tsec pointers to struct tsec_mii_mng memory mapped register regions. This solves the sparse warnings for mixig normal pointers with __iomem pointers for tsec. E.g.: fsl_mdio.c:34:19: warning: incorrect type in argument 1 (different address spaces) fsl_mdio.c:34:19: expected unsigned int volatile [noderef] *addr fsl_mdio.c:34:19: got unsigned int * [...] tsec.c:91:35: warning: incorrect type in argument 1 (different address spaces) tsec.c:91:35: expected struct tsec_mii_mng *phyregs tsec.c:91:35: got struct tsec_mii_mng [noderef] *phyregs_sgmii [...] tsec.c:680:19: warning: incorrect type in assignment (different address spaces) tsec.c:680:19: expected struct tsec_mii_mng *regs tsec.c:680:19: got struct tsec_mii_mng [noderef] * [...] Signed-off-by: Claudiu Manoil --- drivers/net/fsl_mdio.c | 17 ++++++++++------- include/fsl_mdio.h | 8 ++++---- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index ce36bd7a34..1d88e6504b 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc. * Jun-jie Zhang * Mingkai Hu * @@ -13,7 +13,7 @@ #include #include -void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, +void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int regnum, int value) { int timeout = 1000000; @@ -26,7 +26,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, ; } -int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, +int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int regnum) { int value; @@ -57,7 +57,8 @@ int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, static int fsl_pq_mdio_reset(struct mii_dev *bus) { - struct tsec_mii_mng *regs = bus->priv; + struct tsec_mii_mng __iomem *regs = + (struct tsec_mii_mng __iomem *)bus->priv; /* Reset MII (due to new addresses) */ out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT); @@ -72,7 +73,8 @@ static int fsl_pq_mdio_reset(struct mii_dev *bus) int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum) { - struct tsec_mii_mng *phyregs = bus->priv; + struct tsec_mii_mng __iomem *phyregs = + (struct tsec_mii_mng __iomem *)bus->priv; return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum); } @@ -80,7 +82,8 @@ int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum) int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, u16 value) { - struct tsec_mii_mng *phyregs = bus->priv; + struct tsec_mii_mng __iomem *phyregs = + (struct tsec_mii_mng __iomem *)bus->priv; tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value); @@ -101,7 +104,7 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info) bus->reset = fsl_pq_mdio_reset; sprintf(bus->name, info->name); - bus->priv = info->regs; + bus->priv = (void *)info->regs; return mdio_register(bus); } diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index 9c0b762773..b58713d896 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2012 Freescale Semiconductor, Inc. + * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc. * Jun-jie Zhang * Mingkai Hu * @@ -31,9 +31,9 @@ #define MIIMIND_BUSY 0x00000001 #define MIIMIND_NOTVALID 0x00000004 -void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr, +void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int reg, int value); -int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr, +int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, int dev_addr, int regnum); int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum); int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum, @@ -44,7 +44,7 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, int regnum); struct fsl_pq_mdio_info { - struct tsec_mii_mng *regs; + struct tsec_mii_mng __iomem *regs; char *name; }; int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info); -- cgit v1.2.1 From 18b338fb3486ac91291e1f94561cb47fd0f4aef2 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:44 +0300 Subject: net: tsec: Fix CamelCase issues around BD code Fix bufPtr and the rxIdx/ txIdx occurrences to solve the related checkpatch warnings for the coming patches. Signed-off-by: Claudiu Manoil --- drivers/net/tsec.c | 60 +++++++++++++++++++++++++++--------------------------- include/tsec.h | 4 ++-- 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index adb6c123e5..289229a42b 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -25,8 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; #define TX_BUF_CNT 2 -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ +static uint rx_idx; /* index of the current RX buffer */ +static uint tx_idx; /* index of the current TX buffer */ typedef volatile struct rtxbd { txbd8_t txbd[TX_BUF_CNT]; @@ -278,20 +278,20 @@ void redundant_init(struct eth_device *dev) tsec_send(dev, (void *)pkt, sizeof(pkt)); /* Wait for buffer to be received */ - for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) { + for (t = 0; rtx.rxbd[rx_idx].status & RXBD_EMPTY; t++) { if (t >= 10 * TOUT_LOOP) { printf("%s: tsec: rx error\n", dev->name); break; } } - if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt))) + if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt))) fail = 0; - rtx.rxbd[rxIdx].length = 0; - rtx.rxbd[rxIdx].status = - RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); - rxIdx = (rxIdx + 1) % PKTBUFSRX; + rtx.rxbd[rx_idx].length = 0; + rtx.rxbd[rx_idx].status = + RXBD_EMPTY | (((rx_idx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + rx_idx = (rx_idx + 1) % PKTBUFSRX; if (in_be32(®s->ievent) & IEVENT_BSY) { out_be32(®s->ievent, IEVENT_BSY); @@ -324,21 +324,21 @@ static void startup_tsec(struct eth_device *dev) struct tsec __iomem *regs = priv->regs; /* reset the indices to zero */ - rxIdx = 0; - txIdx = 0; + rx_idx = 0; + tx_idx = 0; #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 uint svr; #endif /* Point to the buffer descriptors */ - out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); - out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx])); + out_be32(®s->tbase, (unsigned int)(&rtx.txbd[tx_idx])); + out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rx_idx])); /* Initialize the Rx Buffer descriptors */ for (i = 0; i < PKTBUFSRX; i++) { rtx.rxbd[i].status = RXBD_EMPTY; rtx.rxbd[i].length = 0; - rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; + rtx.rxbd[i].bufptr = (uint) NetRxPackets[i]; } rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; @@ -346,7 +346,7 @@ static void startup_tsec(struct eth_device *dev) for (i = 0; i < TX_BUF_CNT; i++) { rtx.txbd[i].status = 0; rtx.txbd[i].length = 0; - rtx.txbd[i].bufPtr = 0; + rtx.txbd[i].bufptr = 0; } rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; @@ -378,31 +378,31 @@ static int tsec_send(struct eth_device *dev, void *packet, int length) struct tsec __iomem *regs = priv->regs; /* Find an empty buffer descriptor */ - for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; rtx.txbd[tx_idx].status & TXBD_READY; i++) { if (i >= TOUT_LOOP) { debug("%s: tsec: tx buffers full\n", dev->name); return result; } } - rtx.txbd[txIdx].bufPtr = (uint) packet; - rtx.txbd[txIdx].length = length; - rtx.txbd[txIdx].status |= + rtx.txbd[tx_idx].bufptr = (uint) packet; + rtx.txbd[tx_idx].length = length; + rtx.txbd[tx_idx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); /* Tell the DMA to go */ out_be32(®s->tstat, TSTAT_CLEAR_THALT); /* Wait for buffer to be transmitted */ - for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) { + for (i = 0; rtx.txbd[tx_idx].status & TXBD_READY; i++) { if (i >= TOUT_LOOP) { debug("%s: tsec: tx error\n", dev->name); return result; } } - txIdx = (txIdx + 1) % TX_BUF_CNT; - result = rtx.txbd[txIdx].status & TXBD_STATS; + tx_idx = (tx_idx + 1) % TX_BUF_CNT; + result = rtx.txbd[tx_idx].status & TXBD_STATS; return result; } @@ -413,25 +413,25 @@ static int tsec_recv(struct eth_device *dev) struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; - while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) { + while (!(rtx.rxbd[rx_idx].status & RXBD_EMPTY)) { - length = rtx.rxbd[rxIdx].length; + length = rtx.rxbd[rx_idx].length; /* Send the packet up if there were no errors */ - if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) { - NetReceive(NetRxPackets[rxIdx], length - 4); + if (!(rtx.rxbd[rx_idx].status & RXBD_STATS)) { + NetReceive(NetRxPackets[rx_idx], length - 4); } else { printf("Got error %x\n", - (rtx.rxbd[rxIdx].status & RXBD_STATS)); + (rtx.rxbd[rx_idx].status & RXBD_STATS)); } - rtx.rxbd[rxIdx].length = 0; + rtx.rxbd[rx_idx].length = 0; /* Set the wrap bit if this is the last element in the list */ - rtx.rxbd[rxIdx].status = - RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + rtx.rxbd[rx_idx].status = + RXBD_EMPTY | (((rx_idx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); - rxIdx = (rxIdx + 1) % PKTBUFSRX; + rx_idx = (rx_idx + 1) % PKTBUFSRX; } if (in_be32(®s->ievent) & IEVENT_BSY) { diff --git a/include/tsec.h b/include/tsec.h index c30aafbc06..6bc43ef65f 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -202,14 +202,14 @@ typedef struct txbd8 { ushort status; /* Status Fields */ ushort length; /* Buffer length */ - uint bufPtr; /* Buffer Pointer */ + uint bufptr; /* Buffer Pointer */ } txbd8_t; typedef struct rxbd8 { ushort status; /* Status Fields */ ushort length; /* Buffer Length */ - uint bufPtr; /* Buffer Pointer */ + uint bufptr; /* Buffer Pointer */ } rxbd8_t; typedef struct rmon_mib -- cgit v1.2.1 From 9c9141fd04f0991209dab9fe2716ce19b2a4f552 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Fri, 4 Oct 2013 19:13:53 +0300 Subject: net: tsec: Use portable types and accessors for BDs Currently, the buffer descriptor (BD) fields cannot be correctly accessed by a little endian processor. This patch fixes the issue by making the access of BDs to be portable among different cpu architectures. Use portable data types for the Rx/Tx buffer descriptor fields. Use portable I/O accessors to insure that the big endian BDs are correctly accessed by little endian cpus too, and to insure proper sync with the H/W. Removed the redundant RTXBD "volatile" type, as proper synchronization around BD data accesses is provided by the I/O accessors now. The "sparse" tool was also used to verify the correctness of these changes. Cc: Scott Wood Signed-off-by: Claudiu Manoil --- drivers/net/tsec.c | 88 ++++++++++++++++++++++++++++-------------------------- include/tsec.h | 22 +++++++------- 2 files changed, 56 insertions(+), 54 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 289229a42b..e354fad218 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -28,13 +28,10 @@ DECLARE_GLOBAL_DATA_PTR; static uint rx_idx; /* index of the current RX buffer */ static uint tx_idx; /* index of the current TX buffer */ -typedef volatile struct rtxbd { - txbd8_t txbd[TX_BUF_CNT]; - rxbd8_t rxbd[PKTBUFSRX]; -} RTXBD; - #ifdef __GNUC__ -static RTXBD rtx __attribute__ ((aligned(8))); +static struct txbd8 __iomem txbd[TX_BUF_CNT] __aligned(8); +static struct rxbd8 __iomem rxbd[PKTBUFSRX] __aligned(8); + #else #error "rtx must be 64-bit aligned" #endif @@ -275,10 +272,11 @@ void redundant_init(struct eth_device *dev) clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); do { + uint16_t status; tsec_send(dev, (void *)pkt, sizeof(pkt)); /* Wait for buffer to be received */ - for (t = 0; rtx.rxbd[rx_idx].status & RXBD_EMPTY; t++) { + for (t = 0; in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY; t++) { if (t >= 10 * TOUT_LOOP) { printf("%s: tsec: rx error\n", dev->name); break; @@ -288,9 +286,11 @@ void redundant_init(struct eth_device *dev) if (!memcmp(pkt, (void *)NetRxPackets[rx_idx], sizeof(pkt))) fail = 0; - rtx.rxbd[rx_idx].length = 0; - rtx.rxbd[rx_idx].status = - RXBD_EMPTY | (((rx_idx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + out_be16(&rxbd[rx_idx].length, 0); + status = RXBD_EMPTY; + if ((rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&rxbd[rx_idx].status, status); rx_idx = (rx_idx + 1) % PKTBUFSRX; if (in_be32(®s->ievent) & IEVENT_BSY) { @@ -319,9 +319,10 @@ void redundant_init(struct eth_device *dev) */ static void startup_tsec(struct eth_device *dev) { - int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; + uint16_t status; + int i; /* reset the indices to zero */ rx_idx = 0; @@ -331,24 +332,26 @@ static void startup_tsec(struct eth_device *dev) #endif /* Point to the buffer descriptors */ - out_be32(®s->tbase, (unsigned int)(&rtx.txbd[tx_idx])); - out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rx_idx])); + out_be32(®s->tbase, (u32)&txbd[0]); + out_be32(®s->rbase, (u32)&rxbd[0]); /* Initialize the Rx Buffer descriptors */ for (i = 0; i < PKTBUFSRX; i++) { - rtx.rxbd[i].status = RXBD_EMPTY; - rtx.rxbd[i].length = 0; - rtx.rxbd[i].bufptr = (uint) NetRxPackets[i]; + out_be16(&rxbd[i].status, RXBD_EMPTY); + out_be16(&rxbd[i].length, 0); + out_be32(&rxbd[i].bufptr, (u32)NetRxPackets[i]); } - rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; + status = in_be16(&rxbd[PKTBUFSRX - 1].status); + out_be16(&rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP); /* Initialize the TX Buffer Descriptors */ for (i = 0; i < TX_BUF_CNT; i++) { - rtx.txbd[i].status = 0; - rtx.txbd[i].length = 0; - rtx.txbd[i].bufptr = 0; + out_be16(&txbd[i].status, 0); + out_be16(&txbd[i].length, 0); + out_be32(&txbd[i].bufptr, 0); } - rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; + status = in_be16(&txbd[TX_BUF_CNT - 1].status); + out_be16(&txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP); #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 svr = get_svr(); @@ -372,29 +375,31 @@ static void startup_tsec(struct eth_device *dev) */ static int tsec_send(struct eth_device *dev, void *packet, int length) { - int i; - int result = 0; struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; + uint16_t status; + int result = 0; + int i; /* Find an empty buffer descriptor */ - for (i = 0; rtx.txbd[tx_idx].status & TXBD_READY; i++) { + for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { if (i >= TOUT_LOOP) { debug("%s: tsec: tx buffers full\n", dev->name); return result; } } - rtx.txbd[tx_idx].bufptr = (uint) packet; - rtx.txbd[tx_idx].length = length; - rtx.txbd[tx_idx].status |= - (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT); + out_be32(&txbd[tx_idx].bufptr, (u32)packet); + out_be16(&txbd[tx_idx].length, length); + status = in_be16(&txbd[tx_idx].status); + out_be16(&txbd[tx_idx].status, status | + (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT)); /* Tell the DMA to go */ out_be32(®s->tstat, TSTAT_CLEAR_THALT); /* Wait for buffer to be transmitted */ - for (i = 0; rtx.txbd[tx_idx].status & TXBD_READY; i++) { + for (i = 0; in_be16(&txbd[tx_idx].status) & TXBD_READY; i++) { if (i >= TOUT_LOOP) { debug("%s: tsec: tx error\n", dev->name); return result; @@ -402,34 +407,33 @@ static int tsec_send(struct eth_device *dev, void *packet, int length) } tx_idx = (tx_idx + 1) % TX_BUF_CNT; - result = rtx.txbd[tx_idx].status & TXBD_STATS; + result = in_be16(&txbd[tx_idx].status) & TXBD_STATS; return result; } static int tsec_recv(struct eth_device *dev) { - int length; struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; - while (!(rtx.rxbd[rx_idx].status & RXBD_EMPTY)) { - - length = rtx.rxbd[rx_idx].length; + while (!(in_be16(&rxbd[rx_idx].status) & RXBD_EMPTY)) { + int length = in_be16(&rxbd[rx_idx].length); + uint16_t status = in_be16(&rxbd[rx_idx].status); /* Send the packet up if there were no errors */ - if (!(rtx.rxbd[rx_idx].status & RXBD_STATS)) { + if (!(status & RXBD_STATS)) NetReceive(NetRxPackets[rx_idx], length - 4); - } else { - printf("Got error %x\n", - (rtx.rxbd[rx_idx].status & RXBD_STATS)); - } + else + printf("Got error %x\n", (status & RXBD_STATS)); - rtx.rxbd[rx_idx].length = 0; + out_be16(&rxbd[rx_idx].length, 0); + status = RXBD_EMPTY; /* Set the wrap bit if this is the last element in the list */ - rtx.rxbd[rx_idx].status = - RXBD_EMPTY | (((rx_idx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0); + if ((rx_idx + 1) == PKTBUFSRX) + status |= RXBD_WRAP; + out_be16(&rxbd[rx_idx].status, status); rx_idx = (rx_idx + 1) % PKTBUFSRX; } diff --git a/include/tsec.h b/include/tsec.h index 6bc43ef65f..95054be5fb 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -198,19 +198,17 @@ #define RXBD_TRUNCATED 0x0001 #define RXBD_STATS 0x003f -typedef struct txbd8 -{ - ushort status; /* Status Fields */ - ushort length; /* Buffer length */ - uint bufptr; /* Buffer Pointer */ -} txbd8_t; +struct txbd8 { + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer length */ + uint32_t bufptr; /* Buffer Pointer */ +}; -typedef struct rxbd8 -{ - ushort status; /* Status Fields */ - ushort length; /* Buffer Length */ - uint bufptr; /* Buffer Pointer */ -} rxbd8_t; +struct rxbd8 { + uint16_t status; /* Status Fields */ + uint16_t length; /* Buffer Length */ + uint32_t bufptr; /* Buffer Pointer */ +}; typedef struct rmon_mib { -- cgit v1.2.1 From 82ef75ca5c69c7d053c07f509a901d2ad2e29570 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:46 +0300 Subject: net: tsec: Use portable regs type (uint->u32) Use cross arch portable u32 instead of uint for the tsec registers. Remove the typedefs for the register struct definitions in the process. Fix long lines. Signed-off-by: Claudiu Manoil --- drivers/net/tsec.c | 2 +- include/tsec.h | 278 ++++++++++++++++++++++++++--------------------------- 2 files changed, 139 insertions(+), 141 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e354fad218..082cdecb3a 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -166,7 +166,7 @@ static void init_registers(struct tsec __iomem *regs) out_be32(®s->rctrl, 0x00000000); /* Init RMON mib registers */ - memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t)); + memset((void *)®s->rmon, 0, sizeof(regs->rmon)); out_be32(®s->rmon.cam1, 0xffffffff); out_be32(®s->rmon.cam2, 0xffffffff); diff --git a/include/tsec.h b/include/tsec.h index 95054be5fb..1046426c5c 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -210,179 +210,177 @@ struct rxbd8 { uint32_t bufptr; /* Buffer Pointer */ }; -typedef struct rmon_mib -{ +struct tsec_rmon_mib { /* Transmit and Receive Counters */ - uint tr64; /* Transmit and Receive 64-byte Frame Counter */ - uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ - uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ - uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ - uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ - uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ - uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ + u32 tr64; /* Tx/Rx 64-byte Frame Counter */ + u32 tr127; /* Tx/Rx 65-127 byte Frame Counter */ + u32 tr255; /* Tx/Rx 128-255 byte Frame Counter */ + u32 tr511; /* Tx/Rx 256-511 byte Frame Counter */ + u32 tr1k; /* Tx/Rx 512-1023 byte Frame Counter */ + u32 trmax; /* Tx/Rx 1024-1518 byte Frame Counter */ + u32 trmgv; /* Tx/Rx 1519-1522 byte Good VLAN Frame */ /* Receive Counters */ - uint rbyt; /* Receive Byte Counter */ - uint rpkt; /* Receive Packet Counter */ - uint rfcs; /* Receive FCS Error Counter */ - uint rmca; /* Receive Multicast Packet (Counter) */ - uint rbca; /* Receive Broadcast Packet */ - uint rxcf; /* Receive Control Frame Packet */ - uint rxpf; /* Receive Pause Frame Packet */ - uint rxuo; /* Receive Unknown OP Code */ - uint raln; /* Receive Alignment Error */ - uint rflr; /* Receive Frame Length Error */ - uint rcde; /* Receive Code Error */ - uint rcse; /* Receive Carrier Sense Error */ - uint rund; /* Receive Undersize Packet */ - uint rovr; /* Receive Oversize Packet */ - uint rfrg; /* Receive Fragments */ - uint rjbr; /* Receive Jabber */ - uint rdrp; /* Receive Drop */ + u32 rbyt; /* Receive Byte Counter */ + u32 rpkt; /* Receive Packet Counter */ + u32 rfcs; /* Receive FCS Error Counter */ + u32 rmca; /* Receive Multicast Packet (Counter) */ + u32 rbca; /* Receive Broadcast Packet */ + u32 rxcf; /* Receive Control Frame Packet */ + u32 rxpf; /* Receive Pause Frame Packet */ + u32 rxuo; /* Receive Unknown OP Code */ + u32 raln; /* Receive Alignment Error */ + u32 rflr; /* Receive Frame Length Error */ + u32 rcde; /* Receive Code Error */ + u32 rcse; /* Receive Carrier Sense Error */ + u32 rund; /* Receive Undersize Packet */ + u32 rovr; /* Receive Oversize Packet */ + u32 rfrg; /* Receive Fragments */ + u32 rjbr; /* Receive Jabber */ + u32 rdrp; /* Receive Drop */ /* Transmit Counters */ - uint tbyt; /* Transmit Byte Counter */ - uint tpkt; /* Transmit Packet */ - uint tmca; /* Transmit Multicast Packet */ - uint tbca; /* Transmit Broadcast Packet */ - uint txpf; /* Transmit Pause Control Frame */ - uint tdfr; /* Transmit Deferral Packet */ - uint tedf; /* Transmit Excessive Deferral Packet */ - uint tscl; /* Transmit Single Collision Packet */ + u32 tbyt; /* Transmit Byte Counter */ + u32 tpkt; /* Transmit Packet */ + u32 tmca; /* Transmit Multicast Packet */ + u32 tbca; /* Transmit Broadcast Packet */ + u32 txpf; /* Transmit Pause Control Frame */ + u32 tdfr; /* Transmit Deferral Packet */ + u32 tedf; /* Transmit Excessive Deferral Packet */ + u32 tscl; /* Transmit Single Collision Packet */ /* (0x2_n700) */ - uint tmcl; /* Transmit Multiple Collision Packet */ - uint tlcl; /* Transmit Late Collision Packet */ - uint txcl; /* Transmit Excessive Collision Packet */ - uint tncl; /* Transmit Total Collision */ - - uint res2; - - uint tdrp; /* Transmit Drop Frame */ - uint tjbr; /* Transmit Jabber Frame */ - uint tfcs; /* Transmit FCS Error */ - uint txcf; /* Transmit Control Frame */ - uint tovr; /* Transmit Oversize Frame */ - uint tund; /* Transmit Undersize Frame */ - uint tfrg; /* Transmit Fragments Frame */ + u32 tmcl; /* Transmit Multiple Collision Packet */ + u32 tlcl; /* Transmit Late Collision Packet */ + u32 txcl; /* Transmit Excessive Collision Packet */ + u32 tncl; /* Transmit Total Collision */ + + u32 res2; + + u32 tdrp; /* Transmit Drop Frame */ + u32 tjbr; /* Transmit Jabber Frame */ + u32 tfcs; /* Transmit FCS Error */ + u32 txcf; /* Transmit Control Frame */ + u32 tovr; /* Transmit Oversize Frame */ + u32 tund; /* Transmit Undersize Frame */ + u32 tfrg; /* Transmit Fragments Frame */ /* General Registers */ - uint car1; /* Carry Register One */ - uint car2; /* Carry Register Two */ - uint cam1; /* Carry Register One Mask */ - uint cam2; /* Carry Register Two Mask */ -} rmon_mib_t; - -typedef struct tsec_hash_regs -{ - uint iaddr0; /* Individual Address Register 0 */ - uint iaddr1; /* Individual Address Register 1 */ - uint iaddr2; /* Individual Address Register 2 */ - uint iaddr3; /* Individual Address Register 3 */ - uint iaddr4; /* Individual Address Register 4 */ - uint iaddr5; /* Individual Address Register 5 */ - uint iaddr6; /* Individual Address Register 6 */ - uint iaddr7; /* Individual Address Register 7 */ - uint res1[24]; - uint gaddr0; /* Group Address Register 0 */ - uint gaddr1; /* Group Address Register 1 */ - uint gaddr2; /* Group Address Register 2 */ - uint gaddr3; /* Group Address Register 3 */ - uint gaddr4; /* Group Address Register 4 */ - uint gaddr5; /* Group Address Register 5 */ - uint gaddr6; /* Group Address Register 6 */ - uint gaddr7; /* Group Address Register 7 */ - uint res2[24]; -} tsec_hash_t; + u32 car1; /* Carry Register One */ + u32 car2; /* Carry Register Two */ + u32 cam1; /* Carry Register One Mask */ + u32 cam2; /* Carry Register Two Mask */ +}; + +struct tsec_hash_regs { + u32 iaddr0; /* Individual Address Register 0 */ + u32 iaddr1; /* Individual Address Register 1 */ + u32 iaddr2; /* Individual Address Register 2 */ + u32 iaddr3; /* Individual Address Register 3 */ + u32 iaddr4; /* Individual Address Register 4 */ + u32 iaddr5; /* Individual Address Register 5 */ + u32 iaddr6; /* Individual Address Register 6 */ + u32 iaddr7; /* Individual Address Register 7 */ + u32 res1[24]; + u32 gaddr0; /* Group Address Register 0 */ + u32 gaddr1; /* Group Address Register 1 */ + u32 gaddr2; /* Group Address Register 2 */ + u32 gaddr3; /* Group Address Register 3 */ + u32 gaddr4; /* Group Address Register 4 */ + u32 gaddr5; /* Group Address Register 5 */ + u32 gaddr6; /* Group Address Register 6 */ + u32 gaddr7; /* Group Address Register 7 */ + u32 res2[24]; +}; struct tsec { /* General Control and Status Registers (0x2_n000) */ - uint res000[4]; + u32 res000[4]; - uint ievent; /* Interrupt Event */ - uint imask; /* Interrupt Mask */ - uint edis; /* Error Disabled */ - uint res01c; - uint ecntrl; /* Ethernet Control */ - uint minflr; /* Minimum Frame Length */ - uint ptv; /* Pause Time Value */ - uint dmactrl; /* DMA Control */ - uint tbipa; /* TBI PHY Address */ + u32 ievent; /* Interrupt Event */ + u32 imask; /* Interrupt Mask */ + u32 edis; /* Error Disabled */ + u32 res01c; + u32 ecntrl; /* Ethernet Control */ + u32 minflr; /* Minimum Frame Length */ + u32 ptv; /* Pause Time Value */ + u32 dmactrl; /* DMA Control */ + u32 tbipa; /* TBI PHY Address */ - uint res034[3]; - uint res040[48]; + u32 res034[3]; + u32 res040[48]; /* Transmit Control and Status Registers (0x2_n100) */ - uint tctrl; /* Transmit Control */ - uint tstat; /* Transmit Status */ - uint res108; - uint tbdlen; /* Tx BD Data Length */ - uint res110[5]; - uint ctbptr; /* Current TxBD Pointer */ - uint res128[23]; - uint tbptr; /* TxBD Pointer */ - uint res188[30]; + u32 tctrl; /* Transmit Control */ + u32 tstat; /* Transmit Status */ + u32 res108; + u32 tbdlen; /* Tx BD Data Length */ + u32 res110[5]; + u32 ctbptr; /* Current TxBD Pointer */ + u32 res128[23]; + u32 tbptr; /* TxBD Pointer */ + u32 res188[30]; /* (0x2_n200) */ - uint res200; - uint tbase; /* TxBD Base Address */ - uint res208[42]; - uint ostbd; /* Out of Sequence TxBD */ - uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ - uint res2b8[18]; + u32 res200; + u32 tbase; /* TxBD Base Address */ + u32 res208[42]; + u32 ostbd; /* Out of Sequence TxBD */ + u32 ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ + u32 res2b8[18]; /* Receive Control and Status Registers (0x2_n300) */ - uint rctrl; /* Receive Control */ - uint rstat; /* Receive Status */ - uint res308; - uint rbdlen; /* RxBD Data Length */ - uint res310[4]; - uint res320; - uint crbptr; /* Current Receive Buffer Pointer */ - uint res328[6]; - uint mrblr; /* Maximum Receive Buffer Length */ - uint res344[16]; - uint rbptr; /* RxBD Pointer */ - uint res388[30]; + u32 rctrl; /* Receive Control */ + u32 rstat; /* Receive Status */ + u32 res308; + u32 rbdlen; /* RxBD Data Length */ + u32 res310[4]; + u32 res320; + u32 crbptr; /* Current Receive Buffer Pointer */ + u32 res328[6]; + u32 mrblr; /* Maximum Receive Buffer Length */ + u32 res344[16]; + u32 rbptr; /* RxBD Pointer */ + u32 res388[30]; /* (0x2_n400) */ - uint res400; - uint rbase; /* RxBD Base Address */ - uint res408[62]; + u32 res400; + u32 rbase; /* RxBD Base Address */ + u32 res408[62]; /* MAC Registers (0x2_n500) */ - uint maccfg1; /* MAC Configuration #1 */ - uint maccfg2; /* MAC Configuration #2 */ - uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ - uint hafdup; /* Half-duplex */ - uint maxfrm; /* Maximum Frame */ - uint res514; - uint res518; + u32 maccfg1; /* MAC Configuration #1 */ + u32 maccfg2; /* MAC Configuration #2 */ + u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ + u32 hafdup; /* Half-duplex */ + u32 maxfrm; /* Maximum Frame */ + u32 res514; + u32 res518; - uint res51c; + u32 res51c; - uint resmdio[6]; + u32 resmdio[6]; - uint res538; + u32 res538; - uint ifstat; /* Interface Status */ - uint macstnaddr1; /* Station Address, part 1 */ - uint macstnaddr2; /* Station Address, part 2 */ - uint res548[46]; + u32 ifstat; /* Interface Status */ + u32 macstnaddr1; /* Station Address, part 1 */ + u32 macstnaddr2; /* Station Address, part 2 */ + u32 res548[46]; /* (0x2_n600) */ - uint res600[32]; + u32 res600[32]; /* RMON MIB Registers (0x2_n680-0x2_n73c) */ - rmon_mib_t rmon; - uint res740[48]; + struct tsec_rmon_mib rmon; + u32 res740[48]; /* Hash Function Registers (0x2_n800) */ - tsec_hash_t hash; + struct tsec_hash_regs hash; - uint res900[128]; + u32 res900[128]; /* Pattern Registers (0x2_nb00) */ - uint resb00[62]; - uint attr; /* Default Attribute Register */ - uint attreli; /* Default Attribute Extract Length and Index */ + u32 resb00[62]; + u32 attr; /* Default Attribute Register */ + u32 attreli; /* Default Attribute Extract Length and Index */ /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ - uint resc00[256]; + u32 resc00[256]; }; #define TSEC_GIGABIT (1 << 0) -- cgit v1.2.1 From b1690bc39cfdba82be34b1a98abc319339070698 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Mon, 30 Sep 2013 12:44:47 +0300 Subject: net: tsec: Fix mac addr setup portability, cleanup Fix the 32-bit memory access that is not "endianess safe", i.e. not giving the desired byte layout for LE cpus: tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'. Free the stack from rendundant local vars: tmpbuf[] and i. Use a portable type (u32) for the 32bit tsec register value holder: tempval. Signed-off-by: Claudiu Manoil --- drivers/net/tsec.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 082cdecb3a..e9138f0338 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -473,11 +473,9 @@ static void tsec_halt(struct eth_device *dev) */ static int tsec_init(struct eth_device *dev, bd_t * bd) { - uint tempval; - char tmpbuf[MAC_ADDR_LEN]; - int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; struct tsec __iomem *regs = priv->regs; + u32 tempval; int ret; /* Make sure the controller is stopped */ @@ -490,16 +488,16 @@ static int tsec_init(struct eth_device *dev, bd_t * bd) out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS); /* Copy the station address into the address registers. - * Backwards, because little endian MACS are dumb */ - for (i = 0; i < MAC_ADDR_LEN; i++) - tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i]; - - tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) | - tmpbuf[3]; + * For a station address of 0x12345678ABCD in transmission + * order (BE), MACnADDR1 is set to 0xCDAB7856 and + * MACnADDR2 is set to 0x34120000. + */ + tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) | + (dev->enetaddr[3] << 8) | dev->enetaddr[2]; out_be32(®s->macstnaddr1, tempval); - tempval = *((uint *) (tmpbuf + 4)); + tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16); out_be32(®s->macstnaddr2, tempval); -- cgit v1.2.1 From 317745785341774644b8bb1cbb0300155f31cee6 Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Fri, 1 Nov 2013 17:17:44 +0800 Subject: net/phy: Fix the phy id mask of AR8031 The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan Cc: Joe Hershberger Patch: 287748 --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index f225d93a36..215658ab28 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -50,7 +50,7 @@ static struct phy_driver AR8021_driver = { static struct phy_driver AR8031_driver = { .name = "AR8031/AR8033", .uid = 0x4dd074, - .mask = 0xffffff, + .mask = 0x4fffff, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, -- cgit v1.2.1 From e003ba5bfc57ff7d065967e263fa24e3ef28ea0a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Sat, 2 Nov 2013 16:40:42 -0200 Subject: net: phy: atheros: Fix masks for AR8035 and AR8021 The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton Signed-off-by: Fabio Estevam Patch: 288018 --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 215658ab28..b20b4df981 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -40,7 +40,7 @@ static int ar8035_config(struct phy_device *phydev) static struct phy_driver AR8021_driver = { .name = "AR8021", .uid = 0x4dd040, - .mask = 0xfffff0, + .mask = 0x4fffff, .features = PHY_GBIT_FEATURES, .config = ar8021_config, .startup = genphy_startup, -- cgit v1.2.1 From 8e52533d109571915a0006533e2e1adb01face00 Mon Sep 17 00:00:00 2001 From: Andrew Ruder Date: Tue, 22 Oct 2013 19:10:28 -0500 Subject: net: tftpsrv: Get correct client MAC address NetServerEther was not being cleared in the tftp server code, so the destination MAC address would be whatever the last destination MAC address was. Scenario: U-Boot: dhcp tftpsrv Host: Send device WRQ Device: Responds with ACK to dhcp server mac address with host ip address By clearing NetServerEther, we force a lookup of the host MAC address to go with the associated host IP. Signed-off-by: Andrew Ruder --- net/tftp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/tftp.c b/net/tftp.c index 2e06808d16..966d1cfba3 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -849,6 +849,9 @@ TftpStartServer(void) TftpState = STATE_RECV_WRQ; net_set_udp_handler(TftpHandler); + + /* zero out server ether in case the server ip has changed */ + memset(NetServerEther, 0, 6); } #endif /* CONFIG_CMD_TFTPSRV */ -- cgit v1.2.1 From 8712adfd0595ea68ce06fb22420489dacc3a6cc6 Mon Sep 17 00:00:00 2001 From: Rojhalat Ibrahim Date: Mon, 7 Oct 2013 18:30:39 +0200 Subject: drivers/net/e1000: Introduce CONFIG_E1000_NO_NVM The e1000 driver expects to always have some kind of non-volatile memory attached directly to the ethernet controller chip. This means that I would have to add an additional separate flash chip to my custom board just to store essentially the MAC address. Since I don't want to do that, this patch introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables all accesses to the NVM. I have tested the patch with a 82574 controller. Signed-off-by: Rojhalat Ibrahim --- drivers/net/e1000.c | 34 +++++++++++++++++++++++++++++----- drivers/net/e1000.h | 9 +++++++++ 2 files changed, 38 insertions(+), 5 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 57aa53dbae..9a66e68ae0 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -114,12 +114,13 @@ static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, static int32_t e1000_phy_hw_reset(struct e1000_hw *hw); static int e1000_phy_reset(struct e1000_hw *hw); static int e1000_detect_gig_phy(struct e1000_hw *hw); -static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); static void e1000_set_media_type(struct e1000_hw *hw); static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw); +#ifndef CONFIG_E1000_NO_NVM +static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); @@ -885,6 +886,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) return -E1000_ERR_EEPROM; } +#endif /* CONFIG_E1000_NO_NVM */ /***************************************************************************** * Set PHY to class A mode @@ -897,6 +899,7 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) static int32_t e1000_set_phy_mode(struct e1000_hw *hw) { +#ifndef CONFIG_E1000_NO_NVM int32_t ret_val; uint16_t eeprom_data; @@ -923,10 +926,11 @@ e1000_set_phy_mode(struct e1000_hw *hw) hw->phy_reset_disable = false; } } - +#endif return E1000_SUCCESS; } +#ifndef CONFIG_E1000_NO_NVM /*************************************************************************** * * Obtaining software semaphore bit (SMBI) before resetting PHY. @@ -965,6 +969,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw) return E1000_SUCCESS; } +#endif /*************************************************************************** * This function clears HW semaphore bits. @@ -977,6 +982,7 @@ e1000_get_software_semaphore(struct e1000_hw *hw) static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) { +#ifndef CONFIG_E1000_NO_NVM uint32_t swsm; DEBUGFUNC(); @@ -991,6 +997,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) } else swsm &= ~(E1000_SWSM_SWESMBI); E1000_WRITE_REG(hw, SWSM, swsm); +#endif } /*************************************************************************** @@ -1007,6 +1014,7 @@ e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) { +#ifndef CONFIG_E1000_NO_NVM int32_t timeout; uint32_t swsm; @@ -1043,7 +1051,7 @@ e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) "SWESMBI bit is set.\n"); return -E1000_ERR_EEPROM; } - +#endif return E1000_SUCCESS; } @@ -1097,6 +1105,7 @@ static bool e1000_is_second_port(struct e1000_hw *hw) } } +#ifndef CONFIG_E1000_NO_NVM /****************************************************************************** * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the * second function of dual function devices @@ -1136,6 +1145,7 @@ e1000_read_mac_addr(struct eth_device *nic) #endif return 0; } +#endif /****************************************************************************** * Initializes receive address filters. @@ -1764,9 +1774,11 @@ static int e1000_setup_link(struct eth_device *nic) { struct e1000_hw *hw = nic->priv; - uint32_t ctrl_ext; int32_t ret_val; +#ifndef CONFIG_E1000_NO_NVM + uint32_t ctrl_ext; uint16_t eeprom_data; +#endif DEBUGFUNC(); @@ -1775,6 +1787,7 @@ e1000_setup_link(struct eth_device *nic) if (e1000_check_phy_reset_block(hw)) return E1000_SUCCESS; +#ifndef CONFIG_E1000_NO_NVM /* Read and store word 0x0F of the EEPROM. This word contains bits * that determine the hardware's default PAUSE (flow control) mode, * a bit that determines whether the HW defaults to enabling or @@ -1788,7 +1801,7 @@ e1000_setup_link(struct eth_device *nic) DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } - +#endif if (hw->fc == e1000_fc_default) { switch (hw->mac_type) { case e1000_ich8lan: @@ -1797,6 +1810,7 @@ e1000_setup_link(struct eth_device *nic) hw->fc = e1000_fc_full; break; default: +#ifndef CONFIG_E1000_NO_NVM ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data); if (ret_val) { @@ -1809,6 +1823,7 @@ e1000_setup_link(struct eth_device *nic) EEPROM_WORD0F_ASM_DIR) hw->fc = e1000_fc_tx_pause; else +#endif hw->fc = e1000_fc_full; break; } @@ -1828,6 +1843,7 @@ e1000_setup_link(struct eth_device *nic) DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); +#ifndef CONFIG_E1000_NO_NVM /* Take the 4 bits from EEPROM word 0x0F that determine the initial * polarity value for the SW controlled pins, and setup the * Extended Device Control reg with that info. @@ -1840,6 +1856,7 @@ e1000_setup_link(struct eth_device *nic) SWDPIO__EXT_SHIFT); E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); } +#endif /* Call the necessary subroutine to configure the link. */ ret_val = (hw->media_type == e1000_media_type_fiber) ? @@ -5196,6 +5213,7 @@ e1000_initialize(bd_t * bis) e1000_reset_hw(hw); list_add_tail(&hw->list_node, &e1000_hw_list); +#ifndef CONFIG_E1000_NO_NVM /* Validate the EEPROM and get chipset information */ #if !defined(CONFIG_MVBC_1G) if (e1000_init_eeprom_params(hw)) { @@ -5206,11 +5224,17 @@ e1000_initialize(bd_t * bis) continue; #endif e1000_read_mac_addr(nic); +#endif e1000_get_bus_type(hw); +#ifndef CONFIG_E1000_NO_NVM printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); +#else + memset(nic->enetaddr, 0, 6); + printf("e1000: no NVM\n"); +#endif /* Set up the function pointers and register the device */ nic->init = e1000_init; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 25884f5bc5..ff87af2ef8 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -63,11 +63,14 @@ struct e1000_hw_stats; /* Internal E1000 helper functions */ struct e1000_hw *e1000_find_card(unsigned int cardnum); + +#ifndef CONFIG_E1000_NO_NVM int32_t e1000_acquire_eeprom(struct e1000_hw *hw); void e1000_standby_eeprom(struct e1000_hw *hw); void e1000_release_eeprom(struct e1000_hw *hw); void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); +#endif #ifdef CONFIG_E1000_SPI int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, @@ -1019,6 +1022,7 @@ struct e1000_hw_stats { uint64_t tsctfc; }; +#ifndef CONFIG_E1000_NO_NVM struct e1000_eeprom_info { e1000_eeprom_type type; uint16_t word_size; @@ -1029,6 +1033,7 @@ e1000_eeprom_type type; bool use_eerd; bool use_eewr; }; +#endif typedef enum { e1000_smart_speed_default = 0, @@ -1081,10 +1086,14 @@ struct e1000_hw { uint32_t io_base; #endif uint32_t asf_firmware_present; +#ifndef CONFIG_E1000_NO_NVM uint32_t eeprom_semaphore_present; +#endif uint32_t swfw_sync_present; uint32_t swfwhw_semaphore_present; +#ifndef CONFIG_E1000_NO_NVM struct e1000_eeprom_info eeprom; +#endif e1000_ms_type master_slave; e1000_ms_type original_master_slave; e1000_ffe_config ffe_config_state; -- cgit v1.2.1 From c583ee16cb5db73fc299bb679ecb75a5abb3ca47 Mon Sep 17 00:00:00 2001 From: Andrew Ruder Date: Tue, 22 Oct 2013 19:09:02 -0500 Subject: net: dm9000: random mac address support When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random (and valid) locally administered MAC address that allows the system to network boot until a real MAC address can be configured. Signed-off-by: Andrew Ruder --- drivers/net/dm9000x.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index f7170e0554..b68d808c74 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -342,6 +342,15 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS); printf("MAC: %pM\n", dev->enetaddr); + if (!is_valid_ether_addr(dev->enetaddr)) { +#ifdef CONFIG_RANDOM_MACADDR + printf("Bad MAC address (uninitialized EEPROM?), randomizing\n"); + eth_random_enetaddr(dev->enetaddr); + printf("MAC: %pM\n", dev->enetaddr); +#else + printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); +#endif + } /* fill device MAC address registers */ for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++) -- cgit v1.2.1 From 3a530d1b3e947c09e882dda8883aa608458a598c Mon Sep 17 00:00:00 2001 From: David Dueck Date: Tue, 5 Nov 2013 17:23:02 +0100 Subject: phy: Use supported field during autonegotiation The current code incorrectly detects gigabit capabilities for some 100Mbit/s phys. (lan8720a) Signed-off-by: David Dueck --- drivers/net/phy/phy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 62925bb286..c691fbbbc6 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -275,13 +275,14 @@ int genphy_parse_link(struct phy_device *phydev) int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); /* We're using autonegotiation */ - if (mii_reg & BMSR_ANEGCAPABLE) { + if (phydev->supported & SUPPORTED_Autoneg) { u32 lpa = 0; int gblpa = 0; u32 estatus = 0; /* Check for gigabit capability */ - if (mii_reg & BMSR_ERCAP) { + if (phydev->supported & (SUPPORTED_1000baseT_Full | + SUPPORTED_1000baseT_Half)) { /* We want a list of states supported by * both PHYs in the link */ -- cgit v1.2.1 From f27f3b5266d28b8d3e80e0e8f4cafdd14268b62a Mon Sep 17 00:00:00 2001 From: David Dueck Date: Tue, 5 Nov 2013 17:23:03 +0100 Subject: phy: Use general phy code for smsc lan8720a Signed-off-by: David Dueck --- drivers/net/phy/smsc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index 60ed92d203..bfd9815abf 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -12,6 +12,7 @@ */ #include +/* This code does not check the partner abilities. */ static int smsc_parse_status(struct phy_device *phydev) { int mii_reg; @@ -64,7 +65,7 @@ static struct phy_driver lan8710_driver = { .mask = 0xffff0, .features = PHY_BASIC_FEATURES, .config = &genphy_config_aneg, - .startup = &smsc_startup, + .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; -- cgit v1.2.1 From a5144237ac6dce3a38a73a51c217636a37d1e0b6 Mon Sep 17 00:00:00 2001 From: Srikanth Thokala Date: Fri, 8 Nov 2013 22:55:48 +0530 Subject: net: zynq_gem: Add d-cache support Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala Signed-off-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 82 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 53 insertions(+), 29 deletions(-) diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 236a75311f..6a017a8102 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -43,11 +43,6 @@ #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */ -#define ZYNQ_GEM_TXSR_HRESPNOK_MASK 0x00000100 /* Transmit hresp not OK */ -#define ZYNQ_GEM_TXSR_URUN_MASK 0x00000040 /* Transmit underrun */ -/* Transmit buffs exhausted mid frame */ -#define ZYNQ_GEM_TXSR_BUFEXH_MASK 0x00000010 - #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */ #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */ #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ @@ -90,6 +85,11 @@ */ #define PHY_DETECT_MASK 0x1808 +/* TX BD status masks */ +#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff +#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 +#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 + /* Device registers */ struct zynq_gem_regs { u32 nwctrl; /* Network Control reg */ @@ -123,12 +123,18 @@ struct emac_bd { }; #define RX_BUF 3 +/* Page table entries are set to 1MB, or multiples of 1MB + * (not < 1MB). driver uses less bd's so use 1MB bdspace. + */ +#define BD_SPACE 0x100000 +/* BD separation space */ +#define BD_SEPRN_SPACE 64 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */ struct zynq_gem_priv { - struct emac_bd tx_bd; - struct emac_bd rx_bd[RX_BUF]; - char rxbuffers[RX_BUF * PKTSIZE_ALIGN]; + struct emac_bd *tx_bd; + struct emac_bd *rx_bd; + char *rxbuffers; u32 rxbd_current; u32 rx_first_buf; int phyaddr; @@ -299,20 +305,18 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) readl(®s->stat[i]); /* Setup RxBD space */ - memset(&(priv->rx_bd), 0, sizeof(priv->rx_bd)); - /* Create the RxBD ring */ - memset(&(priv->rxbuffers), 0, sizeof(priv->rxbuffers)); + memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd)); for (i = 0; i < RX_BUF; i++) { priv->rx_bd[i].status = 0xF0000000; priv->rx_bd[i].addr = - (u32)((char *)&(priv->rxbuffers) + + ((u32)(priv->rxbuffers) + (i * PKTSIZE_ALIGN)); } /* WRAP bit to last BD */ priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK; /* Write RxBDs to IP */ - writel((u32)&(priv->rx_bd), ®s->rxqbase); + writel((u32)priv->rx_bd, ®s->rxqbase); /* Setup for DMA Configuration register */ writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); @@ -368,32 +372,35 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) static int zynq_gem_send(struct eth_device *dev, void *ptr, int len) { - u32 status; + u32 addr, size; struct zynq_gem_priv *priv = dev->priv; struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase; - const u32 mask = ZYNQ_GEM_TXSR_HRESPNOK_MASK | \ - ZYNQ_GEM_TXSR_URUN_MASK | ZYNQ_GEM_TXSR_BUFEXH_MASK; /* setup BD */ - writel((u32)&(priv->tx_bd), ®s->txqbase); + writel((u32)priv->tx_bd, ®s->txqbase); /* Setup Tx BD */ - memset((void *)&(priv->tx_bd), 0, sizeof(struct emac_bd)); + memset(priv->tx_bd, 0, sizeof(struct emac_bd)); + + priv->tx_bd->addr = (u32)ptr; + priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) | + ZYNQ_GEM_TXBUF_LAST_MASK; - priv->tx_bd.addr = (u32)ptr; - priv->tx_bd.status = len | ZYNQ_GEM_TXBUF_LAST_MASK; + addr = (u32) ptr; + addr &= ~(ARCH_DMA_MINALIGN - 1); + size = roundup(len, ARCH_DMA_MINALIGN); + flush_dcache_range(addr, addr + size); + barrier(); /* Start transmit */ setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK); - /* Read the stat register to know if the packet has been transmitted */ - status = readl(®s->txsr); - if (status & mask) - printf("Something has gone wrong here!? Status is 0x%x.\n", - status); + /* Read TX BD status */ + if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN) + printf("TX underrun\n"); + if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) + printf("TX buffers exhausted in mid frame\n"); - /* Clear Tx status register before leaving . */ - writel(status, ®s->txsr); return 0; } @@ -416,8 +423,12 @@ static int zynq_gem_recv(struct eth_device *dev) frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK; if (frame_len) { - NetReceive((u8 *) (current_bd->addr & - ZYNQ_GEM_RXBUF_ADD_MASK), frame_len); + u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; + addr &= ~(ARCH_DMA_MINALIGN - 1); + u32 size = roundup(frame_len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(addr, addr + size); + + NetReceive((u8 *)addr, frame_len); if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) priv->rx_first_buf = priv->rxbd_current; @@ -471,6 +482,7 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) { struct eth_device *dev; struct zynq_gem_priv *priv; + void *bd_space; dev = calloc(1, sizeof(*dev)); if (dev == NULL) @@ -483,6 +495,18 @@ int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio) } priv = dev->priv; + /* Align rxbuffers to ARCH_DMA_MINALIGN */ + priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN); + memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN); + + /* Align bd_space to 1MB */ + bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); + mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, DCACHE_OFF); + + /* Initialize the bd spaces for tx and rx bd's */ + priv->tx_bd = (struct emac_bd *)bd_space; + priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); + priv->phyaddr = phy_addr; priv->emio = emio; -- cgit v1.2.1 From 22ece0e2e23c5cc5a23a5b8aff3dc75c9832e82f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Sep 2013 16:03:42 +0200 Subject: net: rtl8169: Improve cache maintenance Instead of directly calling the low-level invalidate_dcache_range() and flush_cache() functions, provide thin wrappers that take into account alignment requirements. While at it, fix a case where the cache was flushed but should have been invalidated, two cases where the buffer data was flushed instead of the descriptor and a missing cache invalidation before reading the packet data that the NIC just wrote to memory. Signed-off-by: Thierry Reding Patch: 276474 --- drivers/net/rtl8169.c | 61 ++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 290c9887c0..c47485a969 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -395,6 +395,50 @@ match: return 0; } +/* + * Cache maintenance functions. These are simple wrappers around the more + * general purpose flush_cache() and invalidate_dcache_range() functions. + */ + +static void rtl_inval_rx_desc(struct RxDesc *desc) +{ + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static void rtl_flush_rx_desc(struct RxDesc *desc) +{ + flush_cache((unsigned long)desc, sizeof(*desc)); +} + +static void rtl_inval_tx_desc(struct TxDesc *desc) +{ + unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static void rtl_flush_tx_desc(struct TxDesc *desc) +{ + flush_cache((unsigned long)desc, sizeof(*desc)); +} + +static void rtl_inval_buffer(void *buf, size_t size) +{ + unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static void rtl_flush_buffer(void *buf, size_t size) +{ + flush_cache((unsigned long)buf, size); +} + /************************************************************************** RECV - Receive a frame ***************************************************************************/ @@ -412,14 +456,16 @@ static int rtl_recv(struct eth_device *dev) ioaddr = dev->iobase; cur_rx = tpc->cur_rx; - flush_cache((unsigned long)&tpc->RxDescArray[cur_rx], - sizeof(struct RxDesc)); + + rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); + if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { unsigned char rxdata[RX_BUF_LEN]; length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. status) & 0x00001FFF) - 4; + rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); NetReceive(rxdata, length); @@ -431,8 +477,7 @@ static int rtl_recv(struct eth_device *dev) cpu_to_le32(OWNbit + RX_BUF_SIZE); tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); - flush_cache((unsigned long)tpc->RxBufferRing[cur_rx], - RX_BUF_SIZE); + rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); } else { puts("Error Rx"); } @@ -474,7 +519,7 @@ static int rtl_send(struct eth_device *dev, void *packet, int length) /* point to the current txb incase multiple tx_rings are used */ ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; memcpy(ptxb, (char *)packet, (int)length); - flush_cache((unsigned long)ptxb, length); + rtl_flush_buffer(ptxb, length); while (len < ETH_ZLEN) ptxb[len++] = '\0'; @@ -490,13 +535,13 @@ static int rtl_send(struct eth_device *dev, void *packet, int length) cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | ((len > ETH_ZLEN) ? len : ETH_ZLEN)); } + rtl_flush_tx_desc(&tpc->TxDescArray[entry]); RTL_W8(TxPoll, 0x40); /* set polling bit */ tpc->cur_tx++; to = currticks() + TX_TIMEOUT; do { - flush_cache((unsigned long)&tpc->TxDescArray[entry], - sizeof(struct TxDesc)); + rtl_inval_tx_desc(&tpc->TxDescArray[entry]); } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) && (currticks() < to)); /* wait */ @@ -639,7 +684,7 @@ static void rtl8169_init_ring(struct eth_device *dev) tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; tpc->RxDescArray[i].buf_addr = cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); - flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE); + rtl_flush_rx_desc(&tpc->RxDescArray[i]); } #ifdef DEBUG_RTL8169 -- cgit v1.2.1 From 2287286be4e268d3d4ec3c0347bf31479dbd1f05 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 20 Sep 2013 16:03:43 +0200 Subject: net: rtl8169: Add support for RTL8168d/8111d This chip is compatible with the existing driver, except that it uses BAR2 instead of BAR1 for the I/O memory region. Using this patch I can use the PCIe ethernet interface on the CompuLab Trimslice to boot from the network. Signed-off-by: Thierry Reding Patch: 276477 --- drivers/net/rtl8169.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index c47485a969..d040ab171b 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -246,6 +246,7 @@ static struct { {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, + {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, {"RTL-8101e", 0x34, 0xff7e1880,}, {"RTL-8100e", 0x32, 0xff7e1880,}, @@ -315,6 +316,7 @@ static const unsigned int rtl8169_rx_config = static struct pci_device_id supported[] = { {PCI_VENDOR_ID_REALTEK, 0x8167}, + {PCI_VENDOR_ID_REALTEK, 0x8168}, {PCI_VENDOR_ID_REALTEK, 0x8169}, {} }; @@ -915,11 +917,25 @@ int rtl8169_initialize(bd_t *bis) int idx=0; while(1){ + unsigned int region; + u16 device; + /* Find RTL8169 */ if ((devno = pci_find_devices(supported, idx++)) < 0) break; - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + pci_read_config_word(devno, PCI_DEVICE_ID, &device); + switch (device) { + case 0x8168: + region = 2; + break; + + default: + region = 1; + break; + } + + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); iobase &= ~0xf; debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); -- cgit v1.2.1 From 4b756b013ae0159d77d34981b57f8590f8dba2ee Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 7 Nov 2013 07:39:48 -0500 Subject: hash.c: Correct non-hash subcommand crc32 addr-save support In the case of not having CONFIG_CMD_HASH but having CONFIG_CMD_CRC32 enabled (and not CONFIG_CRC32_VERIFY), we end up in this part of the code path on hash_command(). However, we will only have exactly 3 args here, and 3 > 3 is false, and we will not try and store the hash at the address given as arg #3. The next problem however is that we've been moving argv around so the third value is now in argv[0] not argv[3]. Confirmed on AM335x Beaglebone White. Signed-off-by: Tom Rini --- common/hash.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/hash.c b/common/hash.c index 722c40b3f3..872cd85428 100644 --- a/common/hash.c +++ b/common/hash.c @@ -325,8 +325,8 @@ int hash_command(const char *algo_name, int flags, cmd_tbl_t *cmdtp, int flag, printf("CRC32 for %08lx ... %08lx ==> %08lx\n", addr, addr + len - 1, crc); - if (argc > 3) { - ptr = (ulong *)simple_strtoul(argv[3], NULL, 16); + if (argc >= 3) { + ptr = (ulong *)simple_strtoul(argv[0], NULL, 16); *ptr = crc; } } -- cgit v1.2.1 From 1df7bbba24b5f8f97331e30066358b7ab97ff1df Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Fri, 8 Nov 2013 01:03:50 +0200 Subject: README: document the CONFIG_GPIO_LED symbol The CONFIG_GPIO_LED symbol does not have any documentation in the README file. Document the CONFIG_GPIO_LED symbol. Signed-off-by: Igor Grinberg --- README | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/README b/README index c97ff0af0b..7b393b79b3 100644 --- a/README +++ b/README @@ -1963,6 +1963,14 @@ CBFS (Coreboot Filesystem) support kernel). Defining CONFIG_STATUS_LED enables this feature in U-Boot. + Additional options: + + CONFIG_GPIO_LED + The status LED can be connected to a GPIO pin. + In such cases, the gpio_led driver can be used as a + status LED backend implementation. Define CONFIG_GPIO_LED + to include the gpio_led driver in the U-Boot binary. + - CAN Support: CONFIG_CAN_DRIVER Defining CONFIG_CAN_DRIVER enables CAN driver support -- cgit v1.2.1 From 6516f81b64c71ab2be61f304d0e13dd84f730484 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Fri, 8 Nov 2013 01:03:51 +0200 Subject: gpio_led: check gpio_request() return value Add a check for the gpio_request() function return value and do not try to configure the GPIO if the gpio_request() call fails. Also, print an error message indicating the gpio_request() has failed. Signed-off-by: Igor Grinberg Tested-by: Ilya Ledvich --- drivers/misc/gpio_led.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c index 3fedddc8b5..de2041956b 100644 --- a/drivers/misc/gpio_led.c +++ b/drivers/misc/gpio_led.c @@ -11,7 +11,11 @@ void __led_init(led_id_t mask, int state) { - gpio_request(mask, "gpio_led"); + if (gpio_request(mask, "gpio_led") != 0) { + printf("%s: failed requesting GPIO%lu!\n", __func__, mask); + return; + } + gpio_direction_output(mask, state == STATUS_LED_ON); } -- cgit v1.2.1 From 9dfdcdfed4726f94fc38d94f29f8214f38058576 Mon Sep 17 00:00:00 2001 From: Igor Grinberg Date: Fri, 8 Nov 2013 01:03:52 +0200 Subject: gpio_led: add support for inverted polarity Some GPIO connected LEDs have inverted polarity. Introduce new config option: CONFIG_GPIO_LED_INVERTED_TABLE for the specifying the inverted GPIO LEDs list and add support for this in the gpio_led driver. Signed-off-by: Igor Grinberg Tested-by: Ilya Ledvich --- README | 7 +++++++ drivers/misc/gpio_led.c | 27 +++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/README b/README index 7b393b79b3..5def773ff5 100644 --- a/README +++ b/README @@ -1971,6 +1971,13 @@ CBFS (Coreboot Filesystem) support status LED backend implementation. Define CONFIG_GPIO_LED to include the gpio_led driver in the U-Boot binary. + CONFIG_GPIO_LED_INVERTED_TABLE + Some GPIO connected LEDs may have inverted polarity in which + case the GPIO high value corresponds to LED off state and + GPIO low value corresponds to LED on state. + In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined + with a list of GPIO LEDs that have inverted polarity. + - CAN Support: CONFIG_CAN_DRIVER Defining CONFIG_CAN_DRIVER enables CAN driver support diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c index de2041956b..3e95727d79 100644 --- a/drivers/misc/gpio_led.c +++ b/drivers/misc/gpio_led.c @@ -9,19 +9,42 @@ #include #include +#ifndef CONFIG_GPIO_LED_INVERTED_TABLE +#define CONFIG_GPIO_LED_INVERTED_TABLE {} +#endif + +static led_id_t gpio_led_inv[] = CONFIG_GPIO_LED_INVERTED_TABLE; + +static int gpio_led_gpio_value(led_id_t mask, int state) +{ + int i, gpio_value = (state == STATUS_LED_ON); + + for (i = 0; i < ARRAY_SIZE(gpio_led_inv); i++) { + if (gpio_led_inv[i] == mask) + gpio_value = !gpio_value; + } + + return gpio_value; +} + void __led_init(led_id_t mask, int state) { + int gpio_value; + if (gpio_request(mask, "gpio_led") != 0) { printf("%s: failed requesting GPIO%lu!\n", __func__, mask); return; } - gpio_direction_output(mask, state == STATUS_LED_ON); + gpio_value = gpio_led_gpio_value(mask, state); + gpio_direction_output(mask, gpio_value); } void __led_set(led_id_t mask, int state) { - gpio_set_value(mask, state == STATUS_LED_ON); + int gpio_value = gpio_led_gpio_value(mask, state); + + gpio_set_value(mask, gpio_value); } void __led_toggle(led_id_t mask) -- cgit v1.2.1 From cfe19f917ab14b88c677def857fb2413d12f9fb7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 14 Nov 2013 10:58:56 +0900 Subject: tools: imls: Remove a broken and unused tool. It looks like tools/imls/Makefile is invoked from nowhere. And also it is broken. Signed-off-by: Masahiro Yamada --- tools/imls/Makefile | 84 ----------------- tools/imls/README | 41 --------- tools/imls/imls.c | 256 ---------------------------------------------------- 3 files changed, 381 deletions(-) delete mode 100644 tools/imls/Makefile delete mode 100644 tools/imls/README delete mode 100644 tools/imls/imls.c diff --git a/tools/imls/Makefile b/tools/imls/Makefile deleted file mode 100644 index b045df2df0..0000000000 --- a/tools/imls/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -# -# (C) Copyright 2009 Marco Stornelli -# -# SPDX-License-Identifier: GPL-2.0+ -# - -include $(TOPDIR)/config.mk - -# Generated executable files -BIN_FILES-y += imls - -# Source files which exist outside the tools/imls directory -EXT_OBJ_FILES-y += lib/crc32.o -EXT_OBJ_FILES-y += lib/md5.o -EXT_OBJ_FILES-y += lib/sha1.o -EXT_OBJ_FILES-y += common/image.o - -# Source files located in the tools/imls directory -OBJ_FILES-y += imls.o - -# Flattened device tree objects -LIBFDT_OBJ_FILES-y += fdt.o -LIBFDT_OBJ_FILES-y += fdt_ro.o -LIBFDT_OBJ_FILES-y += fdt_rw.o -LIBFDT_OBJ_FILES-y += fdt_strerror.o -LIBFDT_OBJ_FILES-y += fdt_wip.o - -# now $(obj) is defined -SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) -BINS := $(addprefix $(obj),$(sort $(BIN_FILES-y))) -LIBFDT_OBJS := $(addprefix $(obj),$(LIBFDT_OBJ_FILES-y)) - -# -# Compile for a hosted environment on the target -# Define __KERNEL_STRICT_NAMES to prevent typedef overlaps -# -HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ - -idirafter $(SRCTREE)/arch/$(ARCH)/include \ - -idirafter $(OBJTREE)/include \ - -I $(SRCTREE)/lib/libfdt \ - -I $(SRCTREE)/tools \ - -DUSE_HOSTCC -D__KERNEL_STRICT_NAMES - -ifeq ($(MTD_VERSION),old) -HOSTCPPFLAGS += -DMTD_OLD -endif - -all: $(BINS) - -$(obj)imls: $(obj)imls.o $(obj)crc32.o $(obj)image.o $(obj)md5.o \ - $(obj)sha1.o $(LIBFDT_OBJS) - $(CC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ - $(STRIP) $@ - -# Some files complain if compiled with -pedantic, use HOSTCFLAGS_NOPED -$(obj)image.o: $(SRCTREE)/common/image.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -$(obj)imls.o: $(SRCTREE)/tools/imls/imls.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -# Some of the tool objects need to be accessed from outside the tools/imls directory -$(obj)%.o: $(SRCTREE)/common/%.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/lib/%.c - $(CC) -g $(HOSTCFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/lib/libfdt/%.c - $(CC) -g $(HOSTCFLAGS_NOPED) -c -o $@ $< - -clean: - rm -rf *.o imls - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/tools/imls/README b/tools/imls/README deleted file mode 100644 index 9adf92305d..0000000000 --- a/tools/imls/README +++ /dev/null @@ -1,41 +0,0 @@ -# -# (C) Copyright 2009 Marco Stornelli -# -# SPDX-License-Identifier: GPL-2.0+ -# - -IMLS -------------- - -imls is an implementation of a Linux command line tool to access -to raw flash partitions and list images made with mkimage command. - -For building against older versions of the MTD headers (meaning before -v2.6.8-rc1) it is required to pass the argument "MTD_VERSION=old" to -make. - -Usage examples --------------- - -1) Flash with sectors of 128KiB and 32 sectors: - -> imls -c 32 -s 131072 /dev/mtd0 -Searching... -Image Name: foo -Created: Fri Apr 10 18:11:30 2009 -Image Type: Intel x86 Linux Standalone Program (uncompressed) -Data Size: 10716 Bytes = 10.46 kB = 0.01 MB -Load Address: 00000000 -Entry Point: 00000000 - -2) Flash with sectors of 64KiB and 128 sectors and with a search offset of one -sector: - -> imls -o 1 -c 128 -s 65536 /dev/mtd0 -Searching... -Image Name: foo -Created: Fri Apr 10 18:11:30 2009 -Image Type: Intel x86 Linux Standalone Program (uncompressed) -Data Size: 10716 Bytes = 10.46 kB = 0.01 MB -Load Address: 00000000 -Entry Point: 00000000 diff --git a/tools/imls/imls.c b/tools/imls/imls.c deleted file mode 100644 index 95043b450b..0000000000 --- a/tools/imls/imls.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * (C) Copyright 2009 Marco Stornelli - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef MTD_OLD -#include -#include -#else -#define __user /* nothing */ -#include -#endif - -#include -#include -#include -#include - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -extern unsigned long crc32(unsigned long crc, const char *buf, unsigned int len); -static void usage(void); -static int image_verify_header(char *ptr, int fd); -static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start); - -char *cmdname; -char *devicefile; - -unsigned int sectorcount = 0; -int sflag = 0; -unsigned int sectoroffset = 0; -unsigned int sectorsize = 0; -int cflag = 0; - -int main (int argc, char **argv) -{ - int fd = -1, err = 0, readbyte = 0, j; - struct mtd_info_user mtdinfo; - char buf[sizeof(image_header_t)]; - int found = 0; - - cmdname = *argv; - - while (--argc > 0 && **++argv == '-') { - while (*++*argv) { - switch (**argv) { - case 'c': - if (--argc <= 0) - usage (); - sectorcount = (unsigned int)atoi(*++argv); - cflag = 1; - goto NXTARG; - case 'o': - if (--argc <= 0) - usage (); - sectoroffset = (unsigned int)atoi(*++argv); - goto NXTARG; - - case 's': - if (--argc <= 0) - usage (); - sectorsize = (unsigned int)atoi(*++argv); - sflag = 1; - goto NXTARG; - default: - usage (); - } - } -NXTARG: ; - } - - if (argc != 1 || cflag == 0 || sflag == 0) - usage(); - - devicefile = *argv; - - fd = open(devicefile, O_RDONLY); - if (fd < 0) { - fprintf (stderr, "%s: Can't open %s: %s\n", - cmdname, devicefile, strerror(errno)); - exit(EXIT_FAILURE); - } - - err = ioctl(fd, MEMGETINFO, &mtdinfo); - if (err < 0) { - fprintf(stderr, "%s: Cannot get MTD information: %s\n",cmdname, - strerror(errno)); - exit(EXIT_FAILURE); - } - - if (mtdinfo.type != MTD_NORFLASH && mtdinfo.type != MTD_NANDFLASH) { - fprintf(stderr, "%s: Unsupported flash type %u\n", - cmdname, mtdinfo.type); - exit(EXIT_FAILURE); - } - - if (sectorsize * sectorcount != mtdinfo.size) { - fprintf(stderr, "%s: Partition size (%d) incompatible with " - "sector size and count\n", cmdname, mtdinfo.size); - exit(EXIT_FAILURE); - } - - if (sectorsize * sectoroffset >= mtdinfo.size) { - fprintf(stderr, "%s: Partition size (%d) incompatible with " - "sector offset given\n", cmdname, mtdinfo.size); - exit(EXIT_FAILURE); - } - - if (sectoroffset > sectorcount - 1) { - fprintf(stderr, "%s: Sector offset cannot be grater than " - "sector count minus one\n", cmdname); - exit(EXIT_FAILURE); - } - - printf("Searching....\n"); - - for (j = sectoroffset; j < sectorcount; ++j) { - - if (lseek(fd, j*sectorsize, SEEK_SET) != j*sectorsize) { - fprintf(stderr, "%s: lseek failure: %s\n", - cmdname, strerror(errno)); - exit(EXIT_FAILURE); - } - - err = flash_bad_block(fd, mtdinfo.type, j*sectorsize); - if (err < 0) - exit(EXIT_FAILURE); - if (err) - continue; /* Skip and jump to next */ - - readbyte = read(fd, buf, sizeof(image_header_t)); - if (readbyte != sizeof(image_header_t)) { - fprintf(stderr, "%s: Can't read from device: %s\n", - cmdname, strerror(errno)); - exit(EXIT_FAILURE); - } - - if (fdt_check_header(buf)) { - /* old-style image */ - if (image_verify_header(buf, fd)) { - found = 1; - image_print_contents((image_header_t *)buf); - } - } else { - /* FIT image */ - fit_print_contents(buf); - } - - } - - close(fd); - - if(!found) - printf("No images found\n"); - - exit(EXIT_SUCCESS); -} - -void usage() -{ - fprintf (stderr, "Usage:\n" - " %s [-o offset] -s size -c count device\n" - " -o ==> number of sectors to use as offset\n" - " -c ==> number of sectors\n" - " -s ==> size of sectors (byte)\n", - cmdname); - - exit(EXIT_FAILURE); -} - -static int image_verify_header(char *ptr, int fd) -{ - int len, nread; - char *data; - uint32_t checksum; - image_header_t *hdr = (image_header_t *)ptr; - char buf[PAGE_SIZE]; - - if (image_get_magic(hdr) != IH_MAGIC) - return 0; - - data = (char *)hdr; - len = image_get_header_size(); - - checksum = image_get_hcrc(hdr); - hdr->ih_hcrc = htonl(0); /* clear for re-calculation */ - - if (crc32(0, data, len) != checksum) { - fprintf(stderr, - "%s: Maybe image found but it has bad header checksum!\n", - cmdname); - return 0; - } - - len = image_get_size(hdr); - checksum = 0; - - while (len > 0) { - nread = read(fd, buf, MIN(len,PAGE_SIZE)); - if (nread != MIN(len,PAGE_SIZE)) { - fprintf(stderr, - "%s: Error while reading: %s\n", - cmdname, strerror(errno)); - exit(EXIT_FAILURE); - } - checksum = crc32(checksum, buf, nread); - len -= nread; - } - - if (checksum != image_get_dcrc(hdr)) { - fprintf (stderr, - "%s: Maybe image found but it has corrupted data!\n", - cmdname); - return 0; - } - - return 1; -} - -/* - * Test for bad block on NAND, just returns 0 on NOR, on NAND: - * 0 - block is good - * > 0 - block is bad - * < 0 - failed to test - */ -static int flash_bad_block(int fd, uint8_t mtd_type, loff_t start) -{ - if (mtd_type == MTD_NANDFLASH) { - int badblock = ioctl(fd, MEMGETBADBLOCK, &start); - - if (badblock < 0) { - fprintf(stderr,"%s: Cannot read bad block mark: %s\n", - cmdname, strerror(errno)); - return badblock; - } - - if (badblock) { - return badblock; - } - } - - return 0; -} -- cgit v1.2.1 From 2e78e75e1f8292baca42a40f0c29978fbe417524 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 14 Nov 2013 11:00:30 +0900 Subject: tools: updater: Remove remainders of dead board tools/updater needs board/MAI/AmigaOneG3SE board for compiling. But AmigaOneG3SE board was already deleted by Commit 953b7e6. Signed-off-by: Masahiro Yamada --- Makefile | 5 +- tools/updater/Makefile | 89 ------- tools/updater/cmd_flash.c | 401 ----------------------------- tools/updater/ctype.c | 40 --- tools/updater/dummy.c | 1 - tools/updater/flash.c | 168 ------------ tools/updater/flash_hw.c | 643 ---------------------------------------------- tools/updater/junk | 1 - tools/updater/ppcstring.S | 213 --------------- tools/updater/string.c | 340 ------------------------ tools/updater/update.c | 63 ----- tools/updater/utils.c | 148 ----------- 12 files changed, 1 insertion(+), 2111 deletions(-) delete mode 100644 tools/updater/Makefile delete mode 100644 tools/updater/cmd_flash.c delete mode 100644 tools/updater/ctype.c delete mode 100644 tools/updater/dummy.c delete mode 100644 tools/updater/flash.c delete mode 100644 tools/updater/flash_hw.c delete mode 100644 tools/updater/junk delete mode 100644 tools/updater/ppcstring.S delete mode 100644 tools/updater/string.c delete mode 100644 tools/updater/update.c delete mode 100644 tools/updater/utils.c diff --git a/Makefile b/Makefile index b8713a4935..2f456e06eb 100644 --- a/Makefile +++ b/Makefile @@ -570,9 +570,6 @@ $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend $(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend $(MAKE) -C spl all CONFIG_TPL_BUILD=y -updater: - $(MAKE) -C tools/updater all - # Explicitly make _depend in subdirs containing multiple targets to prevent # parallel sub-makes creating .depend files simultaneously. depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \ @@ -715,7 +712,7 @@ else # !config.mk all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ $(filter-out tools,$(SUBDIRS)) \ -updater depend dep tags ctags etags cscope $(obj)System.map: +depend dep tags ctags etags cscope $(obj)System.map: @echo "System not configured - see README" >&2 @ exit 1 diff --git a/tools/updater/Makefile b/tools/updater/Makefile deleted file mode 100644 index 19dd5eb6f4..0000000000 --- a/tools/updater/Makefile +++ /dev/null @@ -1,89 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -LOAD_ADDR = 0x40000 - -include $(TOPDIR)/config.mk - -PROG = $(obj)updater -IMAGE = $(obj)updater.image - -COBJS = update.o flash.o flash_hw.o utils.o cmd_flash.o string.o ctype.o dummy.o -COBJS_LINKS = stubs.o -AOBJS = ppcstring.o -AOBJS_LINKS = memio.o - -OBJS := $(addprefix $(obj),$(COBJS) $(COBJS_LINKS) $(AOBJS) $(AOBJS_LINKS)) -SRCS := $(COBJS:.o=.c) $(AOBJS:.o=.S) $(addprefix $(obj), $(COBJS_LINKS:.o:.c) $(AOBJS_LINKS:.o:.S)) - -CPPFLAGS += -I$(TOPDIR) -I$(TOPDIR)/board/MAI/AmigaOneG3SE -CFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE -AFLAGS += -I$(TOPDIR)/board/MAI/AmigaOneG3SE - -DEPS = $(OBJTREE)/u-boot.bin $(OBJTREE)/tools/mkimage -ifneq ($(DEPS),$(wildcard $(DEPS))) -$(error "updater: Missing required objects, please run regular build first") -endif - -all: $(obj).depend $(PROG) $(IMAGE) - -######################################################################### - -$(obj)%.srec: %.o $(LIB) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $< $(LIB) - $(OBJCOPY) -O srec $(<:.o=) $@ - -$(obj)%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< - -$(obj)%.o: %.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)memio.o: $(obj)memio.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)memio.S: - rm -f $(obj)memio.c - ln -s $(SRCTREE)/board/MAI/AmigaOneG3SE/memio.S $(obj)memio.S - -$(obj)stubs.o: $(obj)stubs.c - $(CC) $(CFLAGS) -c -o $@ $< - -$(obj)stubs.c: - rm -f $(obj)stubs.c - ln -s $(SRCTREE)/examples/stubs.c $(obj)stubs.c - -######################################################################### - -$(obj)updater: $(OBJS) - $(LD) -g -Ttext $(LOAD_ADDR) -o $(obj)updater -e _main $(OBJS) - $(OBJCOPY) -O binary $(obj)updater $(obj)updater.bin - -$(obj)updater.image: $(obj)updater $(OBJTREE)/u-boot.bin - cat >/tmp/tempimage $(obj)updater.bin junk $(OBJTREE)/u-boot.bin - $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \ - -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \ - -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image - rm /tmp/tempimage - cp $(obj)updater.image /tftpboot - -(obj)updater.image2: $(obj)updater $(OBJTREE)/u-boot.bin - cat >/tmp/tempimage $(obj)updater.bin junk ../../create_image/image - $(OBJTREE)/tools/mkimage -A ppc -O u-boot -T standalone -C none -a $(LOAD_ADDR) \ - -e `$(NM) $(obj)updater | grep _main | cut --bytes=0-8` \ - -n "Firmware Updater" -d /tmp/tempimage $(obj)updater.image - rm /tmp/tempimage - cp $(obj)updater.image /tftpboot - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/tools/updater/cmd_flash.c b/tools/updater/cmd_flash.c deleted file mode 100644 index 3a604d00d5..0000000000 --- a/tools/updater/cmd_flash.c +++ /dev/null @@ -1,401 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * FLASH support - */ -#include -#include -#include - -#if defined(CONFIG_CMD_FLASH) - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -/* - * The user interface starts numbering for Flash banks with 1 - * for historical reasons. - */ - -/* - * this routine looks for an abbreviated flash range specification. - * the syntax is B:SF[-SL], where B is the bank number, SF is the first - * sector to erase, and SL is the last sector to erase (defaults to SF). - * bank numbers start at 1 to be consistent with other specs, sector numbers - * start at zero. - * - * returns: 1 - correct spec; *pinfo, *psf and *psl are - * set appropriately - * 0 - doesn't look like an abbreviated spec - * -1 - looks like an abbreviated spec, but got - * a parsing error, a number out of range, - * or an invalid flash bank. - */ -static int -abbrev_spec(char *str, flash_info_t **pinfo, int *psf, int *psl) -{ - flash_info_t *fp; - int bank, first, last; - char *p, *ep; - - if ((p = strchr(str, ':')) == NULL) - return 0; - *p++ = '\0'; - - bank = simple_strtoul(str, &ep, 10); - if (ep == str || *ep != '\0' || - bank < 1 || bank > CONFIG_SYS_MAX_FLASH_BANKS || - (fp = &flash_info[bank - 1])->flash_id == FLASH_UNKNOWN) - return -1; - - str = p; - if ((p = strchr(str, '-')) != NULL) - *p++ = '\0'; - - first = simple_strtoul(str, &ep, 10); - if (ep == str || *ep != '\0' || first >= fp->sector_count) - return -1; - - if (p != NULL) { - last = simple_strtoul(p, &ep, 10); - if (ep == p || *ep != '\0' || - last < first || last >= fp->sector_count) - return -1; - } - else - last = first; - - *pinfo = fp; - *psf = first; - *psl = last; - - return 1; -} -int do_flinfo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - ulong bank; - - if (argc == 1) { /* print info for all FLASH banks */ - for (bank=0; bank CONFIG_SYS_MAX_FLASH_BANKS)) { - printf ("Only FLASH Banks # 1 ... # %d supported\n", - CONFIG_SYS_MAX_FLASH_BANKS); - return 1; - } - printf ("\nBank # %ld: ", bank); - flash_print_info (&flash_info[bank-1]); - return 0; -} -int do_flerase(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - flash_info_t *info; - ulong bank, addr_first, addr_last; - int n, sect_first, sect_last; - int rcode = 0; - - if (argc < 2) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "all") == 0) { - for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { - printf ("Erase Flash Bank # %ld ", bank); - info = &flash_info[bank-1]; - rcode = flash_erase (info, 0, info->sector_count-1); - } - return rcode; - } - - if ((n = abbrev_spec(argv[1], &info, §_first, §_last)) != 0) { - if (n < 0) { - printf("Bad sector specification\n"); - return 1; - } - printf ("Erase Flash Sectors %d-%d in Bank # %d ", - sect_first, sect_last, (info-flash_info)+1); - rcode = flash_erase(info, sect_first, sect_last); - return rcode; - } - - if (argc != 3) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "bank") == 0) { - bank = simple_strtoul(argv[2], NULL, 16); - if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) { - printf ("Only FLASH Banks # 1 ... # %d supported\n", - CONFIG_SYS_MAX_FLASH_BANKS); - return 1; - } - printf ("Erase Flash Bank # %ld ", bank); - info = &flash_info[bank-1]; - rcode = flash_erase (info, 0, info->sector_count-1); - return rcode; - } - - addr_first = simple_strtoul(argv[1], NULL, 16); - addr_last = simple_strtoul(argv[2], NULL, 16); - - if (addr_first >= addr_last) - return cmd_usage(cmdtp); - - printf ("Erase Flash from 0x%08lx to 0x%08lx ", addr_first, addr_last); - rcode = flash_sect_erase(addr_first, addr_last); - return rcode; -} - -int flash_sect_erase (ulong addr_first, ulong addr_last) -{ - flash_info_t *info; - ulong bank; - int s_first, s_last; - int erased; - int rcode = 0; - - erased = 0; - - for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) { - ulong b_end; - int sect; - - if (info->flash_id == FLASH_UNKNOWN) { - continue; - } - - b_end = info->start[0] + info->size - 1; /* bank end addr */ - - s_first = -1; /* first sector to erase */ - s_last = -1; /* last sector to erase */ - - for (sect=0; sect < info->sector_count; ++sect) { - ulong end; /* last address in current sect */ - short s_end; - - s_end = info->sector_count - 1; - - end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; - - if (addr_first > end) - continue; - if (addr_last < info->start[sect]) - continue; - - if (addr_first == info->start[sect]) { - s_first = sect; - } - if (addr_last == end) { - s_last = sect; - } - } - if (s_first>=0 && s_first<=s_last) { - erased += s_last - s_first + 1; - rcode = flash_erase (info, s_first, s_last); - } - } - if (erased) { - /* printf ("Erased %d sectors\n", erased); */ - } else { - printf ("Error: start and/or end address" - " not on sector boundary\n"); - rcode = 1; - } - return rcode; -} - - -int do_protect(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) -{ - flash_info_t *info; - ulong bank, addr_first, addr_last; - int i, p, n, sect_first, sect_last; - int rcode = 0; - - if (argc < 3) - return cmd_usage(cmdtp); - - if (strcmp(argv[1], "off") == 0) - p = 0; - else if (strcmp(argv[1], "on") == 0) - p = 1; - else - return cmd_usage(cmdtp); - - if (strcmp(argv[2], "all") == 0) { - for (bank=1; bank<=CONFIG_SYS_MAX_FLASH_BANKS; ++bank) { - info = &flash_info[bank-1]; - if (info->flash_id == FLASH_UNKNOWN) { - continue; - } - /*printf ("%sProtect Flash Bank # %ld\n", */ - /* p ? "" : "Un-", bank); */ - - for (i=0; isector_count; ++i) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - } - -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) puts (" done\n"); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - return rcode; - } - - if ((n = abbrev_spec(argv[2], &info, §_first, §_last)) != 0) { - if (n < 0) { - printf("Bad sector specification\n"); - return 1; - } - /*printf("%sProtect Flash Sectors %d-%d in Bank # %d\n", */ - /* p ? "" : "Un-", sect_first, sect_last, */ - /* (info-flash_info)+1); */ - for (i = sect_first; i <= sect_last; i++) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) puts (" done\n"); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - return rcode; - } - - if (argc != 4) - return cmd_usage(cmdtp); - - if (strcmp(argv[2], "bank") == 0) { - bank = simple_strtoul(argv[3], NULL, 16); - if ((bank < 1) || (bank > CONFIG_SYS_MAX_FLASH_BANKS)) { - printf ("Only FLASH Banks # 1 ... # %d supported\n", - CONFIG_SYS_MAX_FLASH_BANKS); - return 1; - } - printf ("%sProtect Flash Bank # %ld\n", - p ? "" : "Un-", bank); - info = &flash_info[bank-1]; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return 1; - } - for (i=0; isector_count; ++i) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) - puts(" done\n"); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - return rcode; - } - - addr_first = simple_strtoul(argv[2], NULL, 16); - addr_last = simple_strtoul(argv[3], NULL, 16); - - if (addr_first >= addr_last) - return cmd_usage(cmdtp); - - return flash_sect_protect (p, addr_first, addr_last); -} -int flash_sect_protect (int p, ulong addr_first, ulong addr_last) -{ - flash_info_t *info; - ulong bank; - int s_first, s_last; - int protected, i; - int rcode = 0; - - protected = 0; - - for (bank=0,info = &flash_info[0]; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank, ++info) { - ulong b_end; - int sect; - - if (info->flash_id == FLASH_UNKNOWN) { - continue; - } - - b_end = info->start[0] + info->size - 1; /* bank end addr */ - - s_first = -1; /* first sector to erase */ - s_last = -1; /* last sector to erase */ - - for (sect=0; sect < info->sector_count; ++sect) { - ulong end; /* last address in current sect */ - short s_end; - - s_end = info->sector_count - 1; - - end = (sect == s_end) ? b_end : info->start[sect + 1] - 1; - - if (addr_first > end) - continue; - if (addr_last < info->start[sect]) - continue; - - if (addr_first == info->start[sect]) { - s_first = sect; - } - if (addr_last == end) { - s_last = sect; - } - } - if (s_first>=0 && s_first<=s_last) { - protected += s_last - s_first + 1; - for (i=s_first; i<=s_last; ++i) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (flash_real_protect(info, i, p)) - rcode = 1; - putc ('.'); -#else - info->protect[i] = p; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - } -#if defined(CONFIG_SYS_FLASH_PROTECTION) - if (!rcode) putc ('\n'); -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - - } - if (protected) { - /* printf ("%sProtected %d sectors\n", */ - /* p ? "" : "Un-", protected); */ - } else { - printf ("Error: start and/or end address" - " not on sector boundary\n"); - rcode = 1; - } - return rcode; -} - -#endif diff --git a/tools/updater/ctype.c b/tools/updater/ctype.c deleted file mode 100644 index 96fa9ed114..0000000000 --- a/tools/updater/ctype.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * linux/lib/ctype.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - */ - -#include - -unsigned char _ctype[] = { -_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ -_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ -_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ -_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ -_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ -_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ -_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ -_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ -_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ -_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ -_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ -_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ -0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ -_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ -_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ -_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ -_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ -_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ -_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ diff --git a/tools/updater/dummy.c b/tools/updater/dummy.c deleted file mode 100644 index 9fe5ac1b1e..0000000000 --- a/tools/updater/dummy.c +++ /dev/null @@ -1 +0,0 @@ -volatile int __dummy = 0xDEADBEEF; diff --git a/tools/updater/flash.c b/tools/updater/flash.c deleted file mode 100644 index 5388872074..0000000000 --- a/tools/updater/flash.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -extern flash_info_t flash_info[]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ - -/*----------------------------------------------------------------------- - * Set protection status for monitor sectors - * - * The monitor is always located in the _first_ Flash bank. - * If necessary you have to map the second bank at lower addresses. - */ -void -flash_protect (int flag, ulong from, ulong to, flash_info_t *info) -{ - ulong b_end = info->start[0] + info->size - 1; /* bank end address */ - short s_end = info->sector_count - 1; /* index of last sector */ - int i; - - /* Do nothing if input data is bad. */ - if (info->sector_count == 0 || info->size == 0 || to < from) { - return; - } - - /* There is nothing to do if we have no data about the flash - * or the protect range and flash range don't overlap. - */ - if (info->flash_id == FLASH_UNKNOWN || - to < info->start[0] || from > b_end) { - return; - } - - for (i=0; isector_count; ++i) { - ulong end; /* last address in current sect */ - - end = (i == s_end) ? b_end : info->start[i + 1] - 1; - - /* Update protection if any part of the sector - * is in the specified range. - */ - if (from <= end && to >= info->start[i]) { - if (flag & FLAG_PROTECT_CLEAR) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - flash_real_protect(info, i, 0); -#else - info->protect[i] = 0; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - else if (flag & FLAG_PROTECT_SET) { -#if defined(CONFIG_SYS_FLASH_PROTECTION) - flash_real_protect(info, i, 1); -#else - info->protect[i] = 1; -#endif /* CONFIG_SYS_FLASH_PROTECTION */ - } - } - } -} - -/*----------------------------------------------------------------------- - */ - -flash_info_t * -addr2info (ulong addr) -{ -#ifndef CONFIG_SPD823TS - flash_info_t *info; - int i; - - for (i=0, info = &flash_info[0]; iflash_id != FLASH_UNKNOWN && - addr >= info->start[0] && - /* WARNING - The '- 1' is needed if the flash - * is at the end of the address space, since - * info->start[0] + info->size wraps back to 0. - * Please don't change this unless you understand this. - */ - addr <= info->start[0] + info->size - 1) { - return (info); - } - } -#endif /* CONFIG_SPD823TS */ - - return (NULL); -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - * Make sure all target addresses are within Flash bounds, - * and no protected sectors are hit. - * Returns: - * ERR_OK 0 - OK - * ERR_TIMOUT 1 - write timeout - * ERR_NOT_ERASED 2 - Flash not erased - * ERR_PROTECTED 4 - target range includes protected sectors - * ERR_INVAL 8 - target address not in Flash memory - * ERR_ALIGN 16 - target address not aligned on boundary - * (only some targets require alignment) - */ -int -flash_write (char *src, ulong addr, ulong cnt) -{ -#ifdef CONFIG_SPD823TS - return (ERR_TIMOUT); /* any other error codes are possible as well */ -#else - int i; - ulong end = addr + cnt - 1; - flash_info_t *info_first = addr2info (addr); - flash_info_t *info_last = addr2info (end ); - flash_info_t *info; - int j; - - if (cnt == 0) { - return (ERR_OK); - } - - if (!info_first || !info_last) { - return (ERR_INVAL); - } - - for (info = info_first; info <= info_last; ++info) { - ulong b_end = info->start[0] + info->size; /* bank end addr */ - short s_end = info->sector_count - 1; - for (i=0; isector_count; ++i) { - ulong e_addr = (i == s_end) ? b_end : info->start[i + 1]; - - if ((end >= info->start[i]) && (addr < e_addr) && - (info->protect[i] != 0) ) { - return (ERR_PROTECTED); - } - } - } - - printf("\rWriting "); - for (j=0; j<20; j++) putc(177); - printf("\rWriting "); - - /* finally write data to flash */ - for (info = info_first; info <= info_last && cnt>0; ++info) { - ulong len; - - len = info->start[0] + info->size - addr; - if (len > cnt) - len = cnt; - - if ((i = write_buff(info, src, addr, len)) != 0) { - return (i); - } - cnt -= len; - addr += len; - src += len; - } - return (ERR_OK); -#endif /* CONFIG_SPD823TS */ -} - -/*----------------------------------------------------------------------- - */ diff --git a/tools/updater/flash_hw.c b/tools/updater/flash_hw.c deleted file mode 100644 index 54a910b178..0000000000 --- a/tools/updater/flash_hw.c +++ /dev/null @@ -1,643 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber , Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[]; - -static ulong flash_get_size (ulong addr, flash_info_t *info); -static int flash_get_offsets (ulong base, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (ulong addr); - -int flash_xd_nest; - -static void flash_to_xd(void) -{ - unsigned char x; - - flash_xd_nest ++; - - if (flash_xd_nest == 1) - { - DEBUGF("Flash on XD\n"); - x = pci_read_cfg_byte(0, 0, 0x74); - pci_write_cfg_byte(0, 0, 0x74, x|1); - } -} - -static void flash_to_mem(void) -{ - unsigned char x; - - flash_xd_nest --; - - if (flash_xd_nest == 0) - { - DEBUGF("Flash on memory bus\n"); - x = pci_read_cfg_byte(0, 0, 0x74); - pci_write_cfg_byte(0, 0, 0x74, x&0xFE); - } -} - -unsigned long flash_init_old(void) -{ - int i; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) - { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = 0; - flash_info[i].size = 0; - } - - - return 1; -} - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long flash_size = 0; - - flash_xd_nest = 0; - - flash_to_xd(); - - /* Init: no FLASHes known */ - for (i=0; i= CONFIG_SYS_FLASH_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - } else { - printf ("Warning: the BOOT Flash is not initialised !"); - } - - flash_to_mem(); - - return flash_size; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (ulong addr, flash_info_t *info) -{ - short i; - uchar value; - uchar *x = (uchar *)addr; - - flash_to_xd(); - - /* Write auto select command: read Manufacturer ID */ - x[0x0555] = 0xAA; - __asm__ volatile ("sync\n eieio"); - x[0x02AA] = 0x55; - __asm__ volatile ("sync\n eieio"); - x[0x0555] = 0x90; - __asm__ volatile ("sync\n eieio"); - - value = x[0]; - __asm__ volatile ("sync\n eieio"); - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); - - switch (value | (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - flash_reset (addr); - return 0; - } - - value = x[1]; - __asm__ volatile ("sync\n eieio"); - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); - - switch (value) { - case AMD_ID_F040B: - DEBUGF("Am29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV040B: - DEBUGF("Am29LV040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV400T: - DEBUGF("Am29LV400T\n"); - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - DEBUGF("Am29LV800T\n"); - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - DEBUGF("Am29LV160T\n"); - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - DEBUGF("Am29LV160B\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - DEBUGF("Am29LV320T\n"); - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 - /* Has the same ID as AMD_ID_LV320T, to be fixed */ - case AMD_ID_LV320B: - DEBUGF("Am29LV320B\n"); - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case AMD_ID_LV033C: - DEBUGF("Am29LV033C\n"); - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - - case STM_ID_F040B: - DEBUGF("M29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - flash_to_mem(); - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - if (! flash_get_offsets (addr, info)) { - flash_reset (addr); - flash_to_mem(); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - value = in8(info->start[i] + 2); - iobarrier_rw(); - info->protect[i] = (value & 1) != 0; - } - - /* - * Reset bank to read mode - */ - flash_reset (addr); - - flash_to_mem(); - - return (info->size); -} - -static int flash_get_offsets (ulong base, flash_info_t *info) -{ - unsigned int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * info->size / - info->sector_count; - } - break; - default: - return 0; - } - - return 1; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile ulong addr = info->start[0]; - int flag, prot, sect, l_sect; - ulong start, now, last; - - flash_to_xd(); - - if (s_first < 0 || s_first > s_last) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - flash_to_mem(); - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - flash_to_mem(); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf (""); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x80); - iobarrier_rw(); - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = info->start[sect]; - out8(addr, 0x30); - iobarrier_rw(); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = info->start[l_sect]; - - DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT); - - while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - flash_reset (info->start[0]); - flash_to_mem(); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - iobarrier_rw(); - } - -DONE: - /* reset to read mode */ - flash_reset (info->start[0]); - flash_to_mem(); - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - ulong out_cnt = 0; - - flash_to_xd(); - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - flash_to_mem(); - return (rc); - } - wp += 4; - } - - putc(219); - - /* - * handle word aligned part - */ - while (cnt >= 4) { - if (out_cnt>26214) - { - putc(219); - out_cnt = 0; - } - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - flash_to_mem(); - return (rc); - } - wp += 4; - cnt -= 4; - out_cnt += 4; - } - - if (cnt == 0) { - flash_to_mem(); - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - flash_to_mem(); - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile ulong addr = info->start[0]; - ulong start; - int i; - - flash_to_xd(); - - /* Check if Flash is (sufficiently) erased */ - if ((in32(dest) & data) != data) { - flash_to_mem(); - return (2); - } - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - int flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0xA0); - iobarrier_rw(); - out8(dest+i, data_ch[i]); - iobarrier_rw(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flash_reset (addr); - flash_to_mem(); - return (1); - } - iobarrier_rw(); - } - } - - flash_reset (addr); - flash_to_mem(); - return (0); -} - -/* - * Reset bank to read mode - */ -static void flash_reset (ulong addr) -{ - flash_to_xd(); - out8(addr, 0xF0); /* reset bank */ - iobarrier_rw(); - flash_to_mem(); -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_STM: printf ("SGS THOMSON "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size % 0x100000 == 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size / 0x100000, info->sector_count); - } else if (info->size % 0x400 == 0) { - printf (" Size: %ld KB in %d Sectors\n", - info->size / 0x400, info->sector_count); - } else { - printf (" Size: %ld B in %d Sectors\n", - info->size, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} diff --git a/tools/updater/junk b/tools/updater/junk deleted file mode 100644 index f73285a832..0000000000 --- a/tools/updater/junk +++ /dev/null @@ -1 +0,0 @@ -................................................................................................................................................................................................................................................................ \ No newline at end of file diff --git a/tools/updater/ppcstring.S b/tools/updater/ppcstring.S deleted file mode 100644 index 8152ac9b0f..0000000000 --- a/tools/updater/ppcstring.S +++ /dev/null @@ -1,213 +0,0 @@ -/* - * String handling functions for PowerPC. - * - * Copyright (C) 1996 Paul Mackerras. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include - - .globl strcpy -strcpy: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - - .globl strncpy -strncpy: - cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r6) - bdnzf 2,1b /* dec ctr, branch if ctr != 0 && !cr0.eq */ - blr - - .globl strcat -strcat: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r0,1(r5) - cmpwi 0,r0,0 - bne 1b - addi r5,r5,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - stbu r0,1(r5) - bne 1b - blr - - .globl strcmp -strcmp: - addi r5,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r5) - cmpwi 1,r3,0 - lbzu r0,1(r4) - subf. r3,r0,r3 - beqlr 1 - beq 1b - blr - - .globl strlen -strlen: - addi r4,r3,-1 -1: lbzu r0,1(r4) - cmpwi 0,r0,0 - bne 1b - subf r3,r3,r4 - blr - - .globl memset -memset: - rlwimi r4,r4,8,16,23 - rlwimi r4,r4,16,0,15 - addi r6,r3,-4 - cmplwi 0,r5,4 - blt 7f - stwu r4,4(r6) - beqlr - andi. r0,r6,3 - add r5,r0,r5 - subf r6,r0,r6 - rlwinm r0,r5,32-2,2,31 - mtctr r0 - bdz 6f -1: stwu r4,4(r6) - bdnz 1b -6: andi. r5,r5,3 -7: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r6,r6,3 -8: stbu r4,1(r6) - bdnz 8b - blr - - .globl bcopy -bcopy: - mr r6,r3 - mr r3,r4 - mr r4,r6 - b memcpy - - .globl memmove -memmove: - cmplw 0,r3,r4 - bgt backwards_memcpy - /* fall through */ - - .globl memcpy -memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - addi r6,r3,-4 - addi r4,r4,-4 - beq 2f /* if less than 8 bytes to do */ - andi. r0,r6,3 /* get dest word aligned */ - mtctr r7 - bne 5f -1: lwz r7,4(r4) - lwzu r8,8(r4) - stw r7,4(r6) - stwu r8,8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,4(r4) - addi r5,r5,-4 - stwu r0,4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 - addi r4,r4,3 - addi r6,r6,3 -4: lbzu r0,1(r4) - stbu r0,1(r6) - bdnz 4b - blr -5: subfic r0,r0,4 - mtctr r0 -6: lbz r7,4(r4) - addi r4,r4,1 - stb r7,4(r6) - addi r6,r6,1 - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl backwards_memcpy -backwards_memcpy: - rlwinm. r7,r5,32-3,3,31 /* r0 = r5 >> 3 */ - add r6,r3,r5 - add r4,r4,r5 - beq 2f - andi. r0,r6,3 - mtctr r7 - bne 5f -1: lwz r7,-4(r4) - lwzu r8,-8(r4) - stw r7,-4(r6) - stwu r8,-8(r6) - bdnz 1b - andi. r5,r5,7 -2: cmplwi 0,r5,4 - blt 3f - lwzu r0,-4(r4) - subi r5,r5,4 - stwu r0,-4(r6) -3: cmpwi 0,r5,0 - beqlr - mtctr r5 -4: lbzu r0,-1(r4) - stbu r0,-1(r6) - bdnz 4b - blr -5: mtctr r0 -6: lbzu r7,-1(r4) - stbu r7,-1(r6) - bdnz 6b - subf r5,r0,r5 - rlwinm. r7,r5,32-3,3,31 - beq 2b - mtctr r7 - b 1b - - .globl memcmp -memcmp: - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r6,r3,-1 - addi r4,r4,-1 -1: lbzu r3,1(r6) - lbzu r0,1(r4) - subf. r3,r0,r3 - bdnzt 2,1b - blr -2: li r3,0 - blr - - .global memchr -memchr: - cmpwi 0,r5,0 - ble- 2f - mtctr r5 - addi r3,r3,-1 -1: lbzu r0,1(r3) - cmpw 0,r0,r4 - bdnzf 2,1b - beqlr -2: li r3,0 - blr diff --git a/tools/updater/string.c b/tools/updater/string.c deleted file mode 100644 index 954fb01e20..0000000000 --- a/tools/updater/string.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * linux/lib/string.c - * - * Copyright (C) 1991, 1992 Linus Torvalds - */ - -/* - * stupid library routines.. The optimized versions should generally be found - * as inline code in - * - * These are buggy as well.. - */ - -#include -#include -#include - -#define __HAVE_ARCH_BCOPY -#define __HAVE_ARCH_MEMCMP -#define __HAVE_ARCH_MEMCPY -#define __HAVE_ARCH_MEMMOVE -#define __HAVE_ARCH_MEMSET -#define __HAVE_ARCH_STRCAT -#define __HAVE_ARCH_STRCMP -#define __HAVE_ARCH_STRCPY -#define __HAVE_ARCH_STRLEN -#define __HAVE_ARCH_STRNCPY - -char * ___strtok = NULL; - -#ifndef __HAVE_ARCH_STRCPY -char * strcpy(char * dest,const char *src) -{ - char *tmp = dest; - - while ((*dest++ = *src++) != '\0') - /* nothing */; - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRNCPY -char * strncpy(char * dest,const char *src,size_t count) -{ - char *tmp = dest; - - while (count-- && (*dest++ = *src++) != '\0') - /* nothing */; - - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRCAT -char * strcat(char * dest, const char * src) -{ - char *tmp = dest; - - while (*dest) - dest++; - while ((*dest++ = *src++) != '\0') - ; - - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRNCAT -char * strncat(char *dest, const char *src, size_t count) -{ - char *tmp = dest; - - if (count) { - while (*dest) - dest++; - while ((*dest++ = *src++)) { - if (--count == 0) { - *dest = '\0'; - break; - } - } - } - - return tmp; -} -#endif - -#ifndef __HAVE_ARCH_STRCMP -int strcmp(const char * cs,const char * ct) -{ - register signed char __res; - - while (1) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - } - - return __res; -} -#endif - -#ifndef __HAVE_ARCH_STRNCMP -int strncmp(const char * cs,const char * ct,size_t count) -{ - register signed char __res = 0; - - while (count) { - if ((__res = *cs - *ct++) != 0 || !*cs++) - break; - count--; - } - - return __res; -} -#endif - -#ifndef __HAVE_ARCH_STRCHR -char * strchr(const char * s, int c) -{ - for(; *s != (char) c; ++s) - if (*s == '\0') - return NULL; - return (char *) s; -} -#endif - -#ifndef __HAVE_ARCH_STRRCHR -char * strrchr(const char * s, int c) -{ - const char *p = s + strlen(s); - do { - if (*p == (char)c) - return (char *)p; - } while (--p >= s); - return NULL; -} -#endif - -#ifndef __HAVE_ARCH_STRLEN -size_t strlen(const char * s) -{ - const char *sc; - - for (sc = s; *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} -#endif - -#ifndef __HAVE_ARCH_STRNLEN -size_t strnlen(const char * s, size_t count) -{ - const char *sc; - - for (sc = s; count-- && *sc != '\0'; ++sc) - /* nothing */; - return sc - s; -} -#endif - -#ifndef __HAVE_ARCH_STRDUP -char * strdup(const char *s) -{ - char *new; - - if ((s == NULL) || - ((new = malloc (strlen(s) + 1)) == NULL) ) { - return NULL; - } - - strcpy (new, s); - return new; -} -#endif - -#ifndef __HAVE_ARCH_STRSPN -size_t strspn(const char *s, const char *accept) -{ - const char *p; - const char *a; - size_t count = 0; - - for (p = s; *p != '\0'; ++p) { - for (a = accept; *a != '\0'; ++a) { - if (*p == *a) - break; - } - if (*a == '\0') - return count; - ++count; - } - - return count; -} -#endif - -#ifndef __HAVE_ARCH_STRPBRK -char * strpbrk(const char * cs,const char * ct) -{ - const char *sc1,*sc2; - - for( sc1 = cs; *sc1 != '\0'; ++sc1) { - for( sc2 = ct; *sc2 != '\0'; ++sc2) { - if (*sc1 == *sc2) - return (char *) sc1; - } - } - return NULL; -} -#endif - -#ifndef __HAVE_ARCH_STRTOK -char * strtok(char * s,const char * ct) -{ - char *sbegin, *send; - - sbegin = s ? s : ___strtok; - if (!sbegin) { - return NULL; - } - sbegin += strspn(sbegin,ct); - if (*sbegin == '\0') { - ___strtok = NULL; - return( NULL ); - } - send = strpbrk( sbegin, ct); - if (send && *send != '\0') - *send++ = '\0'; - ___strtok = send; - return (sbegin); -} -#endif - -#ifndef __HAVE_ARCH_MEMSET -void * memset(void * s,char c,size_t count) -{ - char *xs = (char *) s; - - while (count--) - *xs++ = c; - - return s; -} -#endif - -#ifndef __HAVE_ARCH_BCOPY -char * bcopy(const char * src, char * dest, int count) -{ - char *tmp = dest; - - while (count--) - *tmp++ = *src++; - - return dest; -} -#endif - -#ifndef __HAVE_ARCH_MEMCPY -void * memcpy(void * dest,const void *src,size_t count) -{ - char *tmp = (char *) dest, *s = (char *) src; - - while (count--) - *tmp++ = *s++; - - return dest; -} -#endif - -#ifndef __HAVE_ARCH_MEMMOVE -void * memmove(void * dest,const void *src,size_t count) -{ - char *tmp, *s; - - if (dest <= src) { - tmp = (char *) dest; - s = (char *) src; - while (count--) - *tmp++ = *s++; - } - else { - tmp = (char *) dest + count; - s = (char *) src + count; - while (count--) - *--tmp = *--s; - } - - return dest; -} -#endif - -#ifndef __HAVE_ARCH_MEMCMP -int memcmp(const void * cs,const void * ct,size_t count) -{ - const unsigned char *su1, *su2; - signed char res = 0; - - for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) - if ((res = *su1 - *su2) != 0) - break; - return res; -} -#endif - -/* - * find the first occurrence of byte 'c', or 1 past the area if none - */ -#ifndef __HAVE_ARCH_MEMSCAN -void * memscan(void * addr, int c, size_t size) -{ - unsigned char * p = (unsigned char *) addr; - - while (size) { - if (*p == c) - return (void *) p; - p++; - size--; - } - return (void *) p; -} -#endif - -#ifndef __HAVE_ARCH_STRSTR -char * strstr(const char * s1,const char * s2) -{ - int l1, l2; - - l2 = strlen(s2); - if (!l2) - return (char *) s1; - l1 = strlen(s1); - while (l1 >= l2) { - l1--; - if (!memcmp(s1,s2,l2)) - return (char *) s1; - s1++; - } - return NULL; -} -#endif diff --git a/tools/updater/update.c b/tools/updater/update.c deleted file mode 100644 index 18f122ad23..0000000000 --- a/tools/updater/update.c +++ /dev/null @@ -1,63 +0,0 @@ -#include -#include - -extern unsigned long __dummy; -void do_reset (void); -void do_updater(void); - -void _main(void) -{ - int i; - printf("U-Boot Firmware Updater\n\n\n"); - printf("****************************************************\n" - "* ATTENTION!! PLEASE READ THIS NOTICE CAREFULLY! *\n" - "****************************************************\n\n" - "This program will update your computer's firmware.\n" - "Do NOT remove the disk, reset the machine, or do\n" - "anything that might disrupt functionality. If this\n"); - printf("Program fails, your computer might be unusable, and\n" - "you will need to return your board for reflashing.\n" - "If you find this too risky, remove the diskette and\n" - "switch off your machine now. Otherwise press the \n" - "SPACE key now to start the process\n\n"); - do - { - char x; - while (!tstc()); - x = getc(); - if (x == ' ') break; - } while (1); - - do_updater(); - - i = 5; - - printf("\nUpdate done. Please remove diskette.\n"); - printf("The machine will automatically reset in %d seconds\n", i); - printf("You can switch off/reset now when the floppy is removed\n\n"); - - while (i) - { - printf("Resetting in %d\r", i); - udelay(1000000); - i--; - } - do_reset(); - while (1); -} - -void do_updater(void) -{ - unsigned long *addr = &__dummy + 65; - unsigned long flash_size = flash_init(); - int rc; - - flash_sect_protect(0, 0xFFF00000, 0xFFF7FFFF); - printf("Erasing "); - flash_sect_erase(0xFFF00000, 0xFFF7FFFF); - printf("Writing "); - rc = flash_write((uchar *)addr, 0xFFF00000, 0x7FFFF); - if (rc != 0) printf("\nFlashing failed due to error %d\n", rc); - else printf("\ndone\n"); - flash_sect_protect(1, 0xFFF00000, 0xFFF7FFFF); -} diff --git a/tools/updater/utils.c b/tools/updater/utils.c deleted file mode 100644 index 61a611876c..0000000000 --- a/tools/updater/utils.c +++ /dev/null @@ -1,148 +0,0 @@ -#include -#include -#include -#include - -static __inline__ unsigned long -get_msr(void) -{ - unsigned long msr; - - asm volatile("mfmsr %0" : "=r" (msr) :); - return msr; -} - -static __inline__ void -set_msr(unsigned long msr) -{ - asm volatile("mtmsr %0" : : "r" (msr)); -} - -static __inline__ unsigned long -get_dec(void) -{ - unsigned long val; - - asm volatile("mfdec %0" : "=r" (val) :); - return val; -} - - -static __inline__ void -set_dec(unsigned long val) -{ - asm volatile("mtdec %0" : : "r" (val)); -} - - -void -enable_interrupts(void) -{ - set_msr (get_msr() | MSR_EE); -} - -/* returns flag if MSR_EE was set before */ -int -disable_interrupts(void) -{ - ulong msr; - - msr = get_msr(); - set_msr (msr & ~MSR_EE); - return ((msr & MSR_EE) != 0); -} - -u8 in8(u32 port) -{ - return in_byte(port); -} - -void out8(u32 port, u8 val) -{ - out_byte(port, val); -} - -unsigned long in32(u32 port) -{ - return in_long(port); -} - -unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) -{ - unsigned long result = 0,value; - - if (*cp == '0') { - cp++; - if ((*cp == 'x') && isxdigit(cp[1])) { - base = 16; - cp++; - } - if (!base) { - base = 8; - } - } - if (!base) { - base = 10; - } - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) - ? toupper(*cp) : *cp)-'A'+10) < base) { - result = result*base + value; - cp++; - } - if (endp) - *endp = (char *)cp; - return result; -} - -long simple_strtol(const char *cp,char **endp,unsigned int base) -{ - if(*cp=='-') - return -simple_strtoul(cp+1,endp,base); - return simple_strtoul(cp,endp,base); -} - -static inline void -soft_restart(unsigned long addr) -{ - /* SRR0 has system reset vector, SRR1 has default MSR value */ - /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */ - - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); - __asm__ __volatile__ ("mtspr 27, 4"); - __asm__ __volatile__ ("rfi"); - - while(1); /* not reached */ -} - -void -do_reset (void) -{ - ulong addr; - /* flush and disable I/D cache */ - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 4"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - __asm__ __volatile__ ("mtspr 1008, 5"); - __asm__ __volatile__ ("isync"); - __asm__ __volatile__ ("sync"); - -#ifdef CONFIG_SYS_RESET_ADDRESS - addr = CONFIG_SYS_RESET_ADDRESS; -#else - /* - * note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, - * CONFIG_SYS_MONITOR_BASE - sizeof (ulong) is usually a valid - * address. Better pick an address known to be invalid on your - * system and assign it to CONFIG_SYS_RESET_ADDRESS. - */ - addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong); -#endif - soft_restart(addr); - while(1); /* not reached */ -} -- cgit v1.2.1 From 1500389c2fc09ea59e76c4a7f315815a09c6bfec Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 09:44:54 +0900 Subject: board: h2200: Delete an unnecessary make rule We have a generic rule to generate .o file from *.S in $(TOPDIR)/config.mk. Signed-off-by: Masahiro Yamada --- board/h2200/Makefile | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/h2200/Makefile b/board/h2200/Makefile index b654a96e0b..d4fa15344c 100644 --- a/board/h2200/Makefile +++ b/board/h2200/Makefile @@ -10,8 +10,5 @@ obj-y := h2200.o extra-y := h2200-header.bin -$(obj)h2200-header.o: h2200-header.S - $(CC) $(CFLAGS) -c -o $@ $< - $(obj)h2200-header.bin: $(obj)h2200-header.o $(OBJCOPY) -O binary $< $@ -- cgit v1.2.1 From 0e53691529a2961e066a1cdfff1ead13a928c829 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 10:25:41 +0900 Subject: post: remove unnecessary include path settings Signed-off-by: Masahiro Yamada --- post/board/lwmon/Makefile | 2 -- post/board/lwmon5/Makefile | 2 -- post/board/netta/Makefile | 2 -- post/board/pdm360ng/Makefile | 2 -- post/cpu/mpc83xx/Makefile | 2 -- post/cpu/mpc8xx/Makefile | 2 -- post/cpu/ppc4xx/Makefile | 2 -- post/drivers/Makefile | 2 -- post/lib_powerpc/Makefile | 2 -- post/lib_powerpc/fpu/Makefile | 2 -- 10 files changed, 20 deletions(-) diff --git a/post/board/lwmon/Makefile b/post/board/lwmon/Makefile index 1ac7aa511d..b23debcabe 100644 --- a/post/board/lwmon/Makefile +++ b/post/board/lwmon/Makefile @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += sysmon.o diff --git a/post/board/lwmon5/Makefile b/post/board/lwmon5/Makefile index d8b195289e..a50ce67cde 100644 --- a/post/board/lwmon5/Makefile +++ b/post/board/lwmon5/Makefile @@ -5,6 +5,4 @@ # # SPDX-License-Identifier: GPL-2.0+ -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += sysmon.o watchdog.o dspic.o fpga.o dsp.o gdc.o diff --git a/post/board/netta/Makefile b/post/board/netta/Makefile index cd27a5ce34..5c37f497cc 100644 --- a/post/board/netta/Makefile +++ b/post/board/netta/Makefile @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += codec.o dsp.o diff --git a/post/board/pdm360ng/Makefile b/post/board/pdm360ng/Makefile index 3f748892a7..b43b77b2d3 100644 --- a/post/board/pdm360ng/Makefile +++ b/post/board/pdm360ng/Makefile @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += coproc_com.o diff --git a/post/cpu/mpc83xx/Makefile b/post/cpu/mpc83xx/Makefile index 0643d01a7b..4b3c50e6af 100644 --- a/post/cpu/mpc83xx/Makefile +++ b/post/cpu/mpc83xx/Makefile @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += ecc.o diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile index 7a2930a797..f8bb6c9343 100644 --- a/post/cpu/mpc8xx/Makefile +++ b/post/cpu/mpc8xx/Makefile @@ -5,7 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += cache_8xx.o obj-$(CONFIG_HAS_POST) += cache.o ether.o spr.o uart.o usb.o watchdog.o diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile index b7435c8252..ed3e8e87fd 100644 --- a/post/cpu/ppc4xx/Makefile +++ b/post/cpu/ppc4xx/Makefile @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += cache_4xx.o obj-$(CONFIG_HAS_POST) += cache.o obj-$(CONFIG_HAS_POST) += denali_ecc.o diff --git a/post/drivers/Makefile b/post/drivers/Makefile index 2f6844cca4..328f880b1d 100644 --- a/post/drivers/Makefile +++ b/post/drivers/Makefile @@ -5,6 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += flash.o i2c.o memory.o rtc.o diff --git a/post/lib_powerpc/Makefile b/post/lib_powerpc/Makefile index f19fea3e5f..d2b8a940df 100644 --- a/post/lib_powerpc/Makefile +++ b/post/lib_powerpc/Makefile @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += asm.o obj-$(CONFIG_HAS_POST) += cpu.o cmp.o cmpi.o two.o twox.o three.o threex.o obj-$(CONFIG_HAS_POST) += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o diff --git a/post/lib_powerpc/fpu/Makefile b/post/lib_powerpc/fpu/Makefile index 6aec96c023..ee01a313f1 100644 --- a/post/lib_powerpc/fpu/Makefile +++ b/post/lib_powerpc/fpu/Makefile @@ -5,8 +5,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CPPFLAGS += -I$(TOPDIR) - obj-$(CONFIG_HAS_POST) += 20001122-1.o obj-$(CONFIG_HAS_POST) += 20010114-2.o obj-$(CONFIG_HAS_POST) += 20010226-1.o -- cgit v1.2.1 From 72b97e4bc9116279a64bc8ca4661a92c7eb4b9c2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 10:34:36 +0900 Subject: spieval: Remove remainders of dead board Commit 69434e4c deleted spieval board support but it missed to clean up include/configs/spieval.h file. Signed-off-by: Masahiro Yamada --- include/configs/spieval.h | 494 ---------------------------------------------- 1 file changed, 494 deletions(-) delete mode 100644 include/configs/spieval.h diff --git a/include/configs/spieval.h b/include/configs/spieval.h deleted file mode 100644 index 07668de4d9..0000000000 --- a/include/configs/spieval.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - * (C) Copyright 2003-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ -#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#ifdef CONFIG_STK52XX -#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ -#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ -#define CONFIG_BOARD_EARLY_INIT_R -#endif /* CONFIG_STK52XX */ - -/* - * PCI Mapping: - * 0x40000000 - 0x4fffffff - PCI Memory - * 0x50000000 - 0x50ffffff - PCI IO Space - */ -#ifdef CONFIG_STK52XX -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 -/* #define CONFIG_PCI_SCAN_SHOW 1 */ - -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x50000000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x01000000 - -#define CONFIG_EEPRO100 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_NS8382X 1 -#endif /* CONFIG_STK52XX */ - -/* - * Video console - */ -#if 1 -#define CONFIG_VIDEO -#define CONFIG_VIDEO_SM501 -#define CONFIG_VIDEO_SM501_32BPP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_LOGO -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_CONSOLE_EXTRA_INFO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#endif - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* USB */ -#ifdef CONFIG_STK52XX -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE -#endif - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - -#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) - #define CONFIG_CMD_IDE - #define CONFIG_CMD_FAT - #define CONFIG_CMD_EXT2 -#endif - -#ifdef CONFIG_STK52XX - #define CONFIG_CMD_USB - #define CONFIG_CMD_FAT -#endif - -#ifdef CONFIG_VIDEO - #define CONFIG_CMD_BMP -#endif - -#ifdef CONFIG_PCI - #define CONFIG_CMD_PCI - #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 -#endif - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * HW-Monitor configuration on Mini-FAP - */ -#if defined (CONFIG_MINIFAP) -#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C -#endif - -/* List of I2C addresses to be verified by POST */ -#if defined (CONFIG_MINIFAP) -#undef CONFIG_SYS_POST_I2C_ADDRS -#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ - CONFIG_SYS_I2C_HWMON_ADDR, \ - CONFIG_SYS_I2C_SLAVE} -#endif - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_LAST_STAGE_INIT - -/* - * SRAM - Do not map below 2 GB in address space, because this area is used - * for SDRAM autosizing. - */ -#define CONFIG_SYS_CS2_START 0xE5000000 -#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ -#define CONFIG_SYS_CS2_CFG 0x0004D930 - -/* - * Grafic controller - Do not map below 2 GB in address space, because this - * area is used for SDRAM autosizing. - */ -#define SM501_FB_BASE 0xE0000000 -#define CONFIG_SYS_CS1_START (SM501_FB_BASE) -#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ -#define CONFIG_SYS_CS1_CFG 0x8F48FF70 -#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -/*----------------------------------------------------------------------- - * USB stuff - *----------------------------------------------------------------------- - */ -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 - -/*----------------------------------------------------------------------- - * IDE/ATA stuff Supports IDE harddisk - *----------------------------------------------------------------------- - */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_IDE_RESET /* reset for ide supported */ -#define CONFIG_IDE_PREINIT - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#endif /* __CONFIG_H */ -- cgit v1.2.1 From dbfb4cb52f3d08a299de7dfc6c18467867b60f5c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 10:39:39 +0900 Subject: board: tqm5200: delete its own object make rule Signed-off-by: Masahiro Yamada --- board/tqc/tqm5200/Makefile | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile index 757f4729ab..80c1eba87c 100644 --- a/board/tqc/tqm5200/Makefile +++ b/board/tqc/tqm5200/Makefile @@ -6,6 +6,3 @@ # obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o - -$(obj)cam5200_flash.o: cam5200_flash.c - $(CC) $(CFLAGS) -c -o $@ $< -- cgit v1.2.1 From fdb87049d861d92093b382622c9e528405c727f9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 11:06:00 +0900 Subject: examples: delete unnecessary CPPFLAGS Signed-off-by: Masahiro Yamada --- examples/api/Makefile | 2 -- examples/standalone/Makefile | 2 -- 2 files changed, 4 deletions(-) diff --git a/examples/api/Makefile b/examples/api/Makefile index 33cc91ba71..1cefbe777d 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -46,8 +46,6 @@ OBJS += $(addprefix $(obj),$(COBJ_FILES-y)) OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y))) OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y))) -CPPFLAGS += -I.. - all: $(obj).depend $(OUTPUT) ######################################################################### diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 93469217ef..f4f102b3e1 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -52,8 +52,6 @@ SREC := $(addprefix $(obj),$(SREC)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) -CPPFLAGS += -I.. - # For PowerPC there's no need to compile standalone applications as a # relocatable executable. The relocation data is not needed, and # also causes the entry point of the standalone application to be -- cgit v1.2.1 From 8a7e7d5697a8b14ec02731d003bed89b1c54dfb7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 11:08:35 +0900 Subject: Makefile: descend into subdirectories only when CONFIG_API is defined All objects under api/ and examples/api/ directories are selected by CONFIG_API. So we can move CONFIG_API switch to the top Makefile. In order to use CONFIG_API, the definition of SUBDIR_EXAMPLES-y must be moved after "sinlude $(obj)include/autoconf.mk". Signed-off-by: Masahiro Yamada --- Makefile | 11 ++++++----- api/Makefile | 5 +++-- examples/api/Makefile | 27 ++++++++++++--------------- 3 files changed, 21 insertions(+), 22 deletions(-) diff --git a/Makefile b/Makefile index 2f456e06eb..ed2864cbeb 100644 --- a/Makefile +++ b/Makefile @@ -136,7 +136,6 @@ unexport CDPATH # The "examples" conditionally depend on U-Boot (say, when USE_PRIVATE_LIBGCC # is "yes"), so compile examples after U-Boot is compiled. SUBDIR_TOOLS = tools -SUBDIR_EXAMPLES = examples/standalone examples/api SUBDIRS = $(SUBDIR_TOOLS) .PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE) @@ -150,8 +149,10 @@ all: sinclude $(obj)include/autoconf.mk.dep sinclude $(obj)include/autoconf.mk +SUBDIR_EXAMPLES-y := examples/standalone +SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api ifndef CONFIG_SANDBOX -SUBDIRS += $(SUBDIR_EXAMPLES) +SUBDIRS += $(SUBDIR_EXAMPLES-y) endif # load ARCH, BOARD, and CPU configuration @@ -277,7 +278,7 @@ LIBS-y += drivers/usb/phy/ LIBS-y += drivers/usb/ulpi/ LIBS-y += common/ LIBS-y += lib/libfdt/ -LIBS-y += api/ +LIBS-$(CONFIG_API) += api/ LIBS-y += post/ LIBS-y += test/ @@ -362,7 +363,7 @@ endif build := -f $(TOPDIR)/scripts/Makefile.build -C -all: $(ALL-y) $(SUBDIR_EXAMPLES) +all: $(ALL-y) $(SUBDIR_EXAMPLES-y) $(obj)u-boot.dtb: checkdtc $(obj)u-boot $(MAKE) $(build) dts binary @@ -550,7 +551,7 @@ $(LIBS): depend $(SUBDIR_TOOLS) $(SUBDIRS): depend $(MAKE) -C $@ all -$(SUBDIR_EXAMPLES): $(obj)u-boot +$(SUBDIR_EXAMPLES-y): $(obj)u-boot $(LDSCRIPT): depend $(MAKE) -C $(dir $@) $(notdir $@) diff --git a/api/Makefile b/api/Makefile index fb130ffe8b..0f85a0b098 100644 --- a/api/Makefile +++ b/api/Makefile @@ -4,5 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_API) += api.o api_display.o api_net.o api_storage.o \ - api_platform-$(ARCH).o +obj-y += api.o api_display.o api_net.o api_storage.o +obj-$(CONFIG_ARM) += api_platform-arm.o +obj-$(CONFIG_PPC) += api_platform-powerpc.c diff --git a/examples/api/Makefile b/examples/api/Makefile index 1cefbe777d..cad10a3ecb 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -14,25 +14,22 @@ endif include $(TOPDIR)/config.mk # Resulting ELF and binary exectuables will be named demo and demo.bin -OUTPUT-$(CONFIG_API) = $(obj)demo -OUTPUT = $(OUTPUT-y) +OUTPUT = $(obj)demo # Source files located in the examples/api directory -SOBJ_FILES-$(CONFIG_API) += crt0.o -COBJ_FILES-$(CONFIG_API) += demo.o -COBJ_FILES-$(CONFIG_API) += glue.o -COBJ_FILES-$(CONFIG_API) += libgenwrap.o +SOBJ_FILES-y += crt0.o +COBJ_FILES-y += demo.o +COBJ_FILES-y += glue.o +COBJ_FILES-y += libgenwrap.o # Source files which exist outside the examples/api directory -EXT_COBJ_FILES-$(CONFIG_API) += lib/crc32.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/ctype.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/div64.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o -EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o -ifeq ($(ARCH),powerpc) -EXT_SOBJ_FILES-$(CONFIG_API) += arch/powerpc/lib/ppcstring.o -endif +EXT_COBJ_FILES-y += lib/crc32.o +EXT_COBJ_FILES-y += lib/ctype.o +EXT_COBJ_FILES-y += lib/div64.o +EXT_COBJ_FILES-y += lib/string.o +EXT_COBJ_FILES-y += lib/time.o +EXT_COBJ_FILES-y += lib/vsprintf.o +EXT_SOBJ_FILES-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o # Create a list of source files so their dependencies can be auto-generated SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c)) -- cgit v1.2.1 From fdc36977b33e2e801866ef3279e98bd12bc07b4d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 11:17:30 +0900 Subject: Makefile: move some libraries to lib/Makefile Signed-off-by: Masahiro Yamada --- Makefile | 5 ----- lib/Makefile | 7 +++++++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index ed2864cbeb..52133a5434 100644 --- a/Makefile +++ b/Makefile @@ -231,11 +231,6 @@ OBJS := $(addprefix $(obj),$(OBJS)) HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n) LIBS-y += lib/ -LIBS-$(CONFIG_RSA) += lib/rsa/ -LIBS-$(CONFIG_LZMA) += lib/lzma/ -LIBS-$(CONFIG_LZO) += lib/lzo/ -LIBS-$(CONFIG_ZLIB) += lib/zlib/ -LIBS-$(CONFIG_TIZEN) += lib/tizen/ LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ LIBS-y += $(CPUDIR)/ ifdef SOC diff --git a/lib/Makefile b/lib/Makefile index 4e3b500f5a..e787f77be8 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -6,6 +6,13 @@ # ifndef CONFIG_SPL_BUILD + +obj-$(CONFIG_RSA) += rsa/ +obj-$(CONFIG_LZMA) += lzma/ +obj-$(CONFIG_LZO) += lzo/ +obj-$(CONFIG_ZLIB) += zlib/ +obj-$(CONFIG_TIZEN) += tizen/ + obj-$(CONFIG_AES) += aes.o obj-$(CONFIG_BZIP2) += bzlib.o obj-$(CONFIG_BZIP2) += bzlib_crctable.o -- cgit v1.2.1 From 3c6dc17eaec13ddc622306a8ddd24b547be91aee Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 11:18:57 +0900 Subject: drivers: delete unnecessary HOSTCFLAGS HOSTCFLAGS is meaningless because no host programs are compiled there. Signed-off-by: Masahiro Yamada --- drivers/bios_emulator/Makefile | 1 - drivers/net/npe/Makefile | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 6f74fdc230..38fc48d1b1 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -12,5 +12,4 @@ EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ -D__PPC__ -D__BIG_ENDIAN__ CFLAGS += $(EXTRA_CFLAGS) -HOSTCFLAGS += $(EXTRA_CFLAGS) CPPFLAGS += $(EXTRA_CFLAGS) diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile index e36c0bbd69..0779255216 100644 --- a/drivers/net/npe/Makefile +++ b/drivers/net/npe/Makefile @@ -8,7 +8,6 @@ LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux CFLAGS += $(LOCAL_CFLAGS) CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend -HOSTCFLAGS += $(LOCAL_CFLAGS) obj-y := npe.o \ miiphy.o \ -- cgit v1.2.1 From 017ce20f46e38df5c7d795c1b5f042f00a614d2b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 18 Nov 2013 16:24:58 +0900 Subject: common: Delete unnecessary rules. The directory tools/ is always built before common/. So when envcrc tool is necessary in common/Makefile, it already exists. Signed-off-by: Masahiro Yamada --- common/Makefile | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/common/Makefile b/common/Makefile index 32acbf9357..74404beb36 100644 --- a/common/Makefile +++ b/common/Makefile @@ -232,14 +232,11 @@ obj-y += stdio.o CPPFLAGS += -I.. -$(obj)env_embedded.o: $(src)env_embedded.c $(obj)../tools/envcrc +$(obj)env_embedded.o: $(src)env_embedded.c $(CC) $(AFLAGS) -Wa,--no-warn \ -DENV_CRC=$(shell $(obj)../tools/envcrc) \ -c -o $@ $(src)env_embedded.c -$(obj)../tools/envcrc: - $(MAKE) -C ../tools - # SEE README.arm-unaligned-accesses $(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) $(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) -- cgit v1.2.1 From ad420282e211cb5156691df0bcc7d9946bf4553c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 20 Nov 2013 12:45:56 +0900 Subject: Makefile: descend into subdirectories only when CONFIG_API is defined All objects under api/ and examples/api/ directories are selected by CONFIG_API. So we can move CONFIG_API switch to the top Makefile. In order to use CONFIG_API, the definition of SUBDIR_EXAMPLES-y must be moved after "sinlude $(obj)include/autoconf.mk". Signed-off-by: Masahiro Yamada --- api/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/api/Makefile b/api/Makefile index 0f85a0b098..3c095eedb6 100644 --- a/api/Makefile +++ b/api/Makefile @@ -6,4 +6,4 @@ obj-y += api.o api_display.o api_net.o api_storage.o obj-$(CONFIG_ARM) += api_platform-arm.o -obj-$(CONFIG_PPC) += api_platform-powerpc.c +obj-$(CONFIG_PPC) += api_platform-powerpc.o -- cgit v1.2.1 From 5310b8b2a894a8e7fa76bf59e50ec0935603b0ca Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 20 Nov 2013 18:11:57 +0900 Subject: nand_spl: trivial refactoring of makefiles Signed-off-by: Masahiro Yamada --- nand_spl/board/amcc/acadia/Makefile | 45 ++++++++++---------- nand_spl/board/amcc/bamboo/Makefile | 35 +++++++--------- nand_spl/board/amcc/canyonlands/Makefile | 35 +++++++--------- nand_spl/board/amcc/kilauea/Makefile | 39 ++++++++--------- nand_spl/board/amcc/sequoia/Makefile | 39 ++++++++--------- nand_spl/board/freescale/mpc8315erdb/Makefile | 26 +++++------- nand_spl/board/freescale/mpc8536ds/Makefile | 60 +++++++++++++-------------- nand_spl/board/freescale/mpc8569mds/Makefile | 60 +++++++++++++-------------- nand_spl/board/freescale/mpc8572ds/Makefile | 60 +++++++++++++-------------- nand_spl/board/freescale/p1023rds/Makefile | 60 +++++++++++++-------------- nand_spl/board/freescale/p1_p2_rdb/Makefile | 60 +++++++++++++-------------- nand_spl/board/sheldon/simpc8313/Makefile | 7 +--- 12 files changed, 242 insertions(+), 284 deletions(-) diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 20459c92e2..022a20555f 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -24,11 +24,9 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ $(nandobj)System.map -all: $(obj).depend $(ALL) - $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -37,13 +35,12 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)System.map: $(nandobj)u-boot-spl @$(NM) $< | \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ - sort > $(nandobj)System.map + sort > $@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ @@ -52,43 +49,43 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)cache.S: - @rm -f $(obj)cache.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@ $(obj)gpio.c: - @rm -f $(obj)gpio.c - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $(obj)gpio.c + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@ $(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ $(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory $(obj)memory.c: - @rm -f $(obj)memory.c - ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c + @rm -f $@ + ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@ $(obj)pll.c: - @rm -f $(obj)pll.c - ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c + @rm -f $@ + ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@ # from nand_spl directory $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory $(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ ######################################################################### diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index ca3dab4f25..d413a480ad 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -24,9 +24,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -36,8 +34,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ @@ -46,36 +43,36 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ $(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory $(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S + @rm -f $@ + ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@ # from nand_spl directory $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory $(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)sdram.c: - @rm -f $(obj)sdram.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $@ endif ######################################################################### diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile index f50d84b8c9..b2ef03f78b 100644 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -29,9 +29,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -41,8 +39,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ @@ -51,36 +48,36 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ $(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory $(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S + @rm -f $@ + ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@ # from nand_spl directory $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory $(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)ddr2_fixed.c: - @rm -f $(obj)ddr2_fixed.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $(obj)ddr2_fixed.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $@ endif ######################################################################### diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 8b4206f57b..5899b9efe8 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -24,9 +24,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -36,8 +34,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ @@ -46,38 +43,38 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)44x_spd_ddr2.c: $(obj)ecc.h - @rm -f $(obj)44x_spd_ddr2.c - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@ $(obj)cache.S: - @rm -f $(obj)cache.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@ $(obj)ecc.h: - @rm -f $(obj)ecc.h - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $(obj)ecc.h + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@ $(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ $(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from nand_spl directory $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/nand directory $(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ ######################################################################### diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile index 0fcf030d43..fea6c4e489 100644 --- a/nand_spl/board/amcc/sequoia/Makefile +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -24,9 +24,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -36,8 +34,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ @@ -46,41 +43,41 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # from cpu directory $(obj)denali_data_eye.c: - @rm -f $(obj)denali_data_eye.c - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@ $(obj)ndfc.c: - @rm -f $(obj)ndfc.c - ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ $(obj)start.S: - @rm -f $(obj)start.S - ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S + @rm -f $@ + ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory $(obj)init.S: - @rm -f $(obj)init.S - ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S + @rm -f $@ + ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@ $(obj)sdram.c: - @rm -f $(obj)sdram.c + @rm -f $@ @rm -f $(obj)sdram.h - ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c + ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@ ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h # from nand_spl directory $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory $(obj)nand_ecc.c: - @rm -f $(obj)nand_ecc.c - ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c + @rm -f $@ + ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ ######################################################################### diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile index 5b11d1067e..c49a6e0b8f 100644 --- a/nand_spl/board/freescale/mpc8315erdb/Makefile +++ b/nand_spl/board/freescale/mpc8315erdb/Makefile @@ -28,9 +28,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -40,8 +38,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ @@ -49,32 +46,31 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)start.S: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $(obj)start.S + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@ $(obj)nand_boot_fsl_elbc.c: - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ $(obj)sdram.c: - ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $(obj)sdram.c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@ $(obj)$(BOARD).c: - ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $(obj)$(BOARD).c + ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@ $(obj)ns16550.c: - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ $(obj)spl_minimal.c: - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $(obj)spl_minimal.c + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ $(obj)cache.c: - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ $(obj)time.c: - ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c + ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $@ $(obj)ticks.S: - ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S + ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $@ ######################################################################### diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index d3dac2074c..62330815cc 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -30,9 +30,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -42,8 +40,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ @@ -52,58 +49,57 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ $(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ $(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ $(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ $(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ $(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c + @rm -f $@ + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ $(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + @rm -f $@ + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ $(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ $(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ $(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ $(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ endif ######################################################################### diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index d3dac2074c..62330815cc 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -30,9 +30,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -42,8 +40,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ @@ -52,58 +49,57 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ $(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ $(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ $(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ $(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ $(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c + @rm -f $@ + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ $(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + @rm -f $@ + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ $(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ $(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ $(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ $(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ endif ######################################################################### diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index d3dac2074c..62330815cc 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -30,9 +30,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -42,8 +40,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ @@ -52,58 +49,57 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ $(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ $(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ $(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ $(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ $(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c + @rm -f $@ + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ $(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + @rm -f $@ + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ $(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ $(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ $(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ $(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ endif ######################################################################### diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index e89d4054ab..dbdfa19895 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -25,9 +25,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -37,8 +35,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ @@ -47,58 +44,57 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ $(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c + @rm -f $@ + ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $@ $(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c + @rm -f $@ + ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $@ $(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ $(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ $(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c + @rm -f $@ + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ $(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + @rm -f $@ + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ $(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S + @rm -f $@ + ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $@ $(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S + @rm -f $@ + ln -sf $(SRCTREE)/$(CPUDIR)/start.S $@ $(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c + @rm -f $@ + ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $@ $(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ endif ######################################################################### diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index d3dac2074c..62330815cc 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -30,9 +30,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -42,8 +40,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ @@ -52,58 +49,57 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files $(obj)cache.c: - @rm -f $(obj)cache.c - ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ $(obj)cpu_init_early.c: - @rm -f $(obj)cpu_init_early.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ $(obj)spl_minimal.c: - @rm -f $(obj)spl_minimal.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $(obj)spl_minimal.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ $(obj)fsl_law.c: - @rm -f $(obj)fsl_law.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ $(obj)law.c: - @rm -f $(obj)law.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ $(obj)nand_boot_fsl_elbc.c: - @rm -f $(obj)nand_boot_fsl_elbc.c - ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \ - $(obj)nand_boot_fsl_elbc.c + @rm -f $@ + ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ $(obj)ns16550.c: - @rm -f $(obj)ns16550.c - ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c + @rm -f $@ + ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ $(obj)resetvec.S: - @rm -f $(obj)resetvec.S - ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S + @rm -f $@ + ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ $(obj)fixed_ivor.S: - @rm -f $(obj)fixed_ivor.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ $(obj)start.S: $(obj)fixed_ivor.S - @rm -f $(obj)start.S - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ $(obj)tlb.c: - @rm -f $(obj)tlb.c - ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c + @rm -f $@ + ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ $(obj)tlb_table.c: - @rm -f $(obj)tlb_table.c - ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c + @rm -f $@ + ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ ifneq ($(OBJTREE), $(SRCTREE)) $(obj)nand_boot.c: - @rm -f $(obj)nand_boot.c - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c + @rm -f $@ + ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ endif ######################################################################### diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile index 08739edc4e..90f132c34c 100644 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -28,9 +28,7 @@ OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) +all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ @@ -40,8 +38,7 @@ $(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl + -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ -- cgit v1.2.1 From f6bab6710c5502325a5c2423f09789ca201b33a7 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 20 Nov 2013 18:14:23 +0900 Subject: bios_emulator: delete an unnecessary include path -I$(TOPDIR)/include is defined in the top config.mk. Signed-off-by: Masahiro Yamada --- drivers/bios_emulator/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 38fc48d1b1..52a2ceb475 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -8,7 +8,7 @@ obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \ +EXTRA_CFLAGS += -I. -I./include \ -D__PPC__ -D__BIG_ENDIAN__ CFLAGS += $(EXTRA_CFLAGS) -- cgit v1.2.1 From 4d1584bd0df86044a17daf3812b4a3b48913d970 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 21 Nov 2013 19:06:58 +0900 Subject: MAKEALL: add -b (--board) option Some board have multiple configurations. For example, the board "m54455evb" has many configurations: M54455EVB, M54455EVB_a66, M54455EVB_i66, M54455EVB_intel, ... When we modify board-related files, we need to test all configurations based on such a board. In such a case, the new option -b is useful. Signed-off-by: Masahiro Yamada --- MAKEALL | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/MAKEALL b/MAKEALL index 80cd4f83e9..a74f0fcead 100755 --- a/MAKEALL +++ b/MAKEALL @@ -18,6 +18,7 @@ usage() -c CPU, --cpu CPU Build all boards with cpu CPU -v VENDOR, --vendor VENDOR Build all boards with vendor VENDOR -s SOC, --soc SOC Build all boards with soc SOC + -b BOARD, --board BOARD Build all boards with board name BOARD -l, --list List all targets to be built -m, --maintainers List all targets and maintainer email -M, --mails List all targets and all affilated emails @@ -59,8 +60,8 @@ usage() exit ${ret} } -SHORT_OPTS="ha:c:v:s:lmMCnr" -LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check,continue,rebuild-errors" +SHORT_OPTS="ha:c:v:s:b:lmMCnr" +LONG_OPTS="help,arch:,cpu:,vendor:,soc:,board:,list,maintainers,mails,check,continue,rebuild-errors" # Option processing based on util-linux-2.13/getopt-parse.bash @@ -121,6 +122,17 @@ while true ; do fi SELECTED='y' shift 2 ;; + -b|--board) + # echo "Option BOARD: argument \`$2'" + if [ "$opt_b" ] ; then + opt_b="${opt_b%)} || \$6 == \"$2\" || \$7 == \"$2\")" + else + # We need to check the 7th field too + # for boards whose 6th field is "-" + opt_b="(\$6 == \"$2\" || \$7 == \"$2\")" + fi + SELECTED='y' + shift 2 ;; -C|--check) CHECK='C=1' shift ;; @@ -158,6 +170,7 @@ FILTER="\$1 !~ /^#/" [ "$opt_c" ] && FILTER="${FILTER} && $opt_c" [ "$opt_s" ] && FILTER="${FILTER} && $opt_s" [ "$opt_v" ] && FILTER="${FILTER} && $opt_v" +[ "$opt_b" ] && FILTER="${FILTER} && $opt_b" if [ "$SELECTED" ] ; then SELECTED=$(awk '('"$FILTER"') { print $7 }' boards.cfg) -- cgit v1.2.1 From a5750b805828f471469d6ad31e052e83a564de2e Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 19 Nov 2013 08:01:44 +0100 Subject: blackfin: don't use 'bool' when it causes problems The use of 'bool' data types in globally used header files cases build errors like this: In file included from arch/blackfin/include/asm/blackfin.h:13:0, from include/common.h:92, from cmd_test.c:17: arch/blackfin/include/asm/blackfin_local.h:54:1: error: unknown type name 'bool' Use plain 'int' instead to avoid such kind of trouble. Signed-off-by: Wolfgang Denk --- arch/blackfin/cpu/os_log.c | 6 +++--- arch/blackfin/include/asm/blackfin_local.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/blackfin/cpu/os_log.c b/arch/blackfin/cpu/os_log.c index e1c8e2948d..2092d9e3b6 100644 --- a/arch/blackfin/cpu/os_log.c +++ b/arch/blackfin/cpu/os_log.c @@ -12,12 +12,12 @@ #define OS_LOG_MAGIC_ADDR ((unsigned long *)0x4f0) #define OS_LOG_PTR_ADDR ((char **)0x4f4) -bool bfin_os_log_check(void) +int bfin_os_log_check(void) { if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC) - return false; + return 0; *OS_LOG_MAGIC_ADDR = 0; - return true; + return 1; } void bfin_os_log_dump(void) diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index ab31dcb815..8ea8cde691 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -51,7 +51,7 @@ extern u_long get_dclk(void); # define bfin_revid() (bfin_read_CHIPID() >> 28) -extern bool bfin_os_log_check(void); +extern int bfin_os_log_check(void); extern void bfin_os_log_dump(void); extern void blackfin_icache_flush_range(const void *, const void *); -- cgit v1.2.1 From e8a8bab52c98950a4befa24526e8ffeb1b3f1c31 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 18 Nov 2013 08:31:56 -0500 Subject: sparc: Correct arch/sparc/cpu/leon3/start.S from SPDX conversion The SPDX tag conversion ate part of this file, put things back to the way they should be. Signed-off-by: Tom Rini --- arch/sparc/cpu/leon3/start.S | 66 +++++++++++++++++++++++++------------------- 1 file changed, 37 insertions(+), 29 deletions(-) diff --git a/arch/sparc/cpu/leon3/start.S b/arch/sparc/cpu/leon3/start.S index bbc1b3476c..cf897f6877 100644 --- a/arch/sparc/cpu/leon3/start.S +++ b/arch/sparc/cpu/leon3/start.S @@ -1,33 +1,41 @@ -#include - -TRAP ta 0; nop; nop; nop; - -/* Software trap. Treat as BAD_TRAP for the time being... */ -#define SOFT_TRAP TRAP(_hwerr) - -#define PSR_INIT 0x1FC0 /* Disable traps, set s and ps */ -#define WIM_INIT 2 - -/* All traps low-level code here must end with this macro. */ -#define RESTORE_ALL b ret_trap_entry; clr %l6; - -#define WRITE_PAUSE nop;nop;nop - -WINDOWSIZE = (16 * 4) -ARGPUSHSIZE = (6 * 4) -ARGPUSH = (WINDOWSIZE + 4) -MINFRAME = (WINDOWSIZE + ARGPUSHSIZE + 4) - -/* Number of register windows */ -#ifndef CONFIG_SYS_SPARC_NWINDOWS -#error Must define number of SPARC register windows, default is 8 -#endif - -#define STACK_ALIGN 8 -#define SA(X) (((X)+(STACK_ALIGN-1)) & ~(STACK_ALIGN-1)) +/* This is where the SPARC/LEON3 starts + * Copyright (C) 2007, + * Daniel Hellstrom, daniel@gaisler.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ - .section ".start", "ax" - .globl _starttate */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* Entry for traps which jump to a programmer-specified trap handler. */ +#define TRAPR(H) \ + wr %g0, 0xfe0, %psr; \ + mov %g0, %tbr; \ + ba (H); \ + mov %g0, %wim; + +#define TRAP(H) \ + mov %psr, %l0; \ + ba (H); \ + nop; nop; + +#define TRAPI(ilevel) \ + mov ilevel, %l7; \ + mov %psr, %l0; \ + b _irq_entry; \ + mov %wim, %l3 + +/* Unexcpected trap will halt the processor by forcing it to error state */ #undef BAD_TRAP #define BAD_TRAP ta 0; nop; nop; nop; -- cgit v1.2.1 From 15d89961a0b9b4554e479125c007ed206390b446 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Fri, 25 Oct 2013 15:26:27 +0530 Subject: powerpc/t1040qds: Correct Maintainer name in boards.cfg Update T1040QDS naem to Poonam Aggrwal. Signed-off-by: Priyanka Jain --- boards.cfg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards.cfg b/boards.cfg index e742746281..d9b0a9af50 100644 --- a/boards.cfg +++ b/boards.cfg @@ -962,7 +962,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - -Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Naveen Burmi +Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach -- cgit v1.2.1 From f40fcfd9111878ba9dbe6cc6b726687bf2adf414 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Thu, 17 Oct 2013 10:47:33 +0800 Subject: mpc85xx: Fix the offset of register address error The offset of register address within GPIO module is just CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080, P5020, P5040, T4240, B4860. Signed-off-by: Tang Yuantian --- arch/powerpc/include/asm/mpc85xx_gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index 3d1188467c..87bb4a092b 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -20,7 +20,7 @@ static inline void mpc85xx_gpio_set(unsigned int mask, unsigned int dir, unsigned int val) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* First mask off the unwanted parts of "dir" and "val" */ dir &= mask; @@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios) static inline unsigned int mpc85xx_gpio_get(unsigned int mask) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); /* Read the requested values */ return in_be32(&gpio->gpdat) & mask; -- cgit v1.2.1 From ac6880782d8f369b7121488e8407ae6ddcf2b9ff Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Thu, 26 Sep 2013 09:10:32 +0800 Subject: p1010rdb: enable mtdparts for NAND The default partition table matches the .dts files for these boards in Linux. This allows these partitions to be used by name with U-Boot's "nand" command. Signed-off-by: Zhao Qiang --- include/configs/P1010RDB.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c1cfbd40b6..50c365a5b1 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -313,6 +313,13 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITION +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=ff800000.flash" +#define MTDPARTS_DEFAULT \ + "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" + #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ -- cgit v1.2.1 From 5614e71b4956c579cd4419b958b33fa6316eaa92 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 30 Sep 2013 09:22:09 -0700 Subject: Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun --- Makefile | 1 + README | 41 +- arch/powerpc/cpu/mpc83xx/Makefile | 6 +- arch/powerpc/cpu/mpc83xx/ecc.c | 4 +- arch/powerpc/cpu/mpc85xx/Makefile | 45 - arch/powerpc/cpu/mpc85xx/cpu.c | 16 +- arch/powerpc/cpu/mpc85xx/ddr-gen1.c | 89 - arch/powerpc/cpu/mpc85xx/ddr-gen2.c | 95 - arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 464 ----- arch/powerpc/cpu/mpc85xx/mp.c | 2 +- arch/powerpc/cpu/mpc86xx/Makefile | 3 - arch/powerpc/cpu/mpc86xx/ddr-8641.c | 85 - arch/powerpc/cpu/mpc8xxx/Makefile | 6 - arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 29 - .../powerpc/cpu/mpc8xxx/ddr/common_timing_params.h | 57 - arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 1656 ----------------- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 105 -- arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c | 343 ---- arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c | 342 ---- arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 341 ---- arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 1870 ------------------- .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 526 ------ arch/powerpc/cpu/mpc8xxx/ddr/main.c | 718 -------- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 1147 ------------ arch/powerpc/cpu/mpc8xxx/ddr/util.c | 264 --- arch/powerpc/include/asm/config.h | 6 + arch/powerpc/include/asm/config_mpc85xx.h | 13 + arch/powerpc/include/asm/config_mpc86xx.h | 2 + arch/powerpc/include/asm/fsl_ddr_dimm_params.h | 101 -- arch/powerpc/include/asm/fsl_ddr_sdram.h | 377 ---- arch/powerpc/include/asm/immap_83xx.h | 6 +- arch/powerpc/include/asm/immap_85xx.h | 6 +- arch/powerpc/include/asm/immap_86xx.h | 4 +- board/exmeritus/hww1u1a/ddr.c | 4 +- board/exmeritus/hww1u1a/hww1u1a.c | 4 +- board/freescale/b4860qds/ddr.c | 6 +- board/freescale/bsc9131rdb/ddr.c | 4 +- board/freescale/bsc9131rdb/spl_minimal.c | 4 +- board/freescale/bsc9132qds/bsc9132qds.c | 4 +- board/freescale/bsc9132qds/ddr.c | 4 +- board/freescale/bsc9132qds/spl_minimal.c | 4 +- board/freescale/c29xpcie/ddr.c | 4 +- board/freescale/corenet_ds/ddr.c | 4 +- board/freescale/corenet_ds/eth_p4080.c | 2 +- board/freescale/corenet_ds/p3041ds_ddr.c | 2 +- board/freescale/corenet_ds/p4080ds_ddr.c | 2 +- board/freescale/corenet_ds/p5020ds_ddr.c | 2 +- board/freescale/corenet_ds/p5040ds_ddr.c | 2 +- board/freescale/mpc8349emds/Makefile | 2 +- board/freescale/mpc8349emds/ddr.c | 4 +- board/freescale/mpc8349emds/mpc8349emds.c | 6 +- board/freescale/mpc8536ds/ddr.c | 4 +- board/freescale/mpc8536ds/mpc8536ds.c | 2 +- board/freescale/mpc8540ads/ddr.c | 4 +- board/freescale/mpc8540ads/mpc8540ads.c | 4 +- board/freescale/mpc8541cds/ddr.c | 4 +- board/freescale/mpc8541cds/mpc8541cds.c | 2 +- board/freescale/mpc8544ds/ddr.c | 4 +- board/freescale/mpc8544ds/mpc8544ds.c | 2 +- board/freescale/mpc8548cds/ddr.c | 4 +- board/freescale/mpc8548cds/mpc8548cds.c | 2 +- board/freescale/mpc8555cds/ddr.c | 4 +- board/freescale/mpc8555cds/mpc8555cds.c | 2 +- board/freescale/mpc8560ads/ddr.c | 4 +- board/freescale/mpc8560ads/mpc8560ads.c | 4 +- board/freescale/mpc8568mds/ddr.c | 4 +- board/freescale/mpc8568mds/mpc8568mds.c | 2 +- board/freescale/mpc8569mds/ddr.c | 4 +- board/freescale/mpc8569mds/mpc8569mds.c | 4 +- board/freescale/mpc8572ds/ddr.c | 4 +- board/freescale/mpc8572ds/mpc8572ds.c | 2 +- board/freescale/mpc8610hpcd/Makefile | 2 +- board/freescale/mpc8610hpcd/ddr.c | 4 +- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +- board/freescale/mpc8641hpcn/Makefile | 2 +- board/freescale/mpc8641hpcn/ddr.c | 4 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +- board/freescale/p1010rdb/ddr.c | 4 +- board/freescale/p1010rdb/spl_minimal.c | 4 +- board/freescale/p1022ds/ddr.c | 4 +- board/freescale/p1022ds/p1022ds.c | 2 +- board/freescale/p1022ds/spl_minimal.c | 2 +- board/freescale/p1023rdb/ddr.c | 4 +- board/freescale/p1023rdb/p1023rdb.c | 2 +- board/freescale/p1023rds/p1023rds.c | 4 +- board/freescale/p1_p2_rdb/ddr.c | 2 +- board/freescale/p1_p2_rdb_pc/ddr.c | 4 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 2 +- board/freescale/p1_twr/ddr.c | 4 +- board/freescale/p1_twr/p1_twr.c | 2 +- board/freescale/p2020come/ddr.c | 4 +- board/freescale/p2020ds/ddr.c | 6 +- board/freescale/p2020ds/p2020ds.c | 4 +- board/freescale/p2041rdb/ddr.c | 4 +- board/freescale/t1040qds/ddr.c | 4 +- board/freescale/t104xrdb/ddr.c | 4 +- board/freescale/t4qds/ddr.c | 4 +- board/freescale/t4qds/eth.c | 2 +- board/gdsys/p1022/controlcenterd.c | 2 +- board/gdsys/p1022/ddr.c | 4 +- board/keymile/kmp204x/ddr.c | 4 +- board/sbc8548/Makefile | 2 +- board/sbc8548/ddr.c | 6 +- board/sbc8548/sbc8548.c | 2 +- board/sbc8641d/Makefile | 2 +- board/sbc8641d/ddr.c | 4 +- board/sbc8641d/sbc8641d.c | 2 +- board/socrates/Makefile | 2 +- board/socrates/ddr.c | 4 +- board/socrates/sdram.c | 4 +- board/stx/stxgp3/Makefile | 2 +- board/stx/stxgp3/ddr.c | 4 +- board/stx/stxgp3/stxgp3.c | 2 +- board/stx/stxssa/Makefile | 2 +- board/stx/stxssa/ddr.c | 4 +- board/stx/stxssa/stxssa.c | 2 +- board/xes/xpedite517x/ddr.c | 4 +- board/xes/xpedite517x/xpedite517x.c | 2 +- board/xes/xpedite520x/ddr.c | 4 +- board/xes/xpedite537x/ddr.c | 4 +- board/xes/xpedite550x/ddr.c | 4 +- drivers/ddr/fsl/Makefile | 34 + drivers/ddr/fsl/ctrl_regs.c | 1657 +++++++++++++++++ drivers/ddr/fsl/ddr1_dimm_params.c | 343 ++++ drivers/ddr/fsl/ddr2_dimm_params.c | 342 ++++ drivers/ddr/fsl/ddr3_dimm_params.c | 341 ++++ drivers/ddr/fsl/interactive.c | 1871 ++++++++++++++++++++ drivers/ddr/fsl/lc_common_dimm_params.c | 526 ++++++ drivers/ddr/fsl/main.c | 718 ++++++++ drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 89 + drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 95 + drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 464 +++++ drivers/ddr/fsl/mpc86xx_ddr.c | 85 + drivers/ddr/fsl/options.c | 1147 ++++++++++++ drivers/ddr/fsl/util.c | 265 +++ include/common_timing_params.h | 57 + include/configs/B4860QDS.h | 2 +- include/configs/BSC9131RDB.h | 2 +- include/configs/BSC9132QDS.h | 2 +- include/configs/C29XPCIE.h | 2 +- include/configs/HWW1U1A.h | 2 +- include/configs/MPC8349EMDS.h | 6 +- include/configs/MPC8536DS.h | 2 +- include/configs/MPC8540ADS.h | 2 +- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8544DS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8555CDS.h | 2 +- include/configs/MPC8560ADS.h | 2 +- include/configs/MPC8568MDS.h | 2 +- include/configs/MPC8569MDS.h | 2 +- include/configs/MPC8572DS.h | 2 +- include/configs/MPC8610HPCD.h | 2 +- include/configs/MPC8641HPCN.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/P1022DS.h | 2 +- include/configs/P1023RDB.h | 2 +- include/configs/P1_P2_RDB.h | 2 +- include/configs/P2020COME.h | 2 +- include/configs/P2020DS.h | 4 +- include/configs/P2041RDB.h | 2 +- include/configs/T1040QDS.h | 2 +- include/configs/T1040RDB.h | 2 +- include/configs/T1042RDB_PI.h | 2 +- include/configs/controlcenterd.h | 2 +- include/configs/corenet_ds.h | 2 +- include/configs/km/kmp204x-common.h | 2 +- include/configs/mpq101.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/p1_twr.h | 2 +- include/configs/sbc8548.h | 2 +- include/configs/socrates.h | 2 +- include/configs/stxgp3.h | 2 +- include/configs/stxssa.h | 2 +- include/configs/t4qds.h | 2 +- include/configs/xpedite517x.h | 2 +- include/configs/xpedite520x.h | 2 +- include/configs/xpedite537x.h | 2 +- include/configs/xpedite550x.h | 2 +- include/fsl_ddr.h | 105 ++ include/fsl_ddr_dimm_params.h | 101 ++ include/fsl_ddr_sdram.h | 377 ++++ nand_spl/board/freescale/mpc8569mds/nand_boot.c | 2 +- nand_spl/board/freescale/p1023rds/nand_boot.c | 4 +- nand_spl/board/freescale/p1_p2_rdb/nand_boot.c | 2 +- spl/Makefile | 1 + 187 files changed, 8894 insertions(+), 8886 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/ddr-gen1.c delete mode 100644 arch/powerpc/cpu/mpc85xx/ddr-gen2.c delete mode 100644 arch/powerpc/cpu/mpc85xx/ddr-gen3.c delete mode 100644 arch/powerpc/cpu/mpc86xx/ddr-8641.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/Makefile delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/main.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/options.c delete mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/util.c delete mode 100644 arch/powerpc/include/asm/fsl_ddr_dimm_params.h delete mode 100644 arch/powerpc/include/asm/fsl_ddr_sdram.h create mode 100644 drivers/ddr/fsl/Makefile create mode 100644 drivers/ddr/fsl/ctrl_regs.c create mode 100644 drivers/ddr/fsl/ddr1_dimm_params.c create mode 100644 drivers/ddr/fsl/ddr2_dimm_params.c create mode 100644 drivers/ddr/fsl/ddr3_dimm_params.c create mode 100644 drivers/ddr/fsl/interactive.c create mode 100644 drivers/ddr/fsl/lc_common_dimm_params.c create mode 100644 drivers/ddr/fsl/main.c create mode 100644 drivers/ddr/fsl/mpc85xx_ddr_gen1.c create mode 100644 drivers/ddr/fsl/mpc85xx_ddr_gen2.c create mode 100644 drivers/ddr/fsl/mpc85xx_ddr_gen3.c create mode 100644 drivers/ddr/fsl/mpc86xx_ddr.c create mode 100644 drivers/ddr/fsl/options.c create mode 100644 drivers/ddr/fsl/util.c create mode 100644 include/common_timing_params.h create mode 100644 include/fsl_ddr.h create mode 100644 include/fsl_ddr_dimm_params.h create mode 100644 include/fsl_ddr_sdram.h diff --git a/Makefile b/Makefile index b8713a4935..2ad1d37a62 100644 --- a/Makefile +++ b/Makefile @@ -267,6 +267,7 @@ LIBS-y += drivers/power/ \ drivers/power/battery/ LIBS-y += drivers/spi/ LIBS-$(CONFIG_FMAN_ENET) += drivers/net/fm/ +LIBS-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ LIBS-y += drivers/serial/ LIBS-y += drivers/usb/eth/ LIBS-y += drivers/usb/gadget/ diff --git a/README b/README index c97ff0af0b..49f4b3af2f 100644 --- a/README +++ b/README @@ -423,16 +423,47 @@ The following options need to be configured: CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. - CONFIG_SYS_FSL_DDR_EMU - Specify emulator support for DDR. Some DDR features such as - deskew training are not available. - - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN Defines the endianess of the CPU. Implementation of those values is arch specific. + CONFIG_SYS_FSL_DDR + Freescale DDR driver in use. This type of DDR controller is + found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core + SoCs. + + CONFIG_SYS_FSL_DDR_ADDR + Freescale DDR memory-mapped register base. + + CONFIG_SYS_FSL_DDR_EMU + Specify emulator support for DDR. Some DDR features such as + deskew training are not available. + + CONFIG_SYS_FSL_DDRC_GEN1 + Freescale DDR1 controller. + + CONFIG_SYS_FSL_DDRC_GEN2 + Freescale DDR2 controller. + + CONFIG_SYS_FSL_DDRC_GEN3 + Freescale DDR3 controller. + + CONFIG_SYS_FSL_DDR1 + Board config to use DDR1. It can be enabled for SoCs with + Freescale DDR1 or DDR2 controllers, depending on the board + implemetation. + + CONFIG_SYS_FSL_DDR2 + Board config to use DDR2. It can be eanbeld for SoCs with + Freescale DDR2 or DDR3 controllers, depending on the board + implementation. + + CONFIG_SYS_FSL_DDR3 + Board config to use DDR3. It can be enabled for SoCs with + Freescale DDR3 controllers. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO @@ -3182,7 +3213,7 @@ FIT uImage format: CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT Set for the SPL on PPC mpc8xxx targets, support for - arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary. + drivers/ddr/fsl/libddr.o in SPL binary. CONFIG_SPL_COMMON_INIT_DDR Set for common ddr init with serial presence detect in diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index d3f7001478..c345dd6ae6 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -38,11 +38,11 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o # Stub implementations of cache management functions for USB obj-y += cache.o -ifdef CONFIG_FSL_DDR2 -obj-$(CONFIG_MPC8349) += ../mpc85xx/ddr-gen2.o +ifdef CONFIG_SYS_FSL_DDR2 +obj-$(CONFIG_MPC8349) += $(SRCTREE)/drivers/ddr/fsl/mpc85xx_ddr_gen2.o else obj-y += spd_sdram.o endif -obj-$(CONFIG_FSL_DDR2) += law.o +obj-$(CONFIG_SYS_FSL_DDR2) += law.o endif # not minimal diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 120b37ba63..6b7f72aa7d 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -15,7 +15,7 @@ void ecc_print_status(void) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#ifdef CONFIG_FSL_DDR2 +#ifdef CONFIG_SYS_FSL_DDR2 ccsr_ddr_t *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; @@ -99,7 +99,7 @@ void ecc_print_status(void) int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#ifdef CONFIG_FSL_DDR2 +#ifdef CONFIG_SYS_FSL_DDR2 ccsr_ddr_t *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index a34014f305..91c8402047 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -29,51 +29,6 @@ obj-$(CONFIG_MP) += release.o obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o obj-$(CONFIG_CPM2) += commproc.o -# supports ddr1 -obj-$(CONFIG_MPC8540) += ddr-gen1.o -obj-$(CONFIG_MPC8560) += ddr-gen1.o -obj-$(CONFIG_MPC8541) += ddr-gen1.o -obj-$(CONFIG_MPC8555) += ddr-gen1.o - -# supports ddr1/2 -obj-$(CONFIG_MPC8548) += ddr-gen2.o -obj-$(CONFIG_MPC8568) += ddr-gen2.o -obj-$(CONFIG_MPC8544) += ddr-gen2.o - -# supports ddr1/2/3 -obj-$(CONFIG_PPC_C29X) += ddr-gen3.o -obj-$(CONFIG_MPC8572) += ddr-gen3.o -obj-$(CONFIG_MPC8536) += ddr-gen3.o -obj-$(CONFIG_MPC8569) += ddr-gen3.o -obj-$(CONFIG_P1010) += ddr-gen3.o -obj-$(CONFIG_P1011) += ddr-gen3.o -obj-$(CONFIG_P1012) += ddr-gen3.o -obj-$(CONFIG_P1013) += ddr-gen3.o -obj-$(CONFIG_P1014) += ddr-gen3.o -obj-$(CONFIG_P1020) += ddr-gen3.o -obj-$(CONFIG_P1021) += ddr-gen3.o -obj-$(CONFIG_P1022) += ddr-gen3.o -obj-$(CONFIG_P1023) += ddr-gen3.o -obj-$(CONFIG_P1024) += ddr-gen3.o -obj-$(CONFIG_P1025) += ddr-gen3.o -obj-$(CONFIG_P2010) += ddr-gen3.o -obj-$(CONFIG_P2020) += ddr-gen3.o -obj-$(CONFIG_PPC_P2041) += ddr-gen3.o -obj-$(CONFIG_PPC_P3041) += ddr-gen3.o -obj-$(CONFIG_PPC_P4080) += ddr-gen3.o -obj-$(CONFIG_PPC_P5020) += ddr-gen3.o -obj-$(CONFIG_PPC_P5040) += ddr-gen3.o -obj-$(CONFIG_PPC_T4240) += ddr-gen3.o -obj-$(CONFIG_PPC_T4160) += ddr-gen3.o -obj-$(CONFIG_PPC_B4420) += ddr-gen3.o -obj-$(CONFIG_PPC_B4860) += ddr-gen3.o -obj-$(CONFIG_BSC9131) += ddr-gen3.o -obj-$(CONFIG_BSC9132) += ddr-gen3.o -obj-$(CONFIG_PPC_T1040) += ddr-gen3.o -obj-$(CONFIG_PPC_T1042) += ddr-gen3.o -obj-$(CONFIG_PPC_T1020) += ddr-gen3.o -obj-$(CONFIG_PPC_T1022) += ddr-gen3.o - obj-$(CONFIG_CPM2) += ether_fcc.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_FSL_CORENET) += liodn.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 1a0196c7c4..552acc6879 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -453,21 +453,21 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { switch (i) { case 0: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; break; #endif -#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: - ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; + ddr[i] = (void *)CONFIG_SYS_FSL_DDR4_ADDR; break; #endif default: diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c deleted file mode 100644 index 4dd8c0b5bf..0000000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - - if (ctrl_num != 0) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); -#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541) - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); -#endif - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - asm("sync;isync;msync"); - udelay(500); -} - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -/* - * Initialize all of memory for ECC, then enable errors. - */ - -void -ddr_enable_ecc(unsigned int dram_size) -{ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* - * Enable errors for ECC. - */ - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); -} - -#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c deleted file mode 100644 index 542bc84acf..0000000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i; - ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - -#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint svr; -#endif - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - -#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 - /* - * Set the DDR IO receiver to an acceptable bias point. - * Fixed in Rev 2.1. - */ - svr = get_svr(); - if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { - if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == - SDRAM_CFG_SDRAM_TYPE_DDR2) - out_be32(&gur->ddrioovcr, 0x90000000); - else - out_be32(&gur->ddrioovcr, 0xA8000000); - } -#endif - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { - udelay(10000); /* throttle polling rate */ - } -} diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c deleted file mode 100644 index 1be51d3307..0000000000 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ /dev/null @@ -1,464 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - - -/* - * regs has the to-be-set values for DDR controller registers - * ctrl_num is the DDR controller number - * step: 0 goes through the initialization in one pass - * 1 sets registers and returns before enabling controller - * 2 resumes from step 1 and continues to initialize - * Dividing the initialization to two steps to deassert DDR reset signal - * to comply with JEDEC specs for RDIMMs. - */ -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i, bus_width; - volatile ccsr_ddr_t *ddr; - u32 temp_sdram_cfg; - u32 total_gb_size_per_controller; - int timeout; -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - int timeout_save; - volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; - unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; - int csn = -1; -#endif - - switch (ctrl_num) { - case 0: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - break; -#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) - case 1: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - break; -#endif -#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) - case 2: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; - break; -#endif -#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) - case 3: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR; - break; -#endif - default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - if (step == 2) - goto step2; - - if (regs->ddr_eor) - out_be32(&ddr->eor, regs->ddr_eor); -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - debug("Workaround for ERRATUM_DDR111_DDR134\n"); - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; - cs_ea = regs->cs[i].bnds & 0xfff; - if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { - csn = i; - csn_bnds_backup = regs->cs[i].bnds; - csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; - if (cs_ea > 0xeff) - *csn_bnds_t = regs->cs[i].bnds + 0x01000000; - else - *csn_bnds_t = regs->cs[i].bnds + 0x01000100; - debug("Found cs%d_bns (0x%08x) covering 0xff000000, " - "change it to 0x%x\n", - csn, csn_bnds_backup, regs->cs[i].bnds); - break; - } - } -#endif - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); - out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); - out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); - out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); - out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); - out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); - out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); -#ifndef CONFIG_SYS_FSL_DDR_EMU - /* - * Skip these two registers if running on emulator - * because emulator doesn't have skew between bytes. - */ - - if (regs->ddr_wrlvl_cntl_2) - out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); - if (regs->ddr_wrlvl_cntl_3) - out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); -#endif - - out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); - out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); - out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); - out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); - out_be32(&ddr->err_disable, regs->err_disable); - out_be32(&ddr->err_int_en, regs->err_int_en); - for (i = 0; i < 32; i++) { - if (regs->debug[i]) { - debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); - out_be32(&ddr->debug[i], regs->debug[i]); - } - } -#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 - out_be32(&ddr->debug[28], 0x30003000); -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 - out_be32(&ddr->debug[12], 0x00000015); - out_be32(&ddr->debug[21], 0x24000000); -#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ - - /* - * For RDIMMs, JEDEC spec requires clocks to be stable before reset is - * deasserted. Clocks start when any chip select is enabled and clock - * control register is set. Because all DDR components are connected to - * one reset signal, this needs to be done in two steps. Step 1 is to - * get the clocks started. Step 2 resumes after reset signal is - * deasserted. - */ - if (step == 1) { - udelay(200); - return; - } - -step2: - /* Set, but do not enable the memory */ - temp_sdram_cfg = regs->ddr_sdram_cfg; - temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 - debug("Workaround for ERRATUM_DDR_A003\n"); - if (regs->ddr_sdram_rcw_2 & 0x00f00000) { - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); - out_be32(&ddr->debug[2], 0x00000400); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); - out_be32(&ddr->mtcr, 0); - out_be32(&ddr->debug[12], 0x00000015); - out_be32(&ddr->debug[21], 0x24000000); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); - - asm volatile("sync;isync"); - while (!(in_be32(&ddr->debug[1]) & 0x2)) - ; - - switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { - case 0x00000000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x02)); - break; - case 0x00100000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x0a)); - break; - case 0x00200000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x12)); - break; - case 0x00300000: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x1a)); - break; - default: - out_be32(&ddr->sdram_md_cntl, - MD_CNTL_MD_EN | - MD_CNTL_CS_SEL_CS0_CS1 | - 0x04000000 | - MD_CNTL_WRCW | - MD_CNTL_MD_VALUE(0x02)); - printf("Unsupported RC10\n"); - break; - } - - while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) - ; - udelay(6); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->debug[2], 0x0); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->debug[12], 0x0); - out_be32(&ddr->debug[21], 0x0); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - - } -#endif - /* - * For 8572 DDR1 erratum - DDR controller may enter illegal state - * when operatiing in 32-bit bus mode with 4-beat bursts, - * This erratum does not affect DDR3 mode, only for DDR2 mode. - */ -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 - debug("Workaround for ERRATUM_DDR_115\n"); - if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) - && in_be32(&ddr->sdram_cfg) & 0x80000) { - /* set DEBUG_1[31] */ - setbits_be32(&ddr->debug[0], 1); - } -#endif -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - debug("Workaround for ERRATUM_DDR111_DDR134\n"); - /* - * This is the combined workaround for DDR111 and DDR134 - * following the published errata for MPC8572 - */ - - /* 1. Set EEBACR[3] */ - setbits_be32(&ecm->eebacr, 0x10000000); - debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); - - /* 2. Set DINIT in SDRAM_CFG_2*/ - setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); - debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", - in_be32(&ddr->sdram_cfg_2)); - - /* 3. Set DEBUG_3[21] */ - setbits_be32(&ddr->debug[2], 0x400); - debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); - -#endif /* part 1 of the workaound */ - - /* - * 500 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - * DDR2 need 200 us, and DDR3 need 500 us from spec, - * we choose the max, that is 500 us for all of case. - */ - udelay(500); - asm volatile("sync;isync"); - - /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); - asm volatile("sync;isync"); - - total_gb_size_per_controller = 0; - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (!(regs->cs[i].config & 0x80000000)) - continue; - total_gb_size_per_controller += 1 << ( - ((regs->cs[i].config >> 14) & 0x3) + 2 + - ((regs->cs[i].config >> 8) & 0x7) + 12 + - ((regs->cs[i].config >> 0) & 0x7) + 8 + - 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - - 26); /* minus 26 (count of 64M) */ - } - if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ - total_gb_size_per_controller *= 3; - else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ - total_gb_size_per_controller <<= 1; - /* - * total memory / bus width = transactions needed - * transactions needed / data rate = seconds - * to add plenty of buffer, double the time - * For example, 2GB on 666MT/s 64-bit bus takes about 402ms - * Let's wait for 800ms - */ - bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) - >> SDRAM_CFG_DBW_SHIFT); - timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - timeout_save = timeout; -#endif - total_gb_size_per_controller >>= 4; /* shift down to gb size */ - debug("total %d GB\n", total_gb_size_per_controller); - debug("Need to wait up to %d * 10ms\n", timeout); - - /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && - (timeout >= 0)) { - udelay(10000); /* throttle polling rate */ - timeout--; - } - - if (timeout <= 0) - printf("Waiting for D_INIT timeout. Memory may not work.\n"); - -#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 - /* continue this workaround */ - - /* 4. Clear DEBUG3[21] */ - clrbits_be32(&ddr->debug[2], 0x400); - debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); - - /* DDR134 workaround starts */ - /* A: Clear sdram_cfg_2[odt_cfg] */ - clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); - debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", - in_be32(&ddr->sdram_cfg_2)); - - /* B: Set DEBUG1[15] */ - setbits_be32(&ddr->debug[0], 0x10000); - debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); - - /* C: Set timing_cfg_2[cpo] to 0b11111 */ - setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); - debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", - in_be32(&ddr->timing_cfg_2)); - - /* D: Set D6 to 0x9f9f9f9f */ - out_be32(&ddr->debug[5], 0x9f9f9f9f); - debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); - - /* E: Set D7 to 0x9f9f9f9f */ - out_be32(&ddr->debug[6], 0x9f9f9f9f); - debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); - - /* F: Set D2[20] */ - setbits_be32(&ddr->debug[1], 0x800); - debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); - - /* G: Poll on D2[20] until cleared */ - while (in_be32(&ddr->debug[1]) & 0x800) - udelay(10000); /* throttle polling rate */ - - /* H: Clear D1[15] */ - clrbits_be32(&ddr->debug[0], 0x10000); - debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); - - /* I: Set sdram_cfg_2[odt_cfg] */ - setbits_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); - debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); - - /* Continuing with the DDR111 workaround */ - /* 5. Set D2[21] */ - setbits_be32(&ddr->debug[1], 0x400); - debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); - - /* 6. Poll D2[21] until its cleared */ - while (in_be32(&ddr->debug[1]) & 0x400) - udelay(10000); /* throttle polling rate */ - - /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ - debug("Wait for %d * 10ms\n", timeout_save); - udelay(timeout_save * 10000); - - /* 8. Set sdram_cfg_2[dinit] if options requires */ - setbits_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); - debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); - - /* 9. Poll until dinit is cleared */ - timeout = timeout_save; - debug("Need to wait up to %d * 10ms\n", timeout); - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && - (timeout >= 0)) { - udelay(10000); /* throttle polling rate */ - timeout--; - } - - if (timeout <= 0) - printf("Waiting for D_INIT timeout. Memory may not work.\n"); - - /* 10. Clear EEBACR[3] */ - clrbits_be32(&ecm->eebacr, 10000000); - debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); - - if (csn != -1) { - csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; - *csn_bnds_t = csn_bnds_backup; - debug("Change cs%d_bnds back to 0x%08x\n", - csn, regs->cs[csn].bnds); - setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ - switch (csn) { - case 0: - out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); - break; - case 1: - out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); - break; - case 2: - out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); - break; - case 3: - out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); - break; - } - clrbits_be32(&ddr->sdram_cfg, 0x2); - } -#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ -} diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 5f198eb305..88c8e65930 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "mp.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile index bcb786dcab..0f790b0efc 100644 --- a/arch/powerpc/cpu/mpc86xx/Makefile +++ b/arch/powerpc/cpu/mpc86xx/Makefile @@ -16,9 +16,6 @@ obj-$(CONFIG_MP) += release.o obj-y += cpu.o obj-y += cpu_init.o -# 8610 & 8641 are identical w/regards to DDR -obj-$(CONFIG_MPC8610) += ddr-8641.o -obj-$(CONFIG_MPC8641) += ddr-8641.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += interrupts.o obj-$(CONFIG_MP) += mp.o diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c deleted file mode 100644 index 33a91f9f78..0000000000 --- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include - -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL -#endif - -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step) -{ - unsigned int i; - volatile ccsr_ddr_t *ddr; - - switch (ctrl_num) { - case 0: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR; - break; - case 1: - ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - break; - default: - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - - } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - - } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - - } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - } - } - - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - debug("before go\n"); - - /* - * 200 painful micro-seconds must elapse between - * the DDR clock setup and the DDR config enable. - */ - udelay(200); - asm volatile("sync;isync"); - - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); - - /* - * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done - */ - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { - udelay(10000); /* throttle polling rate */ - } -} diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 1d083bf354..395fed16b6 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -31,9 +31,3 @@ obj-$(CONFIG_SYS_SRIO) += srio.o obj-$(CONFIG_FSL_LAW) += law.o endif - -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/ -else -obj-y += ddr/ -endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile deleted file mode 100644 index 8cbc06c95a..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright 2008-2011 Freescale Semiconductor, Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# Version 2 as published by the Free Software Foundation. -# - -obj-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o - -obj-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o - -obj-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ - lc_common_dimm_params.o -ifdef CONFIG_DDR_SPD -SPD := y -endif -ifdef CONFIG_SPD_EEPROM -SPD := y -endif -ifdef SPD -obj-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o -obj-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o -obj-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o -endif - -obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h deleted file mode 100644 index 76338d4e6c..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef COMMON_TIMING_PARAMS_H -#define COMMON_TIMING_PARAMS_H - -typedef struct { - /* parameters to constrict */ - - unsigned int tckmin_x_ps; - unsigned int tckmax_ps; - unsigned int tckmax_max_ps; - unsigned int trcd_ps; - unsigned int trp_ps; - unsigned int tras_ps; - - unsigned int twr_ps; /* maximum = 63750 ps */ - unsigned int twtr_ps; /* maximum = 63750 ps */ - unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int trrd_ps; /* maximum = 63750 ps */ - unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - unsigned int extended_op_srt; - - unsigned int tis_ps; /* byte 32, spd->ca_setup */ - unsigned int tih_ps; /* byte 33, spd->ca_hold */ - unsigned int tds_ps; /* byte 34, spd->data_setup */ - unsigned int tdh_ps; /* byte 35, spd->data_hold */ - unsigned int trtp_ps; /* byte 38, spd->trtp */ - unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tqhs_ps; /* byte 45, spd->tqhs */ - - unsigned int ndimms_present; - unsigned int lowest_common_SPD_caslat; - unsigned int highest_common_derated_caslat; - unsigned int additive_latency; - unsigned int all_dimms_burst_lengths_bitmask; - unsigned int all_dimms_registered; - unsigned int all_dimms_unbuffered; - unsigned int all_dimms_ecc_capable; - - unsigned long long total_mem; - unsigned long long base_address; - - /* DDR3 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ -} common_timing_params_t; - -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c deleted file mode 100644 index dcfc48aa95..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ /dev/null @@ -1,1656 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - */ - -#include -#include - -#include "ddr.h" - -#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR - -static u32 fsl_ddr_get_version(void) -{ - ccsr_ddr_t *ddr; - u32 ver_major_minor_errata; - - ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; - - return ver_major_minor_errata; -} - -unsigned int picos_to_mclk(unsigned int picos); - -/* - * Determine Rtt value. - * - * This should likely be either board or controller specific. - * - * Rtt(nominal) - DDR2: - * 0 = Rtt disabled - * 1 = 75 ohm - * 2 = 150 ohm - * 3 = 50 ohm - * Rtt(nominal) - DDR3: - * 0 = Rtt disabled - * 1 = 60 ohm - * 2 = 120 ohm - * 3 = 40 ohm - * 4 = 20 ohm - * 5 = 30 ohm - * - * FIXME: Apparently 8641 needs a value of 2 - * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 - * - * FIXME: There was some effort down this line earlier: - * - * unsigned int i; - * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { - * if (popts->dimmslot[i].num_valid_cs - * && (popts->cs_local_opts[2*i].odt_rd_cfg - * || popts->cs_local_opts[2*i].odt_wr_cfg)) { - * rtt = 2; - * break; - * } - * } - */ -static inline int fsl_ddr_get_rtt(void) -{ - int rtt; - -#if defined(CONFIG_FSL_DDR1) - rtt = 0; -#elif defined(CONFIG_FSL_DDR2) - rtt = 3; -#else - rtt = 0; -#endif - - return rtt; -} - -/* - * compute the CAS write latency according to DDR3 spec - * CWL = 5 if tCK >= 2.5ns - * 6 if 2.5ns > tCK >= 1.875ns - * 7 if 1.875ns > tCK >= 1.5ns - * 8 if 1.5ns > tCK >= 1.25ns - * 9 if 1.25ns > tCK >= 1.07ns - * 10 if 1.07ns > tCK >= 0.935ns - * 11 if 0.935ns > tCK >= 0.833ns - * 12 if 0.833ns > tCK >= 0.75ns - */ -static inline unsigned int compute_cas_write_latency(void) -{ - unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - if (mclk_ps >= 2500) - cwl = 5; - else if (mclk_ps >= 1875) - cwl = 6; - else if (mclk_ps >= 1500) - cwl = 7; - else if (mclk_ps >= 1250) - cwl = 8; - else if (mclk_ps >= 1070) - cwl = 9; - else if (mclk_ps >= 935) - cwl = 10; - else if (mclk_ps >= 833) - cwl = 11; - else if (mclk_ps >= 750) - cwl = 12; - else { - cwl = 12; - printf("Warning: CWL is out of range\n"); - } - return cwl; -} - -/* Chip Select Configuration (CSn_CONFIG) */ -static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const dimm_params_t *dimm_params) -{ - unsigned int cs_n_en = 0; /* Chip Select enable */ - unsigned int intlv_en = 0; /* Memory controller interleave enable */ - unsigned int intlv_ctl = 0; /* Interleaving control */ - unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ - unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ - unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ - unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ - unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ - unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ - int go_config = 0; - - /* Compute CS_CONFIG only for existing ranks of each DIMM. */ - switch (i) { - case 0: - if (dimm_params[dimm_number].n_ranks > 0) { - go_config = 1; - /* These fields only available in CS0_CONFIG */ - if (!popts->memctl_interleaving) - break; - switch (popts->memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - intlv_en = popts->memctl_interleaving; - intlv_ctl = popts->memctl_interleaving_mode; - break; - default: - break; - } - } - break; - case 1: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ - (dimm_number == 1 && dimm_params[1].n_ranks > 0)) - go_config = 1; - break; - case 2: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ - (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) - go_config = 1; - break; - case 3: - if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ - (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ - (dimm_number == 3 && dimm_params[3].n_ranks > 0)) - go_config = 1; - break; - default: - break; - } - if (go_config) { - unsigned int n_banks_per_sdram_device; - cs_n_en = 1; - ap_n_en = popts->cs_local_opts[i].auto_precharge; - odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; - odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; - n_banks_per_sdram_device - = dimm_params[dimm_number].n_banks_per_sdram_device; - ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; - row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; - col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; - } - ddr->cs[i].config = (0 - | ((cs_n_en & 0x1) << 31) - | ((intlv_en & 0x3) << 29) - | ((intlv_ctl & 0xf) << 24) - | ((ap_n_en & 0x1) << 23) - - /* XXX: some implementation only have 1 bit starting at left */ - | ((odt_rd_cfg & 0x7) << 20) - - /* XXX: Some implementation only have 1 bit starting at left */ - | ((odt_wr_cfg & 0x7) << 16) - - | ((ba_bits_cs_n & 0x3) << 14) - | ((row_bits_cs_n & 0x7) << 8) - | ((col_bits_cs_n & 0x7) << 0) - ); - debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); -} - -/* Chip Select Configuration 2 (CSn_CONFIG_2) */ -/* FIXME: 8572 */ -static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int pasr_cfg = 0; /* Partial array self refresh config */ - - ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); - debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); -} - -/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ - -#if !defined(CONFIG_FSL_DDR1) -static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) -{ -#if CONFIG_DIMM_SLOTS_PER_CTLR == 1 - if (dimm_params[0].n_ranks == 4) - return 1; -#endif - -#if CONFIG_DIMM_SLOTS_PER_CTLR == 2 - if ((dimm_params[0].n_ranks == 2) && - (dimm_params[1].n_ranks == 2)) - return 1; - -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (dimm_params[0].n_ranks == 4) - return 1; -#endif -#endif - return 0; -} - -/* - * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) - * - * Avoid writing for DDR I. The new PQ38 DDR controller - * dreams up non-zero default values to be backwards compatible. - */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const dimm_params_t *dimm_params) -{ - unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ - unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ - /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ - unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ - unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ - - /* Active powerdown exit timing (tXARD and tXARDS). */ - unsigned char act_pd_exit_mclk; - /* Precharge powerdown exit timing (tXP). */ - unsigned char pre_pd_exit_mclk; - /* ODT powerdown exit timing (tAXPD). */ - unsigned char taxpd_mclk; - /* Mode register set cycle time (tMRD). */ - unsigned char tmrd_mclk; - -#ifdef CONFIG_FSL_DDR3 - /* - * (tXARD and tXARDS). Empirical? - * The DDR3 spec has not tXARD, - * we use the tXP instead of it. - * tXP=max(3nCK, 7.5ns) for DDR3. - * spec has not the tAXPD, we use - * tAXPD=1, need design to confirm. - */ - int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - unsigned int data_rate = get_ddr_freq(0); - tmrd_mclk = 4; - /* set the turnaround time */ - - /* - * for single quad-rank DIMM and two dual-rank DIMMs - * to avoid ODT overlap - */ - if (avoid_odt_overlap(dimm_params)) { - twwt_mclk = 2; - trrt_mclk = 1; - } - /* for faster clock, need more time for data setup */ - trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; - - if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) - twrt_mclk = 1; - - if (popts->dynamic_power == 0) { /* powerdown is not used */ - act_pd_exit_mclk = 1; - pre_pd_exit_mclk = 1; - taxpd_mclk = 1; - } else { - /* act_pd_exit_mclk = tXARD, see above */ - act_pd_exit_mclk = picos_to_mclk(tXP); - /* Mode register MR0[A12] is '1' - fast exit */ - pre_pd_exit_mclk = act_pd_exit_mclk; - taxpd_mclk = 1; - } -#else /* CONFIG_FSL_DDR2 */ - /* - * (tXARD and tXARDS). Empirical? - * tXARD = 2 for DDR2 - * tXP=2 - * tAXPD=8 - */ - act_pd_exit_mclk = 2; - pre_pd_exit_mclk = 2; - taxpd_mclk = 8; - tmrd_mclk = 2; -#endif - - if (popts->trwt_override) - trwt_mclk = popts->trwt; - - ddr->timing_cfg_0 = (0 - | ((trwt_mclk & 0x3) << 30) /* RWT */ - | ((twrt_mclk & 0x3) << 28) /* WRT */ - | ((trrt_mclk & 0x3) << 26) /* RRT */ - | ((twwt_mclk & 0x3) << 24) /* WWT */ - | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ - | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ - | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ - | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ - ); - debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); -} -#endif /* defined(CONFIG_FSL_DDR2) */ - -/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ -static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Extended precharge to activate interval (tRP) */ - unsigned int ext_pretoact = 0; - /* Extended Activate to precharge interval (tRAS) */ - unsigned int ext_acttopre = 0; - /* Extended activate to read/write interval (tRCD) */ - unsigned int ext_acttorw = 0; - /* Extended refresh recovery time (tRFC) */ - unsigned int ext_refrec; - /* Extended MCAS latency from READ cmd */ - unsigned int ext_caslat = 0; - /* Extended last data to precharge interval (tWR) */ - unsigned int ext_wrrec = 0; - /* Control Adjust */ - unsigned int cntl_adj = 0; - - ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; - ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; - ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; - ext_caslat = (2 * cas_latency - 1) >> 4; - ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; - /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ - ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + - (popts->otf_burst_chop_en ? 2 : 0)) >> 4; - - ddr->timing_cfg_3 = (0 - | ((ext_pretoact & 0x1) << 28) - | ((ext_acttopre & 0x3) << 24) - | ((ext_acttorw & 0x1) << 22) - | ((ext_refrec & 0x1F) << 16) - | ((ext_caslat & 0x3) << 12) - | ((ext_wrrec & 0x1) << 8) - | ((cntl_adj & 0x7) << 0) - ); - debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); -} - -/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ -static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) -{ - /* Precharge-to-activate interval (tRP) */ - unsigned char pretoact_mclk; - /* Activate to precharge interval (tRAS) */ - unsigned char acttopre_mclk; - /* Activate to read/write interval (tRCD) */ - unsigned char acttorw_mclk; - /* CASLAT */ - unsigned char caslat_ctrl; - /* Refresh recovery time (tRFC) ; trfc_low */ - unsigned char refrec_ctrl; - /* Last data to precharge minimum interval (tWR) */ - unsigned char wrrec_mclk; - /* Activate-to-activate interval (tRRD) */ - unsigned char acttoact_mclk; - /* Last write data pair to read command issue interval (tWTR) */ - unsigned char wrtord_mclk; - /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ - static const u8 wrrec_table[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; - - pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); - acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); - acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); - - /* - * Translate CAS Latency to a DDR controller field value: - * - * CAS Lat DDR I DDR II Ctrl - * Clocks SPD Bit SPD Bit Value - * ------- ------- ------- ----- - * 1.0 0 0001 - * 1.5 1 0010 - * 2.0 2 2 0011 - * 2.5 3 0100 - * 3.0 4 3 0101 - * 3.5 5 0110 - * 4.0 4 0111 - * 4.5 1000 - * 5.0 5 1001 - */ -#if defined(CONFIG_FSL_DDR1) - caslat_ctrl = (cas_latency + 1) & 0x07; -#elif defined(CONFIG_FSL_DDR2) - caslat_ctrl = 2 * cas_latency - 1; -#else - /* - * if the CAS latency more than 8 cycle, - * we need set extend bit for it at - * TIMING_CFG_3[EXT_CASLAT] - */ - caslat_ctrl = 2 * cas_latency - 1; -#endif - - refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - - if (wrrec_mclk > 16) - printf("Error: WRREC doesn't support more than 16 clocks\n"); - else - wrrec_mclk = wrrec_table[wrrec_mclk - 1]; - if (popts->otf_burst_chop_en) - wrrec_mclk += 2; - - acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); - /* - * JEDEC has min requirement for tRRD - */ -#if defined(CONFIG_FSL_DDR3) - if (acttoact_mclk < 4) - acttoact_mclk = 4; -#endif - wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); - /* - * JEDEC has some min requirements for tWTR - */ -#if defined(CONFIG_FSL_DDR2) - if (wrtord_mclk < 2) - wrtord_mclk = 2; -#elif defined(CONFIG_FSL_DDR3) - if (wrtord_mclk < 4) - wrtord_mclk = 4; -#endif - if (popts->otf_burst_chop_en) - wrtord_mclk += 2; - - ddr->timing_cfg_1 = (0 - | ((pretoact_mclk & 0x0F) << 28) - | ((acttopre_mclk & 0x0F) << 24) - | ((acttorw_mclk & 0xF) << 20) - | ((caslat_ctrl & 0xF) << 16) - | ((refrec_ctrl & 0xF) << 12) - | ((wrrec_mclk & 0x0F) << 8) - | ((acttoact_mclk & 0x0F) << 4) - | ((wrtord_mclk & 0x0F) << 0) - ); - debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); -} - -/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ -static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) -{ - /* Additive latency */ - unsigned char add_lat_mclk; - /* CAS-to-preamble override */ - unsigned short cpo; - /* Write latency */ - unsigned char wr_lat; - /* Read to precharge (tRTP) */ - unsigned char rd_to_pre; - /* Write command to write data strobe timing adjustment */ - unsigned char wr_data_delay; - /* Minimum CKE pulse width (tCKE) */ - unsigned char cke_pls; - /* Window for four activates (tFAW) */ - unsigned short four_act; - - /* FIXME add check that this must be less than acttorw_mclk */ - add_lat_mclk = additive_latency; - cpo = popts->cpo_override; - -#if defined(CONFIG_FSL_DDR1) - /* - * This is a lie. It should really be 1, but if it is - * set to 1, bits overlap into the old controller's - * otherwise unused ACSM field. If we leave it 0, then - * the HW will magically treat it as 1 for DDR 1. Oh Yea. - */ - wr_lat = 0; -#elif defined(CONFIG_FSL_DDR2) - wr_lat = cas_latency - 1; -#else - wr_lat = compute_cas_write_latency(); -#endif - - rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); - /* - * JEDEC has some min requirements for tRTP - */ -#if defined(CONFIG_FSL_DDR2) - if (rd_to_pre < 2) - rd_to_pre = 2; -#elif defined(CONFIG_FSL_DDR3) - if (rd_to_pre < 4) - rd_to_pre = 4; -#endif - if (additive_latency) - rd_to_pre += additive_latency; - if (popts->otf_burst_chop_en) - rd_to_pre += 2; /* according to UM */ - - wr_data_delay = popts->write_data_delay; - cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps); - four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); - - ddr->timing_cfg_2 = (0 - | ((add_lat_mclk & 0xf) << 28) - | ((cpo & 0x1f) << 23) - | ((wr_lat & 0xf) << 19) - | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) - | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) - | ((cke_pls & 0x7) << 6) - | ((four_act & 0x3f) << 0) - ); - debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); -} - -/* DDR SDRAM Register Control Word */ -static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - if (common_dimm->all_dimms_registered && - !common_dimm->all_dimms_unbuffered) { - if (popts->rcw_override) { - ddr->ddr_sdram_rcw_1 = popts->rcw_1; - ddr->ddr_sdram_rcw_2 = popts->rcw_2; - } else { - ddr->ddr_sdram_rcw_1 = - common_dimm->rcw[0] << 28 | \ - common_dimm->rcw[1] << 24 | \ - common_dimm->rcw[2] << 20 | \ - common_dimm->rcw[3] << 16 | \ - common_dimm->rcw[4] << 12 | \ - common_dimm->rcw[5] << 8 | \ - common_dimm->rcw[6] << 4 | \ - common_dimm->rcw[7]; - ddr->ddr_sdram_rcw_2 = - common_dimm->rcw[8] << 28 | \ - common_dimm->rcw[9] << 24 | \ - common_dimm->rcw[10] << 20 | \ - common_dimm->rcw[11] << 16 | \ - common_dimm->rcw[12] << 12 | \ - common_dimm->rcw[13] << 8 | \ - common_dimm->rcw[14] << 4 | \ - common_dimm->rcw[15]; - } - debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); - debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); - } -} - -/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ -static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int mem_en; /* DDR SDRAM interface logic enable */ - unsigned int sren; /* Self refresh enable (during sleep) */ - unsigned int ecc_en; /* ECC enable. */ - unsigned int rd_en; /* Registered DIMM enable */ - unsigned int sdram_type; /* Type of SDRAM */ - unsigned int dyn_pwr; /* Dynamic power management mode */ - unsigned int dbw; /* DRAM dta bus width */ - unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ - unsigned int ncap = 0; /* Non-concurrent auto-precharge */ - unsigned int threet_en; /* Enable 3T timing */ - unsigned int twot_en; /* Enable 2T timing */ - unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ - unsigned int x32_en = 0; /* x32 enable */ - unsigned int pchb8 = 0; /* precharge bit 8 enable */ - unsigned int hse; /* Global half strength override */ - unsigned int mem_halt = 0; /* memory controller halt */ - unsigned int bi = 0; /* Bypass initialization */ - - mem_en = 1; - sren = popts->self_refresh_in_sleep; - if (common_dimm->all_dimms_ecc_capable) { - /* Allow setting of ECC only if all DIMMs are ECC. */ - ecc_en = popts->ecc_mode; - } else { - ecc_en = 0; - } - - if (common_dimm->all_dimms_registered && - !common_dimm->all_dimms_unbuffered) { - rd_en = 1; - twot_en = 0; - } else { - rd_en = 0; - twot_en = popts->twot_en; - } - - sdram_type = CONFIG_FSL_SDRAM_TYPE; - - dyn_pwr = popts->dynamic_power; - dbw = popts->data_bus_width; - /* 8-beat burst enable DDR-III case - * we must clear it when use the on-the-fly mode, - * must set it when use the 32-bits bus mode. - */ - if (sdram_type == SDRAM_TYPE_DDR3) { - if (popts->burst_length == DDR_BL8) - eight_be = 1; - if (popts->burst_length == DDR_OTF) - eight_be = 0; - if (dbw == 0x1) - eight_be = 1; - } - - threet_en = popts->threet_en; - ba_intlv_ctl = popts->ba_intlv_ctl; - hse = popts->half_strength_driver_enable; - - ddr->ddr_sdram_cfg = (0 - | ((mem_en & 0x1) << 31) - | ((sren & 0x1) << 30) - | ((ecc_en & 0x1) << 29) - | ((rd_en & 0x1) << 28) - | ((sdram_type & 0x7) << 24) - | ((dyn_pwr & 0x1) << 21) - | ((dbw & 0x3) << 19) - | ((eight_be & 0x1) << 18) - | ((ncap & 0x1) << 17) - | ((threet_en & 0x1) << 16) - | ((twot_en & 0x1) << 15) - | ((ba_intlv_ctl & 0x7F) << 8) - | ((x32_en & 0x1) << 5) - | ((pchb8 & 0x1) << 4) - | ((hse & 0x1) << 3) - | ((mem_halt & 0x1) << 1) - | ((bi & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); -} - -/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ -static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const unsigned int unq_mrs_en) -{ - unsigned int frc_sr = 0; /* Force self refresh */ - unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ - unsigned int dll_rst_dis; /* DLL reset disable */ - unsigned int dqs_cfg; /* DQS configuration */ - unsigned int odt_cfg = 0; /* ODT configuration */ - unsigned int num_pr; /* Number of posted refreshes */ - unsigned int slow = 0; /* DDR will be run less than 1250 */ - unsigned int x4_en = 0; /* x4 DRAM enable */ - unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ - unsigned int ap_en; /* Address Parity Enable */ - unsigned int d_init; /* DRAM data initialization */ - unsigned int rcw_en = 0; /* Register Control Word Enable */ - unsigned int md_en = 0; /* Mirrored DIMM Enable */ - unsigned int qd_en = 0; /* quad-rank DIMM Enable */ - int i; - - dll_rst_dis = 1; /* Make this configurable */ - dqs_cfg = popts->dqs_config; - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->cs_local_opts[i].odt_rd_cfg - || popts->cs_local_opts[i].odt_wr_cfg) { - odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; - break; - } - } - - num_pr = 1; /* Make this configurable */ - - /* - * 8572 manual says - * {TIMING_CFG_1[PRETOACT] - * + [DDR_SDRAM_CFG_2[NUM_PR] - * * ({EXT_REFREC || REFREC} + 8 + 2)]} - * << DDR_SDRAM_INTERVAL[REFINT] - */ -#if defined(CONFIG_FSL_DDR3) - obc_cfg = popts->otf_burst_chop_en; -#else - obc_cfg = 0; -#endif - -#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) - slow = get_ddr_freq(0) < 1249000000; -#endif - - if (popts->registered_dimm_en) { - rcw_en = 1; - ap_en = popts->ap_en; - } else { - ap_en = 0; - } - - x4_en = popts->x4_en ? 1 : 0; - -#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Use the DDR controller to auto initialize memory. */ - d_init = popts->ecc_init_using_memctl; - ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; - debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); -#else - /* Memory will be initialized via DMA, or not at all. */ - d_init = 0; -#endif - -#if defined(CONFIG_FSL_DDR3) - md_en = popts->mirrored_dimm; -#endif - qd_en = popts->quad_rank_present ? 1 : 0; - ddr->ddr_sdram_cfg_2 = (0 - | ((frc_sr & 0x1) << 31) - | ((sr_ie & 0x1) << 30) - | ((dll_rst_dis & 0x1) << 29) - | ((dqs_cfg & 0x3) << 26) - | ((odt_cfg & 0x3) << 21) - | ((num_pr & 0xf) << 12) - | ((slow & 1) << 11) - | (x4_en << 10) - | (qd_en << 9) - | (unq_mrs_en << 8) - | ((obc_cfg & 0x1) << 6) - | ((ap_en & 0x1) << 5) - | ((d_init & 0x1) << 4) - | ((rcw_en & 0x1) << 2) - | ((md_en & 0x1) << 0) - ); - debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); -} - -/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ - unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ - -#if defined(CONFIG_FSL_DDR3) - int i; - unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ - unsigned int srt = 0; /* self-refresh temerature, normal range */ - unsigned int asr = 0; /* auto self-refresh disable */ - unsigned int cwl = compute_cas_write_latency() - 5; - unsigned int pasr = 0; /* partial array self refresh disable */ - - if (popts->rtt_override) - rtt_wr = popts->rtt_wr_override_value; - else - rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; - - if (common_dimm->extended_op_srt) - srt = common_dimm->extended_op_srt; - - esdmode2 = (0 - | ((rtt_wr & 0x3) << 9) - | ((srt & 0x1) << 7) - | ((asr & 0x1) << 6) - | ((cwl & 0x7) << 3) - | ((pasr & 0x7) << 0)); -#endif - ddr->ddr_sdram_mode_2 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); - -#ifdef CONFIG_FSL_DDR3 - if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->rtt_override) - rtt_wr = popts->rtt_wr_override_value; - else - rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; - - esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ - esdmode2 |= (rtt_wr & 0x3) << 9; - switch (i) { - case 1: - ddr->ddr_sdram_mode_4 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - case 2: - ddr->ddr_sdram_mode_6 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - case 3: - ddr->ddr_sdram_mode_8 = (0 - | ((esdmode2 & 0xFFFF) << 16) - | ((esdmode3 & 0xFFFF) << 0) - ); - break; - } - } - debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", - ddr->ddr_sdram_mode_4); - debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", - ddr->ddr_sdram_mode_6); - debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", - ddr->ddr_sdram_mode_8); - } -#endif -} - -/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ -static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) -{ - unsigned int refint; /* Refresh interval */ - unsigned int bstopre; /* Precharge interval */ - - refint = picos_to_mclk(common_dimm->refresh_rate_ps); - - bstopre = popts->bstopre; - - /* refint field used 0x3FFF in earlier controllers */ - ddr->ddr_sdram_interval = (0 - | ((refint & 0xFFFF) << 16) - | ((bstopre & 0x3FFF) << 0) - ); - debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); -} - -#if defined(CONFIG_FSL_DDR3) -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* Mode Register - MR1 */ - unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ - unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ - unsigned int rtt; - unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ - unsigned int al = 0; /* Posted CAS# additive latency (AL) */ - unsigned int dic = 0; /* Output driver impedance, 40ohm */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register - MR0 */ - unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ - unsigned int wr = 0; /* Write Recovery */ - unsigned int dll_rst; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ - /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - - unsigned int wr_mclk; - /* - * DDR_SDRAM_MODE doesn't support 9,11,13,15 - * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 - * for this table - */ - static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; - - const unsigned int mclk_ps = get_memory_clk_period_ps(); - int i; - - if (popts->rtt_override) - rtt = popts->rtt_override_value; - else - rtt = popts->cs_local_opts[0].odt_rtt_norm; - - if (additive_latency == (cas_latency - 1)) - al = 1; - if (additive_latency == (cas_latency - 2)) - al = 2; - - if (popts->quad_rank_present) - dic = 1; /* output driver impedance 240/7 ohm */ - - /* - * The esdmode value will also be used for writing - * MR1 during write leveling for DDR3, although the - * bits specifically related to the write leveling - * scheme will be handled automatically by the DDR - * controller. so we set the wrlvl_en = 0 here. - */ - esdmode = (0 - | ((qoff & 0x1) << 12) - | ((tdqs_en & 0x1) << 11) - | ((rtt & 0x4) << 7) /* rtt field is split */ - | ((wrlvl_en & 0x1) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((dic & 0x2) << 4) /* DIC field is split */ - | ((al & 0x3) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((dic & 0x1) << 1) /* DIC field is split */ - | ((dll_en & 0x1) << 0) - ); - - /* - * DLL control for precharge PD - * 0=slow exit DLL off (tXPDLL) - * 1=fast exit DLL on (tXP) - */ - dll_on = 1; - - wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps; - if (wr_mclk <= 16) { - wr = wr_table[wr_mclk - 5]; - } else { - printf("Error: unsupported write recovery for mode register " - "wr_mclk = %d\n", wr_mclk); - } - - dll_rst = 0; /* dll no reset */ - mode = 0; /* normal mode */ - - /* look up table to get the cas latency bits */ - if (cas_latency >= 5 && cas_latency <= 16) { - unsigned char cas_latency_table[] = { - 0x2, /* 5 clocks */ - 0x4, /* 6 clocks */ - 0x6, /* 7 clocks */ - 0x8, /* 8 clocks */ - 0xa, /* 9 clocks */ - 0xc, /* 10 clocks */ - 0xe, /* 11 clocks */ - 0x1, /* 12 clocks */ - 0x3, /* 13 clocks */ - 0x5, /* 14 clocks */ - 0x7, /* 15 clocks */ - 0x9, /* 16 clocks */ - }; - caslat = cas_latency_table[cas_latency - 5]; - } else { - printf("Error: unsupported cas latency for mode register\n"); - } - - bt = 0; /* Nibble sequential */ - - switch (popts->burst_length) { - case DDR_BL8: - bl = 0; - break; - case DDR_OTF: - bl = 1; - break; - case DDR_BC4: - bl = 2; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to on-the-fly BC4 or BL8 beats.\n", - popts->burst_length); - bl = 1; - break; - } - - sdmode = (0 - | ((dll_on & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_rst & 0x1) << 8) - | ((mode & 0x1) << 7) - | (((caslat >> 1) & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((caslat & 1) << 2) - | ((bl & 0x3) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); - - if (unq_mrs_en) { /* unique mode registers are supported */ - for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - if (popts->rtt_override) - rtt = popts->rtt_override_value; - else - rtt = popts->cs_local_opts[i].odt_rtt_norm; - - esdmode &= 0xFDBB; /* clear bit 9,6,2 */ - esdmode |= (0 - | ((rtt & 0x4) << 7) /* rtt field is split */ - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((rtt & 0x1) << 2) /* rtt field is split */ - ); - switch (i) { - case 1: - ddr->ddr_sdram_mode_3 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - case 2: - ddr->ddr_sdram_mode_5 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - case 3: - ddr->ddr_sdram_mode_7 = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - break; - } - } - debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", - ddr->ddr_sdram_mode_3); - debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", - ddr->ddr_sdram_mode_5); - debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", - ddr->ddr_sdram_mode_5); - } -} - -#else /* !CONFIG_FSL_DDR3 */ - -/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency, - const unsigned int unq_mrs_en) -{ - unsigned short esdmode; /* Extended SDRAM mode */ - unsigned short sdmode; /* SDRAM mode */ - - /* - * FIXME: This ought to be pre-calculated in a - * technology-specific routine, - * e.g. compute_DDR2_mode_register(), and then the - * sdmode and esdmode passed in as part of common_dimm. - */ - - /* Extended Mode Register */ - unsigned int mrs = 0; /* Mode Register Set */ - unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ - unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ - unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ - unsigned int ocd = 0; /* 0x0=OCD not supported, - 0x7=OCD default state */ - unsigned int rtt; - unsigned int al; /* Posted CAS# additive latency (AL) */ - unsigned int ods = 0; /* Output Drive Strength: - 0 = Full strength (18ohm) - 1 = Reduced strength (4ohm) */ - unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), - 1=Disable (Test/Debug) */ - - /* Mode Register (MR) */ - unsigned int mr; /* Mode Register Definition */ - unsigned int pd; /* Power-Down Mode */ - unsigned int wr; /* Write Recovery */ - unsigned int dll_res; /* DLL Reset */ - unsigned int mode; /* Normal=0 or Test=1 */ - unsigned int caslat = 0;/* CAS# latency */ - /* BT: Burst Type (0=Sequential, 1=Interleaved) */ - unsigned int bt; - unsigned int bl; /* BL: Burst Length */ - -#if defined(CONFIG_FSL_DDR2) - const unsigned int mclk_ps = get_memory_clk_period_ps(); -#endif - dqs_en = !popts->dqs_config; - rtt = fsl_ddr_get_rtt(); - - al = additive_latency; - - esdmode = (0 - | ((mrs & 0x3) << 14) - | ((outputs & 0x1) << 12) - | ((rdqs_en & 0x1) << 11) - | ((dqs_en & 0x1) << 10) - | ((ocd & 0x7) << 7) - | ((rtt & 0x2) << 5) /* rtt field is split */ - | ((al & 0x7) << 3) - | ((rtt & 0x1) << 2) /* rtt field is split */ - | ((ods & 0x1) << 1) - | ((dll_en & 0x1) << 0) - ); - - mr = 0; /* FIXME: CHECKME */ - - /* - * 0 = Fast Exit (Normal) - * 1 = Slow Exit (Low Power) - */ - pd = 0; - -#if defined(CONFIG_FSL_DDR1) - wr = 0; /* Historical */ -#elif defined(CONFIG_FSL_DDR2) - wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1; -#endif - dll_res = 0; - mode = 0; - -#if defined(CONFIG_FSL_DDR1) - if (1 <= cas_latency && cas_latency <= 4) { - unsigned char mode_caslat_table[4] = { - 0x5, /* 1.5 clocks */ - 0x2, /* 2.0 clocks */ - 0x6, /* 2.5 clocks */ - 0x3 /* 3.0 clocks */ - }; - caslat = mode_caslat_table[cas_latency - 1]; - } else { - printf("Warning: unknown cas_latency %d\n", cas_latency); - } -#elif defined(CONFIG_FSL_DDR2) - caslat = cas_latency; -#endif - bt = 0; - - switch (popts->burst_length) { - case DDR_BL4: - bl = 2; - break; - case DDR_BL8: - bl = 3; - break; - default: - printf("Error: invalid burst length of %u specified. " - " Defaulting to 4 beats.\n", - popts->burst_length); - bl = 2; - break; - } - - sdmode = (0 - | ((mr & 0x3) << 14) - | ((pd & 0x1) << 12) - | ((wr & 0x7) << 9) - | ((dll_res & 0x1) << 8) - | ((mode & 0x1) << 7) - | ((caslat & 0x7) << 4) - | ((bt & 0x1) << 3) - | ((bl & 0x7) << 0) - ); - - ddr->ddr_sdram_mode = (0 - | ((esdmode & 0xFFFF) << 16) - | ((sdmode & 0xFFFF) << 0) - ); - debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); -} -#endif - -/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ -static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_value; /* Initialization value */ - -#ifdef CONFIG_MEM_INIT_VALUE - init_value = CONFIG_MEM_INIT_VALUE; -#else - init_value = 0xDEADBEEF; -#endif - ddr->ddr_data_init = init_value; -} - -/* - * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) - * The old controller on the 8540/60 doesn't have this register. - * Hope it's OK to set it (to 0) anyway. - */ -static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int clk_adjust; /* Clock adjust */ - - clk_adjust = popts->clk_adjust; - ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; - debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); -} - -/* DDR Initialization Address (DDR_INIT_ADDR) */ -static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int init_addr = 0; /* Initialization address */ - - ddr->ddr_init_addr = init_addr; -} - -/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ -static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int uia = 0; /* Use initialization address */ - unsigned int init_ext_addr = 0; /* Initialization address */ - - ddr->ddr_init_ext_addr = (0 - | ((uia & 0x1) << 31) - | (init_ext_addr & 0xF) - ); -} - -/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ -static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts) -{ - unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ - unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ - unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ - unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ - unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ - -#if defined(CONFIG_FSL_DDR3) - if (popts->burst_length == DDR_BL8) { - /* We set BL/2 for fixed BL8 */ - rrt = 0; /* BL/2 clocks */ - wwt = 0; /* BL/2 clocks */ - } else { - /* We need to set BL/2 + 2 to BC4 and OTF */ - rrt = 2; /* BL/2 + 2 clocks */ - wwt = 2; /* BL/2 + 2 clocks */ - } - dll_lock = 1; /* tDLLK = 512 clocks from spec */ -#endif - ddr->timing_cfg_4 = (0 - | ((rwt & 0xf) << 28) - | ((wrt & 0xf) << 24) - | ((rrt & 0xf) << 20) - | ((wwt & 0xf) << 16) - | (dll_lock & 0x3) - ); - debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); -} - -/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ -static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) -{ - unsigned int rodt_on = 0; /* Read to ODT on */ - unsigned int rodt_off = 0; /* Read to ODT off */ - unsigned int wodt_on = 0; /* Write to ODT on */ - unsigned int wodt_off = 0; /* Write to ODT off */ - -#if defined(CONFIG_FSL_DDR3) - /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ - rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1; - rodt_off = 4; /* 4 clocks */ - wodt_on = 1; /* 1 clocks */ - wodt_off = 4; /* 4 clocks */ -#endif - - ddr->timing_cfg_5 = (0 - | ((rodt_on & 0x1f) << 24) - | ((rodt_off & 0x7) << 20) - | ((wodt_on & 0x1f) << 12) - | ((wodt_off & 0x7) << 8) - ); - debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); -} - -/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ -static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) -{ - unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ - /* Normal Operation Full Calibration Time (tZQoper) */ - unsigned int zqoper = 0; - /* Normal Operation Short Calibration Time (tZQCS) */ - unsigned int zqcs = 0; - - if (zq_en) { - zqinit = 9; /* 512 clocks */ - zqoper = 8; /* 256 clocks */ - zqcs = 6; /* 64 clocks */ - } - - ddr->ddr_zq_cntl = (0 - | ((zq_en & 0x1) << 31) - | ((zqinit & 0xF) << 24) - | ((zqoper & 0xF) << 16) - | ((zqcs & 0xF) << 8) - ); - debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); -} - -/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, - const memctl_options_t *popts) -{ - /* - * First DQS pulse rising edge after margining mode - * is programmed (tWL_MRD) - */ - unsigned int wrlvl_mrd = 0; - /* ODT delay after margining mode is programmed (tWL_ODTEN) */ - unsigned int wrlvl_odten = 0; - /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ - unsigned int wrlvl_dqsen = 0; - /* WRLVL_SMPL: Write leveling sample time */ - unsigned int wrlvl_smpl = 0; - /* WRLVL_WLR: Write leveling repeition time */ - unsigned int wrlvl_wlr = 0; - /* WRLVL_START: Write leveling start time */ - unsigned int wrlvl_start = 0; - - /* suggest enable write leveling for DDR3 due to fly-by topology */ - if (wrlvl_en) { - /* tWL_MRD min = 40 nCK, we set it 64 */ - wrlvl_mrd = 0x6; - /* tWL_ODTEN 128 */ - wrlvl_odten = 0x7; - /* tWL_DQSEN min = 25 nCK, we set it 32 */ - wrlvl_dqsen = 0x5; - /* - * Write leveling sample time at least need 6 clocks - * higher than tWLO to allow enough time for progagation - * delay and sampling the prime data bits. - */ - wrlvl_smpl = 0xf; - /* - * Write leveling repetition time - * at least tWLO + 6 clocks clocks - * we set it 64 - */ - wrlvl_wlr = 0x6; - /* - * Write leveling start time - * The value use for the DQS_ADJUST for the first sample - * when write leveling is enabled. It probably needs to be - * overriden per platform. - */ - wrlvl_start = 0x8; - /* - * Override the write leveling sample and start time - * according to specific board - */ - if (popts->wrlvl_override) { - wrlvl_smpl = popts->wrlvl_sample; - wrlvl_start = popts->wrlvl_start; - } - } - - ddr->ddr_wrlvl_cntl = (0 - | ((wrlvl_en & 0x1) << 31) - | ((wrlvl_mrd & 0x7) << 24) - | ((wrlvl_odten & 0x7) << 20) - | ((wrlvl_dqsen & 0x7) << 16) - | ((wrlvl_smpl & 0xf) << 12) - | ((wrlvl_wlr & 0x7) << 8) - | ((wrlvl_start & 0x1F) << 0) - ); - debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); - ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; - debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); - ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; - debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); - -} - -/* DDR Self Refresh Counter (DDR_SR_CNTR) */ -static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) -{ - /* Self Refresh Idle Threshold */ - ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; -} - -static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - if (popts->addr_hash) { - ddr->ddr_eor = 0x40000000; /* address hash enable */ - puts("Address hashing enabled.\n"); - } -} - -static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - ddr->ddr_cdr1 = popts->ddr_cdr1; - debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); -} - -static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) -{ - ddr->ddr_cdr2 = popts->ddr_cdr2; - debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); -} - -unsigned int -check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int res = 0; - - /* - * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are - * not set at the same time. - */ - if (ddr->ddr_sdram_cfg & 0x10000000 - && ddr->ddr_sdram_cfg & 0x00008000) { - printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " - " should not be set at the same time.\n"); - res++; - } - - return res; -} - -unsigned int -compute_fsl_memctl_config_regs(const memctl_options_t *popts, - fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - const dimm_params_t *dimm_params, - unsigned int dbw_cap_adj, - unsigned int size_only) -{ - unsigned int i; - unsigned int cas_latency; - unsigned int additive_latency; - unsigned int sr_it; - unsigned int zq_en; - unsigned int wrlvl_en; - unsigned int ip_rev = 0; - unsigned int unq_mrs_en = 0; - int cs_en = 1; - - memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); - - if (common_dimm == NULL) { - printf("Error: subset DIMM params struct null pointer\n"); - return 1; - } - - /* - * Process overrides first. - * - * FIXME: somehow add dereated caslat to this - */ - cas_latency = (popts->cas_latency_override) - ? popts->cas_latency_override_value - : common_dimm->lowest_common_SPD_caslat; - - additive_latency = (popts->additive_latency_override) - ? popts->additive_latency_override_value - : common_dimm->additive_latency; - - sr_it = (popts->auto_self_refresh_en) - ? popts->sr_it - : 0; - /* ZQ calibration */ - zq_en = (popts->zq_en) ? 1 : 0; - /* write leveling */ - wrlvl_en = (popts->wrlvl_en) ? 1 : 0; - - /* Chip Select Memory Bounds (CSn_BNDS) */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - unsigned long long ea, sa; - unsigned int cs_per_dimm - = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; - unsigned int dimm_number - = i / cs_per_dimm; - unsigned long long rank_density - = dimm_params[dimm_number].rank_density >> dbw_cap_adj; - - if (dimm_params[dimm_number].n_ranks == 0) { - debug("Skipping setup of CS%u " - "because n_ranks on DIMM %u is 0\n", i, dimm_number); - continue; - } - if (popts->memctl_interleaving) { - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - break; - case FSL_DDR_CS0_CS1: - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if (i > 1) - cs_en = 0; - break; - case FSL_DDR_CS2_CS3: - default: - if (i > 0) - cs_en = 0; - break; - } - sa = common_dimm->base_address; - ea = sa + common_dimm->total_mem - 1; - } else if (!popts->memctl_interleaving) { - /* - * If memory interleaving between controllers is NOT - * enabled, the starting address for each memory - * controller is distinct. However, because rank - * interleaving is enabled, the starting and ending - * addresses of the total memory on that memory - * controller needs to be programmed into its - * respective CS0_BNDS. - */ - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - sa = common_dimm->base_address; - ea = sa + common_dimm->total_mem - 1; - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - if ((i >= 2) && (dimm_number == 0)) { - sa = dimm_params[dimm_number].base_address + - 2 * rank_density; - ea = sa + 2 * rank_density - 1; - } else { - sa = dimm_params[dimm_number].base_address; - ea = sa + 2 * rank_density - 1; - } - break; - case FSL_DDR_CS0_CS1: - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (i != 1) - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - if (i == 0) - ea += rank_density; - break; - case FSL_DDR_CS2_CS3: - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (i != 3) - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - if (i == 2) - ea += (rank_density >> dbw_cap_adj); - break; - default: /* No bank(chip-select) interleaving */ - sa = dimm_params[dimm_number].base_address; - ea = sa + rank_density - 1; - if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { - sa += (i % cs_per_dimm) * rank_density; - ea += (i % cs_per_dimm) * rank_density; - } else { - sa = 0; - ea = 0; - } - break; - } - } - - sa >>= 24; - ea >>= 24; - - if (cs_en) { - ddr->cs[i].bnds = (0 - | ((sa & 0xFFF) << 16)/* starting address MSB */ - | ((ea & 0xFFF) << 0) /* ending address MSB */ - ); - } else { - /* setting bnds to 0xffffffff for inactive CS */ - ddr->cs[i].bnds = 0xffffffff; - } - - debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); - set_csn_config(dimm_number, i, ddr, popts, dimm_params); - set_csn_config_2(i, ddr); - } - - /* - * In the case we only need to compute the ddr sdram size, we only need - * to set csn registers, so return from here. - */ - if (size_only) - return 0; - - set_ddr_eor(ddr, popts); - -#if !defined(CONFIG_FSL_DDR1) - set_timing_cfg_0(ddr, popts, dimm_params); -#endif - - set_timing_cfg_3(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_2(ddr, popts, common_dimm, - cas_latency, additive_latency); - - set_ddr_cdr1(ddr, popts); - set_ddr_cdr2(ddr, popts); - set_ddr_sdram_cfg(ddr, popts, common_dimm); - ip_rev = fsl_ddr_get_version(); - if (ip_rev > 0x40400) - unq_mrs_en = 1; - - set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); - set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency, unq_mrs_en); - set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); - set_ddr_sdram_interval(ddr, popts, common_dimm); - set_ddr_data_init(ddr); - set_ddr_sdram_clk_cntl(ddr, popts); - set_ddr_init_addr(ddr); - set_ddr_init_ext_addr(ddr); - set_timing_cfg_4(ddr, popts); - set_timing_cfg_5(ddr, cas_latency); - - set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); - - set_ddr_sr_cntr(ddr, sr_it); - - set_ddr_sdram_rcw(ddr, popts, common_dimm); - -#ifdef CONFIG_SYS_FSL_DDR_EMU - /* disble DDR training for emulator */ - ddr->debug[2] = 0x00000400; - ddr->debug[4] = 0xff800000; -#endif - return check_fsl_memctl_config_regs(ddr); -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h deleted file mode 100644 index e3b414e666..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef FSL_DDR_MAIN_H -#define FSL_DDR_MAIN_H - -#include -#include - -#include "common_timing_params.h" - -#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) -/* - * Bind the main DDR setup driver's generic names - * to this specific DDR technology. - */ -static __inline__ int -compute_dimm_parameters(const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); -} -#endif - -/* - * Data Structures - * - * All data structures have to be on the stack - */ -#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR - -typedef struct { - generic_spd_eeprom_t - spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; - struct dimm_params_s - dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; - memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; - common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; - fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; -} fsl_ddr_info_t; - -/* Compute steps */ -#define STEP_GET_SPD (1 << 0) -#define STEP_COMPUTE_DIMM_PARMS (1 << 1) -#define STEP_COMPUTE_COMMON_PARMS (1 << 2) -#define STEP_GATHER_OPTS (1 << 3) -#define STEP_ASSIGN_ADDRESSES (1 << 4) -#define STEP_COMPUTE_REGS (1 << 5) -#define STEP_PROGRAM_REGS (1 << 6) -#define STEP_ALL 0xFFF - -unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, - unsigned int size_only); - -const char *step_to_string(unsigned int step); - -unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, - fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm, - const dimm_params_t *dimm_parameters, - unsigned int dbw_capacity_adjust, - unsigned int size_only); -unsigned int compute_lowest_common_dimm_parameters( - const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms); -unsigned int populate_memctl_options(int all_dimms_registered, - memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num); -void check_interleaving_options(fsl_ddr_info_t *pinfo); - -unsigned int mclk_to_picos(unsigned int mclk); -unsigned int get_memory_clk_period_ps(void); -unsigned int picos_to_mclk(unsigned int picos); -void fsl_ddr_set_lawbar( - const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); - -int fsl_ddr_interactive_env_var_exists(void); -unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); - -int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); -unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); - -/* processor specific function */ -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step); - -/* board specific function */ -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number); -#endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c deleted file mode 100644 index f137fcee34..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include "ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Study these table from Byte 31 of JEDEC SPD Spec. - * - * DDR I DDR II - * Bit Size Size - * --- ----- ------ - * 7 high 512MB 512MB - * 6 256MB 256MB - * 5 128MB 128MB - * 4 64MB 16GB - * 3 32MB 8GB - * 2 16MB 4GB - * 1 2GB 2GB - * 0 low 1GB 1GB - * - * Reorder Table to be linear by stripping the bottom - * 2 or 5 bits off and shifting them up to the top. - */ - -static unsigned long long -compute_ranksize(unsigned int mem_type, unsigned char row_dens) -{ - unsigned long long bsize; - - /* Bottom 2 bits up to the top. */ - bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)); - bsize <<= 24ULL; - debug("DDR: DDR I rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * Convert a two-nibble BCD value into a cycle time. - * While the spec calls for nano-seconds, picos are returned. - * - * This implements the tables for bytes 9, 23 and 25 for both - * DDR I and II. No allowance for distinguishing the invalid - * fields absent for DDR I yet present in DDR II is made. - * (That is, cycle times of .25, .33, .66 and .75 ns are - * allowed for both DDR II and I.) - */ -static unsigned int -convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) -{ - /* Table look up the lower nibble, allow DDR I & II. */ - unsigned int tenths_ps[16] = { - 0, - 100, - 200, - 300, - 400, - 500, - 600, - 700, - 800, - 900, - 250, /* This and the next 3 entries valid ... */ - 330, /* ... only for tCK calculations. */ - 660, - 750, - 0, /* undefined */ - 0 /* undefined */ - }; - - unsigned int whole_ns = (spd_val & 0xF0) >> 4; - unsigned int tenth_ns = spd_val & 0x0F; - unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; - - return ps; -} - -static unsigned int -convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) -{ - unsigned int tenth_ns = (spd_val & 0xF0) >> 4; - unsigned int hundredth_ns = spd_val & 0x0F; - unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; - - return ps; -} - -static unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, /* supposed to be RFC, but not sure what that means */ - 0 /* Undefined */ -}; - -static unsigned int -compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) -{ - unsigned int trfc_ps; - - trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 - + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; - - return trfc_ps; -} - -static unsigned int -compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) -{ - unsigned int trc_ps; - - trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; - - return trc_ps; -} - -/* - * tCKmax from DDR I SPD Byte 43 - * - * Bits 7:2 == whole ns - * Bits 1:0 == quarter ns - * 00 == 0.00 ns - * 01 == 0.25 ns - * 10 == 0.50 ns - * 11 == 0.75 ns - * - * Returns picoseconds. - */ -static unsigned int -compute_tckmax_from_spd_ps(unsigned int byte43) -{ - return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250; -} - -/* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ -static unsigned int -determine_refresh_rate_ps(const unsigned int spd_refresh) -{ - unsigned int refresh_time_ps[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - return refresh_time_ps[spd_refresh & 0x7]; -} - -/* - * The purpose of this function is to compute a suitable - * CAS latency given the DRAM clock period. The SPD only - * defines at most 3 CAS latencies. Typically the slower in - * frequency the DIMM runs at, the shorter its CAS latency can be. - * If the DIMM is operating at a sufficiently low frequency, - * it may be able to run at a CAS latency shorter than the - * shortest SPD-defined CAS latency. - * - * If a CAS latency is not found, 0 is returned. - * - * Do this by finding in the standard speed bin table the longest - * tCKmin that doesn't exceed the value of mclk_ps (tCK). - * - * An assumption made is that the SDRAM device allows the - * CL to be programmed for a value that is lower than those - * advertised by the SPD. This is not always the case, - * as those modes not defined in the SPD are optional. - * - * CAS latency de-rating based upon values JEDEC Standard No. 79-E - * Table 11. - * - * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2 - */ - /* CL2.0 CL2.5 CL3.0 */ -unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 }; - -unsigned int -compute_derated_DDR1_CAS_latency(unsigned int mclk_ps) -{ - const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins); - unsigned int lowest_tCKmin_found = 0; - unsigned int lowest_tCKmin_CL = 0; - unsigned int i; - - debug("mclk_ps = %u\n", mclk_ps); - - for (i = 0; i < num_speed_bins; i++) { - unsigned int x = ddr1_speed_bins[i]; - debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", - i, x, lowest_tCKmin_found); - if (x && lowest_tCKmin_found <= x && x <= mclk_ps) { - lowest_tCKmin_found = x; - lowest_tCKmin_CL = i + 1; - } - } - - debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); - - return lowest_tCKmin_CL; -} - -/* - * ddr_compute_dimm_parameters for DDR1 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the dimm_params_t structure pointed by pdimm. - * - * FIXME: use #define for the retvals - */ -unsigned int -ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - unsigned int retval; - - if (spd->mem_type) { - if (spd->mem_type != SPD_MEMTYPE_DDR) { - printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number); - return 1; - } - } else { - memset(pdimm, 0, sizeof(dimm_params_t)); - return 1; - } - - retval = ddr1_spd_check(spd); - if (retval) { - printf("DIMM %u: failed checksum\n", dimm_number); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = spd->nrows; - pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->data_width = spd->dataw_lsb; - pdimm->primary_sdram_width = spd->primw; - pdimm->ec_sdram_width = spd->ecw; - - /* - * FIXME: Need to determine registered_dimm status. - * 1 == register buffered - * 0 == unbuffered - */ - pdimm->registered_dimm = 0; /* unbuffered */ - - /* SDRAM device parameters */ - pdimm->n_row_addr = spd->nrow_addr; - pdimm->n_col_addr = spd->ncol_addr; - pdimm->n_banks_per_sdram_device = spd->nbanks; - pdimm->edc_config = spd->config; - pdimm->burst_lengths_bitmask = spd->burstl; - pdimm->row_density = spd->bank_dens; - - /* - * Calculate the Maximum Data Rate based on the Minimum Cycle time. - * The SPD clk_cycle field (tCKmin) is measured in tenths of - * nanoseconds and represented as BCD. - */ - pdimm->tckmin_x_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tckmin_x_minus_1_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tckmin_x_minus_2_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - - pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); - - /* - * Compute CAS latencies defined by SPD - * The SPD caslat_x should have at least 1 and at most 3 bits set. - * - * If cas_lat after masking is 0, the __ilog2 function returns - * 255 into the variable. This behavior is abused once. - */ - pdimm->caslat_x = __ilog2(spd->cas_lat); - pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x)); - pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x) - & ~(1 << pdimm->caslat_x_minus_1)); - - /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps()); - - /* Compute timing parameters */ - pdimm->trcd_ps = spd->trcd * 250; - pdimm->trp_ps = spd->trp * 250; - pdimm->tras_ps = spd->tras * 1000; - - pdimm->twr_ps = mclk_to_picos(3); - pdimm->twtr_ps = mclk_to_picos(1); - pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); - - pdimm->trrd_ps = spd->trrd * 250; - pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc); - - pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - - pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tds_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tdh_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - - pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */ - pdimm->tdqsq_max_ps = spd->tdqsq * 10; - pdimm->tqhs_ps = spd->tqhs * 10; - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c deleted file mode 100644 index e4d02e8f61..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ /dev/null @@ -1,342 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include "ddr.h" -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * Study these table from Byte 31 of JEDEC SPD Spec. - * - * DDR I DDR II - * Bit Size Size - * --- ----- ------ - * 7 high 512MB 512MB - * 6 256MB 256MB - * 5 128MB 128MB - * 4 64MB 16GB - * 3 32MB 8GB - * 2 16MB 4GB - * 1 2GB 2GB - * 0 low 1GB 1GB - * - * Reorder Table to be linear by stripping the bottom - * 2 or 5 bits off and shifting them up to the top. - * - */ -static unsigned long long -compute_ranksize(unsigned int mem_type, unsigned char row_dens) -{ - unsigned long long bsize; - - /* Bottom 5 bits up to the top. */ - bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)); - bsize <<= 27ULL; - debug("DDR: DDR II rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * Convert a two-nibble BCD value into a cycle time. - * While the spec calls for nano-seconds, picos are returned. - * - * This implements the tables for bytes 9, 23 and 25 for both - * DDR I and II. No allowance for distinguishing the invalid - * fields absent for DDR I yet present in DDR II is made. - * (That is, cycle times of .25, .33, .66 and .75 ns are - * allowed for both DDR II and I.) - */ -static unsigned int -convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) -{ - /* Table look up the lower nibble, allow DDR I & II. */ - unsigned int tenths_ps[16] = { - 0, - 100, - 200, - 300, - 400, - 500, - 600, - 700, - 800, - 900, - 250, /* This and the next 3 entries valid ... */ - 330, /* ... only for tCK calculations. */ - 660, - 750, - 0, /* undefined */ - 0 /* undefined */ - }; - - unsigned int whole_ns = (spd_val & 0xF0) >> 4; - unsigned int tenth_ns = spd_val & 0x0F; - unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; - - return ps; -} - -static unsigned int -convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) -{ - unsigned int tenth_ns = (spd_val & 0xF0) >> 4; - unsigned int hundredth_ns = spd_val & 0x0F; - unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; - - return ps; -} - -static unsigned int byte40_table_ps[8] = { - 0, - 250, - 330, - 500, - 660, - 750, - 0, /* supposed to be RFC, but not sure what that means */ - 0 /* Undefined */ -}; - -static unsigned int -compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) -{ - unsigned int trfc_ps; - - trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 - + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; - - return trfc_ps; -} - -static unsigned int -compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) -{ - unsigned int trc_ps; - - trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; - - return trc_ps; -} - -/* - * Determine Refresh Rate. Ignore self refresh bit on DDR I. - * Table from SPD Spec, Byte 12, converted to picoseconds and - * filled in with "default" normal values. - */ -static unsigned int -determine_refresh_rate_ps(const unsigned int spd_refresh) -{ - unsigned int refresh_time_ps[8] = { - 15625000, /* 0 Normal 1.00x */ - 3900000, /* 1 Reduced .25x */ - 7800000, /* 2 Extended .50x */ - 31300000, /* 3 Extended 2.00x */ - 62500000, /* 4 Extended 4.00x */ - 125000000, /* 5 Extended 8.00x */ - 15625000, /* 6 Normal 1.00x filler */ - 15625000, /* 7 Normal 1.00x filler */ - }; - - return refresh_time_ps[spd_refresh & 0x7]; -} - -/* - * The purpose of this function is to compute a suitable - * CAS latency given the DRAM clock period. The SPD only - * defines at most 3 CAS latencies. Typically the slower in - * frequency the DIMM runs at, the shorter its CAS latency can. - * be. If the DIMM is operating at a sufficiently low frequency, - * it may be able to run at a CAS latency shorter than the - * shortest SPD-defined CAS latency. - * - * If a CAS latency is not found, 0 is returned. - * - * Do this by finding in the standard speed bin table the longest - * tCKmin that doesn't exceed the value of mclk_ps (tCK). - * - * An assumption made is that the SDRAM device allows the - * CL to be programmed for a value that is lower than those - * advertised by the SPD. This is not always the case, - * as those modes not defined in the SPD are optional. - * - * CAS latency de-rating based upon values JEDEC Standard No. 79-2C - * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS, - * and tRC for corresponding bin" - * - * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 - * Not certain if any good value exists for CL=2 - */ - /* CL2 CL3 CL4 CL5 CL6 CL7*/ -unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; - -unsigned int -compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) -{ - const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins); - unsigned int lowest_tCKmin_found = 0; - unsigned int lowest_tCKmin_CL = 0; - unsigned int i; - - debug("mclk_ps = %u\n", mclk_ps); - - for (i = 0; i < num_speed_bins; i++) { - unsigned int x = ddr2_speed_bins[i]; - debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", - i, x, lowest_tCKmin_found); - if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) { - lowest_tCKmin_found = x; - lowest_tCKmin_CL = i + 2; - } - } - - debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); - - return lowest_tCKmin_CL; -} - -/* - * ddr_compute_dimm_parameters for DDR2 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the dimm_params_t structure pointed by pdimm. - * - * FIXME: use #define for the retvals - */ -unsigned int -ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - unsigned int retval; - - if (spd->mem_type) { - if (spd->mem_type != SPD_MEMTYPE_DDR2) { - printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number); - return 1; - } - } else { - memset(pdimm, 0, sizeof(dimm_params_t)); - return 1; - } - - retval = ddr2_spd_check(spd); - if (retval) { - printf("DIMM %u: failed checksum\n", dimm_number); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1; - pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->data_width = spd->dataw; - pdimm->primary_sdram_width = spd->primw; - pdimm->ec_sdram_width = spd->ecw; - - /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ - switch (spd->dimm_type) { - case DDR2_SPD_DIMMTYPE_RDIMM: - case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: - case DDR2_SPD_DIMMTYPE_MINI_RDIMM: - /* Registered/buffered DIMMs */ - pdimm->registered_dimm = 1; - break; - - case DDR2_SPD_DIMMTYPE_UDIMM: - case DDR2_SPD_DIMMTYPE_SO_DIMM: - case DDR2_SPD_DIMMTYPE_MICRO_DIMM: - case DDR2_SPD_DIMMTYPE_MINI_UDIMM: - /* Unbuffered DIMMs */ - pdimm->registered_dimm = 0; - break; - - case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: - default: - printf("unknown dimm_type 0x%02X\n", spd->dimm_type); - return 1; - } - - /* SDRAM device parameters */ - pdimm->n_row_addr = spd->nrow_addr; - pdimm->n_col_addr = spd->ncol_addr; - pdimm->n_banks_per_sdram_device = spd->nbanks; - pdimm->edc_config = spd->config; - pdimm->burst_lengths_bitmask = spd->burstl; - pdimm->row_density = spd->rank_dens; - - /* - * Calculate the Maximum Data Rate based on the Minimum Cycle time. - * The SPD clk_cycle field (tCKmin) is measured in tenths of - * nanoseconds and represented as BCD. - */ - pdimm->tckmin_x_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); - pdimm->tckmin_x_minus_1_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); - pdimm->tckmin_x_minus_2_ps - = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); - - pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); - - /* - * Compute CAS latencies defined by SPD - * The SPD caslat_x should have at least 1 and at most 3 bits set. - * - * If cas_lat after masking is 0, the __ilog2 function returns - * 255 into the variable. This behavior is abused once. - */ - pdimm->caslat_x = __ilog2(spd->cas_lat); - pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x)); - pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat - & ~(1 << pdimm->caslat_x) - & ~(1 << pdimm->caslat_x_minus_1)); - - /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); - - /* Compute timing parameters */ - pdimm->trcd_ps = spd->trcd * 250; - pdimm->trp_ps = spd->trp * 250; - pdimm->tras_ps = spd->tras * 1000; - - pdimm->twr_ps = spd->twr * 250; - pdimm->twtr_ps = spd->twtr * 250; - pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); - - pdimm->trrd_ps = spd->trrd * 250; - pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); - - pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); - - pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); - pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); - pdimm->tds_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); - pdimm->tdh_ps - = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - - pdimm->trtp_ps = spd->trtp * 250; - pdimm->tdqsq_max_ps = spd->tdqsq * 10; - pdimm->tqhs_ps = spd->tqhs * 10; - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c deleted file mode 100644 index 4c8645da56..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * Dave Liu - * - * calculate the organization and timing parameter - * from ddr3 spd, please refer to the spec - * JEDEC standard No.21-C 4_01_02_11R18.pdf - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include "ddr.h" - -/* - * Calculate the Density of each Physical Rank. - * Returned size is in bytes. - * - * each rank size = - * sdram capacity(bit) / 8 * primary bus width / sdram width - * - * where: sdram capacity = spd byte4[3:0] - * primary bus width = spd byte8[2:0] - * sdram width = spd byte7[2:0] - * - * SPD byte4 - sdram density and banks - * bit[3:0] size(bit) size(byte) - * 0000 256Mb 32MB - * 0001 512Mb 64MB - * 0010 1Gb 128MB - * 0011 2Gb 256MB - * 0100 4Gb 512MB - * 0101 8Gb 1GB - * 0110 16Gb 2GB - * - * SPD byte8 - module memory bus width - * bit[2:0] primary bus width - * 000 8bits - * 001 16bits - * 010 32bits - * 011 64bits - * - * SPD byte7 - module organiztion - * bit[2:0] sdram device width - * 000 4bits - * 001 8bits - * 010 16bits - * 011 32bits - * - */ -static unsigned long long -compute_ranksize(const ddr3_spd_eeprom_t *spd) -{ - unsigned long long bsize; - - int nbit_sdram_cap_bsize = 0; - int nbit_primary_bus_width = 0; - int nbit_sdram_width = 0; - - if ((spd->density_banks & 0xf) < 7) - nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; - if ((spd->bus_width & 0x7) < 4) - nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; - if ((spd->organization & 0x7) < 4) - nbit_sdram_width = (spd->organization & 0x7) + 2; - - bsize = 1ULL << (nbit_sdram_cap_bsize - 3 - + nbit_primary_bus_width - nbit_sdram_width); - - debug("DDR: DDR III rank density = 0x%16llx\n", bsize); - - return bsize; -} - -/* - * ddr_compute_dimm_parameters for DDR3 SPD - * - * Compute DIMM parameters based upon the SPD information in spd. - * Writes the results to the dimm_params_t structure pointed by pdimm. - * - */ -unsigned int -ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) -{ - unsigned int retval; - unsigned int mtb_ps; - int ftb_10th_ps; - int i; - - if (spd->mem_type) { - if (spd->mem_type != SPD_MEMTYPE_DDR3) { - printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); - return 1; - } - } else { - memset(pdimm, 0, sizeof(dimm_params_t)); - return 1; - } - - retval = ddr3_spd_check(spd); - if (retval) { - printf("DIMM %u: failed checksum\n", dimm_number); - return 2; - } - - /* - * The part name in ASCII in the SPD EEPROM is not null terminated. - * Guarantee null termination here by presetting all bytes to 0 - * and copying the part name in ASCII from the SPD onto it - */ - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - if ((spd->info_size_crc & 0xF) > 1) - memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); - - /* DIMM organization parameters */ - pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; - pdimm->rank_density = compute_ranksize(spd); - pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; - pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); - if ((spd->bus_width >> 3) & 0x3) - pdimm->ec_sdram_width = 8; - else - pdimm->ec_sdram_width = 0; - pdimm->data_width = pdimm->primary_sdram_width - + pdimm->ec_sdram_width; - pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); - - /* These are the types defined by the JEDEC DDR3 SPD spec */ - pdimm->mirrored_dimm = 0; - pdimm->registered_dimm = 0; - switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { - case DDR3_SPD_MODULETYPE_RDIMM: - case DDR3_SPD_MODULETYPE_MINI_RDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: - /* Registered/buffered DIMMs */ - pdimm->registered_dimm = 1; - for (i = 0; i < 16; i += 2) { - u8 rcw = spd->mod_section.registered.rcw[i/2]; - pdimm->rcw[i] = (rcw >> 0) & 0x0F; - pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; - } - break; - - case DDR3_SPD_MODULETYPE_UDIMM: - case DDR3_SPD_MODULETYPE_SO_DIMM: - case DDR3_SPD_MODULETYPE_MICRO_DIMM: - case DDR3_SPD_MODULETYPE_MINI_UDIMM: - case DDR3_SPD_MODULETYPE_MINI_CDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: - case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: - case DDR3_SPD_MODULETYPE_LRDIMM: - case DDR3_SPD_MODULETYPE_16B_SO_DIMM: - case DDR3_SPD_MODULETYPE_32B_SO_DIMM: - /* Unbuffered DIMMs */ - if (spd->mod_section.unbuffered.addr_mapping & 0x1) - pdimm->mirrored_dimm = 1; - break; - - default: - printf("unknown module_type 0x%02X\n", spd->module_type); - return 1; - } - - /* SDRAM device parameters */ - pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; - pdimm->n_col_addr = (spd->addressing & 0x7) + 9; - pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7); - - /* - * The SPD spec has not the ECC bit, - * We consider the DIMM as ECC capability - * when the extension bus exist - */ - if (pdimm->ec_sdram_width) - pdimm->edc_config = 0x02; - else - pdimm->edc_config = 0x00; - - /* - * The SPD spec has not the burst length byte - * but DDR3 spec has nature BL8 and BC4, - * BL8 -bit3, BC4 -bit2 - */ - pdimm->burst_lengths_bitmask = 0x0c; - pdimm->row_density = __ilog2(pdimm->rank_density); - - /* MTB - medium timebase - * The unit in the SPD spec is ns, - * We convert it to ps. - * eg: MTB = 0.125ns (125ps) - */ - mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor; - pdimm->mtb_ps = mtb_ps; - - /* - * FTB - fine timebase - * use 1/10th of ps as our unit to avoid floating point - * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps - */ - ftb_10th_ps = - ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f); - pdimm->ftb_10th_ps = ftb_10th_ps; - /* - * sdram minimum cycle time - * we assume the MTB is 0.125ns - * eg: - * tck_min=15 MTB (1.875ns) ->DDR3-1066 - * =12 MTB (1.5ns) ->DDR3-1333 - * =10 MTB (1.25ns) ->DDR3-1600 - */ - pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + - (spd->fine_tck_min * ftb_10th_ps) / 10; - - /* - * CAS latency supported - * bit4 - CL4 - * bit5 - CL5 - * bit18 - CL18 - */ - pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; - - /* - * min CAS latency time - * eg: taa_min = - * DDR3-800D 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25ns) - */ - pdimm->taa_ps = spd->taa_min * mtb_ps + - (spd->fine_taa_min * ftb_10th_ps) / 10; - - /* - * min write recovery time - * eg: - * twr_min = 120 MTB (15ns) -> all speed grades. - */ - pdimm->twr_ps = spd->twr_min * mtb_ps; - - /* - * min RAS to CAS delay time - * eg: trcd_min = - * DDR3-800 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25) - */ - pdimm->trcd_ps = spd->trcd_min * mtb_ps + - (spd->fine_trcd_min * ftb_10th_ps) / 10; - - /* - * min row active to row active delay time - * eg: trrd_min = - * DDR3-800(1KB page) 80 MTB (10ns) - * DDR3-1333(1KB page) 48 MTB (6ns) - */ - pdimm->trrd_ps = spd->trrd_min * mtb_ps; - - /* - * min row precharge delay time - * eg: trp_min = - * DDR3-800D 100 MTB (12.5ns) - * DDR3-1066F 105 MTB (13.125ns) - * DDR3-1333H 108 MTB (13.5ns) - * DDR3-1600H 90 MTB (11.25ns) - */ - pdimm->trp_ps = spd->trp_min * mtb_ps + - (spd->fine_trp_min * ftb_10th_ps) / 10; - - /* min active to precharge delay time - * eg: tRAS_min = - * DDR3-800D 300 MTB (37.5ns) - * DDR3-1066F 300 MTB (37.5ns) - * DDR3-1333H 288 MTB (36ns) - * DDR3-1600H 280 MTB (35ns) - */ - pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) - * mtb_ps; - /* - * min active to actice/refresh delay time - * eg: tRC_min = - * DDR3-800D 400 MTB (50ns) - * DDR3-1066F 405 MTB (50.625ns) - * DDR3-1333H 396 MTB (49.5ns) - * DDR3-1600H 370 MTB (46.25ns) - */ - pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) - * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; - /* - * min refresh recovery delay time - * eg: tRFC_min = - * 512Mb 720 MTB (90ns) - * 1Gb 880 MTB (110ns) - * 2Gb 1280 MTB (160ns) - */ - pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) - * mtb_ps; - /* - * min internal write to read command delay time - * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. - * tWRT is at least 4 mclk independent of operating freq. - */ - pdimm->twtr_ps = spd->twtr_min * mtb_ps; - - /* - * min internal read to precharge command delay time - * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. - * tRTP is at least 4 mclk independent of operating freq. - */ - pdimm->trtp_ps = spd->trtp_min * mtb_ps; - - /* - * Average periodic refresh interval - * tREFI = 7.8 us at normal temperature range - * = 3.9 us at ext temperature range - */ - pdimm->refresh_rate_ps = 7800000; - if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { - pdimm->refresh_rate_ps = 3900000; - pdimm->extended_op_srt = 1; - } - - /* - * min four active window delay time - * eg: tfaw_min = - * DDR3-800(1KB page) 320 MTB (40ns) - * DDR3-1066(1KB page) 300 MTB (37.5ns) - * DDR3-1333(1KB page) 240 MTB (30ns) - * DDR3-1600(1KB page) 240 MTB (30ns) - */ - pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) - * mtb_ps; - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c deleted file mode 100644 index 3b661129cb..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ /dev/null @@ -1,1870 +0,0 @@ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - * York Sun [at freescale.com] - */ - -#include -#include -#include - -#include -#include "ddr.h" - -/* Option parameter Structures */ -struct options_string { - const char *option_name; - size_t offset; - unsigned int size; - const char printhex; -}; - -static unsigned int picos_to_mhz(unsigned int picos) -{ - return 1000000 / picos; -} - -static void print_option_table(const struct options_string *table, - int table_size, - const void *base) -{ - unsigned int i; - unsigned int *ptr; - unsigned long long *ptr_l; - - for (i = 0; i < table_size; i++) { - switch (table[i].size) { - case 4: - ptr = (unsigned int *) (base + table[i].offset); - if (table[i].printhex) { - printf("%s = 0x%08X\n", - table[i].option_name, *ptr); - } else { - printf("%s = %u\n", - table[i].option_name, *ptr); - } - break; - case 8: - ptr_l = (unsigned long long *) (base + table[i].offset); - printf("%s = %llu\n", - table[i].option_name, *ptr_l); - break; - default: - printf("Unrecognized size!\n"); - break; - } - } -} - -static int handle_option_table(const struct options_string *table, - int table_size, - void *base, - const char *opt, - const char *val) -{ - unsigned int i; - unsigned int value, *ptr; - unsigned long long value_l, *ptr_l; - - for (i = 0; i < table_size; i++) { - if (strcmp(table[i].option_name, opt) != 0) - continue; - switch (table[i].size) { - case 4: - value = simple_strtoul(val, NULL, 0); - ptr = base + table[i].offset; - *ptr = value; - break; - case 8: - value_l = simple_strtoull(val, NULL, 0); - ptr_l = base + table[i].offset; - *ptr_l = value_l; - break; - default: - printf("Unrecognized size!\n"); - break; - } - return 1; - } - - return 0; -} - -static void fsl_ddr_generic_edit(void *pdata, - void *pend, - unsigned int element_size, - unsigned int element_num, - unsigned int value) -{ - char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */ - - pcdata += element_num * element_size; - if ((pcdata + element_size) > (char *) pend) { - printf("trying to write past end of data\n"); - return; - } - - switch (element_size) { - case 1: - __raw_writeb(value, pcdata); - break; - case 2: - __raw_writew(value, pcdata); - break; - case 4: - __raw_writel(value, pcdata); - break; - default: - printf("unexpected element size %u\n", element_size); - break; - } -} - -static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - unsigned int dimm_num, - unsigned int element_num, - unsigned int value) -{ - generic_spd_eeprom_t *pspd; - - pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); - fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value); -} - -#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \ - sizeof((common_timing_params_t *)0)->x, 0} - -static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - const char *optname_str, - const char *value_str) -{ - common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; - - static const struct options_string options[] = { - COMMON_TIMING(tckmin_x_ps), - COMMON_TIMING(tckmax_ps), - COMMON_TIMING(tckmax_max_ps), - COMMON_TIMING(trcd_ps), - COMMON_TIMING(trp_ps), - COMMON_TIMING(tras_ps), - COMMON_TIMING(twr_ps), - COMMON_TIMING(twtr_ps), - COMMON_TIMING(trfc_ps), - COMMON_TIMING(trrd_ps), - COMMON_TIMING(trc_ps), - COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tis_ps), - COMMON_TIMING(tih_ps), - COMMON_TIMING(tds_ps), - COMMON_TIMING(tdh_ps), - COMMON_TIMING(trtp_ps), - COMMON_TIMING(tdqsq_max_ps), - COMMON_TIMING(tqhs_ps), - COMMON_TIMING(ndimms_present), - COMMON_TIMING(lowest_common_SPD_caslat), - COMMON_TIMING(highest_common_derated_caslat), - COMMON_TIMING(additive_latency), - COMMON_TIMING(all_dimms_burst_lengths_bitmask), - COMMON_TIMING(all_dimms_registered), - COMMON_TIMING(all_dimms_unbuffered), - COMMON_TIMING(all_dimms_ecc_capable), - COMMON_TIMING(total_mem), - COMMON_TIMING(base_address), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, optname_str, value_str)) - return; - - printf("Error: couldn't find option string %s\n", optname_str); -} - -#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ - sizeof((dimm_params_t *)0)->x, 0} - -static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - unsigned int dimm_num, - const char *optname_str, - const char *value_str) -{ - dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); - - static const struct options_string options[] = { - DIMM_PARM(n_ranks), - DIMM_PARM(data_width), - DIMM_PARM(primary_sdram_width), - DIMM_PARM(ec_sdram_width), - DIMM_PARM(registered_dimm), - DIMM_PARM(device_width), - - DIMM_PARM(n_row_addr), - DIMM_PARM(n_col_addr), - DIMM_PARM(edc_config), - DIMM_PARM(n_banks_per_sdram_device), - DIMM_PARM(burst_lengths_bitmask), - DIMM_PARM(row_density), - - DIMM_PARM(tckmin_x_ps), - DIMM_PARM(tckmin_x_minus_1_ps), - DIMM_PARM(tckmin_x_minus_2_ps), - DIMM_PARM(tckmax_ps), - - DIMM_PARM(caslat_x), - DIMM_PARM(caslat_x_minus_1), - DIMM_PARM(caslat_x_minus_2), - - DIMM_PARM(caslat_lowest_derated), - - DIMM_PARM(trcd_ps), - DIMM_PARM(trp_ps), - DIMM_PARM(tras_ps), - DIMM_PARM(twr_ps), - DIMM_PARM(twtr_ps), - DIMM_PARM(trfc_ps), - DIMM_PARM(trrd_ps), - DIMM_PARM(trc_ps), - DIMM_PARM(refresh_rate_ps), - - DIMM_PARM(tis_ps), - DIMM_PARM(tih_ps), - DIMM_PARM(tds_ps), - DIMM_PARM(tdh_ps), - DIMM_PARM(trtp_ps), - DIMM_PARM(tdqsq_max_ps), - DIMM_PARM(tqhs_ps), - - DIMM_PARM(rank_density), - DIMM_PARM(capacity), - DIMM_PARM(base_address), - }; - - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, optname_str, value_str)) - return; - - printf("couldn't find option string %s\n", optname_str); -} - -static void print_dimm_parameters(const dimm_params_t *pdimm) -{ - static const struct options_string options[] = { - DIMM_PARM(n_ranks), - DIMM_PARM(data_width), - DIMM_PARM(primary_sdram_width), - DIMM_PARM(ec_sdram_width), - DIMM_PARM(registered_dimm), - DIMM_PARM(device_width), - - DIMM_PARM(n_row_addr), - DIMM_PARM(n_col_addr), - DIMM_PARM(edc_config), - DIMM_PARM(n_banks_per_sdram_device), - - DIMM_PARM(tckmin_x_ps), - DIMM_PARM(tckmin_x_minus_1_ps), - DIMM_PARM(tckmin_x_minus_2_ps), - DIMM_PARM(tckmax_ps), - - DIMM_PARM(caslat_x), - DIMM_PARM(taa_ps), - DIMM_PARM(caslat_x_minus_1), - DIMM_PARM(caslat_x_minus_2), - DIMM_PARM(caslat_lowest_derated), - - DIMM_PARM(trcd_ps), - DIMM_PARM(trp_ps), - DIMM_PARM(tras_ps), - DIMM_PARM(twr_ps), - DIMM_PARM(twtr_ps), - DIMM_PARM(trfc_ps), - DIMM_PARM(trrd_ps), - DIMM_PARM(trc_ps), - DIMM_PARM(refresh_rate_ps), - - DIMM_PARM(tis_ps), - DIMM_PARM(tih_ps), - DIMM_PARM(tds_ps), - DIMM_PARM(tdh_ps), - DIMM_PARM(trtp_ps), - DIMM_PARM(tdqsq_max_ps), - DIMM_PARM(tqhs_ps), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (pdimm->n_ranks == 0) { - printf("DIMM not present\n"); - return; - } - printf("DIMM organization parameters:\n"); - printf("module part name = %s\n", pdimm->mpart); - printf("rank_density = %llu bytes (%llu megabytes)\n", - pdimm->rank_density, pdimm->rank_density / 0x100000); - printf("capacity = %llu bytes (%llu megabytes)\n", - pdimm->capacity, pdimm->capacity / 0x100000); - printf("burst_lengths_bitmask = %02X\n", - pdimm->burst_lengths_bitmask); - printf("base_addresss = %llu (%08llX %08llX)\n", - pdimm->base_address, - (pdimm->base_address >> 32), - pdimm->base_address & 0xFFFFFFFF); - print_option_table(options, n_opts, pdimm); -} - -static void print_lowest_common_dimm_parameters( - const common_timing_params_t *plcd_dimm_params) -{ - static const struct options_string options[] = { - COMMON_TIMING(tckmax_max_ps), - COMMON_TIMING(trcd_ps), - COMMON_TIMING(trp_ps), - COMMON_TIMING(tras_ps), - COMMON_TIMING(twr_ps), - COMMON_TIMING(twtr_ps), - COMMON_TIMING(trfc_ps), - COMMON_TIMING(trrd_ps), - COMMON_TIMING(trc_ps), - COMMON_TIMING(refresh_rate_ps), - COMMON_TIMING(tis_ps), - COMMON_TIMING(tds_ps), - COMMON_TIMING(tdh_ps), - COMMON_TIMING(trtp_ps), - COMMON_TIMING(tdqsq_max_ps), - COMMON_TIMING(tqhs_ps), - COMMON_TIMING(lowest_common_SPD_caslat), - COMMON_TIMING(highest_common_derated_caslat), - COMMON_TIMING(additive_latency), - COMMON_TIMING(ndimms_present), - COMMON_TIMING(all_dimms_registered), - COMMON_TIMING(all_dimms_unbuffered), - COMMON_TIMING(all_dimms_ecc_capable), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - /* Clock frequencies */ - printf("tckmin_x_ps = %u (%u MHz)\n", - plcd_dimm_params->tckmin_x_ps, - picos_to_mhz(plcd_dimm_params->tckmin_x_ps)); - printf("tckmax_ps = %u (%u MHz)\n", - plcd_dimm_params->tckmax_ps, - picos_to_mhz(plcd_dimm_params->tckmax_ps)); - printf("all_dimms_burst_lengths_bitmask = %02X\n", - plcd_dimm_params->all_dimms_burst_lengths_bitmask); - - print_option_table(options, n_opts, plcd_dimm_params); - - printf("total_mem = %llu (%llu megabytes)\n", - plcd_dimm_params->total_mem, - plcd_dimm_params->total_mem / 0x100000); - printf("base_address = %llu (%llu megabytes)\n", - plcd_dimm_params->base_address, - plcd_dimm_params->base_address / 0x100000); -} - -#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \ - sizeof((memctl_options_t *)0)->x, 0} -#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \ - offsetof(memctl_options_t, cs_local_opts[x].y), \ - sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0} - -static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, - unsigned int ctl_num, - const char *optname_str, - const char *value_str) -{ - memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); - /* - * This array all on the stack and *computed* each time this - * function is rung. - */ - static const struct options_string options[] = { - CTRL_OPTIONS_CS(0, odt_rd_cfg), - CTRL_OPTIONS_CS(0, odt_wr_cfg), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rd_cfg), - CTRL_OPTIONS_CS(1, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rd_cfg), - CTRL_OPTIONS_CS(2, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(3, odt_rd_cfg), - CTRL_OPTIONS_CS(3, odt_wr_cfg), -#endif -#if defined(CONFIG_FSL_DDR3) - CTRL_OPTIONS_CS(0, odt_rtt_norm), - CTRL_OPTIONS_CS(0, odt_rtt_wr), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rtt_norm), - CTRL_OPTIONS_CS(1, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rtt_norm), - CTRL_OPTIONS_CS(2, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(3, odt_rtt_norm), - CTRL_OPTIONS_CS(3, odt_rtt_wr), -#endif -#endif - CTRL_OPTIONS(memctl_interleaving), - CTRL_OPTIONS(memctl_interleaving_mode), - CTRL_OPTIONS(ba_intlv_ctl), - CTRL_OPTIONS(ecc_mode), - CTRL_OPTIONS(ecc_init_using_memctl), - CTRL_OPTIONS(dqs_config), - CTRL_OPTIONS(self_refresh_in_sleep), - CTRL_OPTIONS(dynamic_power), - CTRL_OPTIONS(data_bus_width), - CTRL_OPTIONS(burst_length), - CTRL_OPTIONS(cas_latency_override), - CTRL_OPTIONS(cas_latency_override_value), - CTRL_OPTIONS(use_derated_caslat), - CTRL_OPTIONS(additive_latency_override), - CTRL_OPTIONS(additive_latency_override_value), - CTRL_OPTIONS(clk_adjust), - CTRL_OPTIONS(cpo_override), - CTRL_OPTIONS(write_data_delay), - CTRL_OPTIONS(half_strength_driver_enable), - - /* - * These can probably be changed to 2T_EN and 3T_EN - * (using a leading numerical character) without problem - */ - CTRL_OPTIONS(twot_en), - CTRL_OPTIONS(threet_en), - CTRL_OPTIONS(ap_en), - CTRL_OPTIONS(x4_en), - CTRL_OPTIONS(bstopre), - CTRL_OPTIONS(wrlvl_override), - CTRL_OPTIONS(wrlvl_sample), - CTRL_OPTIONS(wrlvl_start), - CTRL_OPTIONS(rcw_override), - CTRL_OPTIONS(rcw_1), - CTRL_OPTIONS(rcw_2), - CTRL_OPTIONS(ddr_cdr1), - CTRL_OPTIONS(ddr_cdr2), - CTRL_OPTIONS(tcke_clock_pulse_width_ps), - CTRL_OPTIONS(tfaw_window_four_activates_ps), - CTRL_OPTIONS(trwt_override), - CTRL_OPTIONS(trwt), - }; - - static const unsigned int n_opts = ARRAY_SIZE(options); - - if (handle_option_table(options, n_opts, p, - optname_str, value_str)) - return; - - printf("couldn't find option string %s\n", optname_str); -} - -#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \ - sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1} -#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \ - offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \ - sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1} - -static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) -{ - unsigned int i; - static const struct options_string options[] = { - CFG_REGS_CS(0, bnds), - CFG_REGS_CS(0, config), - CFG_REGS_CS(0, config_2), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CFG_REGS_CS(1, bnds), - CFG_REGS_CS(1, config), - CFG_REGS_CS(1, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(2, bnds), - CFG_REGS_CS(2, config), - CFG_REGS_CS(2, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(3, bnds), - CFG_REGS_CS(3, config), - CFG_REGS_CS(3, config_2), -#endif - CFG_REGS(timing_cfg_3), - CFG_REGS(timing_cfg_0), - CFG_REGS(timing_cfg_1), - CFG_REGS(timing_cfg_2), - CFG_REGS(ddr_sdram_cfg), - CFG_REGS(ddr_sdram_cfg_2), - CFG_REGS(ddr_sdram_mode), - CFG_REGS(ddr_sdram_mode_2), - CFG_REGS(ddr_sdram_mode_3), - CFG_REGS(ddr_sdram_mode_4), - CFG_REGS(ddr_sdram_mode_5), - CFG_REGS(ddr_sdram_mode_6), - CFG_REGS(ddr_sdram_mode_7), - CFG_REGS(ddr_sdram_mode_8), - CFG_REGS(ddr_sdram_interval), - CFG_REGS(ddr_data_init), - CFG_REGS(ddr_sdram_clk_cntl), - CFG_REGS(ddr_init_addr), - CFG_REGS(ddr_init_ext_addr), - CFG_REGS(timing_cfg_4), - CFG_REGS(timing_cfg_5), - CFG_REGS(ddr_zq_cntl), - CFG_REGS(ddr_wrlvl_cntl), - CFG_REGS(ddr_wrlvl_cntl_2), - CFG_REGS(ddr_wrlvl_cntl_3), - CFG_REGS(ddr_sr_cntr), - CFG_REGS(ddr_sdram_rcw_1), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_cdr1), - CFG_REGS(ddr_cdr2), - CFG_REGS(err_disable), - CFG_REGS(err_int_en), - CFG_REGS(ddr_eor), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - print_option_table(options, n_opts, ddr); - - for (i = 0; i < 32; i++) - printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); -} - -static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, - unsigned int ctrl_num, - const char *regname, - const char *value_str) -{ - unsigned int i; - fsl_ddr_cfg_regs_t *ddr; - char buf[20]; - static const struct options_string options[] = { - CFG_REGS_CS(0, bnds), - CFG_REGS_CS(0, config), - CFG_REGS_CS(0, config_2), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CFG_REGS_CS(1, bnds), - CFG_REGS_CS(1, config), - CFG_REGS_CS(1, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CFG_REGS_CS(2, bnds), - CFG_REGS_CS(2, config), - CFG_REGS_CS(2, config_2), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CFG_REGS_CS(3, bnds), - CFG_REGS_CS(3, config), - CFG_REGS_CS(3, config_2), -#endif - CFG_REGS(timing_cfg_3), - CFG_REGS(timing_cfg_0), - CFG_REGS(timing_cfg_1), - CFG_REGS(timing_cfg_2), - CFG_REGS(ddr_sdram_cfg), - CFG_REGS(ddr_sdram_cfg_2), - CFG_REGS(ddr_sdram_mode), - CFG_REGS(ddr_sdram_mode_2), - CFG_REGS(ddr_sdram_mode_3), - CFG_REGS(ddr_sdram_mode_4), - CFG_REGS(ddr_sdram_mode_5), - CFG_REGS(ddr_sdram_mode_6), - CFG_REGS(ddr_sdram_mode_7), - CFG_REGS(ddr_sdram_mode_8), - CFG_REGS(ddr_sdram_interval), - CFG_REGS(ddr_data_init), - CFG_REGS(ddr_sdram_clk_cntl), - CFG_REGS(ddr_init_addr), - CFG_REGS(ddr_init_ext_addr), - CFG_REGS(timing_cfg_4), - CFG_REGS(timing_cfg_5), - CFG_REGS(ddr_zq_cntl), - CFG_REGS(ddr_wrlvl_cntl), - CFG_REGS(ddr_wrlvl_cntl_2), - CFG_REGS(ddr_wrlvl_cntl_3), - CFG_REGS(ddr_sr_cntr), - CFG_REGS(ddr_sdram_rcw_1), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_cdr1), - CFG_REGS(ddr_cdr2), - CFG_REGS(err_disable), - CFG_REGS(err_int_en), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_sdram_rcw_2), - CFG_REGS(ddr_eor), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - debug("fsl_ddr_regs_edit: ctrl_num = %u, " - "regname = %s, value = %s\n", - ctrl_num, regname, value_str); - if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS) - return; - - ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); - - if (handle_option_table(options, n_opts, ddr, regname, value_str)) - return; - - for (i = 0; i < 32; i++) { - unsigned int value = simple_strtoul(value_str, NULL, 0); - sprintf(buf, "debug_%u", i + 1); - if (strcmp(buf, regname) == 0) { - ddr->debug[i] = value; - return; - } - } - printf("Error: couldn't find register string %s\n", regname); -} - -#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \ - sizeof((memctl_options_t *)0)->x, 1} - -static void print_memctl_options(const memctl_options_t *popts) -{ - static const struct options_string options[] = { - CTRL_OPTIONS_CS(0, odt_rd_cfg), - CTRL_OPTIONS_CS(0, odt_wr_cfg), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rd_cfg), - CTRL_OPTIONS_CS(1, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rd_cfg), - CTRL_OPTIONS_CS(2, odt_wr_cfg), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CTRL_OPTIONS_CS(3, odt_rd_cfg), - CTRL_OPTIONS_CS(3, odt_wr_cfg), -#endif -#if defined(CONFIG_FSL_DDR3) - CTRL_OPTIONS_CS(0, odt_rtt_norm), - CTRL_OPTIONS_CS(0, odt_rtt_wr), -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) - CTRL_OPTIONS_CS(1, odt_rtt_norm), - CTRL_OPTIONS_CS(1, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) - CTRL_OPTIONS_CS(2, odt_rtt_norm), - CTRL_OPTIONS_CS(2, odt_rtt_wr), -#endif -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) - CTRL_OPTIONS_CS(3, odt_rtt_norm), - CTRL_OPTIONS_CS(3, odt_rtt_wr), -#endif -#endif - CTRL_OPTIONS(memctl_interleaving), - CTRL_OPTIONS(memctl_interleaving_mode), - CTRL_OPTIONS_HEX(ba_intlv_ctl), - CTRL_OPTIONS(ecc_mode), - CTRL_OPTIONS(ecc_init_using_memctl), - CTRL_OPTIONS(dqs_config), - CTRL_OPTIONS(self_refresh_in_sleep), - CTRL_OPTIONS(dynamic_power), - CTRL_OPTIONS(data_bus_width), - CTRL_OPTIONS(burst_length), - CTRL_OPTIONS(cas_latency_override), - CTRL_OPTIONS(cas_latency_override_value), - CTRL_OPTIONS(use_derated_caslat), - CTRL_OPTIONS(additive_latency_override), - CTRL_OPTIONS(additive_latency_override_value), - CTRL_OPTIONS(clk_adjust), - CTRL_OPTIONS(cpo_override), - CTRL_OPTIONS(write_data_delay), - CTRL_OPTIONS(half_strength_driver_enable), - /* - * These can probably be changed to 2T_EN and 3T_EN - * (using a leading numerical character) without problem - */ - CTRL_OPTIONS(twot_en), - CTRL_OPTIONS(threet_en), - CTRL_OPTIONS(registered_dimm_en), - CTRL_OPTIONS(ap_en), - CTRL_OPTIONS(x4_en), - CTRL_OPTIONS(bstopre), - CTRL_OPTIONS(wrlvl_override), - CTRL_OPTIONS(wrlvl_sample), - CTRL_OPTIONS(wrlvl_start), - CTRL_OPTIONS(rcw_override), - CTRL_OPTIONS(rcw_1), - CTRL_OPTIONS(rcw_2), - CTRL_OPTIONS_HEX(ddr_cdr1), - CTRL_OPTIONS_HEX(ddr_cdr2), - CTRL_OPTIONS(tcke_clock_pulse_width_ps), - CTRL_OPTIONS(tfaw_window_four_activates_ps), - CTRL_OPTIONS(trwt_override), - CTRL_OPTIONS(trwt), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - print_option_table(options, n_opts, popts); -} - -#ifdef CONFIG_FSL_DDR1 -void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) -{ - unsigned int i; - - printf("%-3d : %02x %s\n", 0, spd->info_size, - " spd->info_size, * 0 # bytes written into serial memory *"); - printf("%-3d : %02x %s\n", 1, spd->chip_size, - " spd->chip_size, * 1 Total # bytes of SPD memory device *"); - printf("%-3d : %02x %s\n", 2, spd->mem_type, - " spd->mem_type, * 2 Fundamental memory type *"); - printf("%-3d : %02x %s\n", 3, spd->nrow_addr, - " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); - printf("%-3d : %02x %s\n", 4, spd->ncol_addr, - " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); - printf("%-3d : %02x %s\n", 5, spd->nrows, - " spd->nrows * 5 # of DIMM Banks *"); - printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, - " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); - printf("%-3d : %02x %s\n", 7, spd->dataw_msb, - " spd->dataw_msb, * 7 Data Width msb of this assembly *"); - printf("%-3d : %02x %s\n", 8, spd->voltage, - " spd->voltage, * 8 Voltage intf std of this assembly *"); - printf("%-3d : %02x %s\n", 9, spd->clk_cycle, - " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); - printf("%-3d : %02x %s\n", 10, spd->clk_access, - " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); - printf("%-3d : %02x %s\n", 11, spd->config, - " spd->config, * 11 DIMM Configuration type *"); - printf("%-3d : %02x %s\n", 12, spd->refresh, - " spd->refresh, * 12 Refresh Rate/Type *"); - printf("%-3d : %02x %s\n", 13, spd->primw, - " spd->primw, * 13 Primary SDRAM Width *"); - printf("%-3d : %02x %s\n", 14, spd->ecw, - " spd->ecw, * 14 Error Checking SDRAM width *"); - printf("%-3d : %02x %s\n", 15, spd->min_delay, - " spd->min_delay, * 15 Back to Back Random Access *"); - printf("%-3d : %02x %s\n", 16, spd->burstl, - " spd->burstl, * 16 Burst Lengths Supported *"); - printf("%-3d : %02x %s\n", 17, spd->nbanks, - " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); - printf("%-3d : %02x %s\n", 18, spd->cas_lat, - " spd->cas_lat, * 18 CAS# Latencies Supported *"); - printf("%-3d : %02x %s\n", 19, spd->cs_lat, - " spd->cs_lat, * 19 Chip Select Latency *"); - printf("%-3d : %02x %s\n", 20, spd->write_lat, - " spd->write_lat, * 20 Write Latency/Recovery *"); - printf("%-3d : %02x %s\n", 21, spd->mod_attr, - " spd->mod_attr, * 21 SDRAM Module Attributes *"); - printf("%-3d : %02x %s\n", 22, spd->dev_attr, - " spd->dev_attr, * 22 SDRAM Device Attributes *"); - printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, - " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); - printf("%-3d : %02x %s\n", 24, spd->clk_access2, - " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); - printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, - " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); - printf("%-3d : %02x %s\n", 26, spd->clk_access3, - " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); - printf("%-3d : %02x %s\n", 27, spd->trp, - " spd->trp, * 27 Min Row Precharge Time (tRP)*"); - printf("%-3d : %02x %s\n", 28, spd->trrd, - " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); - printf("%-3d : %02x %s\n", 29, spd->trcd, - " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); - printf("%-3d : %02x %s\n", 30, spd->tras, - " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); - printf("%-3d : %02x %s\n", 31, spd->bank_dens, - " spd->bank_dens, * 31 Density of each bank on module *"); - printf("%-3d : %02x %s\n", 32, spd->ca_setup, - " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); - printf("%-3d : %02x %s\n", 33, spd->ca_hold, - " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); - printf("%-3d : %02x %s\n", 34, spd->data_setup, - " spd->data_setup, * 34 Data signal input setup time *"); - printf("%-3d : %02x %s\n", 35, spd->data_hold, - " spd->data_hold, * 35 Data signal input hold time *"); - printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], - " spd->res_36_40[0], * 36 Reserved / tWR *"); - printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], - " spd->res_36_40[1], * 37 Reserved / tWTR *"); - printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], - " spd->res_36_40[2], * 38 Reserved / tRTP *"); - printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], - " spd->res_36_40[3], * 39 Reserved / mem_probe *"); - printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], - " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); - printf("%-3d : %02x %s\n", 41, spd->trc, - " spd->trc, * 41 Min Active to Auto refresh time tRC *"); - printf("%-3d : %02x %s\n", 42, spd->trfc, - " spd->trfc, * 42 Min Auto to Active period tRFC *"); - printf("%-3d : %02x %s\n", 43, spd->tckmax, - " spd->tckmax, * 43 Max device cycle time tCKmax *"); - printf("%-3d : %02x %s\n", 44, spd->tdqsq, - " spd->tdqsq, * 44 Max DQS to DQ skew *"); - printf("%-3d : %02x %s\n", 45, spd->tqhs, - " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); - printf("%-3d : %02x %s\n", 46, spd->res_46, - " spd->res_46, * 46 Reserved/ PLL Relock time *"); - printf("%-3d : %02x %s\n", 47, spd->dimm_height, - " spd->dimm_height * 47 SDRAM DIMM Height *"); - - printf("%-3d-%3d: ", 48, 61); - - for (i = 0; i < 14; i++) - printf("%02x", spd->res_48_61[i]); - - printf(" * 48-61 IDD in SPD and Reserved space *\n"); - - printf("%-3d : %02x %s\n", 62, spd->spd_rev, - " spd->spd_rev, * 62 SPD Data Revision Code *"); - printf("%-3d : %02x %s\n", 63, spd->cksum, - " spd->cksum, * 63 Checksum for bytes 0-62 *"); - printf("%-3d-%3d: ", 64, 71); - - for (i = 0; i < 8; i++) - printf("%02x", spd->mid[i]); - - printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); - printf("%-3d : %02x %s\n", 72, spd->mloc, - " spd->mloc, * 72 Manufacturing Location *"); - - printf("%-3d-%3d: >>", 73, 90); - - for (i = 0; i < 18; i++) - printf("%c", spd->mpart[i]); - - printf("<<* 73 Manufacturer's Part Number *\n"); - - printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], - "* 91 Revision Code *"); - printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], - "* 93 Manufacturing Date *"); - printf("%-3d-%3d: ", 95, 98); - - for (i = 0; i < 4; i++) - printf("%02x", spd->sernum[i]); - - printf("* 95 Assembly Serial Number *\n"); - - printf("%-3d-%3d: ", 99, 127); - - for (i = 0; i < 27; i++) - printf("%02x", spd->mspec[i]); - - printf("* 99 Manufacturer Specific Data *\n"); -} -#endif - -#ifdef CONFIG_FSL_DDR2 -void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) -{ - unsigned int i; - - printf("%-3d : %02x %s\n", 0, spd->info_size, - " spd->info_size, * 0 # bytes written into serial memory *"); - printf("%-3d : %02x %s\n", 1, spd->chip_size, - " spd->chip_size, * 1 Total # bytes of SPD memory device *"); - printf("%-3d : %02x %s\n", 2, spd->mem_type, - " spd->mem_type, * 2 Fundamental memory type *"); - printf("%-3d : %02x %s\n", 3, spd->nrow_addr, - " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); - printf("%-3d : %02x %s\n", 4, spd->ncol_addr, - " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); - printf("%-3d : %02x %s\n", 5, spd->mod_ranks, - " spd->mod_ranks * 5 # of Module Rows on this assembly *"); - printf("%-3d : %02x %s\n", 6, spd->dataw, - " spd->dataw, * 6 Data Width of this assembly *"); - printf("%-3d : %02x %s\n", 7, spd->res_7, - " spd->res_7, * 7 Reserved *"); - printf("%-3d : %02x %s\n", 8, spd->voltage, - " spd->voltage, * 8 Voltage intf std of this assembly *"); - printf("%-3d : %02x %s\n", 9, spd->clk_cycle, - " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); - printf("%-3d : %02x %s\n", 10, spd->clk_access, - " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); - printf("%-3d : %02x %s\n", 11, spd->config, - " spd->config, * 11 DIMM Configuration type *"); - printf("%-3d : %02x %s\n", 12, spd->refresh, - " spd->refresh, * 12 Refresh Rate/Type *"); - printf("%-3d : %02x %s\n", 13, spd->primw, - " spd->primw, * 13 Primary SDRAM Width *"); - printf("%-3d : %02x %s\n", 14, spd->ecw, - " spd->ecw, * 14 Error Checking SDRAM width *"); - printf("%-3d : %02x %s\n", 15, spd->res_15, - " spd->res_15, * 15 Reserved *"); - printf("%-3d : %02x %s\n", 16, spd->burstl, - " spd->burstl, * 16 Burst Lengths Supported *"); - printf("%-3d : %02x %s\n", 17, spd->nbanks, - " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); - printf("%-3d : %02x %s\n", 18, spd->cas_lat, - " spd->cas_lat, * 18 CAS# Latencies Supported *"); - printf("%-3d : %02x %s\n", 19, spd->mech_char, - " spd->mech_char, * 19 Mechanical Characteristics *"); - printf("%-3d : %02x %s\n", 20, spd->dimm_type, - " spd->dimm_type, * 20 DIMM type *"); - printf("%-3d : %02x %s\n", 21, spd->mod_attr, - " spd->mod_attr, * 21 SDRAM Module Attributes *"); - printf("%-3d : %02x %s\n", 22, spd->dev_attr, - " spd->dev_attr, * 22 SDRAM Device Attributes *"); - printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, - " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); - printf("%-3d : %02x %s\n", 24, spd->clk_access2, - " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); - printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, - " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); - printf("%-3d : %02x %s\n", 26, spd->clk_access3, - " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); - printf("%-3d : %02x %s\n", 27, spd->trp, - " spd->trp, * 27 Min Row Precharge Time (tRP)*"); - printf("%-3d : %02x %s\n", 28, spd->trrd, - " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); - printf("%-3d : %02x %s\n", 29, spd->trcd, - " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); - printf("%-3d : %02x %s\n", 30, spd->tras, - " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); - printf("%-3d : %02x %s\n", 31, spd->rank_dens, - " spd->rank_dens, * 31 Density of each rank on module *"); - printf("%-3d : %02x %s\n", 32, spd->ca_setup, - " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); - printf("%-3d : %02x %s\n", 33, spd->ca_hold, - " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); - printf("%-3d : %02x %s\n", 34, spd->data_setup, - " spd->data_setup, * 34 Data signal input setup time *"); - printf("%-3d : %02x %s\n", 35, spd->data_hold, - " spd->data_hold, * 35 Data signal input hold time *"); - printf("%-3d : %02x %s\n", 36, spd->twr, - " spd->twr, * 36 Write Recovery time tWR *"); - printf("%-3d : %02x %s\n", 37, spd->twtr, - " spd->twtr, * 37 Int write to read delay tWTR *"); - printf("%-3d : %02x %s\n", 38, spd->trtp, - " spd->trtp, * 38 Int read to precharge delay tRTP *"); - printf("%-3d : %02x %s\n", 39, spd->mem_probe, - " spd->mem_probe, * 39 Mem analysis probe characteristics *"); - printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, - " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); - printf("%-3d : %02x %s\n", 41, spd->trc, - " spd->trc, * 41 Min Active to Auto refresh time tRC *"); - printf("%-3d : %02x %s\n", 42, spd->trfc, - " spd->trfc, * 42 Min Auto to Active period tRFC *"); - printf("%-3d : %02x %s\n", 43, spd->tckmax, - " spd->tckmax, * 43 Max device cycle time tCKmax *"); - printf("%-3d : %02x %s\n", 44, spd->tdqsq, - " spd->tdqsq, * 44 Max DQS to DQ skew *"); - printf("%-3d : %02x %s\n", 45, spd->tqhs, - " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); - printf("%-3d : %02x %s\n", 46, spd->pll_relock, - " spd->pll_relock, * 46 PLL Relock time *"); - printf("%-3d : %02x %s\n", 47, spd->t_casemax, - " spd->t_casemax, * 47 t_casemax *"); - printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram, - " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package " - "from Top (Case) to Ambient (Psi T-A DRAM) *"); - printf("%-3d : %02x %s\n", 49, spd->dt0_mode, - " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " - "Ambient due to Activate-Precharge/Mode Bits " - "(DT0/Mode Bits) *)"); - printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, - " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " - "Ambient due to Precharge/Quiet Standby " - "(DT2N/DT2Q) *"); - printf("%-3d : %02x %s\n", 51, spd->dt2p, - " spd->dt2p, * 51 DRAM Case Temperature Rise from " - "Ambient due to Precharge Power-Down (DT2P) *"); - printf("%-3d : %02x %s\n", 52, spd->dt3n, - " spd->dt3n, * 52 DRAM Case Temperature Rise from " - "Ambient due to Active Standby (DT3N) *"); - printf("%-3d : %02x %s\n", 53, spd->dt3pfast, - " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " - "Ambient due to Active Power-Down with Fast PDN Exit " - "(DT3Pfast) *"); - printf("%-3d : %02x %s\n", 54, spd->dt3pslow, - " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " - "Ambient due to Active Power-Down with Slow PDN Exit " - "(DT3Pslow) *"); - printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, - " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " - "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " - "(DT4R/DT4R4W Mode Bit) *"); - printf("%-3d : %02x %s\n", 56, spd->dt5b, - " spd->dt5b, * 56 DRAM Case Temperature Rise from " - "Ambient due to Burst Refresh (DT5B) *"); - printf("%-3d : %02x %s\n", 57, spd->dt7, - " spd->dt7, * 57 DRAM Case Temperature Rise from " - "Ambient due to Bank Interleave Reads with " - "Auto-Precharge (DT7) *"); - printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll, - " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form" - " Top (Case) to Ambient (Psi T-A PLL) *"); - printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg, - " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package" - " from Top (Case) to Ambient (Psi T-A Register) *"); - printf("%-3d : %02x %s\n", 60, spd->dtpllactive, - " spd->dtpllactive, * 60 PLL Case Temperature Rise from " - "Ambient due to PLL Active (DT PLL Active) *"); - printf("%-3d : %02x %s\n", 61, spd->dtregact, - " spd->dtregact, " - "* 61 Register Case Temperature Rise from Ambient due to " - "Register Active/Mode Bit (DT Register Active/Mode Bit) *"); - printf("%-3d : %02x %s\n", 62, spd->spd_rev, - " spd->spd_rev, * 62 SPD Data Revision Code *"); - printf("%-3d : %02x %s\n", 63, spd->cksum, - " spd->cksum, * 63 Checksum for bytes 0-62 *"); - - printf("%-3d-%3d: ", 64, 71); - - for (i = 0; i < 8; i++) - printf("%02x", spd->mid[i]); - - printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); - - printf("%-3d : %02x %s\n", 72, spd->mloc, - " spd->mloc, * 72 Manufacturing Location *"); - - printf("%-3d-%3d: >>", 73, 90); - for (i = 0; i < 18; i++) - printf("%c", spd->mpart[i]); - - - printf("<<* 73 Manufacturer's Part Number *\n"); - - printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], - "* 91 Revision Code *"); - printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], - "* 93 Manufacturing Date *"); - printf("%-3d-%3d: ", 95, 98); - - for (i = 0; i < 4; i++) - printf("%02x", spd->sernum[i]); - - printf("* 95 Assembly Serial Number *\n"); - - printf("%-3d-%3d: ", 99, 127); - for (i = 0; i < 27; i++) - printf("%02x", spd->mspec[i]); - - - printf("* 99 Manufacturer Specific Data *\n"); -} -#endif - -#ifdef CONFIG_FSL_DDR3 -void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) -{ - unsigned int i; - - /* General Section: Bytes 0-59 */ - -#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); -#define PRINT_NNXXS(n0, n1, x0, x1, s) \ - printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); - - PRINT_NXS(0, spd->info_size_crc, - "info_size_crc bytes written into serial memory, " - "CRC coverage"); - PRINT_NXS(1, spd->spd_rev, - "spd_rev SPD Revision"); - PRINT_NXS(2, spd->mem_type, - "mem_type Key Byte / DRAM Device Type"); - PRINT_NXS(3, spd->module_type, - "module_type Key Byte / Module Type"); - PRINT_NXS(4, spd->density_banks, - "density_banks SDRAM Density and Banks"); - PRINT_NXS(5, spd->addressing, - "addressing SDRAM Addressing"); - PRINT_NXS(6, spd->module_vdd, - "module_vdd Module Nominal Voltage, VDD"); - PRINT_NXS(7, spd->organization, - "organization Module Organization"); - PRINT_NXS(8, spd->bus_width, - "bus_width Module Memory Bus Width"); - PRINT_NXS(9, spd->ftb_div, - "ftb_div Fine Timebase (FTB) Dividend / Divisor"); - PRINT_NXS(10, spd->mtb_dividend, - "mtb_dividend Medium Timebase (MTB) Dividend"); - PRINT_NXS(11, spd->mtb_divisor, - "mtb_divisor Medium Timebase (MTB) Divisor"); - PRINT_NXS(12, spd->tck_min, - "tck_min SDRAM Minimum Cycle Time"); - PRINT_NXS(13, spd->res_13, - "res_13 Reserved"); - PRINT_NXS(14, spd->caslat_lsb, - "caslat_lsb CAS Latencies Supported, LSB"); - PRINT_NXS(15, spd->caslat_msb, - "caslat_msb CAS Latencies Supported, MSB"); - PRINT_NXS(16, spd->taa_min, - "taa_min Min CAS Latency Time"); - PRINT_NXS(17, spd->twr_min, - "twr_min Min Write REcovery Time"); - PRINT_NXS(18, spd->trcd_min, - "trcd_min Min RAS# to CAS# Delay Time"); - PRINT_NXS(19, spd->trrd_min, - "trrd_min Min Row Active to Row Active Delay Time"); - PRINT_NXS(20, spd->trp_min, - "trp_min Min Row Precharge Delay Time"); - PRINT_NXS(21, spd->tras_trc_ext, - "tras_trc_ext Upper Nibbles for tRAS and tRC"); - PRINT_NXS(22, spd->tras_min_lsb, - "tras_min_lsb Min Active to Precharge Delay Time, LSB"); - PRINT_NXS(23, spd->trc_min_lsb, - "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB"); - PRINT_NXS(24, spd->trfc_min_lsb, - "trfc_min_lsb Min Refresh Recovery Delay Time LSB"); - PRINT_NXS(25, spd->trfc_min_msb, - "trfc_min_msb Min Refresh Recovery Delay Time MSB"); - PRINT_NXS(26, spd->twtr_min, - "twtr_min Min Internal Write to Read Command Delay Time"); - PRINT_NXS(27, spd->trtp_min, - "trtp_min " - "Min Internal Read to Precharge Command Delay Time"); - PRINT_NXS(28, spd->tfaw_msb, - "tfaw_msb Upper Nibble for tFAW"); - PRINT_NXS(29, spd->tfaw_min, - "tfaw_min Min Four Activate Window Delay Time"); - PRINT_NXS(30, spd->opt_features, - "opt_features SDRAM Optional Features"); - PRINT_NXS(31, spd->therm_ref_opt, - "therm_ref_opt SDRAM Thermal and Refresh Opts"); - PRINT_NXS(32, spd->therm_sensor, - "therm_sensor SDRAM Thermal Sensor"); - PRINT_NXS(33, spd->device_type, - "device_type SDRAM Device Type"); - PRINT_NXS(34, spd->fine_tck_min, - "fine_tck_min Fine offset for tCKmin"); - PRINT_NXS(35, spd->fine_taa_min, - "fine_taa_min Fine offset for tAAmin"); - PRINT_NXS(36, spd->fine_trcd_min, - "fine_trcd_min Fine offset for tRCDmin"); - PRINT_NXS(37, spd->fine_trp_min, - "fine_trp_min Fine offset for tRPmin"); - PRINT_NXS(38, spd->fine_trc_min, - "fine_trc_min Fine offset for tRCmin"); - - printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ - - for (i = 39; i <= 59; i++) - printf("%02x ", spd->res_39_59[i - 39]); - - puts("\n"); - - switch (spd->module_type) { - case 0x02: /* UDIMM */ - case 0x03: /* SO-DIMM */ - case 0x04: /* Micro-DIMM */ - case 0x06: /* Mini-UDIMM */ - PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, - "mod_height (Unbuffered) Module Nominal Height"); - PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, - "mod_thickness (Unbuffered) Module Maximum Thickness"); - PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, - "ref_raw_card (Unbuffered) Reference Raw Card Used"); - PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, - "addr_mapping (Unbuffered) Address mapping from " - "Edge Connector to DRAM"); - break; - case 0x01: /* RDIMM */ - case 0x05: /* Mini-RDIMM */ - PRINT_NXS(60, spd->mod_section.registered.mod_height, - "mod_height (Registered) Module Nominal Height"); - PRINT_NXS(61, spd->mod_section.registered.mod_thickness, - "mod_thickness (Registered) Module Maximum Thickness"); - PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, - "ref_raw_card (Registered) Reference Raw Card Used"); - PRINT_NXS(63, spd->mod_section.registered.modu_attr, - "modu_attr (Registered) DIMM Module Attributes"); - PRINT_NXS(64, spd->mod_section.registered.thermal, - "thermal (Registered) Thermal Heat " - "Spreader Solution"); - PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, - "reg_id_lo (Registered) Register Manufacturer ID " - "Code, LSB"); - PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, - "reg_id_hi (Registered) Register Manufacturer ID " - "Code, MSB"); - PRINT_NXS(67, spd->mod_section.registered.reg_rev, - "reg_rev (Registered) Register " - "Revision Number"); - PRINT_NXS(68, spd->mod_section.registered.reg_type, - "reg_type (Registered) Register Type"); - for (i = 69; i <= 76; i++) { - printf("%-3d : %02x rcw[%d]\n", i, - spd->mod_section.registered.rcw[i-69], i-69); - } - break; - default: - /* Module-specific Section, Unsupported Module Type */ - printf("%-3d-%3d: ", 60, 116); - - for (i = 60; i <= 116; i++) - printf("%02x", spd->mod_section.uc[i - 60]); - - break; - } - - /* Unique Module ID: Bytes 117-125 */ - PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); - PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); - PRINT_NXS(119, spd->mloc, "Mfg Location"); - PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); - - printf("%-3d-%3d: ", 122, 125); - - for (i = 122; i <= 125; i++) - printf("%02x ", spd->sernum[i - 122]); - printf(" Module Serial Number\n"); - - /* CRC: Bytes 126-127 */ - PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); - - /* Other Manufacturer Fields and User Space: Bytes 128-255 */ - printf("%-3d-%3d: ", 128, 145); - for (i = 128; i <= 145; i++) - printf("%02x ", spd->mpart[i - 128]); - printf(" Mfg's Module Part Number\n"); - - PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], - "Module Revision code"); - - PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); - PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); - - printf("%-3d-%3d: ", 150, 175); - for (i = 150; i <= 175; i++) - printf("%02x ", spd->msd[i - 150]); - printf(" Mfg's Specific Data\n"); - - printf("%-3d-%3d: ", 176, 255); - for (i = 176; i <= 255; i++) - printf("%02x", spd->cust[i - 176]); - printf(" Mfg's Specific Data\n"); - -} -#endif - -static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) -{ -#if defined(CONFIG_FSL_DDR1) - ddr1_spd_dump(spd); -#elif defined(CONFIG_FSL_DDR2) - ddr2_spd_dump(spd); -#elif defined(CONFIG_FSL_DDR3) - ddr3_spd_dump(spd); -#endif -} - -static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo, - unsigned int ctrl_mask, - unsigned int dimm_mask, - unsigned int do_mask) -{ - unsigned int i, j, retval; - - /* STEP 1: DIMM SPD data */ - if (do_mask & STEP_GET_SPD) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - if (!(dimm_mask & (1 << j))) - continue; - - printf("SPD info: Controller=%u " - "DIMM=%u\n", i, j); - generic_spd_dump( - &(pinfo->spd_installed_dimms[i][j])); - printf("\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 2: DIMM Parameters */ - if (do_mask & STEP_COMPUTE_DIMM_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - if (!(dimm_mask & (1 << j))) - continue; - printf("DIMM parameters: Controller=%u " - "DIMM=%u\n", i, j); - print_dimm_parameters( - &(pinfo->dimm_params[i][j])); - printf("\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 3: Common Parameters */ - if (do_mask & STEP_COMPUTE_COMMON_PARMS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("\"lowest common\" DIMM parameters: " - "Controller=%u\n", i); - print_lowest_common_dimm_parameters( - &pinfo->common_timing_params[i]); - printf("\n"); - } - printf("\n"); - } - - /* STEP 4: User Configuration Options */ - if (do_mask & STEP_GATHER_OPTS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("User Config Options: Controller=%u\n", i); - print_memctl_options(&pinfo->memctl_opts[i]); - printf("\n"); - } - printf("\n"); - } - - /* STEP 5: Address assignment */ - if (do_mask & STEP_ASSIGN_ADDRESSES) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - printf("Address Assignment: Controller=%u " - "DIMM=%u\n", i, j); - printf("Don't have this functionality yet\n"); - } - printf("\n"); - } - printf("\n"); - } - - /* STEP 6: computed controller register values */ - if (do_mask & STEP_COMPUTE_REGS) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (!(ctrl_mask & (1 << i))) - continue; - printf("Computed Register Values: Controller=%u\n", i); - print_fsl_memctl_config_regs( - &pinfo->fsl_ddr_config_reg[i]); - retval = check_fsl_memctl_config_regs( - &pinfo->fsl_ddr_config_reg[i]); - if (retval) { - printf("check_fsl_memctl_config_regs " - "result = %u\n", retval); - } - printf("\n"); - } - printf("\n"); - } -} - -struct data_strings { - const char *data_name; - unsigned int step_mask; - unsigned int dimm_number_required; -}; - -#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm} - -static unsigned int fsl_ddr_parse_interactive_cmd( - char **argv, - int argc, - unsigned int *pstep_mask, - unsigned int *pctlr_mask, - unsigned int *pdimm_mask, - unsigned int *pdimm_number_required - ) { - - static const struct data_strings options[] = { - DATA_OPTIONS(spd, STEP_GET_SPD, 1), - DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1), - DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0), - DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0), - DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0), - DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0), - }; - static const unsigned int n_opts = ARRAY_SIZE(options); - - unsigned int i, j; - unsigned int error = 0; - - for (i = 1; i < argc; i++) { - unsigned int matched = 0; - - for (j = 0; j < n_opts; j++) { - if (strcmp(options[j].data_name, argv[i]) != 0) - continue; - *pstep_mask |= options[j].step_mask; - *pdimm_number_required = - options[j].dimm_number_required; - matched = 1; - break; - } - - if (matched) - continue; - - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) - *pctlr_mask |= 1 << (c - '0'); - continue; - } - - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) - *pdimm_mask |= 1 << (c - '0'); - continue; - } - - printf("unknown arg %s\n", argv[i]); - *pstep_mask = 0; - error = 1; - break; - } - - return error; -} - -int fsl_ddr_interactive_env_var_exists(void) -{ - char buffer[CONFIG_SYS_CBSIZE]; - - if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0) - return 1; - - return 0; -} - -unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) -{ - unsigned long long ddrsize; - const char *prompt = "FSL DDR>"; - char buffer[CONFIG_SYS_CBSIZE]; - char buffer2[CONFIG_SYS_CBSIZE]; - char *p = NULL; - char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ - int argc; - unsigned int next_step = STEP_GET_SPD; - const char *usage = { - "commands:\n" - "print print SPD and intermediate computed data\n" - "reset reboot machine\n" - "recompute reload SPD and options to default and recompute regs\n" - "edit modify spd, parameter, or option\n" - "compute recompute registers from current next_step to end\n" - "copy copy parameters\n" - "next_step shows current next_step\n" - "help this message\n" - "go program the memory controller and continue with u-boot\n" - }; - - if (var_is_set) { - if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) { - p = buffer2; - } else { - var_is_set = 0; - } - } - - /* - * The strategy for next_step is that it points to the next - * step in the computation process that needs to be done. - */ - while (1) { - if (var_is_set) { - char *pend = strchr(p, ';'); - if (pend) { - /* found command separator, copy sub-command */ - *pend = '\0'; - strcpy(buffer, p); - p = pend + 1; - } else { - /* separator not found, copy whole string */ - strcpy(buffer, p); - p = NULL; - var_is_set = 0; - } - } else { - /* - * No need to worry for buffer overflow here in - * this function; readline() maxes out at CFG_CBSIZE - */ - readline_into_buffer(prompt, buffer, 0); - } - argc = parse_line(buffer, argv); - if (argc == 0) - continue; - - - if (strcmp(argv[0], "help") == 0) { - puts(usage); - continue; - } - - if (strcmp(argv[0], "next_step") == 0) { - printf("next_step = 0x%02X (%s)\n", - next_step, - step_to_string(next_step)); - continue; - } - - if (strcmp(argv[0], "copy") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int src_ctlr_mask = 0; - unsigned int src_dimm_mask = 0; - unsigned int dimm_number_required = 0; - unsigned int src_ctlr_num = 0; - unsigned int src_dimm_num = 0; - unsigned int dst_ctlr_num = -1; - unsigned int dst_dimm_num = -1; - unsigned int i, num_dest_parms; - - if (argc == 1) { - printf("copy \n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc, - &step_mask, - &src_ctlr_mask, - &src_dimm_mask, - &dimm_number_required - ); - - /* XXX: only dimm_number_required and step_mask will - be used by this function. Parse the controller and - DIMM number separately because it is easier. */ - - if (error) - continue; - - /* parse source destination controller / DIMM */ - - num_dest_parms = dimm_number_required ? 2 : 1; - - for (i = 0; i < argc; i++) { - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) { - src_ctlr_num = (c - '0'); - break; - } - } - } - - for (i = 0; i < argc; i++) { - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) { - src_dimm_num = (c - '0'); - break; - } - } - } - - /* parse destination controller / DIMM */ - - for (i = argc - 1; i >= argc - num_dest_parms; i--) { - if (argv[i][0] == 'c') { - char c = argv[i][1]; - if (isdigit(c)) { - dst_ctlr_num = (c - '0'); - break; - } - } - } - - for (i = argc - 1; i >= argc - num_dest_parms; i--) { - if (argv[i][0] == 'd') { - char c = argv[i][1]; - if (isdigit(c)) { - dst_dimm_num = (c - '0'); - break; - } - } - } - - /* TODO: validate inputs */ - - debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n", - src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask); - - - switch (step_mask) { - - case STEP_GET_SPD: - memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]), - &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]), - sizeof(pinfo->spd_installed_dimms[0][0])); - break; - - case STEP_COMPUTE_DIMM_PARMS: - memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]), - &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]), - sizeof(pinfo->dimm_params[0][0])); - break; - - case STEP_COMPUTE_COMMON_PARMS: - memcpy(&(pinfo->common_timing_params[dst_ctlr_num]), - &(pinfo->common_timing_params[src_ctlr_num]), - sizeof(pinfo->common_timing_params[0])); - break; - - case STEP_GATHER_OPTS: - memcpy(&(pinfo->memctl_opts[dst_ctlr_num]), - &(pinfo->memctl_opts[src_ctlr_num]), - sizeof(pinfo->memctl_opts[0])); - break; - - /* someday be able to have addresses to copy addresses... */ - - case STEP_COMPUTE_REGS: - memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]), - &(pinfo->fsl_ddr_config_reg[src_ctlr_num]), - sizeof(pinfo->memctl_opts[0])); - break; - - default: - printf("unexpected step_mask value\n"); - } - - continue; - - } - - if (strcmp(argv[0], "edit") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int ctlr_mask = 0; - unsigned int dimm_mask = 0; - char *p_element = NULL; - char *p_value = NULL; - unsigned int dimm_number_required = 0; - unsigned int ctrl_num; - unsigned int dimm_num; - - if (argc == 1) { - /* Only the element and value must be last */ - printf("edit " - " \n"); - printf("for spd, specify byte number for " - "element\n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc - 2, - &step_mask, - &ctlr_mask, - &dimm_mask, - &dimm_number_required - ); - - if (error) - continue; - - - /* Check arguments */ - - /* ERROR: If no steps were found */ - if (step_mask == 0) { - printf("Error: No valid steps were specified " - "in argument.\n"); - continue; - } - - /* ERROR: If multiple steps were found */ - if (step_mask & (step_mask - 1)) { - printf("Error: Multiple steps specified in " - "argument.\n"); - continue; - } - - /* ERROR: Controller not specified */ - if (ctlr_mask == 0) { - printf("Error: controller number not " - "specified or no element and " - "value specified\n"); - continue; - } - - if (ctlr_mask & (ctlr_mask - 1)) { - printf("Error: multiple controllers " - "specified, %X\n", ctlr_mask); - continue; - } - - /* ERROR: DIMM number not specified */ - if (dimm_number_required && dimm_mask == 0) { - printf("Error: DIMM number number not " - "specified or no element and " - "value specified\n"); - continue; - } - - if (dimm_mask & (dimm_mask - 1)) { - printf("Error: multipled DIMMs specified\n"); - continue; - } - - p_element = argv[argc - 2]; - p_value = argv[argc - 1]; - - ctrl_num = __ilog2(ctlr_mask); - dimm_num = __ilog2(dimm_mask); - - switch (step_mask) { - case STEP_GET_SPD: - { - unsigned int element_num; - unsigned int value; - - element_num = simple_strtoul(p_element, - NULL, 0); - value = simple_strtoul(p_value, - NULL, 0); - fsl_ddr_spd_edit(pinfo, - ctrl_num, - dimm_num, - element_num, - value); - next_step = STEP_COMPUTE_DIMM_PARMS; - } - break; - - case STEP_COMPUTE_DIMM_PARMS: - fsl_ddr_dimm_parameters_edit( - pinfo, ctrl_num, dimm_num, - p_element, p_value); - next_step = STEP_COMPUTE_COMMON_PARMS; - break; - - case STEP_COMPUTE_COMMON_PARMS: - lowest_common_dimm_parameters_edit(pinfo, - ctrl_num, p_element, p_value); - next_step = STEP_GATHER_OPTS; - break; - - case STEP_GATHER_OPTS: - fsl_ddr_options_edit(pinfo, ctrl_num, - p_element, p_value); - next_step = STEP_ASSIGN_ADDRESSES; - break; - - case STEP_ASSIGN_ADDRESSES: - printf("editing of address assignment " - "not yet implemented\n"); - break; - - case STEP_COMPUTE_REGS: - { - fsl_ddr_regs_edit(pinfo, - ctrl_num, - p_element, - p_value); - next_step = STEP_PROGRAM_REGS; - } - break; - - default: - printf("programming error\n"); - while (1) - ; - break; - } - continue; - } - - if (strcmp(argv[0], "reset") == 0) { - /* - * Reboot machine. - * Args don't seem to matter because this - * doesn't return - */ - do_reset(NULL, 0, 0, NULL); - printf("Reset didn't work\n"); - } - - if (strcmp(argv[0], "recompute") == 0) { - /* - * Recalculate everything, starting with - * loading SPD EEPROM from DIMMs - */ - next_step = STEP_GET_SPD; - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - continue; - } - - if (strcmp(argv[0], "compute") == 0) { - /* - * Compute rest of steps starting at - * the current next_step/ - */ - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - continue; - } - - if (strcmp(argv[0], "print") == 0) { - unsigned int error = 0; - unsigned int step_mask = 0; - unsigned int ctlr_mask = 0; - unsigned int dimm_mask = 0; - unsigned int dimm_number_required = 0; - - if (argc == 1) { - printf("print [c] [d] [spd] [dimmparms] " - "[commonparms] [opts] [addresses] [regs]\n"); - continue; - } - - error = fsl_ddr_parse_interactive_cmd( - argv, argc, - &step_mask, - &ctlr_mask, - &dimm_mask, - &dimm_number_required - ); - - if (error) - continue; - - /* If no particular controller was found, print all */ - if (ctlr_mask == 0) - ctlr_mask = 0xFF; - - /* If no particular dimm was found, print all dimms. */ - if (dimm_mask == 0) - dimm_mask = 0xFF; - - /* If no steps were found, print all steps. */ - if (step_mask == 0) - step_mask = STEP_ALL; - - fsl_ddr_printinfo(pinfo, ctlr_mask, - dimm_mask, step_mask); - continue; - } - - if (strcmp(argv[0], "go") == 0) { - if (next_step) - ddrsize = fsl_ddr_compute(pinfo, next_step, 0); - break; - } - - printf("unknown command %s\n", argv[0]); - } - - debug("end of memory = %llu\n", (u64)ddrsize); - - return ddrsize; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c deleted file mode 100644 index 332fe25c48..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ /dev/null @@ -1,526 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include - -#include "ddr.h" - -#if defined(CONFIG_FSL_DDR3) -static unsigned int -compute_cas_latency_ddr3(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - unsigned int number_of_dimms) -{ - unsigned int i; - unsigned int taamin_ps = 0; - unsigned int tckmin_x_ps = 0; - unsigned int common_caslat; - unsigned int caslat_actual; - unsigned int retry = 16; - unsigned int tmp; - const unsigned int mclk_ps = get_memory_clk_period_ps(); - - /* compute the common CAS latency supported between slots */ - tmp = dimm_params[0].caslat_x; - for (i = 1; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) - tmp &= dimm_params[i].caslat_x; - } - common_caslat = tmp; - - /* compute the max tAAmin tCKmin between slots */ - for (i = 0; i < number_of_dimms; i++) { - taamin_ps = max(taamin_ps, dimm_params[i].taa_ps); - tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); - } - /* validate if the memory clk is in the range of dimms */ - if (mclk_ps < tckmin_x_ps) { - printf("DDR clock (MCLK cycle %u ps) is faster than " - "the slowest DIMM(s) (tCKmin %u ps) can support.\n", - mclk_ps, tckmin_x_ps); - } - /* determine the acutal cas latency */ - caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps; - /* check if the dimms support the CAS latency */ - while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { - caslat_actual++; - retry--; - } - /* once the caculation of caslat_actual is completed - * we must verify that this CAS latency value does not - * exceed tAAmax, which is 20 ns for all DDR3 speed grades - */ - if (caslat_actual * mclk_ps > 20000) { - printf("The choosen cas latency %d is too large\n", - caslat_actual); - } - outpdimm->lowest_common_SPD_caslat = caslat_actual; - - return 0; -} -#endif - -/* - * compute_lowest_common_dimm_parameters() - * - * Determine the worst-case DIMM timing parameters from the set of DIMMs - * whose parameters have been computed into the array pointed to - * by dimm_params. - */ -unsigned int -compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, - common_timing_params_t *outpdimm, - const unsigned int number_of_dimms) -{ - unsigned int i, j; - - unsigned int tckmin_x_ps = 0; - unsigned int tckmax_ps = 0xFFFFFFFF; - unsigned int tckmax_max_ps = 0; - unsigned int trcd_ps = 0; - unsigned int trp_ps = 0; - unsigned int tras_ps = 0; - unsigned int twr_ps = 0; - unsigned int twtr_ps = 0; - unsigned int trfc_ps = 0; - unsigned int trrd_ps = 0; - unsigned int trc_ps = 0; - unsigned int refresh_rate_ps = 0; - unsigned int extended_op_srt = 1; - unsigned int tis_ps = 0; - unsigned int tih_ps = 0; - unsigned int tds_ps = 0; - unsigned int tdh_ps = 0; - unsigned int trtp_ps = 0; - unsigned int tdqsq_max_ps = 0; - unsigned int tqhs_ps = 0; - - unsigned int temp1, temp2; - unsigned int additive_latency = 0; -#if !defined(CONFIG_FSL_DDR3) - const unsigned int mclk_ps = get_memory_clk_period_ps(); - unsigned int lowest_good_caslat; - unsigned int not_ok; - - debug("using mclk_ps = %u\n", mclk_ps); -#endif - - temp1 = 0; - for (i = 0; i < number_of_dimms; i++) { - /* - * If there are no ranks on this DIMM, - * it probably doesn't exist, so skip it. - */ - if (dimm_params[i].n_ranks == 0) { - temp1++; - continue; - } - if (dimm_params[i].n_ranks == 4 && i != 0) { - printf("Found Quad-rank DIMM in wrong bank, ignored." - " Software may not run as expected.\n"); - temp1++; - continue; - } - - /* - * check if quad-rank DIMM is plugged if - * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined - * Only the board with proper design is capable - */ -#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (dimm_params[i].n_ranks == 4 && \ - CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { - printf("Found Quad-rank DIMM, not able to support."); - temp1++; - continue; - } -#endif - /* - * Find minimum tckmax_ps to find fastest slow speed, - * i.e., this is the slowest the whole system can go. - */ - tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps); - - /* Either find maximum value to determine slowest - * speed, delay, time, period, etc */ - tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); - tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps); - trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps); - trp_ps = max(trp_ps, dimm_params[i].trp_ps); - tras_ps = max(tras_ps, dimm_params[i].tras_ps); - twr_ps = max(twr_ps, dimm_params[i].twr_ps); - twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps); - trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps); - trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps); - trc_ps = max(trc_ps, dimm_params[i].trc_ps); - tis_ps = max(tis_ps, dimm_params[i].tis_ps); - tih_ps = max(tih_ps, dimm_params[i].tih_ps); - tds_ps = max(tds_ps, dimm_params[i].tds_ps); - tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps); - trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps); - tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps); - refresh_rate_ps = max(refresh_rate_ps, - dimm_params[i].refresh_rate_ps); - /* extended_op_srt is either 0 or 1, 0 having priority */ - extended_op_srt = min(extended_op_srt, - dimm_params[i].extended_op_srt); - - /* - * Find maximum tdqsq_max_ps to find slowest. - * - * FIXME: is finding the slowest value the correct - * strategy for this parameter? - */ - tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps); - } - - outpdimm->ndimms_present = number_of_dimms - temp1; - - if (temp1 == number_of_dimms) { - debug("no dimms this memory controller\n"); - return 0; - } - - outpdimm->tckmin_x_ps = tckmin_x_ps; - outpdimm->tckmax_ps = tckmax_ps; - outpdimm->tckmax_max_ps = tckmax_max_ps; - outpdimm->trcd_ps = trcd_ps; - outpdimm->trp_ps = trp_ps; - outpdimm->tras_ps = tras_ps; - outpdimm->twr_ps = twr_ps; - outpdimm->twtr_ps = twtr_ps; - outpdimm->trfc_ps = trfc_ps; - outpdimm->trrd_ps = trrd_ps; - outpdimm->trc_ps = trc_ps; - outpdimm->refresh_rate_ps = refresh_rate_ps; - outpdimm->extended_op_srt = extended_op_srt; - outpdimm->tis_ps = tis_ps; - outpdimm->tih_ps = tih_ps; - outpdimm->tds_ps = tds_ps; - outpdimm->tdh_ps = tdh_ps; - outpdimm->trtp_ps = trtp_ps; - outpdimm->tdqsq_max_ps = tdqsq_max_ps; - outpdimm->tqhs_ps = tqhs_ps; - - /* Determine common burst length for all DIMMs. */ - temp1 = 0xff; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - temp1 &= dimm_params[i].burst_lengths_bitmask; - } - } - outpdimm->all_dimms_burst_lengths_bitmask = temp1; - - /* Determine if all DIMMs registered buffered. */ - temp1 = temp2 = 0; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - if (dimm_params[i].registered_dimm) { - temp1 = 1; -#ifndef CONFIG_SPL_BUILD - printf("Detected RDIMM %s\n", - dimm_params[i].mpart); -#endif - } else { - temp2 = 1; -#ifndef CONFIG_SPL_BUILD - printf("Detected UDIMM %s\n", - dimm_params[i].mpart); -#endif - } - } - } - - outpdimm->all_dimms_registered = 0; - outpdimm->all_dimms_unbuffered = 0; - if (temp1 && !temp2) { - outpdimm->all_dimms_registered = 1; - } else if (!temp1 && temp2) { - outpdimm->all_dimms_unbuffered = 1; - } else { - printf("ERROR: Mix of registered buffered and unbuffered " - "DIMMs detected!\n"); - } - - temp1 = 0; - if (outpdimm->all_dimms_registered) - for (j = 0; j < 16; j++) { - outpdimm->rcw[j] = dimm_params[0].rcw[j]; - for (i = 1; i < number_of_dimms; i++) { - if (!dimm_params[i].n_ranks) - continue; - if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { - temp1 = 1; - break; - } - } - } - - if (temp1 != 0) - printf("ERROR: Mix different RDIMM detected!\n"); - -#if defined(CONFIG_FSL_DDR3) - if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms)) - return 1; -#else - /* - * Compute a CAS latency suitable for all DIMMs - * - * Strategy for SPD-defined latencies: compute only - * CAS latency defined by all DIMMs. - */ - - /* - * Step 1: find CAS latency common to all DIMMs using bitwise - * operation. - */ - temp1 = 0xFF; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks) { - temp2 = 0; - temp2 |= 1 << dimm_params[i].caslat_x; - temp2 |= 1 << dimm_params[i].caslat_x_minus_1; - temp2 |= 1 << dimm_params[i].caslat_x_minus_2; - /* - * FIXME: If there was no entry for X-2 (X-1) in - * the SPD, then caslat_x_minus_2 - * (caslat_x_minus_1) contains either 255 or - * 0xFFFFFFFF because that's what the glorious - * __ilog2 function returns for an input of 0. - * On 32-bit PowerPC, left shift counts with bit - * 26 set (that the value of 255 or 0xFFFFFFFF - * will have), cause the destination register to - * be 0. That is why this works. - */ - temp1 &= temp2; - } - } - - /* - * Step 2: check each common CAS latency against tCK of each - * DIMM's SPD. - */ - lowest_good_caslat = 0; - temp2 = 0; - while (temp1) { - not_ok = 0; - temp2 = __ilog2(temp1); - debug("checking common caslat = %u\n", temp2); - - /* Check if this CAS latency will work on all DIMMs at tCK. */ - for (i = 0; i < number_of_dimms; i++) { - if (!dimm_params[i].n_ranks) { - continue; - } - if (dimm_params[i].caslat_x == temp2) { - if (mclk_ps >= dimm_params[i].tckmin_x_ps) { - debug("CL = %u ok on DIMM %u at tCK=%u" - " ps with its tCKmin_X_ps of %u\n", - temp2, i, mclk_ps, - dimm_params[i].tckmin_x_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_x_minus_1 == temp2) { - unsigned int tckmin_x_minus_1_ps - = dimm_params[i].tckmin_x_minus_1_ps; - if (mclk_ps >= tckmin_x_minus_1_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tckmin_x_minus_1_ps of %u\n", - temp2, i, mclk_ps, - tckmin_x_minus_1_ps); - continue; - } else { - not_ok++; - } - } - - if (dimm_params[i].caslat_x_minus_2 == temp2) { - unsigned int tckmin_x_minus_2_ps - = dimm_params[i].tckmin_x_minus_2_ps; - if (mclk_ps >= tckmin_x_minus_2_ps) { - debug("CL = %u ok on DIMM %u at " - "tCK=%u ps with its " - "tckmin_x_minus_2_ps of %u\n", - temp2, i, mclk_ps, - tckmin_x_minus_2_ps); - continue; - } else { - not_ok++; - } - } - } - - if (!not_ok) { - lowest_good_caslat = temp2; - } - - temp1 &= ~(1 << temp2); - } - - debug("lowest common SPD-defined CAS latency = %u\n", - lowest_good_caslat); - outpdimm->lowest_common_SPD_caslat = lowest_good_caslat; - - - /* - * Compute a common 'de-rated' CAS latency. - * - * The strategy here is to find the *highest* dereated cas latency - * with the assumption that all of the DIMMs will support a dereated - * CAS latency higher than or equal to their lowest dereated value. - */ - temp1 = 0; - for (i = 0; i < number_of_dimms; i++) { - temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); - } - outpdimm->highest_common_derated_caslat = temp1; - debug("highest common dereated CAS latency = %u\n", temp1); -#endif /* #if defined(CONFIG_FSL_DDR3) */ - - /* Determine if all DIMMs ECC capable. */ - temp1 = 1; - for (i = 0; i < number_of_dimms; i++) { - if (dimm_params[i].n_ranks && - !(dimm_params[i].edc_config & EDC_ECC)) { - temp1 = 0; - break; - } - } - if (temp1) { - debug("all DIMMs ECC capable\n"); - } else { - debug("Warning: not all DIMMs ECC capable, cant enable ECC\n"); - } - outpdimm->all_dimms_ecc_capable = temp1; - -#ifndef CONFIG_FSL_DDR3 - /* FIXME: move to somewhere else to validate. */ - if (mclk_ps > tckmax_max_ps) { - printf("Warning: some of the installed DIMMs " - "can not operate this slowly.\n"); - return 1; - } -#endif - /* - * Compute additive latency. - * - * For DDR1, additive latency should be 0. - * - * For DDR2, with ODT enabled, use "a value" less than ACTTORW, - * which comes from Trcd, and also note that: - * add_lat + caslat must be >= 4 - * - * For DDR3, we use the AL=0 - * - * When to use additive latency for DDR2: - * - * I. Because you are using CL=3 and need to do ODT on writes and - * want functionality. - * 1. Are you going to use ODT? (Does your board not have - * additional termination circuitry for DQ, DQS, DQS_, - * DM, RDQS, RDQS_ for x4/x8 configs?) - * 2. If so, is your lowest supported CL going to be 3? - * 3. If so, then you must set AL=1 because - * - * WL >= 3 for ODT on writes - * RL = AL + CL - * WL = RL - 1 - * -> - * WL = AL + CL - 1 - * AL + CL - 1 >= 3 - * AL + CL >= 4 - * QED - * - * RL >= 3 for ODT on reads - * RL = AL + CL - * - * Since CL aren't usually less than 2, AL=0 is a minimum, - * so the WL-derived AL should be the -- FIXME? - * - * II. Because you are using auto-precharge globally and want to - * use additive latency (posted CAS) to get more bandwidth. - * 1. Are you going to use auto-precharge mode globally? - * - * Use addtivie latency and compute AL to be 1 cycle less than - * tRCD, i.e. the READ or WRITE command is in the cycle - * immediately following the ACTIVATE command.. - * - * III. Because you feel like it or want to do some sort of - * degraded-performance experiment. - * 1. Do you just want to use additive latency because you feel - * like it? - * - * Validation: AL is less than tRCD, and within the other - * read-to-precharge constraints. - */ - - additive_latency = 0; - -#if defined(CONFIG_FSL_DDR2) - if (lowest_good_caslat < 4) { - additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat) - ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0; - if (mclk_to_picos(additive_latency) > trcd_ps) { - additive_latency = picos_to_mclk(trcd_ps); - debug("setting additive_latency to %u because it was " - " greater than tRCD_ps\n", additive_latency); - } - } - -#elif defined(CONFIG_FSL_DDR3) - /* - * The system will not use the global auto-precharge mode. - * However, it uses the page mode, so we set AL=0 - */ - additive_latency = 0; -#endif - - /* - * Validate additive latency - * FIXME: move to somewhere else to validate - * - * AL <= tRCD(min) - */ - if (mclk_to_picos(additive_latency) > trcd_ps) { - printf("Error: invalid additive latency exceeds tRCD(min).\n"); - return 1; - } - - /* - * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled - * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled - * ADD_LAT (the register) must be set to a value less - * than ACTTORW if WL = 1, then AL must be set to 1 - * RD_TO_PRE (the register) must be set to a minimum - * tRTP + AL if AL is nonzero - */ - - /* - * Additive latency will be applied only if the memctl option to - * use it. - */ - outpdimm->additive_latency = additive_latency; - - debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps); - debug("trcd_ps = %u\n", outpdimm->trcd_ps); - debug("trp_ps = %u\n", outpdimm->trp_ps); - debug("tras_ps = %u\n", outpdimm->tras_ps); - debug("twr_ps = %u\n", outpdimm->twr_ps); - debug("twtr_ps = %u\n", outpdimm->twtr_ps); - debug("trfc_ps = %u\n", outpdimm->trfc_ps); - debug("trrd_ps = %u\n", outpdimm->trrd_ps); - debug("trc_ps = %u\n", outpdimm->trc_ps); - - return 0; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c deleted file mode 100644 index 34d8bc3ac0..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ /dev/null @@ -1,718 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -/* - * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. - * Based on code from spd_sdram.c - * Author: James Yang [at freescale.com] - */ - -#include -#include -#include -#include - -#include "ddr.h" - -void fsl_ddr_set_lawbar( - const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); -void fsl_ddr_set_intl3r(const unsigned int granule_size); - -#if defined(SPD_EEPROM_ADDRESS) || \ - defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ - defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) -#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS, -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ - [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ - [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ -}; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { - [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ - [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ - [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ - [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ - [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ - [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ -}; - -#endif - -static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) -{ - int ret; - - i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); - - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, - sizeof(generic_spd_eeprom_t)); - - if (ret) { - if (i2c_address == -#ifdef SPD_EEPROM_ADDRESS - SPD_EEPROM_ADDRESS -#elif defined(SPD_EEPROM_ADDRESS1) - SPD_EEPROM_ADDRESS1 -#endif - ) { - printf("DDR: failed to read SPD from address %u\n", - i2c_address); - } else { - debug("DDR: failed to read SPD from address %u\n", - i2c_address); - } - memset(spd, 0, sizeof(generic_spd_eeprom_t)); - } -} - -__attribute__((weak, alias("__get_spd"))) -void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); - -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - i2c_address = spd_i2c_addr[ctrl_num][i]; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} -#else -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ -} -#endif /* SPD_EEPROM_ADDRESSx */ - -/* - * ASSUMPTIONS: - * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller - * - Same memory data bus width on all controllers - * - * NOTES: - * - * The memory controller and associated documentation use confusing - * terminology when referring to the orgranization of DRAM. - * - * Here is a terminology translation table: - * - * memory controller/documention |industry |this code |signals - * -------------------------------|-----------|-----------|----------------- - * physical bank/bank |rank |rank |chip select (CS) - * logical bank/sub-bank |bank |bank |bank address (BA) - * page/row |row |page |row address - * ??? |column |column |column address - * - * The naming confusion is further exacerbated by the descriptions of the - * memory controller interleaving feature, where accesses are interleaved - * _BETWEEN_ two seperate memory controllers. This is configured only in - * CS0_CONFIG[INTLV_CTL] of each memory controller. - * - * memory controller documentation | number of chip selects - * | per memory controller supported - * --------------------------------|----------------------------------------- - * cache line interleaving | 1 (CS0 only) - * page interleaving | 1 (CS0 only) - * bank interleaving | 1 (CS0 only) - * superbank interleraving | depends on bank (chip select) - * | interleraving [rank interleaving] - * | mode used on every memory controller - * - * Even further confusing is the existence of the interleaving feature - * _WITHIN_ each memory controller. The feature is referred to in - * documentation as chip select interleaving or bank interleaving, - * although it is configured in the DDR_SDRAM_CFG field. - * - * Name of field | documentation name | this code - * -----------------------------|-----------------------|------------------ - * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving - * | interleaving - */ - -const char *step_string_tbl[] = { - "STEP_GET_SPD", - "STEP_COMPUTE_DIMM_PARMS", - "STEP_COMPUTE_COMMON_PARMS", - "STEP_GATHER_OPTS", - "STEP_ASSIGN_ADDRESSES", - "STEP_COMPUTE_REGS", - "STEP_PROGRAM_REGS", - "STEP_ALL" -}; - -const char * step_to_string(unsigned int step) { - - unsigned int s = __ilog2(step); - - if ((1 << s) != step) - return step_string_tbl[7]; - - return step_string_tbl[s]; -} - -static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[]) -{ - int i, j; - unsigned long long total_mem, current_mem_base, total_ctlr_mem; - unsigned long long rank_density, ctlr_density = 0; - - /* - * If a reduced data width is requested, but the SPD - * specifies a physically wider device, adjust the - * computed dimm capacities accordingly before - * assigning addresses. - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - unsigned int found = 0; - - switch (pinfo->memctl_opts[i].data_bus_width) { - case 2: - /* 16-bit */ - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int dw; - if (!pinfo->dimm_params[i][j].n_ranks) - continue; - dw = pinfo->dimm_params[i][j].primary_sdram_width; - if ((dw == 72 || dw == 64)) { - dbw_cap_adj[i] = 2; - break; - } else if ((dw == 40 || dw == 32)) { - dbw_cap_adj[i] = 1; - break; - } - } - break; - - case 1: - /* 32-bit */ - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int dw; - dw = pinfo->dimm_params[i][j].data_width; - if (pinfo->dimm_params[i][j].n_ranks - && (dw == 72 || dw == 64)) { - /* - * FIXME: can't really do it - * like this because this just - * further reduces the memory - */ - found = 1; - break; - } - } - if (found) { - dbw_cap_adj[i] = 1; - } - break; - - case 0: - /* 64-bit */ - break; - - default: - printf("unexpected data bus width " - "specified controller %u\n", i); - return 1; - } - debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); - } - - current_mem_base = 0ull; - total_mem = 0; - if (pinfo->memctl_opts[0].memctl_interleaving) { - rank_density = pinfo->dimm_params[0][0].rank_density >> - dbw_cap_adj[0]; - switch (pinfo->memctl_opts[0].ba_intlv_ctl & - FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: - ctlr_density = 4 * rank_density; - break; - case FSL_DDR_CS0_CS1: - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - ctlr_density = 2 * rank_density; - break; - case FSL_DDR_CS2_CS3: - default: - ctlr_density = rank_density; - break; - } - debug("rank density is 0x%llx, ctlr density is 0x%llx\n", - rank_density, ctlr_density); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (pinfo->memctl_opts[i].memctl_interleaving) { - switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - total_ctlr_mem = 2 * ctlr_density; - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - total_ctlr_mem = 3 * ctlr_density; - break; - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - total_ctlr_mem = 4 * ctlr_density; - break; - default: - panic("Unknown interleaving mode"); - } - pinfo->common_timing_params[i].base_address = - current_mem_base; - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem = current_mem_base + total_ctlr_mem; - debug("ctrl %d base 0x%llx\n", i, current_mem_base); - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - } else { - /* when 3rd controller not interleaved */ - current_mem_base = total_mem; - total_ctlr_mem = 0; - pinfo->common_timing_params[i].base_address = - current_mem_base; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned long long cap = - pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; - pinfo->dimm_params[i][j].base_address = - current_mem_base; - debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); - current_mem_base += cap; - total_ctlr_mem += cap; - } - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem += total_ctlr_mem; - } - } - } else { - /* - * Simple linear assignment if memory - * controllers are not interleaved. - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - total_ctlr_mem = 0; - pinfo->common_timing_params[i].base_address = - current_mem_base; - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - /* Compute DIMM base addresses. */ - unsigned long long cap = - pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; - pinfo->dimm_params[i][j].base_address = - current_mem_base; - debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); - current_mem_base += cap; - total_ctlr_mem += cap; - } - debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); - pinfo->common_timing_params[i].total_mem = - total_ctlr_mem; - total_mem += total_ctlr_mem; - } - } - debug("Total mem by %s is 0x%llx\n", __func__, total_mem); - - return total_mem; -} - -/* Use weak function to allow board file to override the address assignment */ -__attribute__((weak, alias("__step_assign_addresses"))) -unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, - unsigned int dbw_cap_adj[]); - -unsigned long long -fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, - unsigned int size_only) -{ - unsigned int i, j; - unsigned long long total_mem = 0; - int assert_reset; - - fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; - common_timing_params_t *timing_params = pinfo->common_timing_params; - assert_reset = board_need_mem_reset(); - - /* data bus width capacity adjust shift amount */ - unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - dbw_capacity_adjust[i] = 0; - } - - debug("starting at step %u (%s)\n", - start_step, step_to_string(start_step)); - - switch (start_step) { - case STEP_GET_SPD: -#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) - /* STEP 1: Gather all DIMM SPD data */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); - } - - case STEP_COMPUTE_DIMM_PARMS: - /* STEP 2: Compute DIMM parameters from SPD data */ - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - unsigned int retval; - generic_spd_eeprom_t *spd = - &(pinfo->spd_installed_dimms[i][j]); - dimm_params_t *pdimm = - &(pinfo->dimm_params[i][j]); - - retval = compute_dimm_parameters(spd, pdimm, i); -#ifdef CONFIG_SYS_DDR_RAW_TIMING - if (!i && !j && retval) { - printf("SPD error on controller %d! " - "Trying fallback to raw timing " - "calculation\n", i); - fsl_ddr_get_dimm_params(pdimm, i, j); - } -#else - if (retval == 2) { - printf("Error: compute_dimm_parameters" - " non-zero returned FATAL value " - "for memctl=%u dimm=%u\n", i, j); - return 0; - } -#endif - if (retval) { - debug("Warning: compute_dimm_parameters" - " non-zero return value for memctl=%u " - "dimm=%u\n", i, j); - } - } - } - -#elif defined(CONFIG_SYS_DDR_RAW_TIMING) - case STEP_COMPUTE_DIMM_PARMS: - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { - dimm_params_t *pdimm = - &(pinfo->dimm_params[i][j]); - fsl_ddr_get_dimm_params(pdimm, i, j); - } - } - debug("Filling dimm parameters from board specific file\n"); -#endif - case STEP_COMPUTE_COMMON_PARMS: - /* - * STEP 3: Compute a common set of timing parameters - * suitable for all of the DIMMs on each memory controller - */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Computing lowest common DIMM" - " parameters for memctl=%u\n", i); - compute_lowest_common_dimm_parameters( - pinfo->dimm_params[i], - &timing_params[i], - CONFIG_DIMM_SLOTS_PER_CTLR); - } - - case STEP_GATHER_OPTS: - /* STEP 4: Gather configuration requirements from user */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Reloading memory controller " - "configuration options for memctl=%u\n", i); - /* - * This "reloads" the memory controller options - * to defaults. If the user "edits" an option, - * next_step points to the step after this, - * which is currently STEP_ASSIGN_ADDRESSES. - */ - populate_memctl_options( - timing_params[i].all_dimms_registered, - &pinfo->memctl_opts[i], - pinfo->dimm_params[i], i); - /* - * For RDIMMs, JEDEC spec requires clocks to be stable - * before reset signal is deasserted. For the boards - * using fixed parameters, this function should be - * be called from board init file. - */ - if (timing_params[i].all_dimms_registered) - assert_reset = 1; - } - if (assert_reset) { - debug("Asserting mem reset\n"); - board_assert_mem_reset(); - } - - case STEP_ASSIGN_ADDRESSES: - /* STEP 5: Assign addresses to chip selects */ - check_interleaving_options(pinfo); - total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); - - case STEP_COMPUTE_REGS: - /* STEP 6: compute controller register values */ - debug("FSL Memory ctrl register computation\n"); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (timing_params[i].ndimms_present == 0) { - memset(&ddr_reg[i], 0, - sizeof(fsl_ddr_cfg_regs_t)); - continue; - } - - compute_fsl_memctl_config_regs( - &pinfo->memctl_opts[i], - &ddr_reg[i], &timing_params[i], - pinfo->dimm_params[i], - dbw_capacity_adjust[i], - size_only); - } - - default: - break; - } - - { - /* - * Compute the amount of memory available just by - * looking for the highest valid CSn_BNDS value. - * This allows us to also experiment with using - * only CS0 when using dual-rank DIMMs. - */ - unsigned int max_end = 0; - - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { - fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; - if (reg->cs[j].config & 0x80000000) { - unsigned int end; - /* - * 0xfffffff is a special value we put - * for unused bnds - */ - if (reg->cs[j].bnds == 0xffffffff) - continue; - end = reg->cs[j].bnds & 0xffff; - if (end > max_end) { - max_end = end; - } - } - } - } - - total_mem = 1 + (((unsigned long long)max_end << 24ULL) - | 0xFFFFFFULL); - } - - return total_mem; -} - -/* - * fsl_ddr_sdram() -- this is the main function to be called by - * initdram() in the board file. - * - * It returns amount of memory configured in bytes. - */ -phys_size_t fsl_ddr_sdram(void) -{ - unsigned int i; - unsigned int law_memctl = LAW_TRGT_IF_DDR_1; - unsigned long long total_memory; - fsl_ddr_info_t info; - int deassert_reset; - - /* Reset info structure. */ - memset(&info, 0, sizeof(fsl_ddr_info_t)); - - /* Compute it once normally. */ -#ifdef CONFIG_FSL_DDR_INTERACTIVE - if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ - total_memory = fsl_ddr_interactive(&info, 0); - } else if (fsl_ddr_interactive_env_var_exists()) { - total_memory = fsl_ddr_interactive(&info, 1); - } else -#endif - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); - - /* setup 3-way interleaving before enabling DDRC */ - if (info.memctl_opts[0].memctl_interleaving) { - switch (info.memctl_opts[0].memctl_interleaving_mode) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - fsl_ddr_set_intl3r( - info.memctl_opts[0].memctl_interleaving_mode); - break; - default: - break; - } - } - - /* - * Program configuration registers. - * JEDEC specs requires clocks to be stable before deasserting reset - * for RDIMMs. Clocks start after chip select is enabled and clock - * control register is set. During step 1, all controllers have their - * registers set but not enabled. Step 2 proceeds after deasserting - * reset through board FPGA or GPIO. - * For non-registered DIMMs, initialization can go through but it is - * also OK to follow the same flow. - */ - deassert_reset = board_need_mem_reset(); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (info.common_timing_params[i].all_dimms_registered) - deassert_reset = 1; - } - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - debug("Programming controller %u\n", i); - if (info.common_timing_params[i].ndimms_present == 0) { - debug("No dimms present on controller %u; " - "skipping programming\n", i); - continue; - } - /* - * The following call with step = 1 returns before enabling - * the controller. It has to finish with step = 2 later. - */ - fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, - deassert_reset ? 1 : 0); - } - if (deassert_reset) { - /* Use board FPGA or GPIO to deassert reset signal */ - debug("Deasserting mem reset\n"); - board_deassert_mem_reset(); - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - /* Call with step = 2 to continue initialization */ - fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), - i, 2); - } - } - - /* program LAWs */ - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - if (info.memctl_opts[i].memctl_interleaving) { - switch (info.memctl_opts[i].memctl_interleaving_mode) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - if (i == 0) { - law_memctl = LAW_TRGT_IF_DDR_INTRLV; - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } else if (i == 2) { - law_memctl = LAW_TRGT_IF_DDR_INTLV_34; - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - law_memctl = LAW_TRGT_IF_DDR_INTLV_123; - if (i == 0) { - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - break; - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; - if (i == 0) - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - /* place holder for future 4-way interleaving */ - break; - default: - break; - } - } else { - switch (i) { - case 0: - law_memctl = LAW_TRGT_IF_DDR_1; - break; - case 1: - law_memctl = LAW_TRGT_IF_DDR_2; - break; - case 2: - law_memctl = LAW_TRGT_IF_DDR_3; - break; - case 3: - law_memctl = LAW_TRGT_IF_DDR_4; - break; - default: - break; - } - fsl_ddr_set_lawbar(&info.common_timing_params[i], - law_memctl, i); - } - } - - debug("total_memory by %s = %llu\n", __func__, total_memory); - -#if !defined(CONFIG_PHYS_64BIT) - /* Check for 4G or more. Bad. */ - if (total_memory >= (1ull << 32)) { - puts("Detected "); - print_size(total_memory, " of memory\n"); - printf(" This U-Boot only supports < 4G of DDR\n"); - printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); - printf(" "); /* re-align to match init_func_ram print */ - total_memory = CONFIG_MAX_MEM_MAPPED; - } -#endif - - return total_memory; -} - -/* - * fsl_ddr_sdram_size() - This function only returns the size of the total - * memory without setting ddr control registers. - */ -phys_size_t -fsl_ddr_sdram_size(void) -{ - fsl_ddr_info_t info; - unsigned long long total_memory = 0; - - memset(&info, 0 , sizeof(fsl_ddr_info_t)); - - /* Compute it once normally. */ - total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); - - return total_memory; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c deleted file mode 100644 index 1297845553..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ /dev/null @@ -1,1147 +0,0 @@ -/* - * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include "ddr.h" - -/* - * Use our own stack based buffer before relocation to allow accessing longer - * hwconfig strings that might be in the environment before we've relocated. - * This is pretty fragile on both the use of stack and if the buffer is big - * enough. However we will get a warning from getenv_f for the later. - */ - -/* Board-specific functions defined in each board's ddr.c */ -extern void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num); - -struct dynamic_odt { - unsigned int odt_rd_cfg; - unsigned int odt_wr_cfg; - unsigned int odt_rtt_norm; - unsigned int odt_rtt_wr; -}; - -#ifdef CONFIG_FSL_DDR3 -static const struct dynamic_odt single_Q[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS_AND_OTHER_DIMM, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, /* tied high */ - DDR3_RTT_OFF, - DDR3_RTT_120_OHM - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS_AND_OTHER_DIMM, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, /* tied high */ - DDR3_RTT_OFF, - DDR3_RTT_120_OHM - } -}; - -static const struct dynamic_odt single_D[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR3_RTT_OFF, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt single_S[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, -}; - -static const struct dynamic_odt dual_DD[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_30_OHM, - DDR3_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_30_OHM, - DDR3_RTT_OFF - } -}; - -static const struct dynamic_odt dual_DS[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_30_OHM, - DDR3_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0} -}; -static const struct dynamic_odt dual_SD[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_20_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR3_RTT_20_OHM, - DDR3_RTT_OFF - } -}; - -static const struct dynamic_odt dual_SS[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_30_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_ALL, - DDR3_RTT_30_OHM, - DDR3_RTT_120_OHM - }, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_D0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR3_RTT_OFF, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_0D[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_SAME_DIMM, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR3_RTT_OFF, - DDR3_RTT_OFF - } -}; - -static const struct dynamic_odt dual_S0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt dual_0S[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_40_OHM, - DDR3_RTT_OFF - }, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt odt_unknown[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR3_RTT_120_OHM, - DDR3_RTT_OFF - } -}; -#else /* CONFIG_FSL_DDR3 */ -static const struct dynamic_odt single_Q[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt single_D[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt single_S[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0}, -}; - -static const struct dynamic_odt dual_DD[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; - -static const struct dynamic_odt dual_DS[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_SD[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; - -static const struct dynamic_odt dual_SS[4] = { - { /* cs0 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_OTHER_DIMM, - FSL_DDR_ODT_OTHER_DIMM, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_D0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0} -}; - -static const struct dynamic_odt dual_0D[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_ALL, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; - -static const struct dynamic_odt dual_S0[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt dual_0S[4] = { - {0, 0, 0, 0}, - {0, 0, 0, 0}, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_150_OHM, - DDR2_RTT_OFF - }, - {0, 0, 0, 0} - -}; - -static const struct dynamic_odt odt_unknown[4] = { - { /* cs0 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs1 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - }, - { /* cs2 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_CS, - DDR2_RTT_75_OHM, - DDR2_RTT_OFF - }, - { /* cs3 */ - FSL_DDR_ODT_NEVER, - FSL_DDR_ODT_NEVER, - DDR2_RTT_OFF, - DDR2_RTT_OFF - } -}; -#endif - -/* - * Automatically seleect bank interleaving mode based on DIMMs - * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null. - * This function only deal with one or two slots per controller. - */ -static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) -{ -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks == 4) - return FSL_DDR_CS0_CS1_CS2_CS3; - else if (pdimm[0].n_ranks == 2) - return FSL_DDR_CS0_CS1; -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (pdimm[0].n_ranks == 4) - return FSL_DDR_CS0_CS1_CS2_CS3; -#endif - if (pdimm[0].n_ranks == 2) { - if (pdimm[1].n_ranks == 2) - return FSL_DDR_CS0_CS1_CS2_CS3; - else - return FSL_DDR_CS0_CS1; - } -#endif - return 0; -} - -unsigned int populate_memctl_options(int all_dimms_registered, - memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - unsigned int i; - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) - const struct dynamic_odt *pdodt = odt_unknown; -#endif - ulong ddr_freq; - - /* - * Extract hwconfig from environment since we have not properly setup - * the environment but need it for ddr config params - */ - if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) - buf = buffer; - -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) - /* Chip select options. */ - if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { - switch (pdimm[0].n_ranks) { - case 1: - pdodt = single_S; - break; - case 2: - pdodt = single_D; - break; - case 4: - pdodt = single_Q; - break; - } - } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { - switch (pdimm[0].n_ranks) { -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - case 4: - pdodt = single_Q; - if (pdimm[1].n_ranks) - printf("Error: Quad- and Dual-rank DIMMs " - "cannot be used together\n"); - break; -#endif - case 2: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_DD; - break; - case 1: - pdodt = dual_DS; - break; - case 0: - pdodt = dual_D0; - break; - } - break; - case 1: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_SD; - break; - case 1: - pdodt = dual_SS; - break; - case 0: - pdodt = dual_S0; - break; - } - break; - case 0: - switch (pdimm[1].n_ranks) { - case 2: - pdodt = dual_0D; - break; - case 1: - pdodt = dual_0S; - break; - } - break; - } - } -#endif - - /* Pick chip-select local options. */ - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { -#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2) - popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; - popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; - popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; - popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; -#else - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; -#endif - popts->cs_local_opts[i].auto_precharge = 0; - } - - /* Pick interleaving mode. */ - - /* - * 0 = no interleaving - * 1 = interleaving between 2 controllers - */ - popts->memctl_interleaving = 0; - - /* - * 0 = cacheline - * 1 = page - * 2 = (logical) bank - * 3 = superbank (only if CS interleaving is enabled) - */ - popts->memctl_interleaving_mode = 0; - - /* - * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl - * 1: page: bit to the left of the column bits selects the memctl - * 2: bank: bit to the left of the bank bits selects the memctl - * 3: superbank: bit to the left of the chip select selects the memctl - * - * NOTE: ba_intlv (rank interleaving) is independent of memory - * controller interleaving; it is only within a memory controller. - * Must use superbank interleaving if rank interleaving is used and - * memory controller interleaving is enabled. - */ - - /* - * 0 = no - * 0x40 = CS0,CS1 - * 0x20 = CS2,CS3 - * 0x60 = CS0,CS1 + CS2,CS3 - * 0x04 = CS0,CS1,CS2,CS3 - */ - popts->ba_intlv_ctl = 0; - - /* Memory Organization Parameters */ - popts->registered_dimm_en = all_dimms_registered; - - /* Operational Mode Paramters */ - - /* Pick ECC modes */ - popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ -#ifdef CONFIG_DDR_ECC - if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { - if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) - popts->ecc_mode = 1; - } else - popts->ecc_mode = 1; -#endif - popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ - - /* - * Choose DQS config - * 0 for DDR1 - * 1 for DDR2 - */ -#if defined(CONFIG_FSL_DDR1) - popts->dqs_config = 0; -#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) - popts->dqs_config = 1; -#endif - - /* Choose self-refresh during sleep. */ - popts->self_refresh_in_sleep = 1; - - /* Choose dynamic power management mode. */ - popts->dynamic_power = 0; - - /* - * check first dimm for primary sdram width - * presuming all dimms are similar - * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit - */ -#if defined(CONFIG_FSL_DDR1) || defined(CONFIG_FSL_DDR2) - if (pdimm[0].n_ranks != 0) { - if ((pdimm[0].data_width >= 64) && \ - (pdimm[0].data_width <= 72)) - popts->data_bus_width = 0; - else if ((pdimm[0].data_width >= 32) || \ - (pdimm[0].data_width <= 40)) - popts->data_bus_width = 1; - else { - panic("Error: data width %u is invalid!\n", - pdimm[0].data_width); - } - } -#else - if (pdimm[0].n_ranks != 0) { - if (pdimm[0].primary_sdram_width == 64) - popts->data_bus_width = 0; - else if (pdimm[0].primary_sdram_width == 32) - popts->data_bus_width = 1; - else if (pdimm[0].primary_sdram_width == 16) - popts->data_bus_width = 2; - else { - panic("Error: primary sdram width %u is invalid!\n", - pdimm[0].primary_sdram_width); - } - } -#endif - - popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; - - /* Choose burst length. */ -#if defined(CONFIG_FSL_DDR3) -#if defined(CONFIG_E500MC) - popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ - popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ -#else - if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { - /* 32-bit or 16-bit bus */ - popts->otf_burst_chop_en = 0; - popts->burst_length = DDR_BL8; - } else { - popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ - popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ - } -#endif -#else - popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ -#endif - - /* Choose ddr controller address mirror mode */ -#if defined(CONFIG_FSL_DDR3) - popts->mirrored_dimm = pdimm[0].mirrored_dimm; -#endif - - /* Global Timing Parameters. */ - debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); - - /* Pick a caslat override. */ - popts->cas_latency_override = 0; - popts->cas_latency_override_value = 3; - if (popts->cas_latency_override) { - debug("using caslat override value = %u\n", - popts->cas_latency_override_value); - } - - /* Decide whether to use the computed derated latency */ - popts->use_derated_caslat = 0; - - /* Choose an additive latency. */ - popts->additive_latency_override = 0; - popts->additive_latency_override_value = 3; - if (popts->additive_latency_override) { - debug("using additive latency override value = %u\n", - popts->additive_latency_override_value); - } - - /* - * 2T_EN setting - * - * Factors to consider for 2T_EN: - * - number of DIMMs installed - * - number of components, number of active ranks - * - how much time you want to spend playing around - */ - popts->twot_en = 0; - popts->threet_en = 0; - - /* for RDIMM, address parity enable */ - popts->ap_en = 1; - - /* - * BSTTOPRE precharge interval - * - * Set this to 0 for global auto precharge - * - * FIXME: Should this be configured in picoseconds? - * Why it should be in ps: better understanding of this - * relative to actual DRAM timing parameters such as tRAS. - * e.g. tRAS(min) = 40 ns - */ - popts->bstopre = 0x100; - - /* Minimum CKE pulse width -- tCKE(MIN) */ - popts->tcke_clock_pulse_width_ps - = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); - - /* - * Window for four activates -- tFAW - * - * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only - * FIXME: varies depending upon number of column addresses or data - * FIXME: width, was considering looking at pdimm->primary_sdram_width - */ -#if defined(CONFIG_FSL_DDR1) - popts->tfaw_window_four_activates_ps = mclk_to_picos(1); - -#elif defined(CONFIG_FSL_DDR2) - /* - * x4/x8; some datasheets have 35000 - * x16 wide columns only? Use 50000? - */ - popts->tfaw_window_four_activates_ps = 37500; - -#elif defined(CONFIG_FSL_DDR3) - popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; -#endif - popts->zq_en = 0; - popts->wrlvl_en = 0; -#if defined(CONFIG_FSL_DDR3) - /* - * due to ddr3 dimm is fly-by topology - * we suggest to enable write leveling to - * meet the tQDSS under different loading. - */ - popts->wrlvl_en = 1; - popts->zq_en = 1; - popts->wrlvl_override = 0; -#endif - - /* - * Check interleaving configuration from environment. - * Please refer to doc/README.fsl-ddr for the detail. - * - * If memory controller interleaving is enabled, then the data - * bus widths must be programmed identically for all memory controllers. - * - * XXX: Attempt to set all controllers to the same chip select - * interleaving mode. It will do a best effort to get the - * requested ranks interleaved together such that the result - * should be a subset of the requested configuration. - */ -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) - if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) - goto done; - - if (pdimm[0].n_ranks == 0) { - printf("There is no rank on CS0 for controller %d.\n", ctrl_num); - popts->memctl_interleaving = 0; - goto done; - } - popts->memctl_interleaving = 1; - /* - * test null first. if CONFIG_HWCONFIG is not defined - * hwconfig_arg_cmp returns non-zero - */ - if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", - "null", buf)) { - popts->memctl_interleaving = 0; - debug("memory controller interleaving disabled.\n"); - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "cacheline", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "page", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_PAGE_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "bank", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_BANK_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "superbank", buf)) { - popts->memctl_interleaving_mode = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : FSL_DDR_SUPERBANK_INTERLEAVING; - popts->memctl_interleaving = - ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? - 0 : 1; -#if (CONFIG_NUM_DDR_CONTROLLERS == 3) - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "3way_1KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_3WAY_1KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "3way_4KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_3WAY_4KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "3way_8KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_3WAY_8KB_INTERLEAVING; -#elif (CONFIG_NUM_DDR_CONTROLLERS == 4) - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "4way_1KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_4WAY_1KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "4way_4KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_4WAY_4KB_INTERLEAVING; - } else if (hwconfig_subarg_cmp_f("fsl_ddr", - "ctlr_intlv", - "4way_8KB", buf)) { - popts->memctl_interleaving_mode = - FSL_DDR_4WAY_8KB_INTERLEAVING; -#endif - } else { - popts->memctl_interleaving = 0; - printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); - } -done: -#endif - if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && - (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { - /* test null first. if CONFIG_HWCONFIG is not defined, - * hwconfig_subarg_cmp_f returns non-zero */ - if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "null", buf)) - debug("bank interleaving disabled.\n"); - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs0_cs1", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs2_cs3", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs0_cs1_and_cs2_cs3", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "cs0_cs1_cs2_cs3", buf)) - popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", - "auto", buf)) - popts->ba_intlv_ctl = auto_bank_intlv(pdimm); - else - printf("hwconfig has unrecognized parameter for bank_intlv.\n"); - switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { - case FSL_DDR_CS0_CS1_CS2_CS3: -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks < 4) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for " - "CS0+CS1+CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) -#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE - if (pdimm[0].n_ranks == 4) - break; -#endif - if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for " - "CS0+CS1+CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } - if (pdimm[0].capacity != pdimm[1].capacity) { - popts->ba_intlv_ctl = 0; - printf("Not identical DIMM size for " - "CS0+CS1+CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#endif - break; - case FSL_DDR_CS0_CS1: - if (pdimm[0].n_ranks < 2) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for " - "CS0+CS1 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } - break; - case FSL_DDR_CS2_CS3: -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks < 4) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for CS2+CS3 " - "on controller %d, interleaving disabled!\n", ctrl_num); - } -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) - if (pdimm[1].n_ranks < 2) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(chip-select) for CS2+CS3 " - "on controller %d, interleaving disabled!\n", ctrl_num); - } -#endif - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: -#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) - if (pdimm[0].n_ranks < 4) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS0+CS1 and " - "CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) - if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { - popts->ba_intlv_ctl = 0; - printf("Not enough bank(CS) for CS0+CS1 and " - "CS2+CS3 on controller %d, " - "interleaving disabled!\n", ctrl_num); - } -#endif - break; - default: - popts->ba_intlv_ctl = 0; - break; - } - } - - if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { - if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) - popts->addr_hash = 0; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", - "true", buf)) - popts->addr_hash = 1; - } - - if (pdimm[0].n_ranks == 4) - popts->quad_rank_present = 1; - - ddr_freq = get_ddr_freq(0) / 1000000; - if (popts->registered_dimm_en) { - popts->rcw_override = 1; - popts->rcw_1 = 0x000a5a00; - if (ddr_freq <= 800) - popts->rcw_2 = 0x00000000; - else if (ddr_freq <= 1066) - popts->rcw_2 = 0x00100000; - else if (ddr_freq <= 1333) - popts->rcw_2 = 0x00200000; - else - popts->rcw_2 = 0x00300000; - } - - fsl_ddr_board_options(popts, pdimm, ctrl_num); - - return 0; -} - -void check_interleaving_options(fsl_ddr_info_t *pinfo) -{ - int i, j, k, check_n_ranks, intlv_invalid = 0; - unsigned int check_intlv, check_n_row_addr, check_n_col_addr; - unsigned long long check_rank_density; - struct dimm_params_s *dimm; - /* - * Check if all controllers are configured for memory - * controller interleaving. Identical dimms are recommended. At least - * the size, row and col address should be checked. - */ - j = 0; - check_n_ranks = pinfo->dimm_params[0][0].n_ranks; - check_rank_density = pinfo->dimm_params[0][0].rank_density; - check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr; - check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr; - check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode; - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { - dimm = &pinfo->dimm_params[i][0]; - if (!pinfo->memctl_opts[i].memctl_interleaving) { - continue; - } else if (((check_rank_density != dimm->rank_density) || - (check_n_ranks != dimm->n_ranks) || - (check_n_row_addr != dimm->n_row_addr) || - (check_n_col_addr != dimm->n_col_addr) || - (check_intlv != - pinfo->memctl_opts[i].memctl_interleaving_mode))){ - intlv_invalid = 1; - break; - } else { - j++; - } - - } - if (intlv_invalid) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - pinfo->memctl_opts[i].memctl_interleaving = 0; - printf("Not all DIMMs are identical. " - "Memory controller interleaving disabled.\n"); - } else { - switch (check_intlv) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - case FSL_DDR_PAGE_INTERLEAVING: - case FSL_DDR_BANK_INTERLEAVING: - case FSL_DDR_SUPERBANK_INTERLEAVING: - if (3 == CONFIG_NUM_DDR_CONTROLLERS) - k = 2; - else - k = CONFIG_NUM_DDR_CONTROLLERS; - break; - case FSL_DDR_3WAY_1KB_INTERLEAVING: - case FSL_DDR_3WAY_4KB_INTERLEAVING: - case FSL_DDR_3WAY_8KB_INTERLEAVING: - case FSL_DDR_4WAY_1KB_INTERLEAVING: - case FSL_DDR_4WAY_4KB_INTERLEAVING: - case FSL_DDR_4WAY_8KB_INTERLEAVING: - default: - k = CONFIG_NUM_DDR_CONTROLLERS; - break; - } - debug("%d of %d controllers are interleaving.\n", j, k); - if (j && (j != k)) { - for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) - pinfo->memctl_opts[i].memctl_interleaving = 0; - printf("Not all controllers have compatible " - "interleaving mode. All disabled.\n"); - } - } - debug("Checking interleaving options completed\n"); -} - -int fsl_use_spd(void) -{ - int use_spd = 0; - -#ifdef CONFIG_DDR_SPD - char buffer[HWCONFIG_BUFFER_SIZE]; - char *buf = NULL; - - /* - * Extract hwconfig from environment since we have not properly setup - * the environment but need it for ddr config params - */ - if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) - buf = buffer; - - /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ - if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) { - if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf)) - use_spd = 1; - else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", - "fixed", buf)) - use_spd = 0; - else - use_spd = 1; - } else - use_spd = 1; -#endif - - return use_spd; -} diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c deleted file mode 100644 index acfe1f095f..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright 2008-2012 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include -#include -#include - -#include "ddr.h" - -/* To avoid 64-bit full-divides, we factor this here */ -#define ULL_2E12 2000000000000ULL -#define UL_5POW12 244140625UL -#define UL_2POW13 (1UL << 13) - -#define ULL_8FS 0xFFFFFFFFULL - -/* - * Round up mclk_ps to nearest 1 ps in memory controller code - * if the error is 0.5ps or more. - * - * If an imprecise data rate is too high due to rounding error - * propagation, compute a suitably rounded mclk_ps to compute - * a working memory controller configuration. - */ -unsigned int get_memory_clk_period_ps(void) -{ - unsigned int data_rate = get_ddr_freq(0); - unsigned int result; - - /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ - unsigned long long rem, mclk_ps = ULL_2E12; - - /* Now perform the big divide, the result fits in 32-bits */ - rem = do_div(mclk_ps, data_rate); - result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; - - return result; -} - -/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ -unsigned int picos_to_mclk(unsigned int picos) -{ - unsigned long long clks, clks_rem; - unsigned long data_rate = get_ddr_freq(0); - - /* Short circuit for zero picos */ - if (!picos) - return 0; - - /* First multiply the time by the data rate (32x32 => 64) */ - clks = picos * (unsigned long long)data_rate; - /* - * Now divide by 5^12 and track the 32-bit remainder, then divide - * by 2*(2^12) using shifts (and updating the remainder). - */ - clks_rem = do_div(clks, UL_5POW12); - clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; - clks >>= 13; - - /* If we had a remainder greater than the 1ps error, then round up */ - if (clks_rem > data_rate) - clks++; - - /* Clamp to the maximum representable value */ - if (clks > ULL_8FS) - clks = ULL_8FS; - return (unsigned int) clks; -} - -unsigned int mclk_to_picos(unsigned int mclk) -{ - return get_memory_clk_period_ps() * mclk; -} - -void -__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, - unsigned int law_memctl, - unsigned int ctrl_num) -{ - unsigned long long base = memctl_common_params->base_address; - unsigned long long size = memctl_common_params->total_mem; - - /* - * If no DIMMs on this controller, do not proceed any further. - */ - if (!memctl_common_params->ndimms_present) { - return; - } - -#if !defined(CONFIG_PHYS_64BIT) - if (base >= CONFIG_MAX_MEM_MAPPED) - return; - if ((base + size) >= CONFIG_MAX_MEM_MAPPED) - size = CONFIG_MAX_MEM_MAPPED - base; -#endif - if (set_ddr_laws(base, size, law_memctl) < 0) { - printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, - law_memctl); - return ; - } - debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", - base, size, law_memctl); -} - -__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void -fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, - unsigned int memctl_interleaved, - unsigned int ctrl_num); - -void fsl_ddr_set_intl3r(const unsigned int granule_size) -{ -#ifdef CONFIG_E6500 - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); - *mcintl3r = 0x80000000 | (granule_size & 0x1f); - debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); -#endif -} - -u32 fsl_ddr_get_intl3r(void) -{ - u32 val = 0; -#ifdef CONFIG_E6500 - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); - val = *mcintl3r; -#endif - return val; -} - -void board_add_ram_info(int use_default) -{ - ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); - -#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) - u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS > 1) - uint32_t cs0_config = in_be32(&ddr->cs0_config); -#endif - uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); - int cas_lat; - -#if CONFIG_NUM_DDR_CONTROLLERS >= 2 - if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); - } -#endif -#if CONFIG_NUM_DDR_CONTROLLERS >= 3 - if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { - ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); - } -#endif - puts(" (DDR"); - switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> - SDRAM_CFG_SDRAM_TYPE_SHIFT) { - case SDRAM_TYPE_DDR1: - puts("1"); - break; - case SDRAM_TYPE_DDR2: - puts("2"); - break; - case SDRAM_TYPE_DDR3: - puts("3"); - break; - default: - puts("?"); - break; - } - - if (sdram_cfg & SDRAM_CFG_32_BE) - puts(", 32-bit"); - else if (sdram_cfg & SDRAM_CFG_16_BE) - puts(", 16-bit"); - else - puts(", 64-bit"); - - /* Calculate CAS latency based on timing cfg values */ - cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; - if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) - cas_lat += (8 << 1); - printf(", CL=%d", cas_lat >> 1); - if (cas_lat & 0x1) - puts(".5"); - - if (sdram_cfg & SDRAM_CFG_ECC_EN) - puts(", ECC on)"); - else - puts(", ECC off)"); - -#if (CONFIG_NUM_DDR_CONTROLLERS == 3) -#ifdef CONFIG_E6500 - if (*mcintl3r & 0x80000000) { - puts("\n"); - puts(" DDR Controller Interleaving Mode: "); - switch (*mcintl3r & 0x1f) { - case FSL_DDR_3WAY_1KB_INTERLEAVING: - puts("3-way 1KB"); - break; - case FSL_DDR_3WAY_4KB_INTERLEAVING: - puts("3-way 4KB"); - break; - case FSL_DDR_3WAY_8KB_INTERLEAVING: - puts("3-way 8KB"); - break; - default: - puts("3-way UNKNOWN"); - break; - } - } -#endif -#endif -#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) - if (cs0_config & 0x20000000) { - puts("\n"); - puts(" DDR Controller Interleaving Mode: "); - - switch ((cs0_config >> 24) & 0xf) { - case FSL_DDR_CACHE_LINE_INTERLEAVING: - puts("cache line"); - break; - case FSL_DDR_PAGE_INTERLEAVING: - puts("page"); - break; - case FSL_DDR_BANK_INTERLEAVING: - puts("bank"); - break; - case FSL_DDR_SUPERBANK_INTERLEAVING: - puts("super-bank"); - break; - default: - puts("invalid"); - break; - } - } -#endif - - if ((sdram_cfg >> 8) & 0x7f) { - puts("\n"); - puts(" DDR Chip-Select Interleaving Mode: "); - switch(sdram_cfg >> 8 & 0x7f) { - case FSL_DDR_CS0_CS1_CS2_CS3: - puts("CS0+CS1+CS2+CS3"); - break; - case FSL_DDR_CS0_CS1: - puts("CS0+CS1"); - break; - case FSL_DDR_CS2_CS3: - puts("CS2+CS3"); - break; - case FSL_DDR_CS0_CS1_AND_CS2_CS3: - puts("CS0+CS1 and CS2+CS3"); - break; - default: - puts("invalid"); - break; - } - } -} diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 3c17c99146..423a6fb8dc 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -9,10 +9,16 @@ #ifdef CONFIG_MPC85xx #include +#define CONFIG_SYS_FSL_DDR #endif #ifdef CONFIG_MPC86xx #include +#define CONFIG_SYS_FSL_DDR +#endif + +#ifdef CONFIG_MPC83xx +#define CONFIG_SYS_FSL_DDR #endif #ifndef HWCONFIG_BUFFER_SIZE diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d4cd27dd00..047fdf1d8c 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -40,17 +40,20 @@ #elif defined(CONFIG_MPC8540) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8541) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8544) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -59,6 +62,7 @@ #elif defined(CONFIG_MPC8548) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -77,17 +81,20 @@ #elif defined(CONFIG_MPC8555) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8560) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 8 +#define CONFIG_SYS_FSL_DDRC_GEN1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #elif defined(CONFIG_MPC8568) #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 10 +#define CONFIG_SYS_FSL_DDRC_GEN2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 #define QE_MURAM_SIZE 0x10000UL #define MAX_QE_RISC 2 @@ -738,4 +745,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 #endif +#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ + !defined(CONFIG_SYS_FSL_DDRC_GEN3) +#define CONFIG_SYS_FSL_DDRC_GEN3 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h index 694b110302..4f9b2252be 100644 --- a/arch/powerpc/include/asm/config_mpc86xx.h +++ b/arch/powerpc/include/asm/config_mpc86xx.h @@ -7,6 +7,8 @@ #ifndef _ASM_MPC86xx_CONFIG_H_ #define _ASM_MPC86xx_CONFIG_H_ +#define CONFIG_SYS_FSL_DDR_86XX + /* SoC specific defines for Freescale MPC86xx processors */ #if defined(CONFIG_MPC8610) diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h deleted file mode 100644 index 99a72bc6e1..0000000000 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef DDR2_DIMM_PARAMS_H -#define DDR2_DIMM_PARAMS_H - -#define EDC_DATA_PARITY 1 -#define EDC_ECC 2 -#define EDC_AC_PARITY 4 - -/* Parameters for a DDR2 dimm computed from the SPD */ -typedef struct dimm_params_s { - - /* DIMM organization parameters */ - char mpart[19]; /* guaranteed null terminated */ - - unsigned int n_ranks; - unsigned long long rank_density; - unsigned long long capacity; - unsigned int data_width; - unsigned int primary_sdram_width; - unsigned int ec_sdram_width; - unsigned int registered_dimm; - unsigned int device_width; /* x4, x8, x16 components */ - - /* SDRAM device parameters */ - unsigned int n_row_addr; - unsigned int n_col_addr; - unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ - unsigned int n_banks_per_sdram_device; - unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ - unsigned int row_density; - - /* used in computing base address of DIMMs */ - unsigned long long base_address; - /* mirrored DIMMs */ - unsigned int mirrored_dimm; /* only for ddr3 */ - - /* DIMM timing parameters */ - - unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ - unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ - unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ - - /* - * SDRAM clock periods - * The range for these are 1000-10000 so a short should be sufficient - */ - unsigned int tckmin_x_ps; - unsigned int tckmin_x_minus_1_ps; - unsigned int tckmin_x_minus_2_ps; - unsigned int tckmax_ps; - - /* SPD-defined CAS latencies */ - unsigned int caslat_x; - unsigned int caslat_x_minus_1; - unsigned int caslat_x_minus_2; - - unsigned int caslat_lowest_derated; /* Derated CAS latency */ - - /* basic timing parameters */ - unsigned int trcd_ps; - unsigned int trp_ps; - unsigned int tras_ps; - - unsigned int twr_ps; /* maximum = 63750 ps */ - unsigned int twtr_ps; /* maximum = 63750 ps */ - unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns - = 511750 ps */ - - unsigned int trrd_ps; /* maximum = 63750 ps */ - unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ - - unsigned int refresh_rate_ps; - unsigned int extended_op_srt; - - /* DDR3 doesn't need these as below */ - unsigned int tis_ps; /* byte 32, spd->ca_setup */ - unsigned int tih_ps; /* byte 33, spd->ca_hold */ - unsigned int tds_ps; /* byte 34, spd->data_setup */ - unsigned int tdh_ps; /* byte 35, spd->data_hold */ - unsigned int trtp_ps; /* byte 38, spd->trtp */ - unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tqhs_ps; /* byte 45, spd->tqhs */ - - /* DDR3 RDIMM */ - unsigned char rcw[16]; /* Register Control Word 0-15 */ -} dimm_params_t; - -extern unsigned int ddr_compute_dimm_parameters( - const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number); - -#endif diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h deleted file mode 100644 index 2c3c514ba3..0000000000 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright 2008-2011 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#ifndef FSL_DDR_MEMCTL_H -#define FSL_DDR_MEMCTL_H - -/* - * Pick a basic DDR Technology. - */ -#include - -#define SDRAM_TYPE_DDR1 2 -#define SDRAM_TYPE_DDR2 3 -#define SDRAM_TYPE_LPDDR1 6 -#define SDRAM_TYPE_DDR3 7 - -#define DDR_BL4 4 /* burst length 4 */ -#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ -#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ -#define DDR_BL8 8 /* burst length 8 */ - -#define DDR3_RTT_OFF 0 -#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ -#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ -#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ -#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ -#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ - -#define DDR2_RTT_OFF 0 -#define DDR2_RTT_75_OHM 1 -#define DDR2_RTT_150_OHM 2 -#define DDR2_RTT_50_OHM 3 - -#if defined(CONFIG_FSL_DDR1) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) -typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 -#endif -#elif defined(CONFIG_FSL_DDR2) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) -typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 -#endif -#elif defined(CONFIG_FSL_DDR3) -#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ -typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; -#ifndef CONFIG_FSL_SDRAM_TYPE -#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 -#endif -#endif /* #if defined(CONFIG_FSL_DDR1) */ - -#define FSL_DDR_ODT_NEVER 0x0 -#define FSL_DDR_ODT_CS 0x1 -#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 -#define FSL_DDR_ODT_OTHER_DIMM 0x3 -#define FSL_DDR_ODT_ALL 0x4 -#define FSL_DDR_ODT_SAME_DIMM 0x5 -#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 -#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 - -/* define bank(chip select) interleaving mode */ -#define FSL_DDR_CS0_CS1 0x40 -#define FSL_DDR_CS2_CS3 0x20 -#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) -#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) - -/* define memory controller interleaving mode */ -#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 -#define FSL_DDR_PAGE_INTERLEAVING 0x1 -#define FSL_DDR_BANK_INTERLEAVING 0x2 -#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 -#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA -#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC -#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD -/* placeholder for 4-way interleaving */ -#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A -#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C -#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D - -#define SDRAM_CS_CONFIG_EN 0x80000000 - -/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration - */ -#define SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG_SREN 0x40000000 -#define SDRAM_CFG_ECC_EN 0x20000000 -#define SDRAM_CFG_RD_EN 0x10000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 -#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 -#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 -#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 -#define SDRAM_CFG_DYN_PWR 0x00200000 -#define SDRAM_CFG_DBW_MASK 0x00180000 -#define SDRAM_CFG_DBW_SHIFT 19 -#define SDRAM_CFG_32_BE 0x00080000 -#define SDRAM_CFG_16_BE 0x00100000 -#define SDRAM_CFG_8_BE 0x00040000 -#define SDRAM_CFG_NCAP 0x00020000 -#define SDRAM_CFG_2T_EN 0x00008000 -#define SDRAM_CFG_BI 0x00000001 - -#define SDRAM_CFG2_D_INIT 0x00000010 -#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 -#define SDRAM_CFG2_ODT_NEVER 0 -#define SDRAM_CFG2_ODT_ONLY_WRITE 1 -#define SDRAM_CFG2_ODT_ONLY_READ 2 -#define SDRAM_CFG2_ODT_ALWAYS 3 - -#define TIMING_CFG_2_CPO_MASK 0x0F800000 - -#if defined(CONFIG_P4080) -#define RD_TO_PRE_MASK 0xf -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0xf -#define WR_DATA_DELAY_SHIFT 9 -#else -#define RD_TO_PRE_MASK 0x7 -#define RD_TO_PRE_SHIFT 13 -#define WR_DATA_DELAY_MASK 0x7 -#define WR_DATA_DELAY_SHIFT 10 -#endif - -/* DDR_MD_CNTL */ -#define MD_CNTL_MD_EN 0x80000000 -#define MD_CNTL_CS_SEL_CS0 0x00000000 -#define MD_CNTL_CS_SEL_CS1 0x10000000 -#define MD_CNTL_CS_SEL_CS2 0x20000000 -#define MD_CNTL_CS_SEL_CS3 0x30000000 -#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 -#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 -#define MD_CNTL_MD_SEL_MR 0x00000000 -#define MD_CNTL_MD_SEL_EMR 0x01000000 -#define MD_CNTL_MD_SEL_EMR2 0x02000000 -#define MD_CNTL_MD_SEL_EMR3 0x03000000 -#define MD_CNTL_SET_REF 0x00800000 -#define MD_CNTL_SET_PRE 0x00400000 -#define MD_CNTL_CKE_CNTL_LOW 0x00100000 -#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 -#define MD_CNTL_WRCW 0x00080000 -#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) - -/* DDR_CDR1 */ -#define DDR_CDR1_DHC_EN 0x80000000 -#define DDR_CDR1_ODT_SHIFT 17 -#define DDR_CDR1_ODT_MASK 0x6 -#define DDR_CDR2_ODT_MASK 0x1 -#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) -#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) - -#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ - (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) -#define DDR_CDR_ODT_OFF 0x0 -#define DDR_CDR_ODT_120ohm 0x1 -#define DDR_CDR_ODT_180ohm 0x2 -#define DDR_CDR_ODT_75ohm 0x3 -#define DDR_CDR_ODT_110ohm 0x4 -#define DDR_CDR_ODT_60hm 0x5 -#define DDR_CDR_ODT_70ohm 0x6 -#define DDR_CDR_ODT_47ohm 0x7 -#else -#define DDR_CDR_ODT_75ohm 0x0 -#define DDR_CDR_ODT_55ohm 0x1 -#define DDR_CDR_ODT_60ohm 0x2 -#define DDR_CDR_ODT_50ohm 0x3 -#define DDR_CDR_ODT_150ohm 0x4 -#define DDR_CDR_ODT_43ohm 0x5 -#define DDR_CDR_ODT_120ohm 0x6 -#endif - -/* Record of register values computed */ -typedef struct fsl_ddr_cfg_regs_s { - struct { - unsigned int bnds; - unsigned int config; - unsigned int config_2; - } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; - unsigned int timing_cfg_3; - unsigned int timing_cfg_0; - unsigned int timing_cfg_1; - unsigned int timing_cfg_2; - unsigned int ddr_sdram_cfg; - unsigned int ddr_sdram_cfg_2; - unsigned int ddr_sdram_mode; - unsigned int ddr_sdram_mode_2; - unsigned int ddr_sdram_mode_3; - unsigned int ddr_sdram_mode_4; - unsigned int ddr_sdram_mode_5; - unsigned int ddr_sdram_mode_6; - unsigned int ddr_sdram_mode_7; - unsigned int ddr_sdram_mode_8; - unsigned int ddr_sdram_md_cntl; - unsigned int ddr_sdram_interval; - unsigned int ddr_data_init; - unsigned int ddr_sdram_clk_cntl; - unsigned int ddr_init_addr; - unsigned int ddr_init_ext_addr; - unsigned int timing_cfg_4; - unsigned int timing_cfg_5; - unsigned int ddr_zq_cntl; - unsigned int ddr_wrlvl_cntl; - unsigned int ddr_wrlvl_cntl_2; - unsigned int ddr_wrlvl_cntl_3; - unsigned int ddr_sr_cntr; - unsigned int ddr_sdram_rcw_1; - unsigned int ddr_sdram_rcw_2; - unsigned int ddr_eor; - unsigned int ddr_cdr1; - unsigned int ddr_cdr2; - unsigned int err_disable; - unsigned int err_int_en; - unsigned int debug[32]; -} fsl_ddr_cfg_regs_t; - -typedef struct memctl_options_partial_s { - unsigned int all_dimms_ecc_capable; - unsigned int all_dimms_tckmax_ps; - unsigned int all_dimms_burst_lengths_bitmask; - unsigned int all_dimms_registered; - unsigned int all_dimms_unbuffered; - /* unsigned int lowest_common_SPD_caslat; */ - unsigned int all_dimms_minimum_trcd_ps; -} memctl_options_partial_t; - -#define DDR_DATA_BUS_WIDTH_64 0 -#define DDR_DATA_BUS_WIDTH_32 1 -#define DDR_DATA_BUS_WIDTH_16 2 -/* - * Generalized parameters for memory controller configuration, - * might be a little specific to the FSL memory controller - */ -typedef struct memctl_options_s { - /* - * Memory organization parameters - * - * if DIMM is present in the system - * where DIMMs are with respect to chip select - * where chip selects are with respect to memory boundaries - */ - unsigned int registered_dimm_en; /* use registered DIMM support */ - - /* Options local to a Chip Select */ - struct cs_local_opts_s { - unsigned int auto_precharge; - unsigned int odt_rd_cfg; - unsigned int odt_wr_cfg; - unsigned int odt_rtt_norm; - unsigned int odt_rtt_wr; - } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; - - /* Special configurations for chip select */ - unsigned int memctl_interleaving; - unsigned int memctl_interleaving_mode; - unsigned int ba_intlv_ctl; - unsigned int addr_hash; - - /* Operational mode parameters */ - unsigned int ecc_mode; /* Use ECC? */ - /* Initialize ECC using memory controller? */ - unsigned int ecc_init_using_memctl; - unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ - /* SREN - self-refresh during sleep */ - unsigned int self_refresh_in_sleep; - unsigned int dynamic_power; /* DYN_PWR */ - /* memory data width to use (16-bit, 32-bit, 64-bit) */ - unsigned int data_bus_width; - unsigned int burst_length; /* BL4, OTF and BL8 */ - /* On-The-Fly Burst Chop enable */ - unsigned int otf_burst_chop_en; - /* mirrior DIMMs for DDR3 */ - unsigned int mirrored_dimm; - unsigned int quad_rank_present; - unsigned int ap_en; /* address parity enable for RDIMM */ - unsigned int x4_en; /* enable x4 devices */ - - /* Global Timing Parameters */ - unsigned int cas_latency_override; - unsigned int cas_latency_override_value; - unsigned int use_derated_caslat; - unsigned int additive_latency_override; - unsigned int additive_latency_override_value; - - unsigned int clk_adjust; /* */ - unsigned int cpo_override; - unsigned int write_data_delay; /* DQS adjust */ - - unsigned int wrlvl_override; - unsigned int wrlvl_sample; /* Write leveling */ - unsigned int wrlvl_start; - unsigned int wrlvl_ctl_2; - unsigned int wrlvl_ctl_3; - - unsigned int half_strength_driver_enable; - unsigned int twot_en; - unsigned int threet_en; - unsigned int bstopre; - unsigned int tcke_clock_pulse_width_ps; /* tCKE */ - unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ - - /* Rtt impedance */ - unsigned int rtt_override; /* rtt_override enable */ - unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ - unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ - - /* Automatic self refresh */ - unsigned int auto_self_refresh_en; - unsigned int sr_it; - /* ZQ calibration */ - unsigned int zq_en; - /* Write leveling */ - unsigned int wrlvl_en; - /* RCW override for RDIMM */ - unsigned int rcw_override; - unsigned int rcw_1; - unsigned int rcw_2; - /* control register 1 */ - unsigned int ddr_cdr1; - unsigned int ddr_cdr2; - - unsigned int trwt_override; - unsigned int trwt; /* read-to-write turnaround */ -} memctl_options_t; - -extern phys_size_t fsl_ddr_sdram(void); -extern phys_size_t fsl_ddr_sdram_size(void); -extern int fsl_use_spd(void); -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num, int step); -u32 fsl_ddr_get_intl3r(void); - -static void __board_assert_mem_reset(void) -{ -} - -static void __board_deassert_mem_reset(void) -{ -} - -void board_assert_mem_reset(void) - __attribute__((weak, alias("__board_assert_mem_reset"))); - -void board_deassert_mem_reset(void) - __attribute__((weak, alias("__board_deassert_mem_reset"))); - -static int __board_need_mem_reset(void) -{ - return 0; -} - -int board_need_mem_reset(void) - __attribute__((weak, alias("__board_need_mem_reset"))); - -/* - * The 85xx boards have a common prototype for fixed_sdram so put the - * declaration here. - */ -#ifdef CONFIG_MPC85xx -extern phys_size_t fixed_sdram(void); -#endif - -#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - - -typedef struct fixed_ddr_parm{ - int min_freq; - int max_freq; - fsl_ddr_cfg_regs_t *ddr_settings; -} fixed_ddr_parm_t; -#endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 289f7cac52..1042b0c308 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -279,7 +279,7 @@ typedef struct qesba83xx { /* * DDR Memory Controller Memory Map */ -#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) typedef struct ccsr_ddr { u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ u8 res1[4]; @@ -739,7 +739,7 @@ typedef struct immap { u8 dll_ddr[0x100]; u8 dll_lbc[0x100]; u8 res1[0xE00]; -#if defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3) +#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) ccsr_ddr_t ddr; /* DDR Memory Controller Memory */ #else ddr83xx_t ddr; /* DDR Memory Controller Memory */ @@ -1029,7 +1029,7 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) -#define CONFIG_SYS_MPC8xxx_DDR_ADDR \ +#define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) #define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) #define CONFIG_SYS_MPC83xx_DMA_ADDR \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 631261857e..d479216850 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -3048,11 +3048,11 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR_ADDR \ +#define CONFIG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \ +#define CONFIG_SYS_FSL_DDR2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) -#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \ +#define CONFIG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 2a704fe6b7..046a434719 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1253,9 +1253,9 @@ typedef struct immap { extern immap_t *immr; #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 -#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) +#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 -#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) +#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) #define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) #define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c index 23a71d5af5..e1f6865f42 100644 --- a/board/exmeritus/hww1u1a/ddr.c +++ b/board/exmeritus/hww1u1a/ddr.c @@ -9,8 +9,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c index 7c11e38d1c..104987a9b6 100644 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ b/board/exmeritus/hww1u1a/hww1u1a.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -89,7 +89,7 @@ int checkboard(void) * and delay a while before we continue. */ if (mpc85xx_gpio_get(GPIO_RESETS)) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; puts("Debugger detected... extra device reset enabled!\n"); diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index 2d14923139..187c3b3ebc 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -9,11 +9,11 @@ #include #include #include +#include #include -#include -#include +#include +#include #include -#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c index a9e92f2ae0..339c576256 100644 --- a/board/freescale/bsc9131rdb/ddr.c +++ b/board/freescale/bsc9131rdb/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c index dd5ea95e33..974627163a 100644 --- a/board/freescale/bsc9131rdb/spl_minimal.c +++ b/board/freescale/bsc9131rdb/spl_minimal.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; */ static void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index a895e4e297..31bbf62ee5 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #ifdef CONFIG_PCI #include @@ -134,7 +134,7 @@ void dsp_ddr_configure(void) *to the DSP DDR controller as connected DDR memories are similar. */ ccsr_ddr_t __iomem *pa_ddr = - (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR; ccsr_ddr_t temp_ddr; ccsr_ddr_t __iomem *dsp_ddr = (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c index b3130be86d..43f163a2c6 100644 --- a/board/freescale/bsc9132qds/ddr.c +++ b/board/freescale/bsc9132qds/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c index 2bf0a0cfa8..0249dc587f 100644 --- a/board/freescale/bsc9132qds/spl_minimal.c +++ b/board/freescale/bsc9132qds/spl_minimal.c @@ -10,14 +10,14 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; static void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; #if CONFIG_DDR_CLK_FREQ == 100000000 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index 57a9b610ea..968655c1b3 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -6,8 +6,8 @@ #include #include -#include -#include +#include +#include #include "cpld.h" diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 18e2ff617b..e7e893a1ae 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index e5beb55177..5cbec7f5f2 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c index 5a8ed94b04..4dead9c045 100644 --- a/board/freescale/corenet_ds/p3041ds_ddr.c +++ b/board/freescale/corenet_ds/p3041ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include fixed_ddr_parm_t fixed_ddr_parm_0[] = { {0, 0, NULL} diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c index 844e1d736a..d572a5fbed 100644 --- a/board/freescale/corenet_ds/p4080ds_ddr.c +++ b/board/freescale/corenet_ds/p4080ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include #define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000 #define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104 diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c index e65de364d7..9aaf6db997 100644 --- a/board/freescale/corenet_ds/p5020ds_ddr.c +++ b/board/freescale/corenet_ds/p5020ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include fixed_ddr_parm_t fixed_ddr_parm_0[] = { {0, 0, NULL} diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c index e65de364d7..9aaf6db997 100644 --- a/board/freescale/corenet_ds/p5040ds_ddr.c +++ b/board/freescale/corenet_ds/p5040ds_ddr.c @@ -7,7 +7,7 @@ */ #include -#include +#include fixed_ddr_parm_t fixed_ddr_parm_0[] = { {0, 0, NULL} diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile index 23880f52f5..5c315f9f68 100644 --- a/board/freescale/mpc8349emds/Makefile +++ b/board/freescale/mpc8349emds/Makefile @@ -7,4 +7,4 @@ obj-y += mpc8349emds.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_FSL_DDR2) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c index 3d257d0fbf..aae003d121 100644 --- a/board/freescale/mpc8349emds/ddr.c +++ b/board/freescale/mpc8349emds/ddr.c @@ -6,8 +6,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index ec48487294..d9092201aa 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -12,8 +12,8 @@ #include #include #include -#ifdef CONFIG_FSL_DDR2 -#include +#ifdef CONFIG_SYS_FSL_DDR2 +#include #else #include #endif @@ -57,7 +57,7 @@ phys_size_t initdram (int board_type) /* DDR SDRAM - Main SODIMM */ im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) -#ifndef CONFIG_FSL_DDR2 +#ifndef CONFIG_SYS_FSL_DDR2 msize = spd_sdram() * 1024 * 1024; #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) ddr_enable_ecc(msize); diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index d10370c9f2..ebe3ba460c 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 5daab692c6..59e9a35089 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 9e79815278..41d4cfe738 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 175eefcc6b..97a5d19b5e 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include @@ -168,7 +168,7 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index 78d73b0ea8..d2ac6c4ad4 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 8115e5c69b..7b264dddd1 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index 6cf9bc1d75..aa30cabb03 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index dfd8fa6522..1b33db6f31 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index 996ffe206d..b31ea3432e 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 51e4bb5dcb..ca9b43c6b6 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index 78d73b0ea8..d2ac6c4ad4 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index e2093d1bbc..de5f5669e6 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 9e79815278..41d4cfe738 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 90a2522cb9..7104e33156 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -373,7 +373,7 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index b1f4f1f848..6db92ef2da 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index ae80697b38..a8fdcb5f91 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index 68f686b7e6..ef404b1d6f 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index c928a964f9..60f55773da 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include @@ -231,7 +231,7 @@ int checkboard (void) #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; uint d_init; out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index 52e4f4224c..2bfc1a170c 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 657df6a718..2fb4257132 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile index 933ea179ba..2613004f89 100644 --- a/board/freescale/mpc8610hpcd/Makefile +++ b/board/freescale/mpc8610hpcd/Makefile @@ -4,6 +4,6 @@ # obj-y += mpc8610hpcd.o -obj-$(CONFIG_FSL_DDR2) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o obj-y += law.o obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 6cf9bc1d75..aa30cabb03 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index ffdcf2444c..aa99623a43 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile index 8d53af8227..86c70bcb9d 100644 --- a/board/freescale/mpc8641hpcn/Makefile +++ b/board/freescale/mpc8641hpcn/Makefile @@ -7,4 +7,4 @@ obj-y += mpc8641hpcn.o obj-y += law.o -obj-$(CONFIG_FSL_DDR2) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 651652a77d..7cd0395651 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 46a543ebcc..0cd9df1cc9 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c index ab1b41d832..b0d95ea006 100644 --- a/board/freescale/p1010rdb/ddr.c +++ b/board/freescale/p1010rdb/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index d0e712eb30..aa2a3448c5 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 ddr_ratio; unsigned long ddr_freq_mhz; diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index 94d2c2b0db..09212bcee8 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 3d1951cdba..ba789a4daf 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c index 8b34396843..6c7e1ac3cb 100644 --- a/board/freescale/p1022ds/spl_minimal.c +++ b/board/freescale/p1022ds/spl_minimal.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include const static u32 sysclk_tbl[] = { diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c index 9fb61fdab3..d587df527a 100644 --- a/board/freescale/p1023rdb/ddr.c +++ b/board/freescale/p1023rdb/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c index b52b092069..d2d4f8390a 100644 --- a/board/freescale/p1023rdb/p1023rdb.c +++ b/board/freescale/p1023rdb/p1023rdb.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 7c54b65c1d..2cfcdc41f3 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include #include @@ -58,7 +58,7 @@ int checkboard(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 5bee22e638..17d3beac39 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 81cc0930bc..946d5032e7 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 50553dacd9..966abb24a6 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index adfa7b1e0f..92437bc787 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c index 67f69d79bd..a2ce75a40d 100644 --- a/board/freescale/p1_twr/ddr.c +++ b/board/freescale/p1_twr/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c index ea8db6fc07..0e0d0587d7 100644 --- a/board/freescale/p1_twr/p1_twr.c +++ b/board/freescale/p1_twr/p1_twr.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c index da804771fb..b642e1255c 100644 --- a/board/freescale/p2020come/ddr.c +++ b/board/freescale/p2020come/ddr.c @@ -5,8 +5,8 @@ */ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index b12141f296..debe70b18b 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include struct board_specific_parameters { u32 n_ranks; @@ -37,7 +37,7 @@ static const struct board_specific_parameters dimm0[] = { * num| hi| clk| cpo|wrdata|2T * ranks| mhz|adjst| | delay| */ -#ifdef CONFIG_FSL_DDR2 +#ifdef CONFIG_SYS_FSL_DDR2 {2, 549, 4, 0x1f, 2, 0}, {2, 680, 4, 0x1f, 3, 0}, {2, 850, 4, 0x1f, 4, 0}, diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 58a42231a9..dd8c6b10fb 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -68,7 +68,7 @@ int checkboard(void) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; uint d_init; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c index cc1bfae394..b8bbcdf2a8 100644 --- a/board/freescale/p2041rdb/ddr.c +++ b/board/freescale/p2041rdb/ddr.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include struct board_specific_parameters { diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c index 4fd17da160..da89a36b96 100644 --- a/board/freescale/t1040qds/ddr.c +++ b/board/freescale/t1040qds/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include "ddr.h" diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index 8f58dd6832..9009afa3ad 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -8,8 +8,8 @@ #include #include #include -#include -#include +#include +#include #include #include "ddr.h" diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index d70c31051d..7586cc3c4b 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -10,8 +10,8 @@ #include #include #include -#include -#include +#include +#include #include #include "ddr.h" diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c index b5f488bcba..24cf907430 100644 --- a/board/freescale/t4qds/eth.c +++ b/board/freescale/t4qds/eth.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index 81c22bc94c..8ccd9ce6ba 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c index 4a652de430..7596736bfd 100644 --- a/board/gdsys/p1022/ddr.c +++ b/board/gdsys/p1022/ddr.c @@ -12,8 +12,8 @@ #include #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c index bd425aab1a..34ac6979bd 100644 --- a/board/keymile/kmp204x/ddr.c +++ b/board/keymile/kmp204x/ddr.c @@ -11,8 +11,8 @@ #include #include #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index b1e32a668b..4c9b6cd60c 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -11,4 +11,4 @@ obj-y += sbc8548.o obj-y += law.o obj-y += tlb.o -obj-$(CONFIG_FSL_DDR2) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 9508561133..8817103ba7 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -9,8 +9,8 @@ #include #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, @@ -91,7 +91,7 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); out_be32(&ddr->cs0_bnds, 0x0000007f); out_be32(&ddr->cs1_bnds, 0x008000ff); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 3cd945f2c2..d584276253 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile index 9626b06a5a..a9b20266bc 100644 --- a/board/sbc8641d/Makefile +++ b/board/sbc8641d/Makefile @@ -7,4 +7,4 @@ obj-y += sbc8641d.o obj-y += law.o -obj-$(CONFIG_FSL_DDR2) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index 996ffe206d..b31ea3432e 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 0b5e8dc17e..8160c7b580 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/socrates/Makefile b/board/socrates/Makefile index 0a088100e8..79bda718d5 100644 --- a/board/socrates/Makefile +++ b/board/socrates/Makefile @@ -12,4 +12,4 @@ obj-y += law.o obj-y += tlb.o obj-y += nand.o obj-y += sdram.o -obj-$(CONFIG_FSL_DDR2) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index e9db476f48..6bad4da394 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 313efae90f..356e8e82e7 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include #include #include @@ -24,7 +24,7 @@ */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); /* * Disable memory controller. diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile index 9b724347de..78e2d6c96f 100644 --- a/board/stx/stxgp3/Makefile +++ b/board/stx/stxgp3/Makefile @@ -9,4 +9,4 @@ obj-y += stxgp3.o obj-y += law.o obj-y += tlb.o obj-y += flash.o -obj-$(CONFIG_FSL_DDR1) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index 9e79815278..41d4cfe738 100644 --- a/board/stx/stxgp3/ddr.c +++ b/board/stx/stxgp3/ddr.c @@ -8,8 +8,8 @@ #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index bd683f6af8..c80d5259ce 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile index 17e0aaea7e..b1d4b0a270 100644 --- a/board/stx/stxssa/Makefile +++ b/board/stx/stxssa/Makefile @@ -8,4 +8,4 @@ obj-y += stxssa.o obj-y += law.o obj-y += tlb.o -obj-$(CONFIG_FSL_DDR1) += ddr.o +obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index 71be3bf636..1ccd4c5183 100644 --- a/board/stx/stxssa/ddr.c +++ b/board/stx/stxssa/ddr.c @@ -9,8 +9,8 @@ #include #include -#include -#include +#include +#include void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index c08a18bffe..f5c3d750ce 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c index f48c02fdae..fd602ea7e0 100644 --- a/board/xes/xpedite517x/ddr.c +++ b/board/xes/xpedite517x/ddr.c @@ -7,8 +7,8 @@ #include #include -#include -#include +#include +#include void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 1782042510..b7ad349502 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include #include diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index 3671cb8af9..5c5eadc93f 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -9,8 +9,8 @@ #include #include -#include -#include +#include +#include void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c index f41ae73755..56b5a187d8 100644 --- a/board/xes/xpedite537x/ddr.c +++ b/board/xes/xpedite537x/ddr.c @@ -8,8 +8,8 @@ #include #include -#include -#include +#include +#include void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 9fc6f048c4..0c0605e3a9 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -8,8 +8,8 @@ #include #include -#include -#include +#include +#include void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address) { diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile new file mode 100644 index 0000000000..a328b43209 --- /dev/null +++ b/drivers/ddr/fsl/Makefile @@ -0,0 +1,34 @@ +# +# Copyright 2008-2011 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# Version 2 as published by the Free Software Foundation. +# + +obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o + +obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o + +obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ + lc_common_dimm_params.o +ifdef CONFIG_DDR_SPD +SPD := y +endif +ifdef CONFIG_SPD_EEPROM +SPD := y +endif +ifdef SPD +obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o +obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o +endif + +obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o +obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o +obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o +obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c new file mode 100644 index 0000000000..aed4569cb4 --- /dev/null +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -0,0 +1,1657 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + */ + +#include +#include + +#include +#include + +#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR + +static u32 fsl_ddr_get_version(void) +{ + ccsr_ddr_t *ddr; + u32 ver_major_minor_errata; + + ddr = (void *)_DDR_ADDR; + ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; + + return ver_major_minor_errata; +} + +unsigned int picos_to_mclk(unsigned int picos); + +/* + * Determine Rtt value. + * + * This should likely be either board or controller specific. + * + * Rtt(nominal) - DDR2: + * 0 = Rtt disabled + * 1 = 75 ohm + * 2 = 150 ohm + * 3 = 50 ohm + * Rtt(nominal) - DDR3: + * 0 = Rtt disabled + * 1 = 60 ohm + * 2 = 120 ohm + * 3 = 40 ohm + * 4 = 20 ohm + * 5 = 30 ohm + * + * FIXME: Apparently 8641 needs a value of 2 + * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 + * + * FIXME: There was some effort down this line earlier: + * + * unsigned int i; + * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { + * if (popts->dimmslot[i].num_valid_cs + * && (popts->cs_local_opts[2*i].odt_rd_cfg + * || popts->cs_local_opts[2*i].odt_wr_cfg)) { + * rtt = 2; + * break; + * } + * } + */ +static inline int fsl_ddr_get_rtt(void) +{ + int rtt; + +#if defined(CONFIG_SYS_FSL_DDR1) + rtt = 0; +#elif defined(CONFIG_SYS_FSL_DDR2) + rtt = 3; +#else + rtt = 0; +#endif + + return rtt; +} + +/* + * compute the CAS write latency according to DDR3 spec + * CWL = 5 if tCK >= 2.5ns + * 6 if 2.5ns > tCK >= 1.875ns + * 7 if 1.875ns > tCK >= 1.5ns + * 8 if 1.5ns > tCK >= 1.25ns + * 9 if 1.25ns > tCK >= 1.07ns + * 10 if 1.07ns > tCK >= 0.935ns + * 11 if 0.935ns > tCK >= 0.833ns + * 12 if 0.833ns > tCK >= 0.75ns + */ +static inline unsigned int compute_cas_write_latency(void) +{ + unsigned int cwl; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + + if (mclk_ps >= 2500) + cwl = 5; + else if (mclk_ps >= 1875) + cwl = 6; + else if (mclk_ps >= 1500) + cwl = 7; + else if (mclk_ps >= 1250) + cwl = 8; + else if (mclk_ps >= 1070) + cwl = 9; + else if (mclk_ps >= 935) + cwl = 10; + else if (mclk_ps >= 833) + cwl = 11; + else if (mclk_ps >= 750) + cwl = 12; + else { + cwl = 12; + printf("Warning: CWL is out of range\n"); + } + return cwl; +} + +/* Chip Select Configuration (CSn_CONFIG) */ +static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const dimm_params_t *dimm_params) +{ + unsigned int cs_n_en = 0; /* Chip Select enable */ + unsigned int intlv_en = 0; /* Memory controller interleave enable */ + unsigned int intlv_ctl = 0; /* Interleaving control */ + unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ + unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ + unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ + unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ + unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ + unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ + int go_config = 0; + + /* Compute CS_CONFIG only for existing ranks of each DIMM. */ + switch (i) { + case 0: + if (dimm_params[dimm_number].n_ranks > 0) { + go_config = 1; + /* These fields only available in CS0_CONFIG */ + if (!popts->memctl_interleaving) + break; + switch (popts->memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + intlv_en = popts->memctl_interleaving; + intlv_ctl = popts->memctl_interleaving_mode; + break; + default: + break; + } + } + break; + case 1: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ + (dimm_number == 1 && dimm_params[1].n_ranks > 0)) + go_config = 1; + break; + case 2: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ + (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) + go_config = 1; + break; + case 3: + if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ + (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ + (dimm_number == 3 && dimm_params[3].n_ranks > 0)) + go_config = 1; + break; + default: + break; + } + if (go_config) { + unsigned int n_banks_per_sdram_device; + cs_n_en = 1; + ap_n_en = popts->cs_local_opts[i].auto_precharge; + odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; + odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; + n_banks_per_sdram_device + = dimm_params[dimm_number].n_banks_per_sdram_device; + ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; + row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; + col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; + } + ddr->cs[i].config = (0 + | ((cs_n_en & 0x1) << 31) + | ((intlv_en & 0x3) << 29) + | ((intlv_ctl & 0xf) << 24) + | ((ap_n_en & 0x1) << 23) + + /* XXX: some implementation only have 1 bit starting at left */ + | ((odt_rd_cfg & 0x7) << 20) + + /* XXX: Some implementation only have 1 bit starting at left */ + | ((odt_wr_cfg & 0x7) << 16) + + | ((ba_bits_cs_n & 0x3) << 14) + | ((row_bits_cs_n & 0x7) << 8) + | ((col_bits_cs_n & 0x7) << 0) + ); + debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); +} + +/* Chip Select Configuration 2 (CSn_CONFIG_2) */ +/* FIXME: 8572 */ +static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int pasr_cfg = 0; /* Partial array self refresh config */ + + ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); + debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); +} + +/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ + +#if !defined(CONFIG_SYS_FSL_DDR1) +static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) +{ +#if CONFIG_DIMM_SLOTS_PER_CTLR == 1 + if (dimm_params[0].n_ranks == 4) + return 1; +#endif + +#if CONFIG_DIMM_SLOTS_PER_CTLR == 2 + if ((dimm_params[0].n_ranks == 2) && + (dimm_params[1].n_ranks == 2)) + return 1; + +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (dimm_params[0].n_ranks == 4) + return 1; +#endif +#endif + return 0; +} + +/* + * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) + * + * Avoid writing for DDR I. The new PQ38 DDR controller + * dreams up non-zero default values to be backwards compatible. + */ +static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const dimm_params_t *dimm_params) +{ + unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ + unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ + /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ + unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ + unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ + + /* Active powerdown exit timing (tXARD and tXARDS). */ + unsigned char act_pd_exit_mclk; + /* Precharge powerdown exit timing (tXP). */ + unsigned char pre_pd_exit_mclk; + /* ODT powerdown exit timing (tAXPD). */ + unsigned char taxpd_mclk; + /* Mode register set cycle time (tMRD). */ + unsigned char tmrd_mclk; + +#ifdef CONFIG_SYS_FSL_DDR3 + /* + * (tXARD and tXARDS). Empirical? + * The DDR3 spec has not tXARD, + * we use the tXP instead of it. + * tXP=max(3nCK, 7.5ns) for DDR3. + * spec has not the tAXPD, we use + * tAXPD=1, need design to confirm. + */ + int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ + unsigned int data_rate = get_ddr_freq(0); + tmrd_mclk = 4; + /* set the turnaround time */ + + /* + * for single quad-rank DIMM and two dual-rank DIMMs + * to avoid ODT overlap + */ + if (avoid_odt_overlap(dimm_params)) { + twwt_mclk = 2; + trrt_mclk = 1; + } + /* for faster clock, need more time for data setup */ + trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; + + if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) + twrt_mclk = 1; + + if (popts->dynamic_power == 0) { /* powerdown is not used */ + act_pd_exit_mclk = 1; + pre_pd_exit_mclk = 1; + taxpd_mclk = 1; + } else { + /* act_pd_exit_mclk = tXARD, see above */ + act_pd_exit_mclk = picos_to_mclk(tXP); + /* Mode register MR0[A12] is '1' - fast exit */ + pre_pd_exit_mclk = act_pd_exit_mclk; + taxpd_mclk = 1; + } +#else /* CONFIG_SYS_FSL_DDR2 */ + /* + * (tXARD and tXARDS). Empirical? + * tXARD = 2 for DDR2 + * tXP=2 + * tAXPD=8 + */ + act_pd_exit_mclk = 2; + pre_pd_exit_mclk = 2; + taxpd_mclk = 8; + tmrd_mclk = 2; +#endif + + if (popts->trwt_override) + trwt_mclk = popts->trwt; + + ddr->timing_cfg_0 = (0 + | ((trwt_mclk & 0x3) << 30) /* RWT */ + | ((twrt_mclk & 0x3) << 28) /* WRT */ + | ((trrt_mclk & 0x3) << 26) /* RRT */ + | ((twwt_mclk & 0x3) << 24) /* WWT */ + | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ + | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ + | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ + | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ + ); + debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); +} +#endif /* defined(CONFIG_SYS_FSL_DDR2) */ + +/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ +static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) +{ + /* Extended precharge to activate interval (tRP) */ + unsigned int ext_pretoact = 0; + /* Extended Activate to precharge interval (tRAS) */ + unsigned int ext_acttopre = 0; + /* Extended activate to read/write interval (tRCD) */ + unsigned int ext_acttorw = 0; + /* Extended refresh recovery time (tRFC) */ + unsigned int ext_refrec; + /* Extended MCAS latency from READ cmd */ + unsigned int ext_caslat = 0; + /* Extended last data to precharge interval (tWR) */ + unsigned int ext_wrrec = 0; + /* Control Adjust */ + unsigned int cntl_adj = 0; + + ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; + ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; + ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; + ext_caslat = (2 * cas_latency - 1) >> 4; + ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; + /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ + ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + + (popts->otf_burst_chop_en ? 2 : 0)) >> 4; + + ddr->timing_cfg_3 = (0 + | ((ext_pretoact & 0x1) << 28) + | ((ext_acttopre & 0x3) << 24) + | ((ext_acttorw & 0x1) << 22) + | ((ext_refrec & 0x1F) << 16) + | ((ext_caslat & 0x3) << 12) + | ((ext_wrrec & 0x1) << 8) + | ((cntl_adj & 0x7) << 0) + ); + debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); +} + +/* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ +static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) +{ + /* Precharge-to-activate interval (tRP) */ + unsigned char pretoact_mclk; + /* Activate to precharge interval (tRAS) */ + unsigned char acttopre_mclk; + /* Activate to read/write interval (tRCD) */ + unsigned char acttorw_mclk; + /* CASLAT */ + unsigned char caslat_ctrl; + /* Refresh recovery time (tRFC) ; trfc_low */ + unsigned char refrec_ctrl; + /* Last data to precharge minimum interval (tWR) */ + unsigned char wrrec_mclk; + /* Activate-to-activate interval (tRRD) */ + unsigned char acttoact_mclk; + /* Last write data pair to read command issue interval (tWTR) */ + unsigned char wrtord_mclk; + /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ + static const u8 wrrec_table[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; + + pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); + acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); + acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); + + /* + * Translate CAS Latency to a DDR controller field value: + * + * CAS Lat DDR I DDR II Ctrl + * Clocks SPD Bit SPD Bit Value + * ------- ------- ------- ----- + * 1.0 0 0001 + * 1.5 1 0010 + * 2.0 2 2 0011 + * 2.5 3 0100 + * 3.0 4 3 0101 + * 3.5 5 0110 + * 4.0 4 0111 + * 4.5 1000 + * 5.0 5 1001 + */ +#if defined(CONFIG_SYS_FSL_DDR1) + caslat_ctrl = (cas_latency + 1) & 0x07; +#elif defined(CONFIG_SYS_FSL_DDR2) + caslat_ctrl = 2 * cas_latency - 1; +#else + /* + * if the CAS latency more than 8 cycle, + * we need set extend bit for it at + * TIMING_CFG_3[EXT_CASLAT] + */ + caslat_ctrl = 2 * cas_latency - 1; +#endif + + refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; + wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); + + if (wrrec_mclk > 16) + printf("Error: WRREC doesn't support more than 16 clocks\n"); + else + wrrec_mclk = wrrec_table[wrrec_mclk - 1]; + if (popts->otf_burst_chop_en) + wrrec_mclk += 2; + + acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); + /* + * JEDEC has min requirement for tRRD + */ +#if defined(CONFIG_SYS_FSL_DDR3) + if (acttoact_mclk < 4) + acttoact_mclk = 4; +#endif + wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); + /* + * JEDEC has some min requirements for tWTR + */ +#if defined(CONFIG_SYS_FSL_DDR2) + if (wrtord_mclk < 2) + wrtord_mclk = 2; +#elif defined(CONFIG_SYS_FSL_DDR3) + if (wrtord_mclk < 4) + wrtord_mclk = 4; +#endif + if (popts->otf_burst_chop_en) + wrtord_mclk += 2; + + ddr->timing_cfg_1 = (0 + | ((pretoact_mclk & 0x0F) << 28) + | ((acttopre_mclk & 0x0F) << 24) + | ((acttorw_mclk & 0xF) << 20) + | ((caslat_ctrl & 0xF) << 16) + | ((refrec_ctrl & 0xF) << 12) + | ((wrrec_mclk & 0x0F) << 8) + | ((acttoact_mclk & 0x0F) << 4) + | ((wrtord_mclk & 0x0F) << 0) + ); + debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); +} + +/* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ +static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) +{ + /* Additive latency */ + unsigned char add_lat_mclk; + /* CAS-to-preamble override */ + unsigned short cpo; + /* Write latency */ + unsigned char wr_lat; + /* Read to precharge (tRTP) */ + unsigned char rd_to_pre; + /* Write command to write data strobe timing adjustment */ + unsigned char wr_data_delay; + /* Minimum CKE pulse width (tCKE) */ + unsigned char cke_pls; + /* Window for four activates (tFAW) */ + unsigned short four_act; + + /* FIXME add check that this must be less than acttorw_mclk */ + add_lat_mclk = additive_latency; + cpo = popts->cpo_override; + +#if defined(CONFIG_SYS_FSL_DDR1) + /* + * This is a lie. It should really be 1, but if it is + * set to 1, bits overlap into the old controller's + * otherwise unused ACSM field. If we leave it 0, then + * the HW will magically treat it as 1 for DDR 1. Oh Yea. + */ + wr_lat = 0; +#elif defined(CONFIG_SYS_FSL_DDR2) + wr_lat = cas_latency - 1; +#else + wr_lat = compute_cas_write_latency(); +#endif + + rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); + /* + * JEDEC has some min requirements for tRTP + */ +#if defined(CONFIG_SYS_FSL_DDR2) + if (rd_to_pre < 2) + rd_to_pre = 2; +#elif defined(CONFIG_SYS_FSL_DDR3) + if (rd_to_pre < 4) + rd_to_pre = 4; +#endif + if (additive_latency) + rd_to_pre += additive_latency; + if (popts->otf_burst_chop_en) + rd_to_pre += 2; /* according to UM */ + + wr_data_delay = popts->write_data_delay; + cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps); + four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); + + ddr->timing_cfg_2 = (0 + | ((add_lat_mclk & 0xf) << 28) + | ((cpo & 0x1f) << 23) + | ((wr_lat & 0xf) << 19) + | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) + | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) + | ((cke_pls & 0x7) << 6) + | ((four_act & 0x3f) << 0) + ); + debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); +} + +/* DDR SDRAM Register Control Word */ +static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + if (common_dimm->all_dimms_registered && + !common_dimm->all_dimms_unbuffered) { + if (popts->rcw_override) { + ddr->ddr_sdram_rcw_1 = popts->rcw_1; + ddr->ddr_sdram_rcw_2 = popts->rcw_2; + } else { + ddr->ddr_sdram_rcw_1 = + common_dimm->rcw[0] << 28 | \ + common_dimm->rcw[1] << 24 | \ + common_dimm->rcw[2] << 20 | \ + common_dimm->rcw[3] << 16 | \ + common_dimm->rcw[4] << 12 | \ + common_dimm->rcw[5] << 8 | \ + common_dimm->rcw[6] << 4 | \ + common_dimm->rcw[7]; + ddr->ddr_sdram_rcw_2 = + common_dimm->rcw[8] << 28 | \ + common_dimm->rcw[9] << 24 | \ + common_dimm->rcw[10] << 20 | \ + common_dimm->rcw[11] << 16 | \ + common_dimm->rcw[12] << 12 | \ + common_dimm->rcw[13] << 8 | \ + common_dimm->rcw[14] << 4 | \ + common_dimm->rcw[15]; + } + debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); + debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); + } +} + +/* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ +static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + unsigned int mem_en; /* DDR SDRAM interface logic enable */ + unsigned int sren; /* Self refresh enable (during sleep) */ + unsigned int ecc_en; /* ECC enable. */ + unsigned int rd_en; /* Registered DIMM enable */ + unsigned int sdram_type; /* Type of SDRAM */ + unsigned int dyn_pwr; /* Dynamic power management mode */ + unsigned int dbw; /* DRAM dta bus width */ + unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ + unsigned int ncap = 0; /* Non-concurrent auto-precharge */ + unsigned int threet_en; /* Enable 3T timing */ + unsigned int twot_en; /* Enable 2T timing */ + unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ + unsigned int x32_en = 0; /* x32 enable */ + unsigned int pchb8 = 0; /* precharge bit 8 enable */ + unsigned int hse; /* Global half strength override */ + unsigned int mem_halt = 0; /* memory controller halt */ + unsigned int bi = 0; /* Bypass initialization */ + + mem_en = 1; + sren = popts->self_refresh_in_sleep; + if (common_dimm->all_dimms_ecc_capable) { + /* Allow setting of ECC only if all DIMMs are ECC. */ + ecc_en = popts->ecc_mode; + } else { + ecc_en = 0; + } + + if (common_dimm->all_dimms_registered && + !common_dimm->all_dimms_unbuffered) { + rd_en = 1; + twot_en = 0; + } else { + rd_en = 0; + twot_en = popts->twot_en; + } + + sdram_type = CONFIG_FSL_SDRAM_TYPE; + + dyn_pwr = popts->dynamic_power; + dbw = popts->data_bus_width; + /* 8-beat burst enable DDR-III case + * we must clear it when use the on-the-fly mode, + * must set it when use the 32-bits bus mode. + */ + if (sdram_type == SDRAM_TYPE_DDR3) { + if (popts->burst_length == DDR_BL8) + eight_be = 1; + if (popts->burst_length == DDR_OTF) + eight_be = 0; + if (dbw == 0x1) + eight_be = 1; + } + + threet_en = popts->threet_en; + ba_intlv_ctl = popts->ba_intlv_ctl; + hse = popts->half_strength_driver_enable; + + ddr->ddr_sdram_cfg = (0 + | ((mem_en & 0x1) << 31) + | ((sren & 0x1) << 30) + | ((ecc_en & 0x1) << 29) + | ((rd_en & 0x1) << 28) + | ((sdram_type & 0x7) << 24) + | ((dyn_pwr & 0x1) << 21) + | ((dbw & 0x3) << 19) + | ((eight_be & 0x1) << 18) + | ((ncap & 0x1) << 17) + | ((threet_en & 0x1) << 16) + | ((twot_en & 0x1) << 15) + | ((ba_intlv_ctl & 0x7F) << 8) + | ((x32_en & 0x1) << 5) + | ((pchb8 & 0x1) << 4) + | ((hse & 0x1) << 3) + | ((mem_halt & 0x1) << 1) + | ((bi & 0x1) << 0) + ); + debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); +} + +/* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ +static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const unsigned int unq_mrs_en) +{ + unsigned int frc_sr = 0; /* Force self refresh */ + unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ + unsigned int dll_rst_dis; /* DLL reset disable */ + unsigned int dqs_cfg; /* DQS configuration */ + unsigned int odt_cfg = 0; /* ODT configuration */ + unsigned int num_pr; /* Number of posted refreshes */ + unsigned int slow = 0; /* DDR will be run less than 1250 */ + unsigned int x4_en = 0; /* x4 DRAM enable */ + unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ + unsigned int ap_en; /* Address Parity Enable */ + unsigned int d_init; /* DRAM data initialization */ + unsigned int rcw_en = 0; /* Register Control Word Enable */ + unsigned int md_en = 0; /* Mirrored DIMM Enable */ + unsigned int qd_en = 0; /* quad-rank DIMM Enable */ + int i; + + dll_rst_dis = 1; /* Make this configurable */ + dqs_cfg = popts->dqs_config; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->cs_local_opts[i].odt_rd_cfg + || popts->cs_local_opts[i].odt_wr_cfg) { + odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; + break; + } + } + + num_pr = 1; /* Make this configurable */ + + /* + * 8572 manual says + * {TIMING_CFG_1[PRETOACT] + * + [DDR_SDRAM_CFG_2[NUM_PR] + * * ({EXT_REFREC || REFREC} + 8 + 2)]} + * << DDR_SDRAM_INTERVAL[REFINT] + */ +#if defined(CONFIG_SYS_FSL_DDR3) + obc_cfg = popts->otf_burst_chop_en; +#else + obc_cfg = 0; +#endif + +#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) + slow = get_ddr_freq(0) < 1249000000; +#endif + + if (popts->registered_dimm_en) { + rcw_en = 1; + ap_en = popts->ap_en; + } else { + ap_en = 0; + } + + x4_en = popts->x4_en ? 1 : 0; + +#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Use the DDR controller to auto initialize memory. */ + d_init = popts->ecc_init_using_memctl; + ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; + debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); +#else + /* Memory will be initialized via DMA, or not at all. */ + d_init = 0; +#endif + +#if defined(CONFIG_SYS_FSL_DDR3) + md_en = popts->mirrored_dimm; +#endif + qd_en = popts->quad_rank_present ? 1 : 0; + ddr->ddr_sdram_cfg_2 = (0 + | ((frc_sr & 0x1) << 31) + | ((sr_ie & 0x1) << 30) + | ((dll_rst_dis & 0x1) << 29) + | ((dqs_cfg & 0x3) << 26) + | ((odt_cfg & 0x3) << 21) + | ((num_pr & 0xf) << 12) + | ((slow & 1) << 11) + | (x4_en << 10) + | (qd_en << 9) + | (unq_mrs_en << 8) + | ((obc_cfg & 0x1) << 6) + | ((ap_en & 0x1) << 5) + | ((d_init & 0x1) << 4) + | ((rcw_en & 0x1) << 2) + | ((md_en & 0x1) << 0) + ); + debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); +} + +/* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ + unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ + +#if defined(CONFIG_SYS_FSL_DDR3) + int i; + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ + unsigned int srt = 0; /* self-refresh temerature, normal range */ + unsigned int asr = 0; /* auto self-refresh disable */ + unsigned int cwl = compute_cas_write_latency() - 5; + unsigned int pasr = 0; /* partial array self refresh disable */ + + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; + + if (common_dimm->extended_op_srt) + srt = common_dimm->extended_op_srt; + + esdmode2 = (0 + | ((rtt_wr & 0x3) << 9) + | ((srt & 0x1) << 7) + | ((asr & 0x1) << 6) + | ((cwl & 0x7) << 3) + | ((pasr & 0x7) << 0)); +#endif + ddr->ddr_sdram_mode_2 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); + +#ifdef CONFIG_SYS_FSL_DDR3 + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + else + rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; + + esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ + esdmode2 |= (rtt_wr & 0x3) << 9; + switch (i) { + case 1: + ddr->ddr_sdram_mode_4 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_6 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_8 = (0 + | ((esdmode2 & 0xFFFF) << 16) + | ((esdmode3 & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", + ddr->ddr_sdram_mode_4); + debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", + ddr->ddr_sdram_mode_6); + debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", + ddr->ddr_sdram_mode_8); + } +#endif +} + +/* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ +static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) +{ + unsigned int refint; /* Refresh interval */ + unsigned int bstopre; /* Precharge interval */ + + refint = picos_to_mclk(common_dimm->refresh_rate_ps); + + bstopre = popts->bstopre; + + /* refint field used 0x3FFF in earlier controllers */ + ddr->ddr_sdram_interval = (0 + | ((refint & 0xFFFF) << 16) + | ((bstopre & 0x3FFF) << 0) + ); + debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); +} + +#if defined(CONFIG_SYS_FSL_DDR3) +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* Mode Register - MR1 */ + unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ + unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ + unsigned int rtt; + unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ + unsigned int al = 0; /* Posted CAS# additive latency (AL) */ + unsigned int dic = 0; /* Output driver impedance, 40ohm */ + unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), + 1=Disable (Test/Debug) */ + + /* Mode Register - MR0 */ + unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ + unsigned int wr = 0; /* Write Recovery */ + unsigned int dll_rst; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ + /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + + unsigned int wr_mclk; + /* + * DDR_SDRAM_MODE doesn't support 9,11,13,15 + * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 + * for this table + */ + static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; + + const unsigned int mclk_ps = get_memory_clk_period_ps(); + int i; + + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[0].odt_rtt_norm; + + if (additive_latency == (cas_latency - 1)) + al = 1; + if (additive_latency == (cas_latency - 2)) + al = 2; + + if (popts->quad_rank_present) + dic = 1; /* output driver impedance 240/7 ohm */ + + /* + * The esdmode value will also be used for writing + * MR1 during write leveling for DDR3, although the + * bits specifically related to the write leveling + * scheme will be handled automatically by the DDR + * controller. so we set the wrlvl_en = 0 here. + */ + esdmode = (0 + | ((qoff & 0x1) << 12) + | ((tdqs_en & 0x1) << 11) + | ((rtt & 0x4) << 7) /* rtt field is split */ + | ((wrlvl_en & 0x1) << 7) + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((dic & 0x2) << 4) /* DIC field is split */ + | ((al & 0x3) << 3) + | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((dic & 0x1) << 1) /* DIC field is split */ + | ((dll_en & 0x1) << 0) + ); + + /* + * DLL control for precharge PD + * 0=slow exit DLL off (tXPDLL) + * 1=fast exit DLL on (tXP) + */ + dll_on = 1; + + wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps; + if (wr_mclk <= 16) { + wr = wr_table[wr_mclk - 5]; + } else { + printf("Error: unsupported write recovery for mode register " + "wr_mclk = %d\n", wr_mclk); + } + + dll_rst = 0; /* dll no reset */ + mode = 0; /* normal mode */ + + /* look up table to get the cas latency bits */ + if (cas_latency >= 5 && cas_latency <= 16) { + unsigned char cas_latency_table[] = { + 0x2, /* 5 clocks */ + 0x4, /* 6 clocks */ + 0x6, /* 7 clocks */ + 0x8, /* 8 clocks */ + 0xa, /* 9 clocks */ + 0xc, /* 10 clocks */ + 0xe, /* 11 clocks */ + 0x1, /* 12 clocks */ + 0x3, /* 13 clocks */ + 0x5, /* 14 clocks */ + 0x7, /* 15 clocks */ + 0x9, /* 16 clocks */ + }; + caslat = cas_latency_table[cas_latency - 5]; + } else { + printf("Error: unsupported cas latency for mode register\n"); + } + + bt = 0; /* Nibble sequential */ + + switch (popts->burst_length) { + case DDR_BL8: + bl = 0; + break; + case DDR_OTF: + bl = 1; + break; + case DDR_BC4: + bl = 2; + break; + default: + printf("Error: invalid burst length of %u specified. " + " Defaulting to on-the-fly BC4 or BL8 beats.\n", + popts->burst_length); + bl = 1; + break; + } + + sdmode = (0 + | ((dll_on & 0x1) << 12) + | ((wr & 0x7) << 9) + | ((dll_rst & 0x1) << 8) + | ((mode & 0x1) << 7) + | (((caslat >> 1) & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((caslat & 1) << 2) + | ((bl & 0x3) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); + + if (unq_mrs_en) { /* unique mode registers are supported */ + for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (popts->rtt_override) + rtt = popts->rtt_override_value; + else + rtt = popts->cs_local_opts[i].odt_rtt_norm; + + esdmode &= 0xFDBB; /* clear bit 9,6,2 */ + esdmode |= (0 + | ((rtt & 0x4) << 7) /* rtt field is split */ + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((rtt & 0x1) << 2) /* rtt field is split */ + ); + switch (i) { + case 1: + ddr->ddr_sdram_mode_3 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 2: + ddr->ddr_sdram_mode_5 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + case 3: + ddr->ddr_sdram_mode_7 = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + break; + } + } + debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", + ddr->ddr_sdram_mode_3); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", + ddr->ddr_sdram_mode_5); + } +} + +#else /* !CONFIG_SYS_FSL_DDR3 */ + +/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ +static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency, + const unsigned int unq_mrs_en) +{ + unsigned short esdmode; /* Extended SDRAM mode */ + unsigned short sdmode; /* SDRAM mode */ + + /* + * FIXME: This ought to be pre-calculated in a + * technology-specific routine, + * e.g. compute_DDR2_mode_register(), and then the + * sdmode and esdmode passed in as part of common_dimm. + */ + + /* Extended Mode Register */ + unsigned int mrs = 0; /* Mode Register Set */ + unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ + unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ + unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ + unsigned int ocd = 0; /* 0x0=OCD not supported, + 0x7=OCD default state */ + unsigned int rtt; + unsigned int al; /* Posted CAS# additive latency (AL) */ + unsigned int ods = 0; /* Output Drive Strength: + 0 = Full strength (18ohm) + 1 = Reduced strength (4ohm) */ + unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), + 1=Disable (Test/Debug) */ + + /* Mode Register (MR) */ + unsigned int mr; /* Mode Register Definition */ + unsigned int pd; /* Power-Down Mode */ + unsigned int wr; /* Write Recovery */ + unsigned int dll_res; /* DLL Reset */ + unsigned int mode; /* Normal=0 or Test=1 */ + unsigned int caslat = 0;/* CAS# latency */ + /* BT: Burst Type (0=Sequential, 1=Interleaved) */ + unsigned int bt; + unsigned int bl; /* BL: Burst Length */ + +#if defined(CONFIG_SYS_FSL_DDR2) + const unsigned int mclk_ps = get_memory_clk_period_ps(); +#endif + dqs_en = !popts->dqs_config; + rtt = fsl_ddr_get_rtt(); + + al = additive_latency; + + esdmode = (0 + | ((mrs & 0x3) << 14) + | ((outputs & 0x1) << 12) + | ((rdqs_en & 0x1) << 11) + | ((dqs_en & 0x1) << 10) + | ((ocd & 0x7) << 7) + | ((rtt & 0x2) << 5) /* rtt field is split */ + | ((al & 0x7) << 3) + | ((rtt & 0x1) << 2) /* rtt field is split */ + | ((ods & 0x1) << 1) + | ((dll_en & 0x1) << 0) + ); + + mr = 0; /* FIXME: CHECKME */ + + /* + * 0 = Fast Exit (Normal) + * 1 = Slow Exit (Low Power) + */ + pd = 0; + +#if defined(CONFIG_SYS_FSL_DDR1) + wr = 0; /* Historical */ +#elif defined(CONFIG_SYS_FSL_DDR2) + wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1; +#endif + dll_res = 0; + mode = 0; + +#if defined(CONFIG_SYS_FSL_DDR1) + if (1 <= cas_latency && cas_latency <= 4) { + unsigned char mode_caslat_table[4] = { + 0x5, /* 1.5 clocks */ + 0x2, /* 2.0 clocks */ + 0x6, /* 2.5 clocks */ + 0x3 /* 3.0 clocks */ + }; + caslat = mode_caslat_table[cas_latency - 1]; + } else { + printf("Warning: unknown cas_latency %d\n", cas_latency); + } +#elif defined(CONFIG_SYS_FSL_DDR2) + caslat = cas_latency; +#endif + bt = 0; + + switch (popts->burst_length) { + case DDR_BL4: + bl = 2; + break; + case DDR_BL8: + bl = 3; + break; + default: + printf("Error: invalid burst length of %u specified. " + " Defaulting to 4 beats.\n", + popts->burst_length); + bl = 2; + break; + } + + sdmode = (0 + | ((mr & 0x3) << 14) + | ((pd & 0x1) << 12) + | ((wr & 0x7) << 9) + | ((dll_res & 0x1) << 8) + | ((mode & 0x1) << 7) + | ((caslat & 0x7) << 4) + | ((bt & 0x1) << 3) + | ((bl & 0x7) << 0) + ); + + ddr->ddr_sdram_mode = (0 + | ((esdmode & 0xFFFF) << 16) + | ((sdmode & 0xFFFF) << 0) + ); + debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); +} +#endif + +/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ +static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int init_value; /* Initialization value */ + +#ifdef CONFIG_MEM_INIT_VALUE + init_value = CONFIG_MEM_INIT_VALUE; +#else + init_value = 0xDEADBEEF; +#endif + ddr->ddr_data_init = init_value; +} + +/* + * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) + * The old controller on the 8540/60 doesn't have this register. + * Hope it's OK to set it (to 0) anyway. + */ +static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned int clk_adjust; /* Clock adjust */ + + clk_adjust = popts->clk_adjust; + ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; + debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); +} + +/* DDR Initialization Address (DDR_INIT_ADDR) */ +static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int init_addr = 0; /* Initialization address */ + + ddr->ddr_init_addr = init_addr; +} + +/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ +static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int uia = 0; /* Use initialization address */ + unsigned int init_ext_addr = 0; /* Initialization address */ + + ddr->ddr_init_ext_addr = (0 + | ((uia & 0x1) << 31) + | (init_ext_addr & 0xF) + ); +} + +/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ +static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) +{ + unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ + unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ + unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ + unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ + unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ + +#if defined(CONFIG_SYS_FSL_DDR3) + if (popts->burst_length == DDR_BL8) { + /* We set BL/2 for fixed BL8 */ + rrt = 0; /* BL/2 clocks */ + wwt = 0; /* BL/2 clocks */ + } else { + /* We need to set BL/2 + 2 to BC4 and OTF */ + rrt = 2; /* BL/2 + 2 clocks */ + wwt = 2; /* BL/2 + 2 clocks */ + } + dll_lock = 1; /* tDLLK = 512 clocks from spec */ +#endif + ddr->timing_cfg_4 = (0 + | ((rwt & 0xf) << 28) + | ((wrt & 0xf) << 24) + | ((rrt & 0xf) << 20) + | ((wwt & 0xf) << 16) + | (dll_lock & 0x3) + ); + debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); +} + +/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ +static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) +{ + unsigned int rodt_on = 0; /* Read to ODT on */ + unsigned int rodt_off = 0; /* Read to ODT off */ + unsigned int wodt_on = 0; /* Write to ODT on */ + unsigned int wodt_off = 0; /* Write to ODT off */ + +#if defined(CONFIG_SYS_FSL_DDR3) + /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ + rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1; + rodt_off = 4; /* 4 clocks */ + wodt_on = 1; /* 1 clocks */ + wodt_off = 4; /* 4 clocks */ +#endif + + ddr->timing_cfg_5 = (0 + | ((rodt_on & 0x1f) << 24) + | ((rodt_off & 0x7) << 20) + | ((wodt_on & 0x1f) << 12) + | ((wodt_off & 0x7) << 8) + ); + debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); +} + +/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ +static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) +{ + unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ + /* Normal Operation Full Calibration Time (tZQoper) */ + unsigned int zqoper = 0; + /* Normal Operation Short Calibration Time (tZQCS) */ + unsigned int zqcs = 0; + + if (zq_en) { + zqinit = 9; /* 512 clocks */ + zqoper = 8; /* 256 clocks */ + zqcs = 6; /* 64 clocks */ + } + + ddr->ddr_zq_cntl = (0 + | ((zq_en & 0x1) << 31) + | ((zqinit & 0xF) << 24) + | ((zqoper & 0xF) << 16) + | ((zqcs & 0xF) << 8) + ); + debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); +} + +/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ +static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, + const memctl_options_t *popts) +{ + /* + * First DQS pulse rising edge after margining mode + * is programmed (tWL_MRD) + */ + unsigned int wrlvl_mrd = 0; + /* ODT delay after margining mode is programmed (tWL_ODTEN) */ + unsigned int wrlvl_odten = 0; + /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ + unsigned int wrlvl_dqsen = 0; + /* WRLVL_SMPL: Write leveling sample time */ + unsigned int wrlvl_smpl = 0; + /* WRLVL_WLR: Write leveling repeition time */ + unsigned int wrlvl_wlr = 0; + /* WRLVL_START: Write leveling start time */ + unsigned int wrlvl_start = 0; + + /* suggest enable write leveling for DDR3 due to fly-by topology */ + if (wrlvl_en) { + /* tWL_MRD min = 40 nCK, we set it 64 */ + wrlvl_mrd = 0x6; + /* tWL_ODTEN 128 */ + wrlvl_odten = 0x7; + /* tWL_DQSEN min = 25 nCK, we set it 32 */ + wrlvl_dqsen = 0x5; + /* + * Write leveling sample time at least need 6 clocks + * higher than tWLO to allow enough time for progagation + * delay and sampling the prime data bits. + */ + wrlvl_smpl = 0xf; + /* + * Write leveling repetition time + * at least tWLO + 6 clocks clocks + * we set it 64 + */ + wrlvl_wlr = 0x6; + /* + * Write leveling start time + * The value use for the DQS_ADJUST for the first sample + * when write leveling is enabled. It probably needs to be + * overriden per platform. + */ + wrlvl_start = 0x8; + /* + * Override the write leveling sample and start time + * according to specific board + */ + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; + } + } + + ddr->ddr_wrlvl_cntl = (0 + | ((wrlvl_en & 0x1) << 31) + | ((wrlvl_mrd & 0x7) << 24) + | ((wrlvl_odten & 0x7) << 20) + | ((wrlvl_dqsen & 0x7) << 16) + | ((wrlvl_smpl & 0xf) << 12) + | ((wrlvl_wlr & 0x7) << 8) + | ((wrlvl_start & 0x1F) << 0) + ); + debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); + ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; + debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); + ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; + debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); + +} + +/* DDR Self Refresh Counter (DDR_SR_CNTR) */ +static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) +{ + /* Self Refresh Idle Threshold */ + ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; +} + +static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + if (popts->addr_hash) { + ddr->ddr_eor = 0x40000000; /* address hash enable */ + puts("Address hashing enabled.\n"); + } +} + +static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + ddr->ddr_cdr1 = popts->ddr_cdr1; + debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); +} + +static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) +{ + ddr->ddr_cdr2 = popts->ddr_cdr2; + debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); +} + +unsigned int +check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int res = 0; + + /* + * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are + * not set at the same time. + */ + if (ddr->ddr_sdram_cfg & 0x10000000 + && ddr->ddr_sdram_cfg & 0x00008000) { + printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " + " should not be set at the same time.\n"); + res++; + } + + return res; +} + +unsigned int +compute_fsl_memctl_config_regs(const memctl_options_t *popts, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + const dimm_params_t *dimm_params, + unsigned int dbw_cap_adj, + unsigned int size_only) +{ + unsigned int i; + unsigned int cas_latency; + unsigned int additive_latency; + unsigned int sr_it; + unsigned int zq_en; + unsigned int wrlvl_en; + unsigned int ip_rev = 0; + unsigned int unq_mrs_en = 0; + int cs_en = 1; + + memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); + + if (common_dimm == NULL) { + printf("Error: subset DIMM params struct null pointer\n"); + return 1; + } + + /* + * Process overrides first. + * + * FIXME: somehow add dereated caslat to this + */ + cas_latency = (popts->cas_latency_override) + ? popts->cas_latency_override_value + : common_dimm->lowest_common_SPD_caslat; + + additive_latency = (popts->additive_latency_override) + ? popts->additive_latency_override_value + : common_dimm->additive_latency; + + sr_it = (popts->auto_self_refresh_en) + ? popts->sr_it + : 0; + /* ZQ calibration */ + zq_en = (popts->zq_en) ? 1 : 0; + /* write leveling */ + wrlvl_en = (popts->wrlvl_en) ? 1 : 0; + + /* Chip Select Memory Bounds (CSn_BNDS) */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + unsigned long long ea, sa; + unsigned int cs_per_dimm + = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; + unsigned int dimm_number + = i / cs_per_dimm; + unsigned long long rank_density + = dimm_params[dimm_number].rank_density >> dbw_cap_adj; + + if (dimm_params[dimm_number].n_ranks == 0) { + debug("Skipping setup of CS%u " + "because n_ranks on DIMM %u is 0\n", i, dimm_number); + continue; + } + if (popts->memctl_interleaving) { + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + break; + case FSL_DDR_CS0_CS1: + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + if (i > 1) + cs_en = 0; + break; + case FSL_DDR_CS2_CS3: + default: + if (i > 0) + cs_en = 0; + break; + } + sa = common_dimm->base_address; + ea = sa + common_dimm->total_mem - 1; + } else if (!popts->memctl_interleaving) { + /* + * If memory interleaving between controllers is NOT + * enabled, the starting address for each memory + * controller is distinct. However, because rank + * interleaving is enabled, the starting and ending + * addresses of the total memory on that memory + * controller needs to be programmed into its + * respective CS0_BNDS. + */ + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + sa = common_dimm->base_address; + ea = sa + common_dimm->total_mem - 1; + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + if ((i >= 2) && (dimm_number == 0)) { + sa = dimm_params[dimm_number].base_address + + 2 * rank_density; + ea = sa + 2 * rank_density - 1; + } else { + sa = dimm_params[dimm_number].base_address; + ea = sa + 2 * rank_density - 1; + } + break; + case FSL_DDR_CS0_CS1: + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa = dimm_params[dimm_number].base_address; + ea = sa + rank_density - 1; + if (i != 1) + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; + } else { + sa = 0; + ea = 0; + } + if (i == 0) + ea += rank_density; + break; + case FSL_DDR_CS2_CS3: + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa = dimm_params[dimm_number].base_address; + ea = sa + rank_density - 1; + if (i != 3) + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; + } else { + sa = 0; + ea = 0; + } + if (i == 2) + ea += (rank_density >> dbw_cap_adj); + break; + default: /* No bank(chip-select) interleaving */ + sa = dimm_params[dimm_number].base_address; + ea = sa + rank_density - 1; + if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { + sa += (i % cs_per_dimm) * rank_density; + ea += (i % cs_per_dimm) * rank_density; + } else { + sa = 0; + ea = 0; + } + break; + } + } + + sa >>= 24; + ea >>= 24; + + if (cs_en) { + ddr->cs[i].bnds = (0 + | ((sa & 0xFFF) << 16)/* starting address MSB */ + | ((ea & 0xFFF) << 0) /* ending address MSB */ + ); + } else { + /* setting bnds to 0xffffffff for inactive CS */ + ddr->cs[i].bnds = 0xffffffff; + } + + debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); + set_csn_config(dimm_number, i, ddr, popts, dimm_params); + set_csn_config_2(i, ddr); + } + + /* + * In the case we only need to compute the ddr sdram size, we only need + * to set csn registers, so return from here. + */ + if (size_only) + return 0; + + set_ddr_eor(ddr, popts); + +#if !defined(CONFIG_SYS_FSL_DDR1) + set_timing_cfg_0(ddr, popts, dimm_params); +#endif + + set_timing_cfg_3(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_2(ddr, popts, common_dimm, + cas_latency, additive_latency); + + set_ddr_cdr1(ddr, popts); + set_ddr_cdr2(ddr, popts); + set_ddr_sdram_cfg(ddr, popts, common_dimm); + ip_rev = fsl_ddr_get_version(); + if (ip_rev > 0x40400) + unq_mrs_en = 1; + + set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); + set_ddr_sdram_mode(ddr, popts, common_dimm, + cas_latency, additive_latency, unq_mrs_en); + set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); + set_ddr_sdram_interval(ddr, popts, common_dimm); + set_ddr_data_init(ddr); + set_ddr_sdram_clk_cntl(ddr, popts); + set_ddr_init_addr(ddr); + set_ddr_init_ext_addr(ddr); + set_timing_cfg_4(ddr, popts); + set_timing_cfg_5(ddr, cas_latency); + + set_ddr_zq_cntl(ddr, zq_en); + set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); + + set_ddr_sr_cntr(ddr, sr_it); + + set_ddr_sdram_rcw(ddr, popts, common_dimm); + +#ifdef CONFIG_SYS_FSL_DDR_EMU + /* disble DDR training for emulator */ + ddr->debug[2] = 0x00000400; + ddr->debug[4] = 0xff800000; +#endif + return check_fsl_memctl_config_regs(ddr); +} diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c new file mode 100644 index 0000000000..7df27b90b7 --- /dev/null +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -0,0 +1,343 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * Study these table from Byte 31 of JEDEC SPD Spec. + * + * DDR I DDR II + * Bit Size Size + * --- ----- ------ + * 7 high 512MB 512MB + * 6 256MB 256MB + * 5 128MB 128MB + * 4 64MB 16GB + * 3 32MB 8GB + * 2 16MB 4GB + * 1 2GB 2GB + * 0 low 1GB 1GB + * + * Reorder Table to be linear by stripping the bottom + * 2 or 5 bits off and shifting them up to the top. + */ + +static unsigned long long +compute_ranksize(unsigned int mem_type, unsigned char row_dens) +{ + unsigned long long bsize; + + /* Bottom 2 bits up to the top. */ + bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)); + bsize <<= 24ULL; + debug("DDR: DDR I rank density = 0x%16llx\n", bsize); + + return bsize; +} + +/* + * Convert a two-nibble BCD value into a cycle time. + * While the spec calls for nano-seconds, picos are returned. + * + * This implements the tables for bytes 9, 23 and 25 for both + * DDR I and II. No allowance for distinguishing the invalid + * fields absent for DDR I yet present in DDR II is made. + * (That is, cycle times of .25, .33, .66 and .75 ns are + * allowed for both DDR II and I.) + */ +static unsigned int +convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) +{ + /* Table look up the lower nibble, allow DDR I & II. */ + unsigned int tenths_ps[16] = { + 0, + 100, + 200, + 300, + 400, + 500, + 600, + 700, + 800, + 900, + 250, /* This and the next 3 entries valid ... */ + 330, /* ... only for tCK calculations. */ + 660, + 750, + 0, /* undefined */ + 0 /* undefined */ + }; + + unsigned int whole_ns = (spd_val & 0xF0) >> 4; + unsigned int tenth_ns = spd_val & 0x0F; + unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; + + return ps; +} + +static unsigned int +convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) +{ + unsigned int tenth_ns = (spd_val & 0xF0) >> 4; + unsigned int hundredth_ns = spd_val & 0x0F; + unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; + + return ps; +} + +static unsigned int byte40_table_ps[8] = { + 0, + 250, + 330, + 500, + 660, + 750, + 0, /* supposed to be RFC, but not sure what that means */ + 0 /* Undefined */ +}; + +static unsigned int +compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) +{ + unsigned int trfc_ps; + + trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 + + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; + + return trfc_ps; +} + +static unsigned int +compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) +{ + unsigned int trc_ps; + + trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; + + return trc_ps; +} + +/* + * tCKmax from DDR I SPD Byte 43 + * + * Bits 7:2 == whole ns + * Bits 1:0 == quarter ns + * 00 == 0.00 ns + * 01 == 0.25 ns + * 10 == 0.50 ns + * 11 == 0.75 ns + * + * Returns picoseconds. + */ +static unsigned int +compute_tckmax_from_spd_ps(unsigned int byte43) +{ + return (byte43 >> 2) * 1000 + (byte43 & 0x3) * 250; +} + +/* + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. + */ +static unsigned int +determine_refresh_rate_ps(const unsigned int spd_refresh) +{ + unsigned int refresh_time_ps[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + return refresh_time_ps[spd_refresh & 0x7]; +} + +/* + * The purpose of this function is to compute a suitable + * CAS latency given the DRAM clock period. The SPD only + * defines at most 3 CAS latencies. Typically the slower in + * frequency the DIMM runs at, the shorter its CAS latency can be. + * If the DIMM is operating at a sufficiently low frequency, + * it may be able to run at a CAS latency shorter than the + * shortest SPD-defined CAS latency. + * + * If a CAS latency is not found, 0 is returned. + * + * Do this by finding in the standard speed bin table the longest + * tCKmin that doesn't exceed the value of mclk_ps (tCK). + * + * An assumption made is that the SDRAM device allows the + * CL to be programmed for a value that is lower than those + * advertised by the SPD. This is not always the case, + * as those modes not defined in the SPD are optional. + * + * CAS latency de-rating based upon values JEDEC Standard No. 79-E + * Table 11. + * + * ordinal 2, ddr1_speed_bins[1] contains tCK for CL=2 + */ + /* CL2.0 CL2.5 CL3.0 */ +unsigned short ddr1_speed_bins[] = {0, 7500, 6000, 5000 }; + +unsigned int +compute_derated_DDR1_CAS_latency(unsigned int mclk_ps) +{ + const unsigned int num_speed_bins = ARRAY_SIZE(ddr1_speed_bins); + unsigned int lowest_tCKmin_found = 0; + unsigned int lowest_tCKmin_CL = 0; + unsigned int i; + + debug("mclk_ps = %u\n", mclk_ps); + + for (i = 0; i < num_speed_bins; i++) { + unsigned int x = ddr1_speed_bins[i]; + debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", + i, x, lowest_tCKmin_found); + if (x && lowest_tCKmin_found <= x && x <= mclk_ps) { + lowest_tCKmin_found = x; + lowest_tCKmin_CL = i + 1; + } + } + + debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); + + return lowest_tCKmin_CL; +} + +/* + * ddr_compute_dimm_parameters for DDR1 SPD + * + * Compute DIMM parameters based upon the SPD information in spd. + * Writes the results to the dimm_params_t structure pointed by pdimm. + * + * FIXME: use #define for the retvals + */ +unsigned int +ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + unsigned int retval; + + if (spd->mem_type) { + if (spd->mem_type != SPD_MEMTYPE_DDR) { + printf("DIMM %u: is not a DDR1 SPD.\n", dimm_number); + return 1; + } + } else { + memset(pdimm, 0, sizeof(dimm_params_t)); + return 1; + } + + retval = ddr1_spd_check(spd); + if (retval) { + printf("DIMM %u: failed checksum\n", dimm_number); + return 2; + } + + /* + * The part name in ASCII in the SPD EEPROM is not null terminated. + * Guarantee null termination here by presetting all bytes to 0 + * and copying the part name in ASCII from the SPD onto it + */ + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); + + /* DIMM organization parameters */ + pdimm->n_ranks = spd->nrows; + pdimm->rank_density = compute_ranksize(spd->mem_type, spd->bank_dens); + pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; + pdimm->data_width = spd->dataw_lsb; + pdimm->primary_sdram_width = spd->primw; + pdimm->ec_sdram_width = spd->ecw; + + /* + * FIXME: Need to determine registered_dimm status. + * 1 == register buffered + * 0 == unbuffered + */ + pdimm->registered_dimm = 0; /* unbuffered */ + + /* SDRAM device parameters */ + pdimm->n_row_addr = spd->nrow_addr; + pdimm->n_col_addr = spd->ncol_addr; + pdimm->n_banks_per_sdram_device = spd->nbanks; + pdimm->edc_config = spd->config; + pdimm->burst_lengths_bitmask = spd->burstl; + pdimm->row_density = spd->bank_dens; + + /* + * Calculate the Maximum Data Rate based on the Minimum Cycle time. + * The SPD clk_cycle field (tCKmin) is measured in tenths of + * nanoseconds and represented as BCD. + */ + pdimm->tckmin_x_ps + = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); + pdimm->tckmin_x_minus_1_ps + = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); + pdimm->tckmin_x_minus_2_ps + = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); + + pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax); + + /* + * Compute CAS latencies defined by SPD + * The SPD caslat_x should have at least 1 and at most 3 bits set. + * + * If cas_lat after masking is 0, the __ilog2 function returns + * 255 into the variable. This behavior is abused once. + */ + pdimm->caslat_x = __ilog2(spd->cas_lat); + pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x)); + pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x) + & ~(1 << pdimm->caslat_x_minus_1)); + + /* Compute CAS latencies below that defined by SPD */ + pdimm->caslat_lowest_derated + = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps()); + + /* Compute timing parameters */ + pdimm->trcd_ps = spd->trcd * 250; + pdimm->trp_ps = spd->trp * 250; + pdimm->tras_ps = spd->tras * 1000; + + pdimm->twr_ps = mclk_to_picos(3); + pdimm->twtr_ps = mclk_to_picos(1); + pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); + + pdimm->trrd_ps = spd->trrd * 250; + pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc); + + pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); + + pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); + pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); + pdimm->tds_ps + = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); + pdimm->tdh_ps + = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); + + pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */ + pdimm->tdqsq_max_ps = spd->tdqsq * 10; + pdimm->tqhs_ps = spd->tqhs * 10; + + return 0; +} diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c new file mode 100644 index 0000000000..d865df78a8 --- /dev/null +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -0,0 +1,342 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * Study these table from Byte 31 of JEDEC SPD Spec. + * + * DDR I DDR II + * Bit Size Size + * --- ----- ------ + * 7 high 512MB 512MB + * 6 256MB 256MB + * 5 128MB 128MB + * 4 64MB 16GB + * 3 32MB 8GB + * 2 16MB 4GB + * 1 2GB 2GB + * 0 low 1GB 1GB + * + * Reorder Table to be linear by stripping the bottom + * 2 or 5 bits off and shifting them up to the top. + * + */ +static unsigned long long +compute_ranksize(unsigned int mem_type, unsigned char row_dens) +{ + unsigned long long bsize; + + /* Bottom 5 bits up to the top. */ + bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)); + bsize <<= 27ULL; + debug("DDR: DDR II rank density = 0x%16llx\n", bsize); + + return bsize; +} + +/* + * Convert a two-nibble BCD value into a cycle time. + * While the spec calls for nano-seconds, picos are returned. + * + * This implements the tables for bytes 9, 23 and 25 for both + * DDR I and II. No allowance for distinguishing the invalid + * fields absent for DDR I yet present in DDR II is made. + * (That is, cycle times of .25, .33, .66 and .75 ns are + * allowed for both DDR II and I.) + */ +static unsigned int +convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val) +{ + /* Table look up the lower nibble, allow DDR I & II. */ + unsigned int tenths_ps[16] = { + 0, + 100, + 200, + 300, + 400, + 500, + 600, + 700, + 800, + 900, + 250, /* This and the next 3 entries valid ... */ + 330, /* ... only for tCK calculations. */ + 660, + 750, + 0, /* undefined */ + 0 /* undefined */ + }; + + unsigned int whole_ns = (spd_val & 0xF0) >> 4; + unsigned int tenth_ns = spd_val & 0x0F; + unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns]; + + return ps; +} + +static unsigned int +convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val) +{ + unsigned int tenth_ns = (spd_val & 0xF0) >> 4; + unsigned int hundredth_ns = spd_val & 0x0F; + unsigned int ps = tenth_ns * 100 + hundredth_ns * 10; + + return ps; +} + +static unsigned int byte40_table_ps[8] = { + 0, + 250, + 330, + 500, + 660, + 750, + 0, /* supposed to be RFC, but not sure what that means */ + 0 /* Undefined */ +}; + +static unsigned int +compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc) +{ + unsigned int trfc_ps; + + trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000 + + byte40_table_ps[(trctrfc_ext >> 1) & 0x7]; + + return trfc_ps; +} + +static unsigned int +compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc) +{ + unsigned int trc_ps; + + trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7]; + + return trc_ps; +} + +/* + * Determine Refresh Rate. Ignore self refresh bit on DDR I. + * Table from SPD Spec, Byte 12, converted to picoseconds and + * filled in with "default" normal values. + */ +static unsigned int +determine_refresh_rate_ps(const unsigned int spd_refresh) +{ + unsigned int refresh_time_ps[8] = { + 15625000, /* 0 Normal 1.00x */ + 3900000, /* 1 Reduced .25x */ + 7800000, /* 2 Extended .50x */ + 31300000, /* 3 Extended 2.00x */ + 62500000, /* 4 Extended 4.00x */ + 125000000, /* 5 Extended 8.00x */ + 15625000, /* 6 Normal 1.00x filler */ + 15625000, /* 7 Normal 1.00x filler */ + }; + + return refresh_time_ps[spd_refresh & 0x7]; +} + +/* + * The purpose of this function is to compute a suitable + * CAS latency given the DRAM clock period. The SPD only + * defines at most 3 CAS latencies. Typically the slower in + * frequency the DIMM runs at, the shorter its CAS latency can. + * be. If the DIMM is operating at a sufficiently low frequency, + * it may be able to run at a CAS latency shorter than the + * shortest SPD-defined CAS latency. + * + * If a CAS latency is not found, 0 is returned. + * + * Do this by finding in the standard speed bin table the longest + * tCKmin that doesn't exceed the value of mclk_ps (tCK). + * + * An assumption made is that the SDRAM device allows the + * CL to be programmed for a value that is lower than those + * advertised by the SPD. This is not always the case, + * as those modes not defined in the SPD are optional. + * + * CAS latency de-rating based upon values JEDEC Standard No. 79-2C + * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS, + * and tRC for corresponding bin" + * + * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 + * Not certain if any good value exists for CL=2 + */ + /* CL2 CL3 CL4 CL5 CL6 CL7*/ +unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 }; + +unsigned int +compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) +{ + const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins); + unsigned int lowest_tCKmin_found = 0; + unsigned int lowest_tCKmin_CL = 0; + unsigned int i; + + debug("mclk_ps = %u\n", mclk_ps); + + for (i = 0; i < num_speed_bins; i++) { + unsigned int x = ddr2_speed_bins[i]; + debug("i=%u, x = %u, lowest_tCKmin_found = %u\n", + i, x, lowest_tCKmin_found); + if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) { + lowest_tCKmin_found = x; + lowest_tCKmin_CL = i + 2; + } + } + + debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL); + + return lowest_tCKmin_CL; +} + +/* + * ddr_compute_dimm_parameters for DDR2 SPD + * + * Compute DIMM parameters based upon the SPD information in spd. + * Writes the results to the dimm_params_t structure pointed by pdimm. + * + * FIXME: use #define for the retvals + */ +unsigned int +ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + unsigned int retval; + + if (spd->mem_type) { + if (spd->mem_type != SPD_MEMTYPE_DDR2) { + printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number); + return 1; + } + } else { + memset(pdimm, 0, sizeof(dimm_params_t)); + return 1; + } + + retval = ddr2_spd_check(spd); + if (retval) { + printf("DIMM %u: failed checksum\n", dimm_number); + return 2; + } + + /* + * The part name in ASCII in the SPD EEPROM is not null terminated. + * Guarantee null termination here by presetting all bytes to 0 + * and copying the part name in ASCII from the SPD onto it + */ + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); + + /* DIMM organization parameters */ + pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1; + pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens); + pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; + pdimm->data_width = spd->dataw; + pdimm->primary_sdram_width = spd->primw; + pdimm->ec_sdram_width = spd->ecw; + + /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ + switch (spd->dimm_type) { + case DDR2_SPD_DIMMTYPE_RDIMM: + case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: + case DDR2_SPD_DIMMTYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; + break; + + case DDR2_SPD_DIMMTYPE_UDIMM: + case DDR2_SPD_DIMMTYPE_SO_DIMM: + case DDR2_SPD_DIMMTYPE_MICRO_DIMM: + case DDR2_SPD_DIMMTYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + pdimm->registered_dimm = 0; + break; + + case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: + default: + printf("unknown dimm_type 0x%02X\n", spd->dimm_type); + return 1; + } + + /* SDRAM device parameters */ + pdimm->n_row_addr = spd->nrow_addr; + pdimm->n_col_addr = spd->ncol_addr; + pdimm->n_banks_per_sdram_device = spd->nbanks; + pdimm->edc_config = spd->config; + pdimm->burst_lengths_bitmask = spd->burstl; + pdimm->row_density = spd->rank_dens; + + /* + * Calculate the Maximum Data Rate based on the Minimum Cycle time. + * The SPD clk_cycle field (tCKmin) is measured in tenths of + * nanoseconds and represented as BCD. + */ + pdimm->tckmin_x_ps + = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle); + pdimm->tckmin_x_minus_1_ps + = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2); + pdimm->tckmin_x_minus_2_ps + = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3); + + pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax); + + /* + * Compute CAS latencies defined by SPD + * The SPD caslat_x should have at least 1 and at most 3 bits set. + * + * If cas_lat after masking is 0, the __ilog2 function returns + * 255 into the variable. This behavior is abused once. + */ + pdimm->caslat_x = __ilog2(spd->cas_lat); + pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x)); + pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat + & ~(1 << pdimm->caslat_x) + & ~(1 << pdimm->caslat_x_minus_1)); + + /* Compute CAS latencies below that defined by SPD */ + pdimm->caslat_lowest_derated + = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); + + /* Compute timing parameters */ + pdimm->trcd_ps = spd->trcd * 250; + pdimm->trp_ps = spd->trp * 250; + pdimm->tras_ps = spd->tras * 1000; + + pdimm->twr_ps = spd->twr * 250; + pdimm->twtr_ps = spd->twtr * 250; + pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc); + + pdimm->trrd_ps = spd->trrd * 250; + pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc); + + pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh); + + pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup); + pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold); + pdimm->tds_ps + = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup); + pdimm->tdh_ps + = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); + + pdimm->trtp_ps = spd->trtp * 250; + pdimm->tdqsq_max_ps = spd->tdqsq * 10; + pdimm->tqhs_ps = spd->tqhs * 10; + + return 0; +} diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c new file mode 100644 index 0000000000..a4b8c101f5 --- /dev/null +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -0,0 +1,341 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * Dave Liu + * + * calculate the organization and timing parameter + * from ddr3 spd, please refer to the spec + * JEDEC standard No.21-C 4_01_02_11R18.pdf + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +/* + * Calculate the Density of each Physical Rank. + * Returned size is in bytes. + * + * each rank size = + * sdram capacity(bit) / 8 * primary bus width / sdram width + * + * where: sdram capacity = spd byte4[3:0] + * primary bus width = spd byte8[2:0] + * sdram width = spd byte7[2:0] + * + * SPD byte4 - sdram density and banks + * bit[3:0] size(bit) size(byte) + * 0000 256Mb 32MB + * 0001 512Mb 64MB + * 0010 1Gb 128MB + * 0011 2Gb 256MB + * 0100 4Gb 512MB + * 0101 8Gb 1GB + * 0110 16Gb 2GB + * + * SPD byte8 - module memory bus width + * bit[2:0] primary bus width + * 000 8bits + * 001 16bits + * 010 32bits + * 011 64bits + * + * SPD byte7 - module organiztion + * bit[2:0] sdram device width + * 000 4bits + * 001 8bits + * 010 16bits + * 011 32bits + * + */ +static unsigned long long +compute_ranksize(const ddr3_spd_eeprom_t *spd) +{ + unsigned long long bsize; + + int nbit_sdram_cap_bsize = 0; + int nbit_primary_bus_width = 0; + int nbit_sdram_width = 0; + + if ((spd->density_banks & 0xf) < 7) + nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28; + if ((spd->bus_width & 0x7) < 4) + nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; + if ((spd->organization & 0x7) < 4) + nbit_sdram_width = (spd->organization & 0x7) + 2; + + bsize = 1ULL << (nbit_sdram_cap_bsize - 3 + + nbit_primary_bus_width - nbit_sdram_width); + + debug("DDR: DDR III rank density = 0x%16llx\n", bsize); + + return bsize; +} + +/* + * ddr_compute_dimm_parameters for DDR3 SPD + * + * Compute DIMM parameters based upon the SPD information in spd. + * Writes the results to the dimm_params_t structure pointed by pdimm. + * + */ +unsigned int +ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + unsigned int retval; + unsigned int mtb_ps; + int ftb_10th_ps; + int i; + + if (spd->mem_type) { + if (spd->mem_type != SPD_MEMTYPE_DDR3) { + printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); + return 1; + } + } else { + memset(pdimm, 0, sizeof(dimm_params_t)); + return 1; + } + + retval = ddr3_spd_check(spd); + if (retval) { + printf("DIMM %u: failed checksum\n", dimm_number); + return 2; + } + + /* + * The part name in ASCII in the SPD EEPROM is not null terminated. + * Guarantee null termination here by presetting all bytes to 0 + * and copying the part name in ASCII from the SPD onto it + */ + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + if ((spd->info_size_crc & 0xF) > 1) + memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1); + + /* DIMM organization parameters */ + pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1; + pdimm->rank_density = compute_ranksize(spd); + pdimm->capacity = pdimm->n_ranks * pdimm->rank_density; + pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); + if ((spd->bus_width >> 3) & 0x3) + pdimm->ec_sdram_width = 8; + else + pdimm->ec_sdram_width = 0; + pdimm->data_width = pdimm->primary_sdram_width + + pdimm->ec_sdram_width; + pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); + + /* These are the types defined by the JEDEC DDR3 SPD spec */ + pdimm->mirrored_dimm = 0; + pdimm->registered_dimm = 0; + switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { + case DDR3_SPD_MODULETYPE_RDIMM: + case DDR3_SPD_MODULETYPE_MINI_RDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; + for (i = 0; i < 16; i += 2) { + u8 rcw = spd->mod_section.registered.rcw[i/2]; + pdimm->rcw[i] = (rcw >> 0) & 0x0F; + pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; + } + break; + + case DDR3_SPD_MODULETYPE_UDIMM: + case DDR3_SPD_MODULETYPE_SO_DIMM: + case DDR3_SPD_MODULETYPE_MICRO_DIMM: + case DDR3_SPD_MODULETYPE_MINI_UDIMM: + case DDR3_SPD_MODULETYPE_MINI_CDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_UDIMM: + case DDR3_SPD_MODULETYPE_72B_SO_CDIMM: + case DDR3_SPD_MODULETYPE_LRDIMM: + case DDR3_SPD_MODULETYPE_16B_SO_DIMM: + case DDR3_SPD_MODULETYPE_32B_SO_DIMM: + /* Unbuffered DIMMs */ + if (spd->mod_section.unbuffered.addr_mapping & 0x1) + pdimm->mirrored_dimm = 1; + break; + + default: + printf("unknown module_type 0x%02X\n", spd->module_type); + return 1; + } + + /* SDRAM device parameters */ + pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12; + pdimm->n_col_addr = (spd->addressing & 0x7) + 9; + pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7); + + /* + * The SPD spec has not the ECC bit, + * We consider the DIMM as ECC capability + * when the extension bus exist + */ + if (pdimm->ec_sdram_width) + pdimm->edc_config = 0x02; + else + pdimm->edc_config = 0x00; + + /* + * The SPD spec has not the burst length byte + * but DDR3 spec has nature BL8 and BC4, + * BL8 -bit3, BC4 -bit2 + */ + pdimm->burst_lengths_bitmask = 0x0c; + pdimm->row_density = __ilog2(pdimm->rank_density); + + /* MTB - medium timebase + * The unit in the SPD spec is ns, + * We convert it to ps. + * eg: MTB = 0.125ns (125ps) + */ + mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor; + pdimm->mtb_ps = mtb_ps; + + /* + * FTB - fine timebase + * use 1/10th of ps as our unit to avoid floating point + * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps + */ + ftb_10th_ps = + ((spd->ftb_div & 0xf0) >> 4) * 10 / (spd->ftb_div & 0x0f); + pdimm->ftb_10th_ps = ftb_10th_ps; + /* + * sdram minimum cycle time + * we assume the MTB is 0.125ns + * eg: + * tck_min=15 MTB (1.875ns) ->DDR3-1066 + * =12 MTB (1.5ns) ->DDR3-1333 + * =10 MTB (1.25ns) ->DDR3-1600 + */ + pdimm->tckmin_x_ps = spd->tck_min * mtb_ps + + (spd->fine_tck_min * ftb_10th_ps) / 10; + + /* + * CAS latency supported + * bit4 - CL4 + * bit5 - CL5 + * bit18 - CL18 + */ + pdimm->caslat_x = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4; + + /* + * min CAS latency time + * eg: taa_min = + * DDR3-800D 100 MTB (12.5ns) + * DDR3-1066F 105 MTB (13.125ns) + * DDR3-1333H 108 MTB (13.5ns) + * DDR3-1600H 90 MTB (11.25ns) + */ + pdimm->taa_ps = spd->taa_min * mtb_ps + + (spd->fine_taa_min * ftb_10th_ps) / 10; + + /* + * min write recovery time + * eg: + * twr_min = 120 MTB (15ns) -> all speed grades. + */ + pdimm->twr_ps = spd->twr_min * mtb_ps; + + /* + * min RAS to CAS delay time + * eg: trcd_min = + * DDR3-800 100 MTB (12.5ns) + * DDR3-1066F 105 MTB (13.125ns) + * DDR3-1333H 108 MTB (13.5ns) + * DDR3-1600H 90 MTB (11.25) + */ + pdimm->trcd_ps = spd->trcd_min * mtb_ps + + (spd->fine_trcd_min * ftb_10th_ps) / 10; + + /* + * min row active to row active delay time + * eg: trrd_min = + * DDR3-800(1KB page) 80 MTB (10ns) + * DDR3-1333(1KB page) 48 MTB (6ns) + */ + pdimm->trrd_ps = spd->trrd_min * mtb_ps; + + /* + * min row precharge delay time + * eg: trp_min = + * DDR3-800D 100 MTB (12.5ns) + * DDR3-1066F 105 MTB (13.125ns) + * DDR3-1333H 108 MTB (13.5ns) + * DDR3-1600H 90 MTB (11.25ns) + */ + pdimm->trp_ps = spd->trp_min * mtb_ps + + (spd->fine_trp_min * ftb_10th_ps) / 10; + + /* min active to precharge delay time + * eg: tRAS_min = + * DDR3-800D 300 MTB (37.5ns) + * DDR3-1066F 300 MTB (37.5ns) + * DDR3-1333H 288 MTB (36ns) + * DDR3-1600H 280 MTB (35ns) + */ + pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb) + * mtb_ps; + /* + * min active to actice/refresh delay time + * eg: tRC_min = + * DDR3-800D 400 MTB (50ns) + * DDR3-1066F 405 MTB (50.625ns) + * DDR3-1333H 396 MTB (49.5ns) + * DDR3-1600H 370 MTB (46.25ns) + */ + pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb) + * mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10; + /* + * min refresh recovery delay time + * eg: tRFC_min = + * 512Mb 720 MTB (90ns) + * 1Gb 880 MTB (110ns) + * 2Gb 1280 MTB (160ns) + */ + pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb) + * mtb_ps; + /* + * min internal write to read command delay time + * eg: twtr_min = 40 MTB (7.5ns) - all speed bins. + * tWRT is at least 4 mclk independent of operating freq. + */ + pdimm->twtr_ps = spd->twtr_min * mtb_ps; + + /* + * min internal read to precharge command delay time + * eg: trtp_min = 40 MTB (7.5ns) - all speed bins. + * tRTP is at least 4 mclk independent of operating freq. + */ + pdimm->trtp_ps = spd->trtp_min * mtb_ps; + + /* + * Average periodic refresh interval + * tREFI = 7.8 us at normal temperature range + * = 3.9 us at ext temperature range + */ + pdimm->refresh_rate_ps = 7800000; + if ((spd->therm_ref_opt & 0x1) && !(spd->therm_ref_opt & 0x2)) { + pdimm->refresh_rate_ps = 3900000; + pdimm->extended_op_srt = 1; + } + + /* + * min four active window delay time + * eg: tfaw_min = + * DDR3-800(1KB page) 320 MTB (40ns) + * DDR3-1066(1KB page) 300 MTB (37.5ns) + * DDR3-1333(1KB page) 240 MTB (30ns) + * DDR3-1600(1KB page) 240 MTB (30ns) + */ + pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) + * mtb_ps; + + return 0; +} diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c new file mode 100644 index 0000000000..ebf3ed6f38 --- /dev/null +++ b/drivers/ddr/fsl/interactive.c @@ -0,0 +1,1871 @@ +/* + * Copyright 2010-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + * York Sun [at freescale.com] + */ + +#include +#include +#include +#include + +#include +#include + +/* Option parameter Structures */ +struct options_string { + const char *option_name; + size_t offset; + unsigned int size; + const char printhex; +}; + +static unsigned int picos_to_mhz(unsigned int picos) +{ + return 1000000 / picos; +} + +static void print_option_table(const struct options_string *table, + int table_size, + const void *base) +{ + unsigned int i; + unsigned int *ptr; + unsigned long long *ptr_l; + + for (i = 0; i < table_size; i++) { + switch (table[i].size) { + case 4: + ptr = (unsigned int *) (base + table[i].offset); + if (table[i].printhex) { + printf("%s = 0x%08X\n", + table[i].option_name, *ptr); + } else { + printf("%s = %u\n", + table[i].option_name, *ptr); + } + break; + case 8: + ptr_l = (unsigned long long *) (base + table[i].offset); + printf("%s = %llu\n", + table[i].option_name, *ptr_l); + break; + default: + printf("Unrecognized size!\n"); + break; + } + } +} + +static int handle_option_table(const struct options_string *table, + int table_size, + void *base, + const char *opt, + const char *val) +{ + unsigned int i; + unsigned int value, *ptr; + unsigned long long value_l, *ptr_l; + + for (i = 0; i < table_size; i++) { + if (strcmp(table[i].option_name, opt) != 0) + continue; + switch (table[i].size) { + case 4: + value = simple_strtoul(val, NULL, 0); + ptr = base + table[i].offset; + *ptr = value; + break; + case 8: + value_l = simple_strtoull(val, NULL, 0); + ptr_l = base + table[i].offset; + *ptr_l = value_l; + break; + default: + printf("Unrecognized size!\n"); + break; + } + return 1; + } + + return 0; +} + +static void fsl_ddr_generic_edit(void *pdata, + void *pend, + unsigned int element_size, + unsigned int element_num, + unsigned int value) +{ + char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */ + + pcdata += element_num * element_size; + if ((pcdata + element_size) > (char *) pend) { + printf("trying to write past end of data\n"); + return; + } + + switch (element_size) { + case 1: + __raw_writeb(value, pcdata); + break; + case 2: + __raw_writew(value, pcdata); + break; + case 4: + __raw_writel(value, pcdata); + break; + default: + printf("unexpected element size %u\n", element_size); + break; + } +} + +static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + unsigned int dimm_num, + unsigned int element_num, + unsigned int value) +{ + generic_spd_eeprom_t *pspd; + + pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]); + fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value); +} + +#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \ + sizeof((common_timing_params_t *)0)->x, 0} + +static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + const char *optname_str, + const char *value_str) +{ + common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num]; + + static const struct options_string options[] = { + COMMON_TIMING(tckmin_x_ps), + COMMON_TIMING(tckmax_ps), + COMMON_TIMING(tckmax_max_ps), + COMMON_TIMING(trcd_ps), + COMMON_TIMING(trp_ps), + COMMON_TIMING(tras_ps), + COMMON_TIMING(twr_ps), + COMMON_TIMING(twtr_ps), + COMMON_TIMING(trfc_ps), + COMMON_TIMING(trrd_ps), + COMMON_TIMING(trc_ps), + COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(tis_ps), + COMMON_TIMING(tih_ps), + COMMON_TIMING(tds_ps), + COMMON_TIMING(tdh_ps), + COMMON_TIMING(trtp_ps), + COMMON_TIMING(tdqsq_max_ps), + COMMON_TIMING(tqhs_ps), + COMMON_TIMING(ndimms_present), + COMMON_TIMING(lowest_common_SPD_caslat), + COMMON_TIMING(highest_common_derated_caslat), + COMMON_TIMING(additive_latency), + COMMON_TIMING(all_dimms_burst_lengths_bitmask), + COMMON_TIMING(all_dimms_registered), + COMMON_TIMING(all_dimms_unbuffered), + COMMON_TIMING(all_dimms_ecc_capable), + COMMON_TIMING(total_mem), + COMMON_TIMING(base_address), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, optname_str, value_str)) + return; + + printf("Error: couldn't find option string %s\n", optname_str); +} + +#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \ + sizeof((dimm_params_t *)0)->x, 0} + +static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + unsigned int dimm_num, + const char *optname_str, + const char *value_str) +{ + dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]); + + static const struct options_string options[] = { + DIMM_PARM(n_ranks), + DIMM_PARM(data_width), + DIMM_PARM(primary_sdram_width), + DIMM_PARM(ec_sdram_width), + DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), + + DIMM_PARM(n_row_addr), + DIMM_PARM(n_col_addr), + DIMM_PARM(edc_config), + DIMM_PARM(n_banks_per_sdram_device), + DIMM_PARM(burst_lengths_bitmask), + DIMM_PARM(row_density), + + DIMM_PARM(tckmin_x_ps), + DIMM_PARM(tckmin_x_minus_1_ps), + DIMM_PARM(tckmin_x_minus_2_ps), + DIMM_PARM(tckmax_ps), + + DIMM_PARM(caslat_x), + DIMM_PARM(caslat_x_minus_1), + DIMM_PARM(caslat_x_minus_2), + + DIMM_PARM(caslat_lowest_derated), + + DIMM_PARM(trcd_ps), + DIMM_PARM(trp_ps), + DIMM_PARM(tras_ps), + DIMM_PARM(twr_ps), + DIMM_PARM(twtr_ps), + DIMM_PARM(trfc_ps), + DIMM_PARM(trrd_ps), + DIMM_PARM(trc_ps), + DIMM_PARM(refresh_rate_ps), + + DIMM_PARM(tis_ps), + DIMM_PARM(tih_ps), + DIMM_PARM(tds_ps), + DIMM_PARM(tdh_ps), + DIMM_PARM(trtp_ps), + DIMM_PARM(tdqsq_max_ps), + DIMM_PARM(tqhs_ps), + + DIMM_PARM(rank_density), + DIMM_PARM(capacity), + DIMM_PARM(base_address), + }; + + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, optname_str, value_str)) + return; + + printf("couldn't find option string %s\n", optname_str); +} + +static void print_dimm_parameters(const dimm_params_t *pdimm) +{ + static const struct options_string options[] = { + DIMM_PARM(n_ranks), + DIMM_PARM(data_width), + DIMM_PARM(primary_sdram_width), + DIMM_PARM(ec_sdram_width), + DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), + + DIMM_PARM(n_row_addr), + DIMM_PARM(n_col_addr), + DIMM_PARM(edc_config), + DIMM_PARM(n_banks_per_sdram_device), + + DIMM_PARM(tckmin_x_ps), + DIMM_PARM(tckmin_x_minus_1_ps), + DIMM_PARM(tckmin_x_minus_2_ps), + DIMM_PARM(tckmax_ps), + + DIMM_PARM(caslat_x), + DIMM_PARM(taa_ps), + DIMM_PARM(caslat_x_minus_1), + DIMM_PARM(caslat_x_minus_2), + DIMM_PARM(caslat_lowest_derated), + + DIMM_PARM(trcd_ps), + DIMM_PARM(trp_ps), + DIMM_PARM(tras_ps), + DIMM_PARM(twr_ps), + DIMM_PARM(twtr_ps), + DIMM_PARM(trfc_ps), + DIMM_PARM(trrd_ps), + DIMM_PARM(trc_ps), + DIMM_PARM(refresh_rate_ps), + + DIMM_PARM(tis_ps), + DIMM_PARM(tih_ps), + DIMM_PARM(tds_ps), + DIMM_PARM(tdh_ps), + DIMM_PARM(trtp_ps), + DIMM_PARM(tdqsq_max_ps), + DIMM_PARM(tqhs_ps), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (pdimm->n_ranks == 0) { + printf("DIMM not present\n"); + return; + } + printf("DIMM organization parameters:\n"); + printf("module part name = %s\n", pdimm->mpart); + printf("rank_density = %llu bytes (%llu megabytes)\n", + pdimm->rank_density, pdimm->rank_density / 0x100000); + printf("capacity = %llu bytes (%llu megabytes)\n", + pdimm->capacity, pdimm->capacity / 0x100000); + printf("burst_lengths_bitmask = %02X\n", + pdimm->burst_lengths_bitmask); + printf("base_addresss = %llu (%08llX %08llX)\n", + pdimm->base_address, + (pdimm->base_address >> 32), + pdimm->base_address & 0xFFFFFFFF); + print_option_table(options, n_opts, pdimm); +} + +static void print_lowest_common_dimm_parameters( + const common_timing_params_t *plcd_dimm_params) +{ + static const struct options_string options[] = { + COMMON_TIMING(tckmax_max_ps), + COMMON_TIMING(trcd_ps), + COMMON_TIMING(trp_ps), + COMMON_TIMING(tras_ps), + COMMON_TIMING(twr_ps), + COMMON_TIMING(twtr_ps), + COMMON_TIMING(trfc_ps), + COMMON_TIMING(trrd_ps), + COMMON_TIMING(trc_ps), + COMMON_TIMING(refresh_rate_ps), + COMMON_TIMING(tis_ps), + COMMON_TIMING(tds_ps), + COMMON_TIMING(tdh_ps), + COMMON_TIMING(trtp_ps), + COMMON_TIMING(tdqsq_max_ps), + COMMON_TIMING(tqhs_ps), + COMMON_TIMING(lowest_common_SPD_caslat), + COMMON_TIMING(highest_common_derated_caslat), + COMMON_TIMING(additive_latency), + COMMON_TIMING(ndimms_present), + COMMON_TIMING(all_dimms_registered), + COMMON_TIMING(all_dimms_unbuffered), + COMMON_TIMING(all_dimms_ecc_capable), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + /* Clock frequencies */ + printf("tckmin_x_ps = %u (%u MHz)\n", + plcd_dimm_params->tckmin_x_ps, + picos_to_mhz(plcd_dimm_params->tckmin_x_ps)); + printf("tckmax_ps = %u (%u MHz)\n", + plcd_dimm_params->tckmax_ps, + picos_to_mhz(plcd_dimm_params->tckmax_ps)); + printf("all_dimms_burst_lengths_bitmask = %02X\n", + plcd_dimm_params->all_dimms_burst_lengths_bitmask); + + print_option_table(options, n_opts, plcd_dimm_params); + + printf("total_mem = %llu (%llu megabytes)\n", + plcd_dimm_params->total_mem, + plcd_dimm_params->total_mem / 0x100000); + printf("base_address = %llu (%llu megabytes)\n", + plcd_dimm_params->base_address, + plcd_dimm_params->base_address / 0x100000); +} + +#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \ + sizeof((memctl_options_t *)0)->x, 0} +#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \ + offsetof(memctl_options_t, cs_local_opts[x].y), \ + sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0} + +static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, + unsigned int ctl_num, + const char *optname_str, + const char *value_str) +{ + memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]); + /* + * This array all on the stack and *computed* each time this + * function is rung. + */ + static const struct options_string options[] = { + CTRL_OPTIONS_CS(0, odt_rd_cfg), + CTRL_OPTIONS_CS(0, odt_wr_cfg), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rd_cfg), + CTRL_OPTIONS_CS(1, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rd_cfg), + CTRL_OPTIONS_CS(2, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(3, odt_rd_cfg), + CTRL_OPTIONS_CS(3, odt_wr_cfg), +#endif +#if defined(CONFIG_SYS_FSL_DDR3) + CTRL_OPTIONS_CS(0, odt_rtt_norm), + CTRL_OPTIONS_CS(0, odt_rtt_wr), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rtt_norm), + CTRL_OPTIONS_CS(1, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rtt_norm), + CTRL_OPTIONS_CS(2, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(3, odt_rtt_norm), + CTRL_OPTIONS_CS(3, odt_rtt_wr), +#endif +#endif + CTRL_OPTIONS(memctl_interleaving), + CTRL_OPTIONS(memctl_interleaving_mode), + CTRL_OPTIONS(ba_intlv_ctl), + CTRL_OPTIONS(ecc_mode), + CTRL_OPTIONS(ecc_init_using_memctl), + CTRL_OPTIONS(dqs_config), + CTRL_OPTIONS(self_refresh_in_sleep), + CTRL_OPTIONS(dynamic_power), + CTRL_OPTIONS(data_bus_width), + CTRL_OPTIONS(burst_length), + CTRL_OPTIONS(cas_latency_override), + CTRL_OPTIONS(cas_latency_override_value), + CTRL_OPTIONS(use_derated_caslat), + CTRL_OPTIONS(additive_latency_override), + CTRL_OPTIONS(additive_latency_override_value), + CTRL_OPTIONS(clk_adjust), + CTRL_OPTIONS(cpo_override), + CTRL_OPTIONS(write_data_delay), + CTRL_OPTIONS(half_strength_driver_enable), + + /* + * These can probably be changed to 2T_EN and 3T_EN + * (using a leading numerical character) without problem + */ + CTRL_OPTIONS(twot_en), + CTRL_OPTIONS(threet_en), + CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), + CTRL_OPTIONS(bstopre), + CTRL_OPTIONS(wrlvl_override), + CTRL_OPTIONS(wrlvl_sample), + CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(rcw_override), + CTRL_OPTIONS(rcw_1), + CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS(ddr_cdr1), + CTRL_OPTIONS(ddr_cdr2), + CTRL_OPTIONS(tcke_clock_pulse_width_ps), + CTRL_OPTIONS(tfaw_window_four_activates_ps), + CTRL_OPTIONS(trwt_override), + CTRL_OPTIONS(trwt), + }; + + static const unsigned int n_opts = ARRAY_SIZE(options); + + if (handle_option_table(options, n_opts, p, + optname_str, value_str)) + return; + + printf("couldn't find option string %s\n", optname_str); +} + +#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \ + sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1} +#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \ + offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \ + sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1} + +static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) +{ + unsigned int i; + static const struct options_string options[] = { + CFG_REGS_CS(0, bnds), + CFG_REGS_CS(0, config), + CFG_REGS_CS(0, config_2), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CFG_REGS_CS(1, bnds), + CFG_REGS_CS(1, config), + CFG_REGS_CS(1, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(2, bnds), + CFG_REGS_CS(2, config), + CFG_REGS_CS(2, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(3, bnds), + CFG_REGS_CS(3, config), + CFG_REGS_CS(3, config_2), +#endif + CFG_REGS(timing_cfg_3), + CFG_REGS(timing_cfg_0), + CFG_REGS(timing_cfg_1), + CFG_REGS(timing_cfg_2), + CFG_REGS(ddr_sdram_cfg), + CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_mode), + CFG_REGS(ddr_sdram_mode_2), + CFG_REGS(ddr_sdram_mode_3), + CFG_REGS(ddr_sdram_mode_4), + CFG_REGS(ddr_sdram_mode_5), + CFG_REGS(ddr_sdram_mode_6), + CFG_REGS(ddr_sdram_mode_7), + CFG_REGS(ddr_sdram_mode_8), + CFG_REGS(ddr_sdram_interval), + CFG_REGS(ddr_data_init), + CFG_REGS(ddr_sdram_clk_cntl), + CFG_REGS(ddr_init_addr), + CFG_REGS(ddr_init_ext_addr), + CFG_REGS(timing_cfg_4), + CFG_REGS(timing_cfg_5), + CFG_REGS(ddr_zq_cntl), + CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_wrlvl_cntl_2), + CFG_REGS(ddr_wrlvl_cntl_3), + CFG_REGS(ddr_sr_cntr), + CFG_REGS(ddr_sdram_rcw_1), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_cdr1), + CFG_REGS(ddr_cdr2), + CFG_REGS(err_disable), + CFG_REGS(err_int_en), + CFG_REGS(ddr_eor), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + print_option_table(options, n_opts, ddr); + + for (i = 0; i < 32; i++) + printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]); +} + +static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo, + unsigned int ctrl_num, + const char *regname, + const char *value_str) +{ + unsigned int i; + fsl_ddr_cfg_regs_t *ddr; + char buf[20]; + static const struct options_string options[] = { + CFG_REGS_CS(0, bnds), + CFG_REGS_CS(0, config), + CFG_REGS_CS(0, config_2), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CFG_REGS_CS(1, bnds), + CFG_REGS_CS(1, config), + CFG_REGS_CS(1, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CFG_REGS_CS(2, bnds), + CFG_REGS_CS(2, config), + CFG_REGS_CS(2, config_2), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CFG_REGS_CS(3, bnds), + CFG_REGS_CS(3, config), + CFG_REGS_CS(3, config_2), +#endif + CFG_REGS(timing_cfg_3), + CFG_REGS(timing_cfg_0), + CFG_REGS(timing_cfg_1), + CFG_REGS(timing_cfg_2), + CFG_REGS(ddr_sdram_cfg), + CFG_REGS(ddr_sdram_cfg_2), + CFG_REGS(ddr_sdram_mode), + CFG_REGS(ddr_sdram_mode_2), + CFG_REGS(ddr_sdram_mode_3), + CFG_REGS(ddr_sdram_mode_4), + CFG_REGS(ddr_sdram_mode_5), + CFG_REGS(ddr_sdram_mode_6), + CFG_REGS(ddr_sdram_mode_7), + CFG_REGS(ddr_sdram_mode_8), + CFG_REGS(ddr_sdram_interval), + CFG_REGS(ddr_data_init), + CFG_REGS(ddr_sdram_clk_cntl), + CFG_REGS(ddr_init_addr), + CFG_REGS(ddr_init_ext_addr), + CFG_REGS(timing_cfg_4), + CFG_REGS(timing_cfg_5), + CFG_REGS(ddr_zq_cntl), + CFG_REGS(ddr_wrlvl_cntl), + CFG_REGS(ddr_wrlvl_cntl_2), + CFG_REGS(ddr_wrlvl_cntl_3), + CFG_REGS(ddr_sr_cntr), + CFG_REGS(ddr_sdram_rcw_1), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_cdr1), + CFG_REGS(ddr_cdr2), + CFG_REGS(err_disable), + CFG_REGS(err_int_en), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_sdram_rcw_2), + CFG_REGS(ddr_eor), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + debug("fsl_ddr_regs_edit: ctrl_num = %u, " + "regname = %s, value = %s\n", + ctrl_num, regname, value_str); + if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS) + return; + + ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]); + + if (handle_option_table(options, n_opts, ddr, regname, value_str)) + return; + + for (i = 0; i < 32; i++) { + unsigned int value = simple_strtoul(value_str, NULL, 0); + sprintf(buf, "debug_%u", i + 1); + if (strcmp(buf, regname) == 0) { + ddr->debug[i] = value; + return; + } + } + printf("Error: couldn't find register string %s\n", regname); +} + +#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \ + sizeof((memctl_options_t *)0)->x, 1} + +static void print_memctl_options(const memctl_options_t *popts) +{ + static const struct options_string options[] = { + CTRL_OPTIONS_CS(0, odt_rd_cfg), + CTRL_OPTIONS_CS(0, odt_wr_cfg), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rd_cfg), + CTRL_OPTIONS_CS(1, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rd_cfg), + CTRL_OPTIONS_CS(2, odt_wr_cfg), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CTRL_OPTIONS_CS(3, odt_rd_cfg), + CTRL_OPTIONS_CS(3, odt_wr_cfg), +#endif +#if defined(CONFIG_SYS_FSL_DDR3) + CTRL_OPTIONS_CS(0, odt_rtt_norm), + CTRL_OPTIONS_CS(0, odt_rtt_wr), +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1) + CTRL_OPTIONS_CS(1, odt_rtt_norm), + CTRL_OPTIONS_CS(1, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2) + CTRL_OPTIONS_CS(2, odt_rtt_norm), + CTRL_OPTIONS_CS(2, odt_rtt_wr), +#endif +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3) + CTRL_OPTIONS_CS(3, odt_rtt_norm), + CTRL_OPTIONS_CS(3, odt_rtt_wr), +#endif +#endif + CTRL_OPTIONS(memctl_interleaving), + CTRL_OPTIONS(memctl_interleaving_mode), + CTRL_OPTIONS_HEX(ba_intlv_ctl), + CTRL_OPTIONS(ecc_mode), + CTRL_OPTIONS(ecc_init_using_memctl), + CTRL_OPTIONS(dqs_config), + CTRL_OPTIONS(self_refresh_in_sleep), + CTRL_OPTIONS(dynamic_power), + CTRL_OPTIONS(data_bus_width), + CTRL_OPTIONS(burst_length), + CTRL_OPTIONS(cas_latency_override), + CTRL_OPTIONS(cas_latency_override_value), + CTRL_OPTIONS(use_derated_caslat), + CTRL_OPTIONS(additive_latency_override), + CTRL_OPTIONS(additive_latency_override_value), + CTRL_OPTIONS(clk_adjust), + CTRL_OPTIONS(cpo_override), + CTRL_OPTIONS(write_data_delay), + CTRL_OPTIONS(half_strength_driver_enable), + /* + * These can probably be changed to 2T_EN and 3T_EN + * (using a leading numerical character) without problem + */ + CTRL_OPTIONS(twot_en), + CTRL_OPTIONS(threet_en), + CTRL_OPTIONS(registered_dimm_en), + CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), + CTRL_OPTIONS(bstopre), + CTRL_OPTIONS(wrlvl_override), + CTRL_OPTIONS(wrlvl_sample), + CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(rcw_override), + CTRL_OPTIONS(rcw_1), + CTRL_OPTIONS(rcw_2), + CTRL_OPTIONS_HEX(ddr_cdr1), + CTRL_OPTIONS_HEX(ddr_cdr2), + CTRL_OPTIONS(tcke_clock_pulse_width_ps), + CTRL_OPTIONS(tfaw_window_four_activates_ps), + CTRL_OPTIONS(trwt_override), + CTRL_OPTIONS(trwt), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + print_option_table(options, n_opts, popts); +} + +#ifdef CONFIG_SYS_FSL_DDR1 +void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", 5, spd->nrows, + " spd->nrows * 5 # of DIMM Banks *"); + printf("%-3d : %02x %s\n", 6, spd->dataw_lsb, + " spd->dataw_lsb, * 6 Data Width lsb of this assembly *"); + printf("%-3d : %02x %s\n", 7, spd->dataw_msb, + " spd->dataw_msb, * 7 Data Width msb of this assembly *"); + printf("%-3d : %02x %s\n", 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", 15, spd->min_delay, + " spd->min_delay, * 15 Back to Back Random Access *"); + printf("%-3d : %02x %s\n", 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", 19, spd->cs_lat, + " spd->cs_lat, * 19 Chip Select Latency *"); + printf("%-3d : %02x %s\n", 20, spd->write_lat, + " spd->write_lat, * 20 Write Latency/Recovery *"); + printf("%-3d : %02x %s\n", 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", 31, spd->bank_dens, + " spd->bank_dens, * 31 Density of each bank on module *"); + printf("%-3d : %02x %s\n", 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", 36, spd->res_36_40[0], + " spd->res_36_40[0], * 36 Reserved / tWR *"); + printf("%-3d : %02x %s\n", 37, spd->res_36_40[1], + " spd->res_36_40[1], * 37 Reserved / tWTR *"); + printf("%-3d : %02x %s\n", 38, spd->res_36_40[2], + " spd->res_36_40[2], * 38 Reserved / tRTP *"); + printf("%-3d : %02x %s\n", 39, spd->res_36_40[3], + " spd->res_36_40[3], * 39 Reserved / mem_probe *"); + printf("%-3d : %02x %s\n", 40, spd->res_36_40[4], + " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *"); + printf("%-3d : %02x %s\n", 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", 46, spd->res_46, + " spd->res_46, * 46 Reserved/ PLL Relock time *"); + printf("%-3d : %02x %s\n", 47, spd->dimm_height, + " spd->dimm_height * 47 SDRAM DIMM Height *"); + + printf("%-3d-%3d: ", 48, 61); + + for (i = 0; i < 14; i++) + printf("%02x", spd->res_48_61[i]); + + printf(" * 48-61 IDD in SPD and Reserved space *\n"); + + printf("%-3d : %02x %s\n", 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) + printf("%02x", spd->mid[i]); + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + printf("%-3d : %02x %s\n", 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + + for (i = 0; i < 18; i++) + printf("%c", spd->mpart[i]); + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) + printf("%02x", spd->sernum[i]); + + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + + for (i = 0; i < 27; i++) + printf("%02x", spd->mspec[i]); + + printf("* 99 Manufacturer Specific Data *\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_DDR2 +void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd) +{ + unsigned int i; + + printf("%-3d : %02x %s\n", 0, spd->info_size, + " spd->info_size, * 0 # bytes written into serial memory *"); + printf("%-3d : %02x %s\n", 1, spd->chip_size, + " spd->chip_size, * 1 Total # bytes of SPD memory device *"); + printf("%-3d : %02x %s\n", 2, spd->mem_type, + " spd->mem_type, * 2 Fundamental memory type *"); + printf("%-3d : %02x %s\n", 3, spd->nrow_addr, + " spd->nrow_addr, * 3 # of Row Addresses on this assembly *"); + printf("%-3d : %02x %s\n", 4, spd->ncol_addr, + " spd->ncol_addr, * 4 # of Column Addrs on this assembly *"); + printf("%-3d : %02x %s\n", 5, spd->mod_ranks, + " spd->mod_ranks * 5 # of Module Rows on this assembly *"); + printf("%-3d : %02x %s\n", 6, spd->dataw, + " spd->dataw, * 6 Data Width of this assembly *"); + printf("%-3d : %02x %s\n", 7, spd->res_7, + " spd->res_7, * 7 Reserved *"); + printf("%-3d : %02x %s\n", 8, spd->voltage, + " spd->voltage, * 8 Voltage intf std of this assembly *"); + printf("%-3d : %02x %s\n", 9, spd->clk_cycle, + " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *"); + printf("%-3d : %02x %s\n", 10, spd->clk_access, + " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *"); + printf("%-3d : %02x %s\n", 11, spd->config, + " spd->config, * 11 DIMM Configuration type *"); + printf("%-3d : %02x %s\n", 12, spd->refresh, + " spd->refresh, * 12 Refresh Rate/Type *"); + printf("%-3d : %02x %s\n", 13, spd->primw, + " spd->primw, * 13 Primary SDRAM Width *"); + printf("%-3d : %02x %s\n", 14, spd->ecw, + " spd->ecw, * 14 Error Checking SDRAM width *"); + printf("%-3d : %02x %s\n", 15, spd->res_15, + " spd->res_15, * 15 Reserved *"); + printf("%-3d : %02x %s\n", 16, spd->burstl, + " spd->burstl, * 16 Burst Lengths Supported *"); + printf("%-3d : %02x %s\n", 17, spd->nbanks, + " spd->nbanks, * 17 # of Banks on Each SDRAM Device *"); + printf("%-3d : %02x %s\n", 18, spd->cas_lat, + " spd->cas_lat, * 18 CAS# Latencies Supported *"); + printf("%-3d : %02x %s\n", 19, spd->mech_char, + " spd->mech_char, * 19 Mechanical Characteristics *"); + printf("%-3d : %02x %s\n", 20, spd->dimm_type, + " spd->dimm_type, * 20 DIMM type *"); + printf("%-3d : %02x %s\n", 21, spd->mod_attr, + " spd->mod_attr, * 21 SDRAM Module Attributes *"); + printf("%-3d : %02x %s\n", 22, spd->dev_attr, + " spd->dev_attr, * 22 SDRAM Device Attributes *"); + printf("%-3d : %02x %s\n", 23, spd->clk_cycle2, + " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *"); + printf("%-3d : %02x %s\n", 24, spd->clk_access2, + " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *"); + printf("%-3d : %02x %s\n", 25, spd->clk_cycle3, + " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *"); + printf("%-3d : %02x %s\n", 26, spd->clk_access3, + " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *"); + printf("%-3d : %02x %s\n", 27, spd->trp, + " spd->trp, * 27 Min Row Precharge Time (tRP)*"); + printf("%-3d : %02x %s\n", 28, spd->trrd, + " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *"); + printf("%-3d : %02x %s\n", 29, spd->trcd, + " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *"); + printf("%-3d : %02x %s\n", 30, spd->tras, + " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *"); + printf("%-3d : %02x %s\n", 31, spd->rank_dens, + " spd->rank_dens, * 31 Density of each rank on module *"); + printf("%-3d : %02x %s\n", 32, spd->ca_setup, + " spd->ca_setup, * 32 Cmd + Addr signal input setup time *"); + printf("%-3d : %02x %s\n", 33, spd->ca_hold, + " spd->ca_hold, * 33 Cmd and Addr signal input hold time *"); + printf("%-3d : %02x %s\n", 34, spd->data_setup, + " spd->data_setup, * 34 Data signal input setup time *"); + printf("%-3d : %02x %s\n", 35, spd->data_hold, + " spd->data_hold, * 35 Data signal input hold time *"); + printf("%-3d : %02x %s\n", 36, spd->twr, + " spd->twr, * 36 Write Recovery time tWR *"); + printf("%-3d : %02x %s\n", 37, spd->twtr, + " spd->twtr, * 37 Int write to read delay tWTR *"); + printf("%-3d : %02x %s\n", 38, spd->trtp, + " spd->trtp, * 38 Int read to precharge delay tRTP *"); + printf("%-3d : %02x %s\n", 39, spd->mem_probe, + " spd->mem_probe, * 39 Mem analysis probe characteristics *"); + printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext, + " spd->trctrfc_ext, * 40 Extensions to trc and trfc *"); + printf("%-3d : %02x %s\n", 41, spd->trc, + " spd->trc, * 41 Min Active to Auto refresh time tRC *"); + printf("%-3d : %02x %s\n", 42, spd->trfc, + " spd->trfc, * 42 Min Auto to Active period tRFC *"); + printf("%-3d : %02x %s\n", 43, spd->tckmax, + " spd->tckmax, * 43 Max device cycle time tCKmax *"); + printf("%-3d : %02x %s\n", 44, spd->tdqsq, + " spd->tdqsq, * 44 Max DQS to DQ skew *"); + printf("%-3d : %02x %s\n", 45, spd->tqhs, + " spd->tqhs, * 45 Max Read DataHold skew tQHS *"); + printf("%-3d : %02x %s\n", 46, spd->pll_relock, + " spd->pll_relock, * 46 PLL Relock time *"); + printf("%-3d : %02x %s\n", 47, spd->t_casemax, + " spd->t_casemax, * 47 t_casemax *"); + printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram, + " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package " + "from Top (Case) to Ambient (Psi T-A DRAM) *"); + printf("%-3d : %02x %s\n", 49, spd->dt0_mode, + " spd->dt0_mode, * 49 DRAM Case Temperature Rise from " + "Ambient due to Activate-Precharge/Mode Bits " + "(DT0/Mode Bits) *)"); + printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q, + " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from " + "Ambient due to Precharge/Quiet Standby " + "(DT2N/DT2Q) *"); + printf("%-3d : %02x %s\n", 51, spd->dt2p, + " spd->dt2p, * 51 DRAM Case Temperature Rise from " + "Ambient due to Precharge Power-Down (DT2P) *"); + printf("%-3d : %02x %s\n", 52, spd->dt3n, + " spd->dt3n, * 52 DRAM Case Temperature Rise from " + "Ambient due to Active Standby (DT3N) *"); + printf("%-3d : %02x %s\n", 53, spd->dt3pfast, + " spd->dt3pfast, * 53 DRAM Case Temperature Rise from " + "Ambient due to Active Power-Down with Fast PDN Exit " + "(DT3Pfast) *"); + printf("%-3d : %02x %s\n", 54, spd->dt3pslow, + " spd->dt3pslow, * 54 DRAM Case Temperature Rise from " + "Ambient due to Active Power-Down with Slow PDN Exit " + "(DT3Pslow) *"); + printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w, + " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from " + "Ambient due to Page Open Burst Read/DT4R4W Mode Bit " + "(DT4R/DT4R4W Mode Bit) *"); + printf("%-3d : %02x %s\n", 56, spd->dt5b, + " spd->dt5b, * 56 DRAM Case Temperature Rise from " + "Ambient due to Burst Refresh (DT5B) *"); + printf("%-3d : %02x %s\n", 57, spd->dt7, + " spd->dt7, * 57 DRAM Case Temperature Rise from " + "Ambient due to Bank Interleave Reads with " + "Auto-Precharge (DT7) *"); + printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll, + " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form" + " Top (Case) to Ambient (Psi T-A PLL) *"); + printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg, + " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package" + " from Top (Case) to Ambient (Psi T-A Register) *"); + printf("%-3d : %02x %s\n", 60, spd->dtpllactive, + " spd->dtpllactive, * 60 PLL Case Temperature Rise from " + "Ambient due to PLL Active (DT PLL Active) *"); + printf("%-3d : %02x %s\n", 61, spd->dtregact, + " spd->dtregact, " + "* 61 Register Case Temperature Rise from Ambient due to " + "Register Active/Mode Bit (DT Register Active/Mode Bit) *"); + printf("%-3d : %02x %s\n", 62, spd->spd_rev, + " spd->spd_rev, * 62 SPD Data Revision Code *"); + printf("%-3d : %02x %s\n", 63, spd->cksum, + " spd->cksum, * 63 Checksum for bytes 0-62 *"); + + printf("%-3d-%3d: ", 64, 71); + + for (i = 0; i < 8; i++) + printf("%02x", spd->mid[i]); + + printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n"); + + printf("%-3d : %02x %s\n", 72, spd->mloc, + " spd->mloc, * 72 Manufacturing Location *"); + + printf("%-3d-%3d: >>", 73, 90); + for (i = 0; i < 18; i++) + printf("%c", spd->mpart[i]); + + + printf("<<* 73 Manufacturer's Part Number *\n"); + + printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1], + "* 91 Revision Code *"); + printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1], + "* 93 Manufacturing Date *"); + printf("%-3d-%3d: ", 95, 98); + + for (i = 0; i < 4; i++) + printf("%02x", spd->sernum[i]); + + printf("* 95 Assembly Serial Number *\n"); + + printf("%-3d-%3d: ", 99, 127); + for (i = 0; i < 27; i++) + printf("%02x", spd->mspec[i]); + + + printf("* 99 Manufacturer Specific Data *\n"); +} +#endif + +#ifdef CONFIG_SYS_FSL_DDR3 +void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd) +{ + unsigned int i; + + /* General Section: Bytes 0-59 */ + +#define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y); +#define PRINT_NNXXS(n0, n1, x0, x1, s) \ + printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1); + + PRINT_NXS(0, spd->info_size_crc, + "info_size_crc bytes written into serial memory, " + "CRC coverage"); + PRINT_NXS(1, spd->spd_rev, + "spd_rev SPD Revision"); + PRINT_NXS(2, spd->mem_type, + "mem_type Key Byte / DRAM Device Type"); + PRINT_NXS(3, spd->module_type, + "module_type Key Byte / Module Type"); + PRINT_NXS(4, spd->density_banks, + "density_banks SDRAM Density and Banks"); + PRINT_NXS(5, spd->addressing, + "addressing SDRAM Addressing"); + PRINT_NXS(6, spd->module_vdd, + "module_vdd Module Nominal Voltage, VDD"); + PRINT_NXS(7, spd->organization, + "organization Module Organization"); + PRINT_NXS(8, spd->bus_width, + "bus_width Module Memory Bus Width"); + PRINT_NXS(9, spd->ftb_div, + "ftb_div Fine Timebase (FTB) Dividend / Divisor"); + PRINT_NXS(10, spd->mtb_dividend, + "mtb_dividend Medium Timebase (MTB) Dividend"); + PRINT_NXS(11, spd->mtb_divisor, + "mtb_divisor Medium Timebase (MTB) Divisor"); + PRINT_NXS(12, spd->tck_min, + "tck_min SDRAM Minimum Cycle Time"); + PRINT_NXS(13, spd->res_13, + "res_13 Reserved"); + PRINT_NXS(14, spd->caslat_lsb, + "caslat_lsb CAS Latencies Supported, LSB"); + PRINT_NXS(15, spd->caslat_msb, + "caslat_msb CAS Latencies Supported, MSB"); + PRINT_NXS(16, spd->taa_min, + "taa_min Min CAS Latency Time"); + PRINT_NXS(17, spd->twr_min, + "twr_min Min Write REcovery Time"); + PRINT_NXS(18, spd->trcd_min, + "trcd_min Min RAS# to CAS# Delay Time"); + PRINT_NXS(19, spd->trrd_min, + "trrd_min Min Row Active to Row Active Delay Time"); + PRINT_NXS(20, spd->trp_min, + "trp_min Min Row Precharge Delay Time"); + PRINT_NXS(21, spd->tras_trc_ext, + "tras_trc_ext Upper Nibbles for tRAS and tRC"); + PRINT_NXS(22, spd->tras_min_lsb, + "tras_min_lsb Min Active to Precharge Delay Time, LSB"); + PRINT_NXS(23, spd->trc_min_lsb, + "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB"); + PRINT_NXS(24, spd->trfc_min_lsb, + "trfc_min_lsb Min Refresh Recovery Delay Time LSB"); + PRINT_NXS(25, spd->trfc_min_msb, + "trfc_min_msb Min Refresh Recovery Delay Time MSB"); + PRINT_NXS(26, spd->twtr_min, + "twtr_min Min Internal Write to Read Command Delay Time"); + PRINT_NXS(27, spd->trtp_min, + "trtp_min " + "Min Internal Read to Precharge Command Delay Time"); + PRINT_NXS(28, spd->tfaw_msb, + "tfaw_msb Upper Nibble for tFAW"); + PRINT_NXS(29, spd->tfaw_min, + "tfaw_min Min Four Activate Window Delay Time"); + PRINT_NXS(30, spd->opt_features, + "opt_features SDRAM Optional Features"); + PRINT_NXS(31, spd->therm_ref_opt, + "therm_ref_opt SDRAM Thermal and Refresh Opts"); + PRINT_NXS(32, spd->therm_sensor, + "therm_sensor SDRAM Thermal Sensor"); + PRINT_NXS(33, spd->device_type, + "device_type SDRAM Device Type"); + PRINT_NXS(34, spd->fine_tck_min, + "fine_tck_min Fine offset for tCKmin"); + PRINT_NXS(35, spd->fine_taa_min, + "fine_taa_min Fine offset for tAAmin"); + PRINT_NXS(36, spd->fine_trcd_min, + "fine_trcd_min Fine offset for tRCDmin"); + PRINT_NXS(37, spd->fine_trp_min, + "fine_trp_min Fine offset for tRPmin"); + PRINT_NXS(38, spd->fine_trc_min, + "fine_trc_min Fine offset for tRCmin"); + + printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */ + + for (i = 39; i <= 59; i++) + printf("%02x ", spd->res_39_59[i - 39]); + + puts("\n"); + + switch (spd->module_type) { + case 0x02: /* UDIMM */ + case 0x03: /* SO-DIMM */ + case 0x04: /* Micro-DIMM */ + case 0x06: /* Mini-UDIMM */ + PRINT_NXS(60, spd->mod_section.unbuffered.mod_height, + "mod_height (Unbuffered) Module Nominal Height"); + PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness, + "mod_thickness (Unbuffered) Module Maximum Thickness"); + PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card, + "ref_raw_card (Unbuffered) Reference Raw Card Used"); + PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping, + "addr_mapping (Unbuffered) Address mapping from " + "Edge Connector to DRAM"); + break; + case 0x01: /* RDIMM */ + case 0x05: /* Mini-RDIMM */ + PRINT_NXS(60, spd->mod_section.registered.mod_height, + "mod_height (Registered) Module Nominal Height"); + PRINT_NXS(61, spd->mod_section.registered.mod_thickness, + "mod_thickness (Registered) Module Maximum Thickness"); + PRINT_NXS(62, spd->mod_section.registered.ref_raw_card, + "ref_raw_card (Registered) Reference Raw Card Used"); + PRINT_NXS(63, spd->mod_section.registered.modu_attr, + "modu_attr (Registered) DIMM Module Attributes"); + PRINT_NXS(64, spd->mod_section.registered.thermal, + "thermal (Registered) Thermal Heat " + "Spreader Solution"); + PRINT_NXS(65, spd->mod_section.registered.reg_id_lo, + "reg_id_lo (Registered) Register Manufacturer ID " + "Code, LSB"); + PRINT_NXS(66, spd->mod_section.registered.reg_id_hi, + "reg_id_hi (Registered) Register Manufacturer ID " + "Code, MSB"); + PRINT_NXS(67, spd->mod_section.registered.reg_rev, + "reg_rev (Registered) Register " + "Revision Number"); + PRINT_NXS(68, spd->mod_section.registered.reg_type, + "reg_type (Registered) Register Type"); + for (i = 69; i <= 76; i++) { + printf("%-3d : %02x rcw[%d]\n", i, + spd->mod_section.registered.rcw[i-69], i-69); + } + break; + default: + /* Module-specific Section, Unsupported Module Type */ + printf("%-3d-%3d: ", 60, 116); + + for (i = 60; i <= 116; i++) + printf("%02x", spd->mod_section.uc[i - 60]); + + break; + } + + /* Unique Module ID: Bytes 117-125 */ + PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106"); + PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106"); + PRINT_NXS(119, spd->mloc, "Mfg Location"); + PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date"); + + printf("%-3d-%3d: ", 122, 125); + + for (i = 122; i <= 125; i++) + printf("%02x ", spd->sernum[i - 122]); + printf(" Module Serial Number\n"); + + /* CRC: Bytes 126-127 */ + PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC"); + + /* Other Manufacturer Fields and User Space: Bytes 128-255 */ + printf("%-3d-%3d: ", 128, 145); + for (i = 128; i <= 145; i++) + printf("%02x ", spd->mpart[i - 128]); + printf(" Mfg's Module Part Number\n"); + + PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1], + "Module Revision code"); + + PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106"); + PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106"); + + printf("%-3d-%3d: ", 150, 175); + for (i = 150; i <= 175; i++) + printf("%02x ", spd->msd[i - 150]); + printf(" Mfg's Specific Data\n"); + + printf("%-3d-%3d: ", 176, 255); + for (i = 176; i <= 255; i++) + printf("%02x", spd->cust[i - 176]); + printf(" Mfg's Specific Data\n"); + +} +#endif + +static inline void generic_spd_dump(const generic_spd_eeprom_t *spd) +{ +#if defined(CONFIG_SYS_FSL_DDR1) + ddr1_spd_dump(spd); +#elif defined(CONFIG_SYS_FSL_DDR2) + ddr2_spd_dump(spd); +#elif defined(CONFIG_SYS_FSL_DDR3) + ddr3_spd_dump(spd); +#endif +} + +static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo, + unsigned int ctrl_mask, + unsigned int dimm_mask, + unsigned int do_mask) +{ + unsigned int i, j, retval; + + /* STEP 1: DIMM SPD data */ + if (do_mask & STEP_GET_SPD) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + if (!(dimm_mask & (1 << j))) + continue; + + printf("SPD info: Controller=%u " + "DIMM=%u\n", i, j); + generic_spd_dump( + &(pinfo->spd_installed_dimms[i][j])); + printf("\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 2: DIMM Parameters */ + if (do_mask & STEP_COMPUTE_DIMM_PARMS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + if (!(dimm_mask & (1 << j))) + continue; + printf("DIMM parameters: Controller=%u " + "DIMM=%u\n", i, j); + print_dimm_parameters( + &(pinfo->dimm_params[i][j])); + printf("\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 3: Common Parameters */ + if (do_mask & STEP_COMPUTE_COMMON_PARMS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("\"lowest common\" DIMM parameters: " + "Controller=%u\n", i); + print_lowest_common_dimm_parameters( + &pinfo->common_timing_params[i]); + printf("\n"); + } + printf("\n"); + } + + /* STEP 4: User Configuration Options */ + if (do_mask & STEP_GATHER_OPTS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("User Config Options: Controller=%u\n", i); + print_memctl_options(&pinfo->memctl_opts[i]); + printf("\n"); + } + printf("\n"); + } + + /* STEP 5: Address assignment */ + if (do_mask & STEP_ASSIGN_ADDRESSES) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + printf("Address Assignment: Controller=%u " + "DIMM=%u\n", i, j); + printf("Don't have this functionality yet\n"); + } + printf("\n"); + } + printf("\n"); + } + + /* STEP 6: computed controller register values */ + if (do_mask & STEP_COMPUTE_REGS) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (!(ctrl_mask & (1 << i))) + continue; + printf("Computed Register Values: Controller=%u\n", i); + print_fsl_memctl_config_regs( + &pinfo->fsl_ddr_config_reg[i]); + retval = check_fsl_memctl_config_regs( + &pinfo->fsl_ddr_config_reg[i]); + if (retval) { + printf("check_fsl_memctl_config_regs " + "result = %u\n", retval); + } + printf("\n"); + } + printf("\n"); + } +} + +struct data_strings { + const char *data_name; + unsigned int step_mask; + unsigned int dimm_number_required; +}; + +#define DATA_OPTIONS(name, step, dimm) {#name, step, dimm} + +static unsigned int fsl_ddr_parse_interactive_cmd( + char **argv, + int argc, + unsigned int *pstep_mask, + unsigned int *pctlr_mask, + unsigned int *pdimm_mask, + unsigned int *pdimm_number_required + ) { + + static const struct data_strings options[] = { + DATA_OPTIONS(spd, STEP_GET_SPD, 1), + DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1), + DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0), + DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0), + DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0), + DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0), + }; + static const unsigned int n_opts = ARRAY_SIZE(options); + + unsigned int i, j; + unsigned int error = 0; + + for (i = 1; i < argc; i++) { + unsigned int matched = 0; + + for (j = 0; j < n_opts; j++) { + if (strcmp(options[j].data_name, argv[i]) != 0) + continue; + *pstep_mask |= options[j].step_mask; + *pdimm_number_required = + options[j].dimm_number_required; + matched = 1; + break; + } + + if (matched) + continue; + + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) + *pctlr_mask |= 1 << (c - '0'); + continue; + } + + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) + *pdimm_mask |= 1 << (c - '0'); + continue; + } + + printf("unknown arg %s\n", argv[i]); + *pstep_mask = 0; + error = 1; + break; + } + + return error; +} + +int fsl_ddr_interactive_env_var_exists(void) +{ + char buffer[CONFIG_SYS_CBSIZE]; + + if (getenv_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0) + return 1; + + return 0; +} + +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set) +{ + unsigned long long ddrsize; + const char *prompt = "FSL DDR>"; + char buffer[CONFIG_SYS_CBSIZE]; + char buffer2[CONFIG_SYS_CBSIZE]; + char *p = NULL; + char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */ + int argc; + unsigned int next_step = STEP_GET_SPD; + const char *usage = { + "commands:\n" + "print print SPD and intermediate computed data\n" + "reset reboot machine\n" + "recompute reload SPD and options to default and recompute regs\n" + "edit modify spd, parameter, or option\n" + "compute recompute registers from current next_step to end\n" + "copy copy parameters\n" + "next_step shows current next_step\n" + "help this message\n" + "go program the memory controller and continue with u-boot\n" + }; + + if (var_is_set) { + if (getenv_f("ddr_interactive", buffer2, CONFIG_SYS_CBSIZE) > 0) { + p = buffer2; + } else { + var_is_set = 0; + } + } + + /* + * The strategy for next_step is that it points to the next + * step in the computation process that needs to be done. + */ + while (1) { + if (var_is_set) { + char *pend = strchr(p, ';'); + if (pend) { + /* found command separator, copy sub-command */ + *pend = '\0'; + strcpy(buffer, p); + p = pend + 1; + } else { + /* separator not found, copy whole string */ + strcpy(buffer, p); + p = NULL; + var_is_set = 0; + } + } else { + /* + * No need to worry for buffer overflow here in + * this function; readline() maxes out at CFG_CBSIZE + */ + readline_into_buffer(prompt, buffer, 0); + } + argc = parse_line(buffer, argv); + if (argc == 0) + continue; + + + if (strcmp(argv[0], "help") == 0) { + puts(usage); + continue; + } + + if (strcmp(argv[0], "next_step") == 0) { + printf("next_step = 0x%02X (%s)\n", + next_step, + step_to_string(next_step)); + continue; + } + + if (strcmp(argv[0], "copy") == 0) { + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int src_ctlr_mask = 0; + unsigned int src_dimm_mask = 0; + unsigned int dimm_number_required = 0; + unsigned int src_ctlr_num = 0; + unsigned int src_dimm_num = 0; + unsigned int dst_ctlr_num = -1; + unsigned int dst_dimm_num = -1; + unsigned int i, num_dest_parms; + + if (argc == 1) { + printf("copy \n"); + continue; + } + + error = fsl_ddr_parse_interactive_cmd( + argv, argc, + &step_mask, + &src_ctlr_mask, + &src_dimm_mask, + &dimm_number_required + ); + + /* XXX: only dimm_number_required and step_mask will + be used by this function. Parse the controller and + DIMM number separately because it is easier. */ + + if (error) + continue; + + /* parse source destination controller / DIMM */ + + num_dest_parms = dimm_number_required ? 2 : 1; + + for (i = 0; i < argc; i++) { + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) { + src_ctlr_num = (c - '0'); + break; + } + } + } + + for (i = 0; i < argc; i++) { + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) { + src_dimm_num = (c - '0'); + break; + } + } + } + + /* parse destination controller / DIMM */ + + for (i = argc - 1; i >= argc - num_dest_parms; i--) { + if (argv[i][0] == 'c') { + char c = argv[i][1]; + if (isdigit(c)) { + dst_ctlr_num = (c - '0'); + break; + } + } + } + + for (i = argc - 1; i >= argc - num_dest_parms; i--) { + if (argv[i][0] == 'd') { + char c = argv[i][1]; + if (isdigit(c)) { + dst_dimm_num = (c - '0'); + break; + } + } + } + + /* TODO: validate inputs */ + + debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n", + src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask); + + + switch (step_mask) { + + case STEP_GET_SPD: + memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]), + &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]), + sizeof(pinfo->spd_installed_dimms[0][0])); + break; + + case STEP_COMPUTE_DIMM_PARMS: + memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]), + &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]), + sizeof(pinfo->dimm_params[0][0])); + break; + + case STEP_COMPUTE_COMMON_PARMS: + memcpy(&(pinfo->common_timing_params[dst_ctlr_num]), + &(pinfo->common_timing_params[src_ctlr_num]), + sizeof(pinfo->common_timing_params[0])); + break; + + case STEP_GATHER_OPTS: + memcpy(&(pinfo->memctl_opts[dst_ctlr_num]), + &(pinfo->memctl_opts[src_ctlr_num]), + sizeof(pinfo->memctl_opts[0])); + break; + + /* someday be able to have addresses to copy addresses... */ + + case STEP_COMPUTE_REGS: + memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]), + &(pinfo->fsl_ddr_config_reg[src_ctlr_num]), + sizeof(pinfo->memctl_opts[0])); + break; + + default: + printf("unexpected step_mask value\n"); + } + + continue; + + } + + if (strcmp(argv[0], "edit") == 0) { + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int ctlr_mask = 0; + unsigned int dimm_mask = 0; + char *p_element = NULL; + char *p_value = NULL; + unsigned int dimm_number_required = 0; + unsigned int ctrl_num; + unsigned int dimm_num; + + if (argc == 1) { + /* Only the element and value must be last */ + printf("edit " + " \n"); + printf("for spd, specify byte number for " + "element\n"); + continue; + } + + error = fsl_ddr_parse_interactive_cmd( + argv, argc - 2, + &step_mask, + &ctlr_mask, + &dimm_mask, + &dimm_number_required + ); + + if (error) + continue; + + + /* Check arguments */ + + /* ERROR: If no steps were found */ + if (step_mask == 0) { + printf("Error: No valid steps were specified " + "in argument.\n"); + continue; + } + + /* ERROR: If multiple steps were found */ + if (step_mask & (step_mask - 1)) { + printf("Error: Multiple steps specified in " + "argument.\n"); + continue; + } + + /* ERROR: Controller not specified */ + if (ctlr_mask == 0) { + printf("Error: controller number not " + "specified or no element and " + "value specified\n"); + continue; + } + + if (ctlr_mask & (ctlr_mask - 1)) { + printf("Error: multiple controllers " + "specified, %X\n", ctlr_mask); + continue; + } + + /* ERROR: DIMM number not specified */ + if (dimm_number_required && dimm_mask == 0) { + printf("Error: DIMM number number not " + "specified or no element and " + "value specified\n"); + continue; + } + + if (dimm_mask & (dimm_mask - 1)) { + printf("Error: multipled DIMMs specified\n"); + continue; + } + + p_element = argv[argc - 2]; + p_value = argv[argc - 1]; + + ctrl_num = __ilog2(ctlr_mask); + dimm_num = __ilog2(dimm_mask); + + switch (step_mask) { + case STEP_GET_SPD: + { + unsigned int element_num; + unsigned int value; + + element_num = simple_strtoul(p_element, + NULL, 0); + value = simple_strtoul(p_value, + NULL, 0); + fsl_ddr_spd_edit(pinfo, + ctrl_num, + dimm_num, + element_num, + value); + next_step = STEP_COMPUTE_DIMM_PARMS; + } + break; + + case STEP_COMPUTE_DIMM_PARMS: + fsl_ddr_dimm_parameters_edit( + pinfo, ctrl_num, dimm_num, + p_element, p_value); + next_step = STEP_COMPUTE_COMMON_PARMS; + break; + + case STEP_COMPUTE_COMMON_PARMS: + lowest_common_dimm_parameters_edit(pinfo, + ctrl_num, p_element, p_value); + next_step = STEP_GATHER_OPTS; + break; + + case STEP_GATHER_OPTS: + fsl_ddr_options_edit(pinfo, ctrl_num, + p_element, p_value); + next_step = STEP_ASSIGN_ADDRESSES; + break; + + case STEP_ASSIGN_ADDRESSES: + printf("editing of address assignment " + "not yet implemented\n"); + break; + + case STEP_COMPUTE_REGS: + { + fsl_ddr_regs_edit(pinfo, + ctrl_num, + p_element, + p_value); + next_step = STEP_PROGRAM_REGS; + } + break; + + default: + printf("programming error\n"); + while (1) + ; + break; + } + continue; + } + + if (strcmp(argv[0], "reset") == 0) { + /* + * Reboot machine. + * Args don't seem to matter because this + * doesn't return + */ + do_reset(NULL, 0, 0, NULL); + printf("Reset didn't work\n"); + } + + if (strcmp(argv[0], "recompute") == 0) { + /* + * Recalculate everything, starting with + * loading SPD EEPROM from DIMMs + */ + next_step = STEP_GET_SPD; + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + continue; + } + + if (strcmp(argv[0], "compute") == 0) { + /* + * Compute rest of steps starting at + * the current next_step/ + */ + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + continue; + } + + if (strcmp(argv[0], "print") == 0) { + unsigned int error = 0; + unsigned int step_mask = 0; + unsigned int ctlr_mask = 0; + unsigned int dimm_mask = 0; + unsigned int dimm_number_required = 0; + + if (argc == 1) { + printf("print [c] [d] [spd] [dimmparms] " + "[commonparms] [opts] [addresses] [regs]\n"); + continue; + } + + error = fsl_ddr_parse_interactive_cmd( + argv, argc, + &step_mask, + &ctlr_mask, + &dimm_mask, + &dimm_number_required + ); + + if (error) + continue; + + /* If no particular controller was found, print all */ + if (ctlr_mask == 0) + ctlr_mask = 0xFF; + + /* If no particular dimm was found, print all dimms. */ + if (dimm_mask == 0) + dimm_mask = 0xFF; + + /* If no steps were found, print all steps. */ + if (step_mask == 0) + step_mask = STEP_ALL; + + fsl_ddr_printinfo(pinfo, ctlr_mask, + dimm_mask, step_mask); + continue; + } + + if (strcmp(argv[0], "go") == 0) { + if (next_step) + ddrsize = fsl_ddr_compute(pinfo, next_step, 0); + break; + } + + printf("unknown command %s\n", argv[0]); + } + + debug("end of memory = %llu\n", (u64)ddrsize); + + return ddrsize; +} diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c new file mode 100644 index 0000000000..610318ad1e --- /dev/null +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -0,0 +1,526 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +#include + +#if defined(CONFIG_SYS_FSL_DDR3) +static unsigned int +compute_cas_latency_ddr3(const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms) +{ + unsigned int i; + unsigned int taamin_ps = 0; + unsigned int tckmin_x_ps = 0; + unsigned int common_caslat; + unsigned int caslat_actual; + unsigned int retry = 16; + unsigned int tmp; + const unsigned int mclk_ps = get_memory_clk_period_ps(); + + /* compute the common CAS latency supported between slots */ + tmp = dimm_params[0].caslat_x; + for (i = 1; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) + tmp &= dimm_params[i].caslat_x; + } + common_caslat = tmp; + + /* compute the max tAAmin tCKmin between slots */ + for (i = 0; i < number_of_dimms; i++) { + taamin_ps = max(taamin_ps, dimm_params[i].taa_ps); + tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); + } + /* validate if the memory clk is in the range of dimms */ + if (mclk_ps < tckmin_x_ps) { + printf("DDR clock (MCLK cycle %u ps) is faster than " + "the slowest DIMM(s) (tCKmin %u ps) can support.\n", + mclk_ps, tckmin_x_ps); + } + /* determine the acutal cas latency */ + caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps; + /* check if the dimms support the CAS latency */ + while (!(common_caslat & (1 << caslat_actual)) && retry > 0) { + caslat_actual++; + retry--; + } + /* once the caculation of caslat_actual is completed + * we must verify that this CAS latency value does not + * exceed tAAmax, which is 20 ns for all DDR3 speed grades + */ + if (caslat_actual * mclk_ps > 20000) { + printf("The choosen cas latency %d is too large\n", + caslat_actual); + } + outpdimm->lowest_common_SPD_caslat = caslat_actual; + + return 0; +} +#endif + +/* + * compute_lowest_common_dimm_parameters() + * + * Determine the worst-case DIMM timing parameters from the set of DIMMs + * whose parameters have been computed into the array pointed to + * by dimm_params. + */ +unsigned int +compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + const unsigned int number_of_dimms) +{ + unsigned int i, j; + + unsigned int tckmin_x_ps = 0; + unsigned int tckmax_ps = 0xFFFFFFFF; + unsigned int tckmax_max_ps = 0; + unsigned int trcd_ps = 0; + unsigned int trp_ps = 0; + unsigned int tras_ps = 0; + unsigned int twr_ps = 0; + unsigned int twtr_ps = 0; + unsigned int trfc_ps = 0; + unsigned int trrd_ps = 0; + unsigned int trc_ps = 0; + unsigned int refresh_rate_ps = 0; + unsigned int extended_op_srt = 1; + unsigned int tis_ps = 0; + unsigned int tih_ps = 0; + unsigned int tds_ps = 0; + unsigned int tdh_ps = 0; + unsigned int trtp_ps = 0; + unsigned int tdqsq_max_ps = 0; + unsigned int tqhs_ps = 0; + + unsigned int temp1, temp2; + unsigned int additive_latency = 0; +#if !defined(CONFIG_SYS_FSL_DDR3) + const unsigned int mclk_ps = get_memory_clk_period_ps(); + unsigned int lowest_good_caslat; + unsigned int not_ok; + + debug("using mclk_ps = %u\n", mclk_ps); +#endif + + temp1 = 0; + for (i = 0; i < number_of_dimms; i++) { + /* + * If there are no ranks on this DIMM, + * it probably doesn't exist, so skip it. + */ + if (dimm_params[i].n_ranks == 0) { + temp1++; + continue; + } + if (dimm_params[i].n_ranks == 4 && i != 0) { + printf("Found Quad-rank DIMM in wrong bank, ignored." + " Software may not run as expected.\n"); + temp1++; + continue; + } + + /* + * check if quad-rank DIMM is plugged if + * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined + * Only the board with proper design is capable + */ +#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (dimm_params[i].n_ranks == 4 && \ + CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) { + printf("Found Quad-rank DIMM, not able to support."); + temp1++; + continue; + } +#endif + /* + * Find minimum tckmax_ps to find fastest slow speed, + * i.e., this is the slowest the whole system can go. + */ + tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps); + + /* Either find maximum value to determine slowest + * speed, delay, time, period, etc */ + tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps); + tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps); + trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps); + trp_ps = max(trp_ps, dimm_params[i].trp_ps); + tras_ps = max(tras_ps, dimm_params[i].tras_ps); + twr_ps = max(twr_ps, dimm_params[i].twr_ps); + twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps); + trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps); + trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps); + trc_ps = max(trc_ps, dimm_params[i].trc_ps); + tis_ps = max(tis_ps, dimm_params[i].tis_ps); + tih_ps = max(tih_ps, dimm_params[i].tih_ps); + tds_ps = max(tds_ps, dimm_params[i].tds_ps); + tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps); + trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps); + tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps); + refresh_rate_ps = max(refresh_rate_ps, + dimm_params[i].refresh_rate_ps); + /* extended_op_srt is either 0 or 1, 0 having priority */ + extended_op_srt = min(extended_op_srt, + dimm_params[i].extended_op_srt); + + /* + * Find maximum tdqsq_max_ps to find slowest. + * + * FIXME: is finding the slowest value the correct + * strategy for this parameter? + */ + tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps); + } + + outpdimm->ndimms_present = number_of_dimms - temp1; + + if (temp1 == number_of_dimms) { + debug("no dimms this memory controller\n"); + return 0; + } + + outpdimm->tckmin_x_ps = tckmin_x_ps; + outpdimm->tckmax_ps = tckmax_ps; + outpdimm->tckmax_max_ps = tckmax_max_ps; + outpdimm->trcd_ps = trcd_ps; + outpdimm->trp_ps = trp_ps; + outpdimm->tras_ps = tras_ps; + outpdimm->twr_ps = twr_ps; + outpdimm->twtr_ps = twtr_ps; + outpdimm->trfc_ps = trfc_ps; + outpdimm->trrd_ps = trrd_ps; + outpdimm->trc_ps = trc_ps; + outpdimm->refresh_rate_ps = refresh_rate_ps; + outpdimm->extended_op_srt = extended_op_srt; + outpdimm->tis_ps = tis_ps; + outpdimm->tih_ps = tih_ps; + outpdimm->tds_ps = tds_ps; + outpdimm->tdh_ps = tdh_ps; + outpdimm->trtp_ps = trtp_ps; + outpdimm->tdqsq_max_ps = tdqsq_max_ps; + outpdimm->tqhs_ps = tqhs_ps; + + /* Determine common burst length for all DIMMs. */ + temp1 = 0xff; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) { + temp1 &= dimm_params[i].burst_lengths_bitmask; + } + } + outpdimm->all_dimms_burst_lengths_bitmask = temp1; + + /* Determine if all DIMMs registered buffered. */ + temp1 = temp2 = 0; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) { + if (dimm_params[i].registered_dimm) { + temp1 = 1; +#ifndef CONFIG_SPL_BUILD + printf("Detected RDIMM %s\n", + dimm_params[i].mpart); +#endif + } else { + temp2 = 1; +#ifndef CONFIG_SPL_BUILD + printf("Detected UDIMM %s\n", + dimm_params[i].mpart); +#endif + } + } + } + + outpdimm->all_dimms_registered = 0; + outpdimm->all_dimms_unbuffered = 0; + if (temp1 && !temp2) { + outpdimm->all_dimms_registered = 1; + } else if (!temp1 && temp2) { + outpdimm->all_dimms_unbuffered = 1; + } else { + printf("ERROR: Mix of registered buffered and unbuffered " + "DIMMs detected!\n"); + } + + temp1 = 0; + if (outpdimm->all_dimms_registered) + for (j = 0; j < 16; j++) { + outpdimm->rcw[j] = dimm_params[0].rcw[j]; + for (i = 1; i < number_of_dimms; i++) { + if (!dimm_params[i].n_ranks) + continue; + if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) { + temp1 = 1; + break; + } + } + } + + if (temp1 != 0) + printf("ERROR: Mix different RDIMM detected!\n"); + +#if defined(CONFIG_SYS_FSL_DDR3) + if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms)) + return 1; +#else + /* + * Compute a CAS latency suitable for all DIMMs + * + * Strategy for SPD-defined latencies: compute only + * CAS latency defined by all DIMMs. + */ + + /* + * Step 1: find CAS latency common to all DIMMs using bitwise + * operation. + */ + temp1 = 0xFF; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks) { + temp2 = 0; + temp2 |= 1 << dimm_params[i].caslat_x; + temp2 |= 1 << dimm_params[i].caslat_x_minus_1; + temp2 |= 1 << dimm_params[i].caslat_x_minus_2; + /* + * FIXME: If there was no entry for X-2 (X-1) in + * the SPD, then caslat_x_minus_2 + * (caslat_x_minus_1) contains either 255 or + * 0xFFFFFFFF because that's what the glorious + * __ilog2 function returns for an input of 0. + * On 32-bit PowerPC, left shift counts with bit + * 26 set (that the value of 255 or 0xFFFFFFFF + * will have), cause the destination register to + * be 0. That is why this works. + */ + temp1 &= temp2; + } + } + + /* + * Step 2: check each common CAS latency against tCK of each + * DIMM's SPD. + */ + lowest_good_caslat = 0; + temp2 = 0; + while (temp1) { + not_ok = 0; + temp2 = __ilog2(temp1); + debug("checking common caslat = %u\n", temp2); + + /* Check if this CAS latency will work on all DIMMs at tCK. */ + for (i = 0; i < number_of_dimms; i++) { + if (!dimm_params[i].n_ranks) { + continue; + } + if (dimm_params[i].caslat_x == temp2) { + if (mclk_ps >= dimm_params[i].tckmin_x_ps) { + debug("CL = %u ok on DIMM %u at tCK=%u" + " ps with its tCKmin_X_ps of %u\n", + temp2, i, mclk_ps, + dimm_params[i].tckmin_x_ps); + continue; + } else { + not_ok++; + } + } + + if (dimm_params[i].caslat_x_minus_1 == temp2) { + unsigned int tckmin_x_minus_1_ps + = dimm_params[i].tckmin_x_minus_1_ps; + if (mclk_ps >= tckmin_x_minus_1_ps) { + debug("CL = %u ok on DIMM %u at " + "tCK=%u ps with its " + "tckmin_x_minus_1_ps of %u\n", + temp2, i, mclk_ps, + tckmin_x_minus_1_ps); + continue; + } else { + not_ok++; + } + } + + if (dimm_params[i].caslat_x_minus_2 == temp2) { + unsigned int tckmin_x_minus_2_ps + = dimm_params[i].tckmin_x_minus_2_ps; + if (mclk_ps >= tckmin_x_minus_2_ps) { + debug("CL = %u ok on DIMM %u at " + "tCK=%u ps with its " + "tckmin_x_minus_2_ps of %u\n", + temp2, i, mclk_ps, + tckmin_x_minus_2_ps); + continue; + } else { + not_ok++; + } + } + } + + if (!not_ok) { + lowest_good_caslat = temp2; + } + + temp1 &= ~(1 << temp2); + } + + debug("lowest common SPD-defined CAS latency = %u\n", + lowest_good_caslat); + outpdimm->lowest_common_SPD_caslat = lowest_good_caslat; + + + /* + * Compute a common 'de-rated' CAS latency. + * + * The strategy here is to find the *highest* dereated cas latency + * with the assumption that all of the DIMMs will support a dereated + * CAS latency higher than or equal to their lowest dereated value. + */ + temp1 = 0; + for (i = 0; i < number_of_dimms; i++) { + temp1 = max(temp1, dimm_params[i].caslat_lowest_derated); + } + outpdimm->highest_common_derated_caslat = temp1; + debug("highest common dereated CAS latency = %u\n", temp1); +#endif /* #if defined(CONFIG_SYS_FSL_DDR3) */ + + /* Determine if all DIMMs ECC capable. */ + temp1 = 1; + for (i = 0; i < number_of_dimms; i++) { + if (dimm_params[i].n_ranks && + !(dimm_params[i].edc_config & EDC_ECC)) { + temp1 = 0; + break; + } + } + if (temp1) { + debug("all DIMMs ECC capable\n"); + } else { + debug("Warning: not all DIMMs ECC capable, cant enable ECC\n"); + } + outpdimm->all_dimms_ecc_capable = temp1; + +#ifndef CONFIG_SYS_FSL_DDR3 + /* FIXME: move to somewhere else to validate. */ + if (mclk_ps > tckmax_max_ps) { + printf("Warning: some of the installed DIMMs " + "can not operate this slowly.\n"); + return 1; + } +#endif + /* + * Compute additive latency. + * + * For DDR1, additive latency should be 0. + * + * For DDR2, with ODT enabled, use "a value" less than ACTTORW, + * which comes from Trcd, and also note that: + * add_lat + caslat must be >= 4 + * + * For DDR3, we use the AL=0 + * + * When to use additive latency for DDR2: + * + * I. Because you are using CL=3 and need to do ODT on writes and + * want functionality. + * 1. Are you going to use ODT? (Does your board not have + * additional termination circuitry for DQ, DQS, DQS_, + * DM, RDQS, RDQS_ for x4/x8 configs?) + * 2. If so, is your lowest supported CL going to be 3? + * 3. If so, then you must set AL=1 because + * + * WL >= 3 for ODT on writes + * RL = AL + CL + * WL = RL - 1 + * -> + * WL = AL + CL - 1 + * AL + CL - 1 >= 3 + * AL + CL >= 4 + * QED + * + * RL >= 3 for ODT on reads + * RL = AL + CL + * + * Since CL aren't usually less than 2, AL=0 is a minimum, + * so the WL-derived AL should be the -- FIXME? + * + * II. Because you are using auto-precharge globally and want to + * use additive latency (posted CAS) to get more bandwidth. + * 1. Are you going to use auto-precharge mode globally? + * + * Use addtivie latency and compute AL to be 1 cycle less than + * tRCD, i.e. the READ or WRITE command is in the cycle + * immediately following the ACTIVATE command.. + * + * III. Because you feel like it or want to do some sort of + * degraded-performance experiment. + * 1. Do you just want to use additive latency because you feel + * like it? + * + * Validation: AL is less than tRCD, and within the other + * read-to-precharge constraints. + */ + + additive_latency = 0; + +#if defined(CONFIG_SYS_FSL_DDR2) + if (lowest_good_caslat < 4) { + additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat) + ? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0; + if (mclk_to_picos(additive_latency) > trcd_ps) { + additive_latency = picos_to_mclk(trcd_ps); + debug("setting additive_latency to %u because it was " + " greater than tRCD_ps\n", additive_latency); + } + } + +#elif defined(CONFIG_SYS_FSL_DDR3) + /* + * The system will not use the global auto-precharge mode. + * However, it uses the page mode, so we set AL=0 + */ + additive_latency = 0; +#endif + + /* + * Validate additive latency + * FIXME: move to somewhere else to validate + * + * AL <= tRCD(min) + */ + if (mclk_to_picos(additive_latency) > trcd_ps) { + printf("Error: invalid additive latency exceeds tRCD(min).\n"); + return 1; + } + + /* + * RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled + * WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled + * ADD_LAT (the register) must be set to a value less + * than ACTTORW if WL = 1, then AL must be set to 1 + * RD_TO_PRE (the register) must be set to a minimum + * tRTP + AL if AL is nonzero + */ + + /* + * Additive latency will be applied only if the memctl option to + * use it. + */ + outpdimm->additive_latency = additive_latency; + + debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps); + debug("trcd_ps = %u\n", outpdimm->trcd_ps); + debug("trp_ps = %u\n", outpdimm->trp_ps); + debug("tras_ps = %u\n", outpdimm->tras_ps); + debug("twr_ps = %u\n", outpdimm->twr_ps); + debug("twtr_ps = %u\n", outpdimm->twtr_ps); + debug("trfc_ps = %u\n", outpdimm->trfc_ps); + debug("trrd_ps = %u\n", outpdimm->trrd_ps); + debug("trc_ps = %u\n", outpdimm->trc_ps); + + return 0; +} diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c new file mode 100644 index 0000000000..c1cdbdf955 --- /dev/null +++ b/drivers/ddr/fsl/main.c @@ -0,0 +1,718 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +/* + * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. + * Based on code from spd_sdram.c + * Author: James Yang [at freescale.com] + */ + +#include +#include +#include +#include + +#include + +void fsl_ddr_set_lawbar( + const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); +void fsl_ddr_set_intl3r(const unsigned int granule_size); + +#if defined(SPD_EEPROM_ADDRESS) || \ + defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ + defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) +#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS, +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ + [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ +}; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ + [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ + [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ +}; + +#endif + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret; + + i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); + + ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + if (i2c_address == +#ifdef SPD_EEPROM_ADDRESS + SPD_EEPROM_ADDRESS +#elif defined(SPD_EEPROM_ADDRESS1) + SPD_EEPROM_ADDRESS1 +#endif + ) { + printf("DDR: failed to read SPD from address %u\n", + i2c_address); + } else { + debug("DDR: failed to read SPD from address %u\n", + i2c_address); + } + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +__attribute__((weak, alias("__get_spd"))) +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); + +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + i2c_address = spd_i2c_addr[ctrl_num][i]; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} +#else +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ +} +#endif /* SPD_EEPROM_ADDRESSx */ + +/* + * ASSUMPTIONS: + * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller + * - Same memory data bus width on all controllers + * + * NOTES: + * + * The memory controller and associated documentation use confusing + * terminology when referring to the orgranization of DRAM. + * + * Here is a terminology translation table: + * + * memory controller/documention |industry |this code |signals + * -------------------------------|-----------|-----------|----------------- + * physical bank/bank |rank |rank |chip select (CS) + * logical bank/sub-bank |bank |bank |bank address (BA) + * page/row |row |page |row address + * ??? |column |column |column address + * + * The naming confusion is further exacerbated by the descriptions of the + * memory controller interleaving feature, where accesses are interleaved + * _BETWEEN_ two seperate memory controllers. This is configured only in + * CS0_CONFIG[INTLV_CTL] of each memory controller. + * + * memory controller documentation | number of chip selects + * | per memory controller supported + * --------------------------------|----------------------------------------- + * cache line interleaving | 1 (CS0 only) + * page interleaving | 1 (CS0 only) + * bank interleaving | 1 (CS0 only) + * superbank interleraving | depends on bank (chip select) + * | interleraving [rank interleaving] + * | mode used on every memory controller + * + * Even further confusing is the existence of the interleaving feature + * _WITHIN_ each memory controller. The feature is referred to in + * documentation as chip select interleaving or bank interleaving, + * although it is configured in the DDR_SDRAM_CFG field. + * + * Name of field | documentation name | this code + * -----------------------------|-----------------------|------------------ + * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving + * | interleaving + */ + +const char *step_string_tbl[] = { + "STEP_GET_SPD", + "STEP_COMPUTE_DIMM_PARMS", + "STEP_COMPUTE_COMMON_PARMS", + "STEP_GATHER_OPTS", + "STEP_ASSIGN_ADDRESSES", + "STEP_COMPUTE_REGS", + "STEP_PROGRAM_REGS", + "STEP_ALL" +}; + +const char * step_to_string(unsigned int step) { + + unsigned int s = __ilog2(step); + + if ((1 << s) != step) + return step_string_tbl[7]; + + return step_string_tbl[s]; +} + +static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]) +{ + int i, j; + unsigned long long total_mem, current_mem_base, total_ctlr_mem; + unsigned long long rank_density, ctlr_density = 0; + + /* + * If a reduced data width is requested, but the SPD + * specifies a physically wider device, adjust the + * computed dimm capacities accordingly before + * assigning addresses. + */ + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + unsigned int found = 0; + + switch (pinfo->memctl_opts[i].data_bus_width) { + case 2: + /* 16-bit */ + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int dw; + if (!pinfo->dimm_params[i][j].n_ranks) + continue; + dw = pinfo->dimm_params[i][j].primary_sdram_width; + if ((dw == 72 || dw == 64)) { + dbw_cap_adj[i] = 2; + break; + } else if ((dw == 40 || dw == 32)) { + dbw_cap_adj[i] = 1; + break; + } + } + break; + + case 1: + /* 32-bit */ + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int dw; + dw = pinfo->dimm_params[i][j].data_width; + if (pinfo->dimm_params[i][j].n_ranks + && (dw == 72 || dw == 64)) { + /* + * FIXME: can't really do it + * like this because this just + * further reduces the memory + */ + found = 1; + break; + } + } + if (found) { + dbw_cap_adj[i] = 1; + } + break; + + case 0: + /* 64-bit */ + break; + + default: + printf("unexpected data bus width " + "specified controller %u\n", i); + return 1; + } + debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); + } + + current_mem_base = 0ull; + total_mem = 0; + if (pinfo->memctl_opts[0].memctl_interleaving) { + rank_density = pinfo->dimm_params[0][0].rank_density >> + dbw_cap_adj[0]; + switch (pinfo->memctl_opts[0].ba_intlv_ctl & + FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: + ctlr_density = 4 * rank_density; + break; + case FSL_DDR_CS0_CS1: + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + ctlr_density = 2 * rank_density; + break; + case FSL_DDR_CS2_CS3: + default: + ctlr_density = rank_density; + break; + } + debug("rank density is 0x%llx, ctlr density is 0x%llx\n", + rank_density, ctlr_density); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (pinfo->memctl_opts[i].memctl_interleaving) { + switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + total_ctlr_mem = 2 * ctlr_density; + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + total_ctlr_mem = 3 * ctlr_density; + break; + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + total_ctlr_mem = 4 * ctlr_density; + break; + default: + panic("Unknown interleaving mode"); + } + pinfo->common_timing_params[i].base_address = + current_mem_base; + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem = current_mem_base + total_ctlr_mem; + debug("ctrl %d base 0x%llx\n", i, current_mem_base); + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + } else { + /* when 3rd controller not interleaved */ + current_mem_base = total_mem; + total_ctlr_mem = 0; + pinfo->common_timing_params[i].base_address = + current_mem_base; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned long long cap = + pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; + pinfo->dimm_params[i][j].base_address = + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; + } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem += total_ctlr_mem; + } + } + } else { + /* + * Simple linear assignment if memory + * controllers are not interleaved. + */ + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + total_ctlr_mem = 0; + pinfo->common_timing_params[i].base_address = + current_mem_base; + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + /* Compute DIMM base addresses. */ + unsigned long long cap = + pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; + pinfo->dimm_params[i][j].base_address = + current_mem_base; + debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); + current_mem_base += cap; + total_ctlr_mem += cap; + } + debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); + pinfo->common_timing_params[i].total_mem = + total_ctlr_mem; + total_mem += total_ctlr_mem; + } + } + debug("Total mem by %s is 0x%llx\n", __func__, total_mem); + + return total_mem; +} + +/* Use weak function to allow board file to override the address assignment */ +__attribute__((weak, alias("__step_assign_addresses"))) +unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, + unsigned int dbw_cap_adj[]); + +unsigned long long +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only) +{ + unsigned int i, j; + unsigned long long total_mem = 0; + int assert_reset; + + fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; + common_timing_params_t *timing_params = pinfo->common_timing_params; + assert_reset = board_need_mem_reset(); + + /* data bus width capacity adjust shift amount */ + unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + dbw_capacity_adjust[i] = 0; + } + + debug("starting at step %u (%s)\n", + start_step, step_to_string(start_step)); + + switch (start_step) { + case STEP_GET_SPD: +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) + /* STEP 1: Gather all DIMM SPD data */ + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); + } + + case STEP_COMPUTE_DIMM_PARMS: + /* STEP 2: Compute DIMM parameters from SPD data */ + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int retval; + generic_spd_eeprom_t *spd = + &(pinfo->spd_installed_dimms[i][j]); + dimm_params_t *pdimm = + &(pinfo->dimm_params[i][j]); + + retval = compute_dimm_parameters(spd, pdimm, i); +#ifdef CONFIG_SYS_DDR_RAW_TIMING + if (!i && !j && retval) { + printf("SPD error on controller %d! " + "Trying fallback to raw timing " + "calculation\n", i); + fsl_ddr_get_dimm_params(pdimm, i, j); + } +#else + if (retval == 2) { + printf("Error: compute_dimm_parameters" + " non-zero returned FATAL value " + "for memctl=%u dimm=%u\n", i, j); + return 0; + } +#endif + if (retval) { + debug("Warning: compute_dimm_parameters" + " non-zero return value for memctl=%u " + "dimm=%u\n", i, j); + } + } + } + +#elif defined(CONFIG_SYS_DDR_RAW_TIMING) + case STEP_COMPUTE_DIMM_PARMS: + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + dimm_params_t *pdimm = + &(pinfo->dimm_params[i][j]); + fsl_ddr_get_dimm_params(pdimm, i, j); + } + } + debug("Filling dimm parameters from board specific file\n"); +#endif + case STEP_COMPUTE_COMMON_PARMS: + /* + * STEP 3: Compute a common set of timing parameters + * suitable for all of the DIMMs on each memory controller + */ + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + debug("Computing lowest common DIMM" + " parameters for memctl=%u\n", i); + compute_lowest_common_dimm_parameters( + pinfo->dimm_params[i], + &timing_params[i], + CONFIG_DIMM_SLOTS_PER_CTLR); + } + + case STEP_GATHER_OPTS: + /* STEP 4: Gather configuration requirements from user */ + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + debug("Reloading memory controller " + "configuration options for memctl=%u\n", i); + /* + * This "reloads" the memory controller options + * to defaults. If the user "edits" an option, + * next_step points to the step after this, + * which is currently STEP_ASSIGN_ADDRESSES. + */ + populate_memctl_options( + timing_params[i].all_dimms_registered, + &pinfo->memctl_opts[i], + pinfo->dimm_params[i], i); + /* + * For RDIMMs, JEDEC spec requires clocks to be stable + * before reset signal is deasserted. For the boards + * using fixed parameters, this function should be + * be called from board init file. + */ + if (timing_params[i].all_dimms_registered) + assert_reset = 1; + } + if (assert_reset) { + debug("Asserting mem reset\n"); + board_assert_mem_reset(); + } + + case STEP_ASSIGN_ADDRESSES: + /* STEP 5: Assign addresses to chip selects */ + check_interleaving_options(pinfo); + total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); + + case STEP_COMPUTE_REGS: + /* STEP 6: compute controller register values */ + debug("FSL Memory ctrl register computation\n"); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (timing_params[i].ndimms_present == 0) { + memset(&ddr_reg[i], 0, + sizeof(fsl_ddr_cfg_regs_t)); + continue; + } + + compute_fsl_memctl_config_regs( + &pinfo->memctl_opts[i], + &ddr_reg[i], &timing_params[i], + pinfo->dimm_params[i], + dbw_capacity_adjust[i], + size_only); + } + + default: + break; + } + + { + /* + * Compute the amount of memory available just by + * looking for the highest valid CSn_BNDS value. + * This allows us to also experiment with using + * only CS0 when using dual-rank DIMMs. + */ + unsigned int max_end = 0; + + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { + fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; + if (reg->cs[j].config & 0x80000000) { + unsigned int end; + /* + * 0xfffffff is a special value we put + * for unused bnds + */ + if (reg->cs[j].bnds == 0xffffffff) + continue; + end = reg->cs[j].bnds & 0xffff; + if (end > max_end) { + max_end = end; + } + } + } + } + + total_mem = 1 + (((unsigned long long)max_end << 24ULL) + | 0xFFFFFFULL); + } + + return total_mem; +} + +/* + * fsl_ddr_sdram() -- this is the main function to be called by + * initdram() in the board file. + * + * It returns amount of memory configured in bytes. + */ +phys_size_t fsl_ddr_sdram(void) +{ + unsigned int i; + unsigned int law_memctl = LAW_TRGT_IF_DDR_1; + unsigned long long total_memory; + fsl_ddr_info_t info; + int deassert_reset; + + /* Reset info structure. */ + memset(&info, 0, sizeof(fsl_ddr_info_t)); + + /* Compute it once normally. */ +#ifdef CONFIG_FSL_DDR_INTERACTIVE + if (tstc() && (getc() == 'd')) { /* we got a key press of 'd' */ + total_memory = fsl_ddr_interactive(&info, 0); + } else if (fsl_ddr_interactive_env_var_exists()) { + total_memory = fsl_ddr_interactive(&info, 1); + } else +#endif + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); + + /* setup 3-way interleaving before enabling DDRC */ + if (info.memctl_opts[0].memctl_interleaving) { + switch (info.memctl_opts[0].memctl_interleaving_mode) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + fsl_ddr_set_intl3r( + info.memctl_opts[0].memctl_interleaving_mode); + break; + default: + break; + } + } + + /* + * Program configuration registers. + * JEDEC specs requires clocks to be stable before deasserting reset + * for RDIMMs. Clocks start after chip select is enabled and clock + * control register is set. During step 1, all controllers have their + * registers set but not enabled. Step 2 proceeds after deasserting + * reset through board FPGA or GPIO. + * For non-registered DIMMs, initialization can go through but it is + * also OK to follow the same flow. + */ + deassert_reset = board_need_mem_reset(); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (info.common_timing_params[i].all_dimms_registered) + deassert_reset = 1; + } + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + debug("Programming controller %u\n", i); + if (info.common_timing_params[i].ndimms_present == 0) { + debug("No dimms present on controller %u; " + "skipping programming\n", i); + continue; + } + /* + * The following call with step = 1 returns before enabling + * the controller. It has to finish with step = 2 later. + */ + fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, + deassert_reset ? 1 : 0); + } + if (deassert_reset) { + /* Use board FPGA or GPIO to deassert reset signal */ + debug("Deasserting mem reset\n"); + board_deassert_mem_reset(); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + /* Call with step = 2 to continue initialization */ + fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), + i, 2); + } + } + + /* program LAWs */ + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (info.memctl_opts[i].memctl_interleaving) { + switch (info.memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + if (i == 0) { + law_memctl = LAW_TRGT_IF_DDR_INTRLV; + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + } else if (i == 2) { + law_memctl = LAW_TRGT_IF_DDR_INTLV_34; + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + } + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + law_memctl = LAW_TRGT_IF_DDR_INTLV_123; + if (i == 0) { + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + } + break; + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; + if (i == 0) + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + /* place holder for future 4-way interleaving */ + break; + default: + break; + } + } else { + switch (i) { + case 0: + law_memctl = LAW_TRGT_IF_DDR_1; + break; + case 1: + law_memctl = LAW_TRGT_IF_DDR_2; + break; + case 2: + law_memctl = LAW_TRGT_IF_DDR_3; + break; + case 3: + law_memctl = LAW_TRGT_IF_DDR_4; + break; + default: + break; + } + fsl_ddr_set_lawbar(&info.common_timing_params[i], + law_memctl, i); + } + } + + debug("total_memory by %s = %llu\n", __func__, total_memory); + +#if !defined(CONFIG_PHYS_64BIT) + /* Check for 4G or more. Bad. */ + if (total_memory >= (1ull << 32)) { + puts("Detected "); + print_size(total_memory, " of memory\n"); + printf(" This U-Boot only supports < 4G of DDR\n"); + printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); + printf(" "); /* re-align to match init_func_ram print */ + total_memory = CONFIG_MAX_MEM_MAPPED; + } +#endif + + return total_memory; +} + +/* + * fsl_ddr_sdram_size() - This function only returns the size of the total + * memory without setting ddr control registers. + */ +phys_size_t +fsl_ddr_sdram_size(void) +{ + fsl_ddr_info_t info; + unsigned long long total_memory = 0; + + memset(&info, 0 , sizeof(fsl_ddr_info_t)); + + /* Compute it once normally. */ + total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); + + return total_memory; +} diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c new file mode 100644 index 0000000000..ff7d979d6a --- /dev/null +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -0,0 +1,89 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i; + volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + if (ctrl_num != 0) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + } + } + + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); +#if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541) + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); +#endif + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + + asm("sync;isync;msync"); + udelay(500); +} + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +/* + * Initialize all of memory for ECC, then enable errors. + */ + +void +ddr_enable_ecc(unsigned int dram_size) +{ + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); + + dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); + + /* + * Enable errors for ECC. + */ + debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); + ddr->err_disable = 0x00000000; + asm("sync;isync;msync"); + debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable); +} + +#endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */ diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c new file mode 100644 index 0000000000..c22dea5c24 --- /dev/null +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -0,0 +1,95 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i; + ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + +#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + uint svr; +#endif + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + +#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 + /* + * Set the DDR IO receiver to an acceptable bias point. + * Fixed in Rev 2.1. + */ + svr = get_svr(); + if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { + if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == + SDRAM_CFG_SDRAM_TYPE_DDR2) + out_be32(&gur->ddrioovcr, 0x90000000); + else + out_be32(&gur->ddrioovcr, 0xA8000000); + } +#endif + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + } + } + + out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); + out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + out_be32(&ddr->sdram_data_init, regs->ddr_data_init); + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while (in_be32(&ddr->sdram_cfg_2) & 0x10) { + udelay(10000); /* throttle polling rate */ + } +} diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c new file mode 100644 index 0000000000..7b4e8ec93d --- /dev/null +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -0,0 +1,464 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + + +/* + * regs has the to-be-set values for DDR controller registers + * ctrl_num is the DDR controller number + * step: 0 goes through the initialization in one pass + * 1 sets registers and returns before enabling controller + * 2 resumes from step 1 and continues to initialize + * Dividing the initialization to two steps to deassert DDR reset signal + * to comply with JEDEC specs for RDIMMs. + */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i, bus_width; + volatile ccsr_ddr_t *ddr; + u32 temp_sdram_cfg; + u32 total_gb_size_per_controller; + int timeout; +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + int timeout_save; + volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; + unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; + int csn = -1; +#endif + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + if (step == 2) + goto step2; + + if (regs->ddr_eor) + out_be32(&ddr->eor, regs->ddr_eor); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + debug("Workaround for ERRATUM_DDR111_DDR134\n"); + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + cs_sa = (regs->cs[i].bnds >> 16) & 0xfff; + cs_ea = regs->cs[i].bnds & 0xfff; + if ((cs_sa <= 0xff) && (cs_ea >= 0xff)) { + csn = i; + csn_bnds_backup = regs->cs[i].bnds; + csn_bnds_t = (unsigned int *) ®s->cs[i].bnds; + if (cs_ea > 0xeff) + *csn_bnds_t = regs->cs[i].bnds + 0x01000000; + else + *csn_bnds_t = regs->cs[i].bnds + 0x01000100; + debug("Found cs%d_bns (0x%08x) covering 0xff000000, " + "change it to 0x%x\n", + csn, csn_bnds_backup, regs->cs[i].bnds); + break; + } + } +#endif + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); + } + } + + out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); + out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + out_be32(&ddr->sdram_data_init, regs->ddr_data_init); + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); + out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + + if (regs->ddr_wrlvl_cntl_2) + out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + if (regs->ddr_wrlvl_cntl_3) + out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif + + out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + out_be32(&ddr->err_disable, regs->err_disable); + out_be32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) { + if (regs->debug[i]) { + debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); + out_be32(&ddr->debug[i], regs->debug[i]); + } + } +#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 + out_be32(&ddr->debug[28], 0x30003000); +#endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474 + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR_A003474 */ + + /* + * For RDIMMs, JEDEC spec requires clocks to be stable before reset is + * deasserted. Clocks start when any chip select is enabled and clock + * control register is set. Because all DDR components are connected to + * one reset signal, this needs to be done in two steps. Step 1 is to + * get the clocks started. Step 2 resumes after reset signal is + * deasserted. + */ + if (step == 1) { + udelay(200); + return; + } + +step2: + /* Set, but do not enable the memory */ + temp_sdram_cfg = regs->ddr_sdram_cfg; + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 + debug("Workaround for ERRATUM_DDR_A003\n"); + if (regs->ddr_sdram_rcw_2 & 0x00f00000) { + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); + out_be32(&ddr->debug[2], 0x00000400); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); + out_be32(&ddr->mtcr, 0); + out_be32(&ddr->debug[12], 0x00000015); + out_be32(&ddr->debug[21], 0x24000000); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); + + asm volatile("sync;isync"); + while (!(in_be32(&ddr->debug[1]) & 0x2)) + ; + + switch (regs->ddr_sdram_rcw_2 & 0x00f00000) { + case 0x00000000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); + break; + case 0x00100000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x0a)); + break; + case 0x00200000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x12)); + break; + case 0x00300000: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x1a)); + break; + default: + out_be32(&ddr->sdram_md_cntl, + MD_CNTL_MD_EN | + MD_CNTL_CS_SEL_CS0_CS1 | + 0x04000000 | + MD_CNTL_WRCW | + MD_CNTL_MD_VALUE(0x02)); + printf("Unsupported RC10\n"); + break; + } + + while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) + ; + udelay(6); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->debug[2], 0x0); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->debug[12], 0x0); + out_be32(&ddr->debug[21], 0x0); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + + } +#endif + /* + * For 8572 DDR1 erratum - DDR controller may enter illegal state + * when operatiing in 32-bit bus mode with 4-beat bursts, + * This erratum does not affect DDR3 mode, only for DDR2 mode. + */ +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 + debug("Workaround for ERRATUM_DDR_115\n"); + if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) + && in_be32(&ddr->sdram_cfg) & 0x80000) { + /* set DEBUG_1[31] */ + setbits_be32(&ddr->debug[0], 1); + } +#endif +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + debug("Workaround for ERRATUM_DDR111_DDR134\n"); + /* + * This is the combined workaround for DDR111 and DDR134 + * following the published errata for MPC8572 + */ + + /* 1. Set EEBACR[3] */ + setbits_be32(&ecm->eebacr, 0x10000000); + debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); + + /* 2. Set DINIT in SDRAM_CFG_2*/ + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); + debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", + in_be32(&ddr->sdram_cfg_2)); + + /* 3. Set DEBUG_3[21] */ + setbits_be32(&ddr->debug[2], 0x400); + debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); + +#endif /* part 1 of the workaound */ + + /* + * 500 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. + */ + udelay(500); + asm volatile("sync;isync"); + + /* Let the controller go */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("sync;isync"); + + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & 0x80000000)) + continue; + total_gb_size_per_controller += 1 << ( + ((regs->cs[i].config >> 14) & 0x3) + 2 + + ((regs->cs[i].config >> 8) & 0x7) + 12 + + ((regs->cs[i].config >> 0) & 0x7) + 8 + + 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - + 26); /* minus 26 (count of 64M) */ + } + if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */ + total_gb_size_per_controller *= 3; + else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */ + total_gb_size_per_controller <<= 1; + /* + * total memory / bus width = transactions needed + * transactions needed / data rate = seconds + * to add plenty of buffer, double the time + * For example, 2GB on 666MT/s 64-bit bus takes about 402ms + * Let's wait for 800ms + */ + bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) + >> SDRAM_CFG_DBW_SHIFT); + timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / + (get_ddr_freq(0) >> 20)) << 1; +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + timeout_save = timeout; +#endif + total_gb_size_per_controller >>= 4; /* shift down to gb size */ + debug("total %d GB\n", total_gb_size_per_controller); + debug("Need to wait up to %d * 10ms\n", timeout); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); + +#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 + /* continue this workaround */ + + /* 4. Clear DEBUG3[21] */ + clrbits_be32(&ddr->debug[2], 0x400); + debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); + + /* DDR134 workaround starts */ + /* A: Clear sdram_cfg_2[odt_cfg] */ + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); + debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", + in_be32(&ddr->sdram_cfg_2)); + + /* B: Set DEBUG1[15] */ + setbits_be32(&ddr->debug[0], 0x10000); + debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); + + /* C: Set timing_cfg_2[cpo] to 0b11111 */ + setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); + debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", + in_be32(&ddr->timing_cfg_2)); + + /* D: Set D6 to 0x9f9f9f9f */ + out_be32(&ddr->debug[5], 0x9f9f9f9f); + debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); + + /* E: Set D7 to 0x9f9f9f9f */ + out_be32(&ddr->debug[6], 0x9f9f9f9f); + debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); + + /* F: Set D2[20] */ + setbits_be32(&ddr->debug[1], 0x800); + debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); + + /* G: Poll on D2[20] until cleared */ + while (in_be32(&ddr->debug[1]) & 0x800) + udelay(10000); /* throttle polling rate */ + + /* H: Clear D1[15] */ + clrbits_be32(&ddr->debug[0], 0x10000); + debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); + + /* I: Set sdram_cfg_2[odt_cfg] */ + setbits_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK); + debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); + + /* Continuing with the DDR111 workaround */ + /* 5. Set D2[21] */ + setbits_be32(&ddr->debug[1], 0x400); + debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); + + /* 6. Poll D2[21] until its cleared */ + while (in_be32(&ddr->debug[1]) & 0x400) + udelay(10000); /* throttle polling rate */ + + /* 7. Wait for state machine 2nd run, roughly 400ms/GB */ + debug("Wait for %d * 10ms\n", timeout_save); + udelay(timeout_save * 10000); + + /* 8. Set sdram_cfg_2[dinit] if options requires */ + setbits_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT); + debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); + + /* 9. Poll until dinit is cleared */ + timeout = timeout_save; + debug("Need to wait up to %d * 10ms\n", timeout); + while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); + + /* 10. Clear EEBACR[3] */ + clrbits_be32(&ecm->eebacr, 10000000); + debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); + + if (csn != -1) { + csn_bnds_t = (unsigned int *) ®s->cs[csn].bnds; + *csn_bnds_t = csn_bnds_backup; + debug("Change cs%d_bnds back to 0x%08x\n", + csn, regs->cs[csn].bnds); + setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ + switch (csn) { + case 0: + out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); + break; + case 1: + out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); + break; + case 2: + out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); + break; + case 3: + out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); + break; + } + clrbits_be32(&ddr->sdram_cfg, 0x2); + } +#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ +} diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c new file mode 100644 index 0000000000..caffbaf019 --- /dev/null +++ b/drivers/ddr/fsl/mpc86xx_ddr.c @@ -0,0 +1,85 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i; + volatile ccsr_ddr_t *ddr; + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; + default: + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + } + } + + out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); + out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + out_be32(&ddr->sdram_data_init, regs->ddr_data_init); + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + debug("before go\n"); + + /* + * 200 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + */ + udelay(200); + asm volatile("sync;isync"); + + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); + + /* + * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done + */ + while (in_be32(&ddr->sdram_cfg_2) & 0x10) { + udelay(10000); /* throttle polling rate */ + } +} diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c new file mode 100644 index 0000000000..4aafcceaf5 --- /dev/null +++ b/drivers/ddr/fsl/options.c @@ -0,0 +1,1147 @@ +/* + * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include + +/* + * Use our own stack based buffer before relocation to allow accessing longer + * hwconfig strings that might be in the environment before we've relocated. + * This is pretty fragile on both the use of stack and if the buffer is big + * enough. However we will get a warning from getenv_f for the later. + */ + +/* Board-specific functions defined in each board's ddr.c */ +extern void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num); + +struct dynamic_odt { + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; +}; + +#ifdef CONFIG_SYS_FSL_DDR3 +static const struct dynamic_odt single_Q[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, /* tied high */ + DDR3_RTT_OFF, + DDR3_RTT_120_OHM + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS_AND_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, /* tied high */ + DDR3_RTT_OFF, + DDR3_RTT_120_OHM + } +}; + +static const struct dynamic_odt single_D[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt single_S[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, +}; + +static const struct dynamic_odt dual_DD[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + } +}; + +static const struct dynamic_odt dual_DS[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_30_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0} +}; +static const struct dynamic_odt dual_SD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_20_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR3_RTT_20_OHM, + DDR3_RTT_OFF + } +}; + +static const struct dynamic_odt dual_SS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_30_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_ALL, + DDR3_RTT_30_OHM, + DDR3_RTT_120_OHM + }, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_D0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_0D[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_SAME_DIMM, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR3_RTT_OFF, + DDR3_RTT_OFF + } +}; + +static const struct dynamic_odt dual_S0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt dual_0S[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_40_OHM, + DDR3_RTT_OFF + }, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt odt_unknown[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR3_RTT_120_OHM, + DDR3_RTT_OFF + } +}; +#else /* CONFIG_SYS_FSL_DDR3 */ +static const struct dynamic_odt single_Q[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt single_D[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt single_S[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0}, +}; + +static const struct dynamic_odt dual_DD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; + +static const struct dynamic_odt dual_DS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_SD[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; + +static const struct dynamic_odt dual_SS[4] = { + { /* cs0 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_OTHER_DIMM, + FSL_DDR_ODT_OTHER_DIMM, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_D0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0} +}; + +static const struct dynamic_odt dual_0D[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_ALL, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; + +static const struct dynamic_odt dual_S0[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt dual_0S[4] = { + {0, 0, 0, 0}, + {0, 0, 0, 0}, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_150_OHM, + DDR2_RTT_OFF + }, + {0, 0, 0, 0} + +}; + +static const struct dynamic_odt odt_unknown[4] = { + { /* cs0 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs1 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + }, + { /* cs2 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_CS, + DDR2_RTT_75_OHM, + DDR2_RTT_OFF + }, + { /* cs3 */ + FSL_DDR_ODT_NEVER, + FSL_DDR_ODT_NEVER, + DDR2_RTT_OFF, + DDR2_RTT_OFF + } +}; +#endif + +/* + * Automatically seleect bank interleaving mode based on DIMMs + * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null. + * This function only deal with one or two slots per controller. + */ +static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) +{ +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks == 4) + return FSL_DDR_CS0_CS1_CS2_CS3; + else if (pdimm[0].n_ranks == 2) + return FSL_DDR_CS0_CS1; +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (pdimm[0].n_ranks == 4) + return FSL_DDR_CS0_CS1_CS2_CS3; +#endif + if (pdimm[0].n_ranks == 2) { + if (pdimm[1].n_ranks == 2) + return FSL_DDR_CS0_CS1_CS2_CS3; + else + return FSL_DDR_CS0_CS1; + } +#endif + return 0; +} + +unsigned int populate_memctl_options(int all_dimms_registered, + memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + unsigned int i; + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2) + const struct dynamic_odt *pdodt = odt_unknown; +#endif + ulong ddr_freq; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; + +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2) + /* Chip select options. */ + if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { + switch (pdimm[0].n_ranks) { + case 1: + pdodt = single_S; + break; + case 2: + pdodt = single_D; + break; + case 4: + pdodt = single_Q; + break; + } + } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { + switch (pdimm[0].n_ranks) { +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + case 4: + pdodt = single_Q; + if (pdimm[1].n_ranks) + printf("Error: Quad- and Dual-rank DIMMs " + "cannot be used together\n"); + break; +#endif + case 2: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_DD; + break; + case 1: + pdodt = dual_DS; + break; + case 0: + pdodt = dual_D0; + break; + } + break; + case 1: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_SD; + break; + case 1: + pdodt = dual_SS; + break; + case 0: + pdodt = dual_S0; + break; + } + break; + case 0: + switch (pdimm[1].n_ranks) { + case 2: + pdodt = dual_0D; + break; + case 1: + pdodt = dual_0S; + break; + } + break; + } + } +#endif + + /* Pick chip-select local options. */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { +#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2) + popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; + popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; + popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; + popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; +#else + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; +#endif + popts->cs_local_opts[i].auto_precharge = 0; + } + + /* Pick interleaving mode. */ + + /* + * 0 = no interleaving + * 1 = interleaving between 2 controllers + */ + popts->memctl_interleaving = 0; + + /* + * 0 = cacheline + * 1 = page + * 2 = (logical) bank + * 3 = superbank (only if CS interleaving is enabled) + */ + popts->memctl_interleaving_mode = 0; + + /* + * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl + * 1: page: bit to the left of the column bits selects the memctl + * 2: bank: bit to the left of the bank bits selects the memctl + * 3: superbank: bit to the left of the chip select selects the memctl + * + * NOTE: ba_intlv (rank interleaving) is independent of memory + * controller interleaving; it is only within a memory controller. + * Must use superbank interleaving if rank interleaving is used and + * memory controller interleaving is enabled. + */ + + /* + * 0 = no + * 0x40 = CS0,CS1 + * 0x20 = CS2,CS3 + * 0x60 = CS0,CS1 + CS2,CS3 + * 0x04 = CS0,CS1,CS2,CS3 + */ + popts->ba_intlv_ctl = 0; + + /* Memory Organization Parameters */ + popts->registered_dimm_en = all_dimms_registered; + + /* Operational Mode Paramters */ + + /* Pick ECC modes */ + popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ +#ifdef CONFIG_DDR_ECC + if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) + popts->ecc_mode = 1; + } else + popts->ecc_mode = 1; +#endif + popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ + + /* + * Choose DQS config + * 0 for DDR1 + * 1 for DDR2 + */ +#if defined(CONFIG_SYS_FSL_DDR1) + popts->dqs_config = 0; +#elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) + popts->dqs_config = 1; +#endif + + /* Choose self-refresh during sleep. */ + popts->self_refresh_in_sleep = 1; + + /* Choose dynamic power management mode. */ + popts->dynamic_power = 0; + + /* + * check first dimm for primary sdram width + * presuming all dimms are similar + * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit + */ +#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) + if (pdimm[0].n_ranks != 0) { + if ((pdimm[0].data_width >= 64) && \ + (pdimm[0].data_width <= 72)) + popts->data_bus_width = 0; + else if ((pdimm[0].data_width >= 32) || \ + (pdimm[0].data_width <= 40)) + popts->data_bus_width = 1; + else { + panic("Error: data width %u is invalid!\n", + pdimm[0].data_width); + } + } +#else + if (pdimm[0].n_ranks != 0) { + if (pdimm[0].primary_sdram_width == 64) + popts->data_bus_width = 0; + else if (pdimm[0].primary_sdram_width == 32) + popts->data_bus_width = 1; + else if (pdimm[0].primary_sdram_width == 16) + popts->data_bus_width = 2; + else { + panic("Error: primary sdram width %u is invalid!\n", + pdimm[0].primary_sdram_width); + } + } +#endif + + popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; + + /* Choose burst length. */ +#if defined(CONFIG_SYS_FSL_DDR3) +#if defined(CONFIG_E500MC) + popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ + popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ +#else + if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { + /* 32-bit or 16-bit bus */ + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + } else { + popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ + popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ + } +#endif +#else + popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ +#endif + + /* Choose ddr controller address mirror mode */ +#if defined(CONFIG_SYS_FSL_DDR3) + popts->mirrored_dimm = pdimm[0].mirrored_dimm; +#endif + + /* Global Timing Parameters. */ + debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); + + /* Pick a caslat override. */ + popts->cas_latency_override = 0; + popts->cas_latency_override_value = 3; + if (popts->cas_latency_override) { + debug("using caslat override value = %u\n", + popts->cas_latency_override_value); + } + + /* Decide whether to use the computed derated latency */ + popts->use_derated_caslat = 0; + + /* Choose an additive latency. */ + popts->additive_latency_override = 0; + popts->additive_latency_override_value = 3; + if (popts->additive_latency_override) { + debug("using additive latency override value = %u\n", + popts->additive_latency_override_value); + } + + /* + * 2T_EN setting + * + * Factors to consider for 2T_EN: + * - number of DIMMs installed + * - number of components, number of active ranks + * - how much time you want to spend playing around + */ + popts->twot_en = 0; + popts->threet_en = 0; + + /* for RDIMM, address parity enable */ + popts->ap_en = 1; + + /* + * BSTTOPRE precharge interval + * + * Set this to 0 for global auto precharge + * + * FIXME: Should this be configured in picoseconds? + * Why it should be in ps: better understanding of this + * relative to actual DRAM timing parameters such as tRAS. + * e.g. tRAS(min) = 40 ns + */ + popts->bstopre = 0x100; + + /* Minimum CKE pulse width -- tCKE(MIN) */ + popts->tcke_clock_pulse_width_ps + = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); + + /* + * Window for four activates -- tFAW + * + * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only + * FIXME: varies depending upon number of column addresses or data + * FIXME: width, was considering looking at pdimm->primary_sdram_width + */ +#if defined(CONFIG_SYS_FSL_DDR1) + popts->tfaw_window_four_activates_ps = mclk_to_picos(1); + +#elif defined(CONFIG_SYS_FSL_DDR2) + /* + * x4/x8; some datasheets have 35000 + * x16 wide columns only? Use 50000? + */ + popts->tfaw_window_four_activates_ps = 37500; + +#elif defined(CONFIG_SYS_FSL_DDR3) + popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; +#endif + popts->zq_en = 0; + popts->wrlvl_en = 0; +#if defined(CONFIG_SYS_FSL_DDR3) + /* + * due to ddr3 dimm is fly-by topology + * we suggest to enable write leveling to + * meet the tQDSS under different loading. + */ + popts->wrlvl_en = 1; + popts->zq_en = 1; + popts->wrlvl_override = 0; +#endif + + /* + * Check interleaving configuration from environment. + * Please refer to doc/README.fsl-ddr for the detail. + * + * If memory controller interleaving is enabled, then the data + * bus widths must be programmed identically for all memory controllers. + * + * XXX: Attempt to set all controllers to the same chip select + * interleaving mode. It will do a best effort to get the + * requested ranks interleaved together such that the result + * should be a subset of the requested configuration. + */ +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) + goto done; + + if (pdimm[0].n_ranks == 0) { + printf("There is no rank on CS0 for controller %d.\n", ctrl_num); + popts->memctl_interleaving = 0; + goto done; + } + popts->memctl_interleaving = 1; + /* + * test null first. if CONFIG_HWCONFIG is not defined + * hwconfig_arg_cmp returns non-zero + */ + if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", + "null", buf)) { + popts->memctl_interleaving = 0; + debug("memory controller interleaving disabled.\n"); + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "cacheline", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "page", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_PAGE_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "bank", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_BANK_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "superbank", buf)) { + popts->memctl_interleaving_mode = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : FSL_DDR_SUPERBANK_INTERLEAVING; + popts->memctl_interleaving = + ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? + 0 : 1; +#if (CONFIG_NUM_DDR_CONTROLLERS == 3) + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "3way_1KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_3WAY_1KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "3way_4KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_3WAY_4KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "3way_8KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_3WAY_8KB_INTERLEAVING; +#elif (CONFIG_NUM_DDR_CONTROLLERS == 4) + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "4way_1KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_4WAY_1KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "4way_4KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_4WAY_4KB_INTERLEAVING; + } else if (hwconfig_subarg_cmp_f("fsl_ddr", + "ctlr_intlv", + "4way_8KB", buf)) { + popts->memctl_interleaving_mode = + FSL_DDR_4WAY_8KB_INTERLEAVING; +#endif + } else { + popts->memctl_interleaving = 0; + printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); + } +done: +#endif + if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && + (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { + /* test null first. if CONFIG_HWCONFIG is not defined, + * hwconfig_subarg_cmp_f returns non-zero */ + if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "null", buf)) + debug("bank interleaving disabled.\n"); + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1", buf)) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs2_cs3", buf)) + popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1_and_cs2_cs3", buf)) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "cs0_cs1_cs2_cs3", buf)) + popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", + "auto", buf)) + popts->ba_intlv_ctl = auto_bank_intlv(pdimm); + else + printf("hwconfig has unrecognized parameter for bank_intlv.\n"); + switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { + case FSL_DDR_CS0_CS1_CS2_CS3: +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks < 4) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for " + "CS0+CS1+CS2+CS3 on controller %d, " + "interleaving disabled!\n", ctrl_num); + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + if (pdimm[0].n_ranks == 4) + break; +#endif + if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for " + "CS0+CS1+CS2+CS3 on controller %d, " + "interleaving disabled!\n", ctrl_num); + } + if (pdimm[0].capacity != pdimm[1].capacity) { + popts->ba_intlv_ctl = 0; + printf("Not identical DIMM size for " + "CS0+CS1+CS2+CS3 on controller %d, " + "interleaving disabled!\n", ctrl_num); + } +#endif + break; + case FSL_DDR_CS0_CS1: + if (pdimm[0].n_ranks < 2) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for " + "CS0+CS1 on controller %d, " + "interleaving disabled!\n", ctrl_num); + } + break; + case FSL_DDR_CS2_CS3: +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks < 4) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for CS2+CS3 " + "on controller %d, interleaving disabled!\n", ctrl_num); + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if (pdimm[1].n_ranks < 2) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(chip-select) for CS2+CS3 " + "on controller %d, interleaving disabled!\n", ctrl_num); + } +#endif + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: +#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) + if (pdimm[0].n_ranks < 4) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(CS) for CS0+CS1 and " + "CS2+CS3 on controller %d, " + "interleaving disabled!\n", ctrl_num); + } +#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) + if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { + popts->ba_intlv_ctl = 0; + printf("Not enough bank(CS) for CS0+CS1 and " + "CS2+CS3 on controller %d, " + "interleaving disabled!\n", ctrl_num); + } +#endif + break; + default: + popts->ba_intlv_ctl = 0; + break; + } + } + + if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) + popts->addr_hash = 0; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", + "true", buf)) + popts->addr_hash = 1; + } + + if (pdimm[0].n_ranks == 4) + popts->quad_rank_present = 1; + + ddr_freq = get_ddr_freq(0) / 1000000; + if (popts->registered_dimm_en) { + popts->rcw_override = 1; + popts->rcw_1 = 0x000a5a00; + if (ddr_freq <= 800) + popts->rcw_2 = 0x00000000; + else if (ddr_freq <= 1066) + popts->rcw_2 = 0x00100000; + else if (ddr_freq <= 1333) + popts->rcw_2 = 0x00200000; + else + popts->rcw_2 = 0x00300000; + } + + fsl_ddr_board_options(popts, pdimm, ctrl_num); + + return 0; +} + +void check_interleaving_options(fsl_ddr_info_t *pinfo) +{ + int i, j, k, check_n_ranks, intlv_invalid = 0; + unsigned int check_intlv, check_n_row_addr, check_n_col_addr; + unsigned long long check_rank_density; + struct dimm_params_s *dimm; + /* + * Check if all controllers are configured for memory + * controller interleaving. Identical dimms are recommended. At least + * the size, row and col address should be checked. + */ + j = 0; + check_n_ranks = pinfo->dimm_params[0][0].n_ranks; + check_rank_density = pinfo->dimm_params[0][0].rank_density; + check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr; + check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr; + check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode; + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + dimm = &pinfo->dimm_params[i][0]; + if (!pinfo->memctl_opts[i].memctl_interleaving) { + continue; + } else if (((check_rank_density != dimm->rank_density) || + (check_n_ranks != dimm->n_ranks) || + (check_n_row_addr != dimm->n_row_addr) || + (check_n_col_addr != dimm->n_col_addr) || + (check_intlv != + pinfo->memctl_opts[i].memctl_interleaving_mode))){ + intlv_invalid = 1; + break; + } else { + j++; + } + + } + if (intlv_invalid) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + pinfo->memctl_opts[i].memctl_interleaving = 0; + printf("Not all DIMMs are identical. " + "Memory controller interleaving disabled.\n"); + } else { + switch (check_intlv) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + case FSL_DDR_PAGE_INTERLEAVING: + case FSL_DDR_BANK_INTERLEAVING: + case FSL_DDR_SUPERBANK_INTERLEAVING: + if (3 == CONFIG_NUM_DDR_CONTROLLERS) + k = 2; + else + k = CONFIG_NUM_DDR_CONTROLLERS; + break; + case FSL_DDR_3WAY_1KB_INTERLEAVING: + case FSL_DDR_3WAY_4KB_INTERLEAVING: + case FSL_DDR_3WAY_8KB_INTERLEAVING: + case FSL_DDR_4WAY_1KB_INTERLEAVING: + case FSL_DDR_4WAY_4KB_INTERLEAVING: + case FSL_DDR_4WAY_8KB_INTERLEAVING: + default: + k = CONFIG_NUM_DDR_CONTROLLERS; + break; + } + debug("%d of %d controllers are interleaving.\n", j, k); + if (j && (j != k)) { + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) + pinfo->memctl_opts[i].memctl_interleaving = 0; + printf("Not all controllers have compatible " + "interleaving mode. All disabled.\n"); + } + } + debug("Checking interleaving options completed\n"); +} + +int fsl_use_spd(void) +{ + int use_spd = 0; + +#ifdef CONFIG_DDR_SPD + char buffer[HWCONFIG_BUFFER_SIZE]; + char *buf = NULL; + + /* + * Extract hwconfig from environment since we have not properly setup + * the environment but need it for ddr config params + */ + if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + buf = buffer; + + /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ + if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf)) + use_spd = 1; + else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", + "fixed", buf)) + use_spd = 0; + else + use_spd = 1; + } else + use_spd = 1; +#endif + + return use_spd; +} diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c new file mode 100644 index 0000000000..45a7bcc080 --- /dev/null +++ b/drivers/ddr/fsl/util.c @@ -0,0 +1,265 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include +#include + +#include +#include + +/* To avoid 64-bit full-divides, we factor this here */ +#define ULL_2E12 2000000000000ULL +#define UL_5POW12 244140625UL +#define UL_2POW13 (1UL << 13) + +#define ULL_8FS 0xFFFFFFFFULL + +/* + * Round up mclk_ps to nearest 1 ps in memory controller code + * if the error is 0.5ps or more. + * + * If an imprecise data rate is too high due to rounding error + * propagation, compute a suitably rounded mclk_ps to compute + * a working memory controller configuration. + */ +unsigned int get_memory_clk_period_ps(void) +{ + unsigned int data_rate = get_ddr_freq(0); + unsigned int result; + + /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ + unsigned long long rem, mclk_ps = ULL_2E12; + + /* Now perform the big divide, the result fits in 32-bits */ + rem = do_div(mclk_ps, data_rate); + result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps; + + return result; +} + +/* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ +unsigned int picos_to_mclk(unsigned int picos) +{ + unsigned long long clks, clks_rem; + unsigned long data_rate = get_ddr_freq(0); + + /* Short circuit for zero picos */ + if (!picos) + return 0; + + /* First multiply the time by the data rate (32x32 => 64) */ + clks = picos * (unsigned long long)data_rate; + /* + * Now divide by 5^12 and track the 32-bit remainder, then divide + * by 2*(2^12) using shifts (and updating the remainder). + */ + clks_rem = do_div(clks, UL_5POW12); + clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12; + clks >>= 13; + + /* If we had a remainder greater than the 1ps error, then round up */ + if (clks_rem > data_rate) + clks++; + + /* Clamp to the maximum representable value */ + if (clks > ULL_8FS) + clks = ULL_8FS; + return (unsigned int) clks; +} + +unsigned int mclk_to_picos(unsigned int mclk) +{ + return get_memory_clk_period_ps() * mclk; +} + +void +__fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, + unsigned int law_memctl, + unsigned int ctrl_num) +{ + unsigned long long base = memctl_common_params->base_address; + unsigned long long size = memctl_common_params->total_mem; + + /* + * If no DIMMs on this controller, do not proceed any further. + */ + if (!memctl_common_params->ndimms_present) { + return; + } + +#if !defined(CONFIG_PHYS_64BIT) + if (base >= CONFIG_MAX_MEM_MAPPED) + return; + if ((base + size) >= CONFIG_MAX_MEM_MAPPED) + size = CONFIG_MAX_MEM_MAPPED - base; +#endif + if (set_ddr_laws(base, size, law_memctl) < 0) { + printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, + law_memctl); + return ; + } + debug("setup ddr law base = 0x%llx, size 0x%llx, TRGT_ID 0x%x\n", + base, size, law_memctl); +} + +__attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void +fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); + +void fsl_ddr_set_intl3r(const unsigned int granule_size) +{ +#ifdef CONFIG_E6500 + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); + *mcintl3r = 0x80000000 | (granule_size & 0x1f); + debug("Enable MCINTL3R with granule size 0x%x\n", granule_size); +#endif +} + +u32 fsl_ddr_get_intl3r(void) +{ + u32 val = 0; +#ifdef CONFIG_E6500 + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); + val = *mcintl3r; +#endif + return val; +} + +void board_add_ram_info(int use_default) +{ + ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); + +#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) + u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS > 1) + uint32_t cs0_config = in_be32(&ddr->cs0_config); +#endif + uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); + int cas_lat; + +#if CONFIG_NUM_DDR_CONTROLLERS >= 2 + if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { + ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; + sdram_cfg = in_be32(&ddr->sdram_cfg); + } +#endif +#if CONFIG_NUM_DDR_CONTROLLERS >= 3 + if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { + ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; + sdram_cfg = in_be32(&ddr->sdram_cfg); + } +#endif + puts(" (DDR"); + switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> + SDRAM_CFG_SDRAM_TYPE_SHIFT) { + case SDRAM_TYPE_DDR1: + puts("1"); + break; + case SDRAM_TYPE_DDR2: + puts("2"); + break; + case SDRAM_TYPE_DDR3: + puts("3"); + break; + default: + puts("?"); + break; + } + + if (sdram_cfg & SDRAM_CFG_32_BE) + puts(", 32-bit"); + else if (sdram_cfg & SDRAM_CFG_16_BE) + puts(", 16-bit"); + else + puts(", 64-bit"); + + /* Calculate CAS latency based on timing cfg values */ + cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; + if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) + cas_lat += (8 << 1); + printf(", CL=%d", cas_lat >> 1); + if (cas_lat & 0x1) + puts(".5"); + + if (sdram_cfg & SDRAM_CFG_ECC_EN) + puts(", ECC on)"); + else + puts(", ECC off)"); + +#if (CONFIG_NUM_DDR_CONTROLLERS == 3) +#ifdef CONFIG_E6500 + if (*mcintl3r & 0x80000000) { + puts("\n"); + puts(" DDR Controller Interleaving Mode: "); + switch (*mcintl3r & 0x1f) { + case FSL_DDR_3WAY_1KB_INTERLEAVING: + puts("3-way 1KB"); + break; + case FSL_DDR_3WAY_4KB_INTERLEAVING: + puts("3-way 4KB"); + break; + case FSL_DDR_3WAY_8KB_INTERLEAVING: + puts("3-way 8KB"); + break; + default: + puts("3-way UNKNOWN"); + break; + } + } +#endif +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS >= 2) + if (cs0_config & 0x20000000) { + puts("\n"); + puts(" DDR Controller Interleaving Mode: "); + + switch ((cs0_config >> 24) & 0xf) { + case FSL_DDR_CACHE_LINE_INTERLEAVING: + puts("cache line"); + break; + case FSL_DDR_PAGE_INTERLEAVING: + puts("page"); + break; + case FSL_DDR_BANK_INTERLEAVING: + puts("bank"); + break; + case FSL_DDR_SUPERBANK_INTERLEAVING: + puts("super-bank"); + break; + default: + puts("invalid"); + break; + } + } +#endif + + if ((sdram_cfg >> 8) & 0x7f) { + puts("\n"); + puts(" DDR Chip-Select Interleaving Mode: "); + switch(sdram_cfg >> 8 & 0x7f) { + case FSL_DDR_CS0_CS1_CS2_CS3: + puts("CS0+CS1+CS2+CS3"); + break; + case FSL_DDR_CS0_CS1: + puts("CS0+CS1"); + break; + case FSL_DDR_CS2_CS3: + puts("CS2+CS3"); + break; + case FSL_DDR_CS0_CS1_AND_CS2_CS3: + puts("CS0+CS1 and CS2+CS3"); + break; + default: + puts("invalid"); + break; + } + } +} diff --git a/include/common_timing_params.h b/include/common_timing_params.h new file mode 100644 index 0000000000..76338d4e6c --- /dev/null +++ b/include/common_timing_params.h @@ -0,0 +1,57 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef COMMON_TIMING_PARAMS_H +#define COMMON_TIMING_PARAMS_H + +typedef struct { + /* parameters to constrict */ + + unsigned int tckmin_x_ps; + unsigned int tckmax_ps; + unsigned int tckmax_max_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; + + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + unsigned int extended_op_srt; + + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ + + unsigned int ndimms_present; + unsigned int lowest_common_SPD_caslat; + unsigned int highest_common_derated_caslat; + unsigned int additive_latency; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + unsigned int all_dimms_ecc_capable; + + unsigned long long total_mem; + unsigned long long base_address; + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +} common_timing_params_t; + +#endif diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 268f66ec0e..b2a5c19e0e 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -193,7 +193,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 036f264c97..499d8c2054 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -80,7 +80,7 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_SYS_DDR_RAW_TIMING #undef CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 75889b3574..a6601fee86 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -134,7 +134,7 @@ #define CONFIG_SYS_MEMTEST_END 0x01ffffff /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 08156c531d..f173b07b4d 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -103,7 +103,7 @@ #define CONFIG_PANIC_HANG /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x50 diff --git a/include/configs/HWW1U1A.h b/include/configs/HWW1U1A.h index f3f2136668..bbfee7d308 100644 --- a/include/configs/HWW1U1A.h +++ b/include/configs/HWW1U1A.h @@ -255,7 +255,7 @@ /* -------------------------------------------------------------------- */ /* FreeScale DDR2/3 SDRAM Controller */ -#define CONFIG_FSL_DDR2 /* Our SDRAM slot is DDR2 */ +#define CONFIG_SYS_FSL_DDR2 /* Our SDRAM slot is DDR2 */ #define CONFIG_DDR_ECC /* Enable ECC by default */ #define CONFIG_DDR_SPD /* Detect DDR config from SPD EEPROM */ #define CONFIG_SPD_EEPROM /* ...why 2 config variables for this? */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3f742a2bba..a80a6966bf 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -62,11 +62,11 @@ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ /* - * define CONFIG_FSL_DDR2 to use unified DDR driver + * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver * undefine it to use old spd_sdram.c */ -#define CONFIG_FSL_DDR2 -#ifdef CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 +#ifdef CONFIG_SYS_FSL_DDR2 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS1 0x52 #define SPD_EEPROM_ADDRESS2 0x51 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 8197f89e4e..9ab1bc106b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -122,7 +122,7 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 66893688e6..046b14bdda 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -78,7 +78,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index e24c597453..eca3b537b4 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -51,7 +51,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 2e76df681b..8132ec055b 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -63,7 +63,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 9ff048af6d..6acd54db85 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -75,7 +75,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 7f0f927ea1..5ffdd01629 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -51,7 +51,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index b7c4a60309..bb9ae2dcb5 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -75,7 +75,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index c9a15395c3..7406ac3be8 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -60,7 +60,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 341f6a89b4..df5572b3a8 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -98,7 +98,7 @@ extern unsigned long get_clock_freq(void); #endif /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c7511449ea..afb195fe4e 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -106,7 +106,7 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 97f5c877e1..41ebe31dd4 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -92,7 +92,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ #define CONFIG_DDR_SPD diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 8ed5050766..0e666bac01 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -108,7 +108,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* * DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 50c365a5b1..eab386add4 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -178,7 +178,7 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 1470526d0b..262c3e5f1f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -177,7 +177,7 @@ /* DDR Setup */ #define CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index e49523e940..7de6814a03 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -74,7 +74,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 282f5c1a12..b592c1966a 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -141,7 +141,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index 9cc219e5a8..15d2a43cd0 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -105,7 +105,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 8a29eaa507..9d3d9b33e5 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -109,9 +109,9 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM #ifdef CONFIG_DDR2 -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #else -#define CONFIG_FSL_DDR3 1 +#define CONFIG_SYS_FSL_DDR3 1 #endif /* ECC will be enabled based on perf_mode environment variable */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0df6f1a2d9..b238574b5d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -175,7 +175,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 7c6bec8f76..43a5778004 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -170,7 +170,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/T1040RDB.h b/include/configs/T1040RDB.h index 620387fcd0..79312311d8 100644 --- a/include/configs/T1040RDB.h +++ b/include/configs/T1040RDB.h @@ -156,7 +156,7 @@ #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/T1042RDB_PI.h b/include/configs/T1042RDB_PI.h index 4b023f9e84..eff08e3804 100644 --- a/include/configs/T1042RDB_PI.h +++ b/include/configs/T1042RDB_PI.h @@ -156,7 +156,7 @@ #define CONFIG_DDR_SPD #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h index 413f0867f4..46d4f9865f 100644 --- a/include/configs/controlcenterd.h +++ b/include/configs/controlcenterd.h @@ -138,7 +138,7 @@ #define CONFIG_SYS_SDRAM_SIZE 1024 #define CONFIG_VERY_BIG_RAM -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 562caa5845..665295c1a2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -173,7 +173,7 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 2d5320b5cd..7700b38c2d 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -111,7 +111,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h index 6d0d392b77..ec09e15dbf 100644 --- a/include/configs/mpq101.h +++ b/include/configs/mpq101.h @@ -52,7 +52,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 91a678212d..57ed019952 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -325,7 +325,7 @@ #endif /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 76189e136f..9837100e31 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -89,7 +89,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M #define CONFIG_CHIP_SELECTS_PER_CTRL 1 diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 6d970608f2..bdb8eb529d 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -102,7 +102,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_DDR_ECC /* only for ECC DDR module */ /* diff --git a/include/configs/socrates.h b/include/configs/socrates.h index b6fbe23706..0e6b86412d 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -80,7 +80,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 9b3f0cc69f..ee1f1f3ed0 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 805814f4fb..63dd767047 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -112,7 +112,7 @@ #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_FSL_DDR1 +#define CONFIG_SYS_FSL_DDR1 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 3f54f1423e..d9b0ed07d6 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -87,7 +87,7 @@ #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE #define CONFIG_DDR_SPD -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 /* diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index 4738c23350..88d7f88cc0 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -40,7 +40,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index 33428803eb..f39d6f9105 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -39,7 +39,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 9da845d9a2..e1bdf90de4 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -49,7 +49,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR2 +#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index 4137cc9208..2328c7a62e 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -49,7 +49,7 @@ /* * DDR config */ -#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h new file mode 100644 index 0000000000..e03f9db5f2 --- /dev/null +++ b/include/fsl_ddr.h @@ -0,0 +1,105 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef FSL_DDR_MAIN_H +#define FSL_DDR_MAIN_H + +#include +#include + +#include + +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) +/* + * Bind the main DDR setup driver's generic names + * to this specific DDR technology. + */ +static __inline__ int +compute_dimm_parameters(const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) +{ + return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); +} +#endif + +/* + * Data Structures + * + * All data structures have to be on the stack + */ +#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR + +typedef struct { + generic_spd_eeprom_t + spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + struct dimm_params_s + dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; + memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; + common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; + fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; +} fsl_ddr_info_t; + +/* Compute steps */ +#define STEP_GET_SPD (1 << 0) +#define STEP_COMPUTE_DIMM_PARMS (1 << 1) +#define STEP_COMPUTE_COMMON_PARMS (1 << 2) +#define STEP_GATHER_OPTS (1 << 3) +#define STEP_ASSIGN_ADDRESSES (1 << 4) +#define STEP_COMPUTE_REGS (1 << 5) +#define STEP_PROGRAM_REGS (1 << 6) +#define STEP_ALL 0xFFF + +unsigned long long +fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, + unsigned int size_only); + +const char *step_to_string(unsigned int step); + +unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm, + const dimm_params_t *dimm_parameters, + unsigned int dbw_capacity_adjust, + unsigned int size_only); +unsigned int compute_lowest_common_dimm_parameters( + const dimm_params_t *dimm_params, + common_timing_params_t *outpdimm, + unsigned int number_of_dimms); +unsigned int populate_memctl_options(int all_dimms_registered, + memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num); +void check_interleaving_options(fsl_ddr_info_t *pinfo); + +unsigned int mclk_to_picos(unsigned int mclk); +unsigned int get_memory_clk_period_ps(void); +unsigned int picos_to_mclk(unsigned int picos); +void fsl_ddr_set_lawbar( + const common_timing_params_t *memctl_common_params, + unsigned int memctl_interleaved, + unsigned int ctrl_num); + +int fsl_ddr_interactive_env_var_exists(void); +unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num); + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); + +/* processor specific function */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); + +/* board specific function */ +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number); +#endif diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h new file mode 100644 index 0000000000..99a72bc6e1 --- /dev/null +++ b/include/fsl_ddr_dimm_params.h @@ -0,0 +1,101 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef DDR2_DIMM_PARAMS_H +#define DDR2_DIMM_PARAMS_H + +#define EDC_DATA_PARITY 1 +#define EDC_ECC 2 +#define EDC_AC_PARITY 4 + +/* Parameters for a DDR2 dimm computed from the SPD */ +typedef struct dimm_params_s { + + /* DIMM organization parameters */ + char mpart[19]; /* guaranteed null terminated */ + + unsigned int n_ranks; + unsigned long long rank_density; + unsigned long long capacity; + unsigned int data_width; + unsigned int primary_sdram_width; + unsigned int ec_sdram_width; + unsigned int registered_dimm; + unsigned int device_width; /* x4, x8, x16 components */ + + /* SDRAM device parameters */ + unsigned int n_row_addr; + unsigned int n_col_addr; + unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ + unsigned int n_banks_per_sdram_device; + unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ + unsigned int row_density; + + /* used in computing base address of DIMMs */ + unsigned long long base_address; + /* mirrored DIMMs */ + unsigned int mirrored_dimm; /* only for ddr3 */ + + /* DIMM timing parameters */ + + unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ + unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ + unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ + unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ + + /* + * SDRAM clock periods + * The range for these are 1000-10000 so a short should be sufficient + */ + unsigned int tckmin_x_ps; + unsigned int tckmin_x_minus_1_ps; + unsigned int tckmin_x_minus_2_ps; + unsigned int tckmax_ps; + + /* SPD-defined CAS latencies */ + unsigned int caslat_x; + unsigned int caslat_x_minus_1; + unsigned int caslat_x_minus_2; + + unsigned int caslat_lowest_derated; /* Derated CAS latency */ + + /* basic timing parameters */ + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; + + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns + = 511750 ps */ + + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + + unsigned int refresh_rate_ps; + unsigned int extended_op_srt; + + /* DDR3 doesn't need these as below */ + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ + + /* DDR3 RDIMM */ + unsigned char rcw[16]; /* Register Control Word 0-15 */ +} dimm_params_t; + +extern unsigned int ddr_compute_dimm_parameters( + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number); + +#endif diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h new file mode 100644 index 0000000000..16cccc7708 --- /dev/null +++ b/include/fsl_ddr_sdram.h @@ -0,0 +1,377 @@ +/* + * Copyright 2008-2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#ifndef FSL_DDR_MEMCTL_H +#define FSL_DDR_MEMCTL_H + +/* + * Pick a basic DDR Technology. + */ +#include + +#define SDRAM_TYPE_DDR1 2 +#define SDRAM_TYPE_DDR2 3 +#define SDRAM_TYPE_LPDDR1 6 +#define SDRAM_TYPE_DDR3 7 + +#define DDR_BL4 4 /* burst length 4 */ +#define DDR_BC4 DDR_BL4 /* burst chop for ddr3 */ +#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ +#define DDR_BL8 8 /* burst length 8 */ + +#define DDR3_RTT_OFF 0 +#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */ +#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */ +#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */ +#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */ +#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */ + +#define DDR2_RTT_OFF 0 +#define DDR2_RTT_75_OHM 1 +#define DDR2_RTT_150_OHM 2 +#define DDR2_RTT_50_OHM 3 + +#if defined(CONFIG_SYS_FSL_DDR1) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1) +typedef ddr1_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR1 +#endif +#elif defined(CONFIG_SYS_FSL_DDR2) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) +typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR2 +#endif +#elif defined(CONFIG_SYS_FSL_DDR3) +#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ +typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 +#endif +#endif /* #if defined(CONFIG_SYS_FSL_DDR1) */ + +#define FSL_DDR_ODT_NEVER 0x0 +#define FSL_DDR_ODT_CS 0x1 +#define FSL_DDR_ODT_ALL_OTHER_CS 0x2 +#define FSL_DDR_ODT_OTHER_DIMM 0x3 +#define FSL_DDR_ODT_ALL 0x4 +#define FSL_DDR_ODT_SAME_DIMM 0x5 +#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6 +#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 + +/* define bank(chip select) interleaving mode */ +#define FSL_DDR_CS0_CS1 0x40 +#define FSL_DDR_CS2_CS3 0x20 +#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3) +#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04) + +/* define memory controller interleaving mode */ +#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0 +#define FSL_DDR_PAGE_INTERLEAVING 0x1 +#define FSL_DDR_BANK_INTERLEAVING 0x2 +#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA +#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC +#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD +/* placeholder for 4-way interleaving */ +#define FSL_DDR_4WAY_1KB_INTERLEAVING 0x1A +#define FSL_DDR_4WAY_4KB_INTERLEAVING 0x1C +#define FSL_DDR_4WAY_8KB_INTERLEAVING 0x1D + +#define SDRAM_CS_CONFIG_EN 0x80000000 + +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_SHIFT 19 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_16_BE 0x00100000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_BI 0x00000001 + +#define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 +#define SDRAM_CFG2_ODT_NEVER 0 +#define SDRAM_CFG2_ODT_ONLY_WRITE 1 +#define SDRAM_CFG2_ODT_ONLY_READ 2 +#define SDRAM_CFG2_ODT_ALWAYS 3 + +#define TIMING_CFG_2_CPO_MASK 0x0F800000 + +#if defined(CONFIG_P4080) +#define RD_TO_PRE_MASK 0xf +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0xf +#define WR_DATA_DELAY_SHIFT 9 +#else +#define RD_TO_PRE_MASK 0x7 +#define RD_TO_PRE_SHIFT 13 +#define WR_DATA_DELAY_MASK 0x7 +#define WR_DATA_DELAY_SHIFT 10 +#endif + +/* DDR_MD_CNTL */ +#define MD_CNTL_MD_EN 0x80000000 +#define MD_CNTL_CS_SEL_CS0 0x00000000 +#define MD_CNTL_CS_SEL_CS1 0x10000000 +#define MD_CNTL_CS_SEL_CS2 0x20000000 +#define MD_CNTL_CS_SEL_CS3 0x30000000 +#define MD_CNTL_CS_SEL_CS0_CS1 0x40000000 +#define MD_CNTL_CS_SEL_CS2_CS3 0x50000000 +#define MD_CNTL_MD_SEL_MR 0x00000000 +#define MD_CNTL_MD_SEL_EMR 0x01000000 +#define MD_CNTL_MD_SEL_EMR2 0x02000000 +#define MD_CNTL_MD_SEL_EMR3 0x03000000 +#define MD_CNTL_SET_REF 0x00800000 +#define MD_CNTL_SET_PRE 0x00400000 +#define MD_CNTL_CKE_CNTL_LOW 0x00100000 +#define MD_CNTL_CKE_CNTL_HIGH 0x00200000 +#define MD_CNTL_WRCW 0x00080000 +#define MD_CNTL_MD_VALUE(x) (x & 0x0000FFFF) + +/* DDR_CDR1 */ +#define DDR_CDR1_DHC_EN 0x80000000 +#define DDR_CDR1_ODT_SHIFT 17 +#define DDR_CDR1_ODT_MASK 0x6 +#define DDR_CDR2_ODT_MASK 0x1 +#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) +#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) + +#if (defined(CONFIG_SYS_FSL_DDR_VER) && \ + (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) +#define DDR_CDR_ODT_OFF 0x0 +#define DDR_CDR_ODT_120ohm 0x1 +#define DDR_CDR_ODT_180ohm 0x2 +#define DDR_CDR_ODT_75ohm 0x3 +#define DDR_CDR_ODT_110ohm 0x4 +#define DDR_CDR_ODT_60hm 0x5 +#define DDR_CDR_ODT_70ohm 0x6 +#define DDR_CDR_ODT_47ohm 0x7 +#else +#define DDR_CDR_ODT_75ohm 0x0 +#define DDR_CDR_ODT_55ohm 0x1 +#define DDR_CDR_ODT_60ohm 0x2 +#define DDR_CDR_ODT_50ohm 0x3 +#define DDR_CDR_ODT_150ohm 0x4 +#define DDR_CDR_ODT_43ohm 0x5 +#define DDR_CDR_ODT_120ohm 0x6 +#endif + +/* Record of register values computed */ +typedef struct fsl_ddr_cfg_regs_s { + struct { + unsigned int bnds; + unsigned int config; + unsigned int config_2; + } cs[CONFIG_CHIP_SELECTS_PER_CTRL]; + unsigned int timing_cfg_3; + unsigned int timing_cfg_0; + unsigned int timing_cfg_1; + unsigned int timing_cfg_2; + unsigned int ddr_sdram_cfg; + unsigned int ddr_sdram_cfg_2; + unsigned int ddr_sdram_mode; + unsigned int ddr_sdram_mode_2; + unsigned int ddr_sdram_mode_3; + unsigned int ddr_sdram_mode_4; + unsigned int ddr_sdram_mode_5; + unsigned int ddr_sdram_mode_6; + unsigned int ddr_sdram_mode_7; + unsigned int ddr_sdram_mode_8; + unsigned int ddr_sdram_md_cntl; + unsigned int ddr_sdram_interval; + unsigned int ddr_data_init; + unsigned int ddr_sdram_clk_cntl; + unsigned int ddr_init_addr; + unsigned int ddr_init_ext_addr; + unsigned int timing_cfg_4; + unsigned int timing_cfg_5; + unsigned int ddr_zq_cntl; + unsigned int ddr_wrlvl_cntl; + unsigned int ddr_wrlvl_cntl_2; + unsigned int ddr_wrlvl_cntl_3; + unsigned int ddr_sr_cntr; + unsigned int ddr_sdram_rcw_1; + unsigned int ddr_sdram_rcw_2; + unsigned int ddr_eor; + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + unsigned int err_disable; + unsigned int err_int_en; + unsigned int debug[32]; +} fsl_ddr_cfg_regs_t; + +typedef struct memctl_options_partial_s { + unsigned int all_dimms_ecc_capable; + unsigned int all_dimms_tckmax_ps; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; + /* unsigned int lowest_common_SPD_caslat; */ + unsigned int all_dimms_minimum_trcd_ps; +} memctl_options_partial_t; + +#define DDR_DATA_BUS_WIDTH_64 0 +#define DDR_DATA_BUS_WIDTH_32 1 +#define DDR_DATA_BUS_WIDTH_16 2 +/* + * Generalized parameters for memory controller configuration, + * might be a little specific to the FSL memory controller + */ +typedef struct memctl_options_s { + /* + * Memory organization parameters + * + * if DIMM is present in the system + * where DIMMs are with respect to chip select + * where chip selects are with respect to memory boundaries + */ + unsigned int registered_dimm_en; /* use registered DIMM support */ + + /* Options local to a Chip Select */ + struct cs_local_opts_s { + unsigned int auto_precharge; + unsigned int odt_rd_cfg; + unsigned int odt_wr_cfg; + unsigned int odt_rtt_norm; + unsigned int odt_rtt_wr; + } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; + + /* Special configurations for chip select */ + unsigned int memctl_interleaving; + unsigned int memctl_interleaving_mode; + unsigned int ba_intlv_ctl; + unsigned int addr_hash; + + /* Operational mode parameters */ + unsigned int ecc_mode; /* Use ECC? */ + /* Initialize ECC using memory controller? */ + unsigned int ecc_init_using_memctl; + unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ + /* SREN - self-refresh during sleep */ + unsigned int self_refresh_in_sleep; + unsigned int dynamic_power; /* DYN_PWR */ + /* memory data width to use (16-bit, 32-bit, 64-bit) */ + unsigned int data_bus_width; + unsigned int burst_length; /* BL4, OTF and BL8 */ + /* On-The-Fly Burst Chop enable */ + unsigned int otf_burst_chop_en; + /* mirrior DIMMs for DDR3 */ + unsigned int mirrored_dimm; + unsigned int quad_rank_present; + unsigned int ap_en; /* address parity enable for RDIMM */ + unsigned int x4_en; /* enable x4 devices */ + + /* Global Timing Parameters */ + unsigned int cas_latency_override; + unsigned int cas_latency_override_value; + unsigned int use_derated_caslat; + unsigned int additive_latency_override; + unsigned int additive_latency_override_value; + + unsigned int clk_adjust; /* */ + unsigned int cpo_override; + unsigned int write_data_delay; /* DQS adjust */ + + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int wrlvl_ctl_2; + unsigned int wrlvl_ctl_3; + + unsigned int half_strength_driver_enable; + unsigned int twot_en; + unsigned int threet_en; + unsigned int bstopre; + unsigned int tcke_clock_pulse_width_ps; /* tCKE */ + unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Rtt impedance */ + unsigned int rtt_override; /* rtt_override enable */ + unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; + /* ZQ calibration */ + unsigned int zq_en; + /* Write leveling */ + unsigned int wrlvl_en; + /* RCW override for RDIMM */ + unsigned int rcw_override; + unsigned int rcw_1; + unsigned int rcw_2; + /* control register 1 */ + unsigned int ddr_cdr1; + unsigned int ddr_cdr2; + + unsigned int trwt_override; + unsigned int trwt; /* read-to-write turnaround */ +} memctl_options_t; + +extern phys_size_t fsl_ddr_sdram(void); +extern phys_size_t fsl_ddr_sdram_size(void); +extern int fsl_use_spd(void); +extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step); +u32 fsl_ddr_get_intl3r(void); + +static void __board_assert_mem_reset(void) +{ +} + +static void __board_deassert_mem_reset(void) +{ +} + +void board_assert_mem_reset(void) + __attribute__((weak, alias("__board_assert_mem_reset"))); + +void board_deassert_mem_reset(void) + __attribute__((weak, alias("__board_deassert_mem_reset"))); + +static int __board_need_mem_reset(void) +{ + return 0; +} + +int board_need_mem_reset(void) + __attribute__((weak, alias("__board_need_mem_reset"))); + +/* + * The 85xx boards have a common prototype for fixed_sdram so put the + * declaration here. + */ +#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + + +typedef struct fixed_ddr_parm{ + int min_freq; + int max_freq; + fsl_ddr_cfg_regs_t *ddr_settings; +} fixed_ddr_parm_t; +#endif diff --git a/nand_spl/board/freescale/mpc8569mds/nand_boot.c b/nand_spl/board/freescale/mpc8569mds/nand_boot.c index 716b737ad2..ce7f6191ca 100644 --- a/nand_spl/board/freescale/mpc8569mds/nand_boot.c +++ b/nand_spl/board/freescale/mpc8569mds/nand_boot.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #define SYSCLK_66 66666666 diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 94680004f7..58e6cbf289 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -18,7 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); diff --git a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c index 3244c8f6d9..f7e8438438 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1_p2_rdb/nand_boot.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #define SYSCLK_MASK 0x00200000 diff --git a/spl/Makefile b/spl/Makefile index 29d7818df5..2a787afa4f 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -70,6 +70,7 @@ LIBS-$(CONFIG_SPL_LIBDISK_SUPPORT) += disk/ LIBS-$(CONFIG_SPL_I2C_SUPPORT) += drivers/i2c/ LIBS-$(CONFIG_SPL_GPIO_SUPPORT) += drivers/gpio/ LIBS-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/ +LIBS-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/ LIBS-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/ LIBS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/ LIBS-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/ -- cgit v1.2.1 From 9a17eb5b7e7ba528c278a9677c38d7ae722d93ec Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 18 Nov 2013 10:29:32 -0800 Subject: Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc83xx/ecc.c | 4 +- arch/powerpc/cpu/mpc85xx/cpu.c | 4 +- arch/powerpc/include/asm/immap_83xx.h | 106 ++---------------------- arch/powerpc/include/asm/immap_85xx.h | 100 +---------------------- arch/powerpc/include/asm/immap_86xx.h | 74 +---------------- board/exmeritus/hww1u1a/hww1u1a.c | 3 +- board/freescale/bsc9131rdb/spl_minimal.c | 3 +- board/freescale/bsc9132qds/bsc9132qds.c | 14 ++-- board/freescale/bsc9132qds/spl_minimal.c | 3 +- board/freescale/mpc8536ds/mpc8536ds.c | 2 +- board/freescale/mpc8540ads/mpc8540ads.c | 3 +- board/freescale/mpc8569mds/mpc8569mds.c | 3 +- board/freescale/mpc8572ds/mpc8572ds.c | 2 +- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 2 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 3 +- board/freescale/p1023rds/p1023rds.c | 3 +- board/freescale/p2020ds/p2020ds.c | 3 +- board/sbc8548/ddr.c | 3 +- board/sbc8641d/sbc8641d.c | 6 +- board/socrates/sdram.c | 3 +- drivers/ddr/fsl/ctrl_regs.c | 3 +- drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 6 +- drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 3 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/ddr/fsl/mpc86xx_ddr.c | 4 +- drivers/ddr/fsl/util.c | 4 +- include/fsl_immap.h | 112 ++++++++++++++++++++++++++ nand_spl/board/freescale/p1023rds/nand_boot.c | 3 +- 29 files changed, 175 insertions(+), 308 deletions(-) create mode 100644 include/fsl_immap.h diff --git a/arch/powerpc/cpu/mpc83xx/ecc.c b/arch/powerpc/cpu/mpc83xx/ecc.c index 6b7f72aa7d..985a024425 100644 --- a/arch/powerpc/cpu/mpc83xx/ecc.c +++ b/arch/powerpc/cpu/mpc83xx/ecc.c @@ -16,7 +16,7 @@ void ecc_print_status(void) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #ifdef CONFIG_SYS_FSL_DDR2 - ccsr_ddr_t *ddr = &immap->ddr; + struct ccsr_ddr __iomem *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; #endif @@ -100,7 +100,7 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #ifdef CONFIG_SYS_FSL_DDR2 - ccsr_ddr_t *ddr = &immap->ddr; + struct ccsr_ddr __iomem *ddr = &immap->ddr; #else ddr83xx_t *ddr = &immap->ddr; #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 552acc6879..b5a0242e10 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -416,7 +416,7 @@ static void dump_spd_ddr_reg(void) int i, j, k, m; u8 *p_8; u32 *p_32; - ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS]; + struct ccsr_ddr __iomem *ddr[CONFIG_NUM_DDR_CONTROLLERS]; generic_spd_eeprom_t spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR]; @@ -482,7 +482,7 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); puts("\n"); - for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) { + for (k = 0; k < sizeof(struct ccsr_ddr)/4; k++) { m = 0; printf("%6d (0x%04x)", k * 4, k * 4); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 1042b0c308..251840255b 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -14,6 +14,7 @@ #ifndef __IMMAP_83xx__ #define __IMMAP_83xx__ +#include #include #include #include @@ -277,107 +278,10 @@ typedef struct qesba83xx { } qesba83xx_t; /* - * DDR Memory Controller Memory Map + * DDR Memory Controller Memory Map for DDR1 + * The structure of DDR2, or DDR3 is defined in fsl_immap.h */ -#if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) -typedef struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u8 res1[4]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u8 res2[4]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u8 res3[4]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u8 res4[100]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u8 res4a[48]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u8 res5[48]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u8 res6[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res7[20]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u8 res8_1[16]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg8_1a[8]; - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u8 reg8_1aa[4]; - u32 ddr_sr_cntr; /* self refresh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 reg_1ab[8]; - u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ - u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u8 res8_1b[104]; - u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ - u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ - u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ - u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ - u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ - u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u8 res8_1ba[0x908]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u8 res8_1c[200]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u32 eor; /* Enhanced Optimization Register */ - u8 res8_2[252]; - u32 mtcr; /* Memory Test Control Register */ - u8 res8_3[28]; - u32 mtp1; /* Memory Test Pattern 1 */ - u32 mtp2; /* Memory Test Pattern 2 */ - u32 mtp3; /* Memory Test Pattern 3 */ - u32 mtp4; /* Memory Test Pattern 4 */ - u32 mtp5; /* Memory Test Pattern 5 */ - u32 mtp6; /* Memory Test Pattern 6 */ - u32 mtp7; /* Memory Test Pattern 7 */ - u32 mtp8; /* Memory Test Pattern 8 */ - u32 mtp9; /* Memory Test Pattern 9 */ - u32 mtp10; /* Memory Test Pattern 10 */ - u8 res8_4[184]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u8 res9[20]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u8 res10[20]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u8 res11[164]; - u32 debug[32]; /* debug_1 to debug_32 */ - u8 res12[128]; -} ccsr_ddr_t; -#else +#if !defined(CONFIG_SYS_FSL_DDR2) && !defined(CONFIG_SYS_FSL_DDR3) typedef struct ddr_cs_bnds { u32 csbnds; u8 res0[4]; @@ -740,7 +644,7 @@ typedef struct immap { u8 dll_lbc[0x100]; u8 res1[0xE00]; #if defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) - ccsr_ddr_t ddr; /* DDR Memory Controller Memory */ + struct ccsr_ddr ddr; /* DDR Memory Controller Memory */ #else ddr83xx_t ddr; /* DDR Memory Controller Memory */ #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index d479216850..80817dcbc4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -18,6 +18,7 @@ #include #include #include +#include typedef struct ccsr_local { u32 ccsrbarh; /* CCSR Base Addr High */ @@ -112,105 +113,6 @@ typedef struct ccsr_local_ecm { u8 res24[492]; } ccsr_local_ecm_t; -/* DDR memory controller registers */ -typedef struct ccsr_ddr { - u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ - u8 res1[4]; - u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ - u8 res2[4]; - u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ - u8 res3[4]; - u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ - u8 res4[100]; - u32 cs0_config; /* Chip Select Configuration */ - u32 cs1_config; /* Chip Select Configuration */ - u32 cs2_config; /* Chip Select Configuration */ - u32 cs3_config; /* Chip Select Configuration */ - u8 res4a[48]; - u32 cs0_config_2; /* Chip Select Configuration 2 */ - u32 cs1_config_2; /* Chip Select Configuration 2 */ - u32 cs2_config_2; /* Chip Select Configuration 2 */ - u32 cs3_config_2; /* Chip Select Configuration 2 */ - u8 res5[48]; - u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ - u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ - u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ - u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ - u32 sdram_cfg; /* SDRAM Control Configuration */ - u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ - u32 sdram_mode; /* SDRAM Mode Configuration */ - u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ - u32 sdram_md_cntl; /* SDRAM Mode Control */ - u32 sdram_interval; /* SDRAM Interval Configuration */ - u32 sdram_data_init; /* SDRAM Data initialization */ - u8 res6[4]; - u32 sdram_clk_cntl; /* SDRAM Clock Control */ - u8 res7[20]; - u32 init_addr; /* training init addr */ - u32 init_ext_addr; /* training init extended addr */ - u8 res8_1[16]; - u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ - u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ - u8 reg8_1a[8]; - u32 ddr_zq_cntl; /* ZQ calibration control*/ - u32 ddr_wrlvl_cntl; /* write leveling control*/ - u8 reg8_1aa[4]; - u32 ddr_sr_cntr; /* self refresh counter */ - u32 ddr_sdram_rcw_1; /* Control Words 1 */ - u32 ddr_sdram_rcw_2; /* Control Words 2 */ - u8 reg_1ab[8]; - u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ - u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ - u8 res8_1b[104]; - u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ - u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ - u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ - u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ - u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ - u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ - u8 res8_1ba[0x908]; - u32 ddr_dsr1; /* Debug Status 1 */ - u32 ddr_dsr2; /* Debug Status 2 */ - u32 ddr_cdr1; /* Control Driver 1 */ - u32 ddr_cdr2; /* Control Driver 2 */ - u8 res8_1c[200]; - u32 ip_rev1; /* IP Block Revision 1 */ - u32 ip_rev2; /* IP Block Revision 2 */ - u32 eor; /* Enhanced Optimization Register */ - u8 res8_2[252]; - u32 mtcr; /* Memory Test Control Register */ - u8 res8_3[28]; - u32 mtp1; /* Memory Test Pattern 1 */ - u32 mtp2; /* Memory Test Pattern 2 */ - u32 mtp3; /* Memory Test Pattern 3 */ - u32 mtp4; /* Memory Test Pattern 4 */ - u32 mtp5; /* Memory Test Pattern 5 */ - u32 mtp6; /* Memory Test Pattern 6 */ - u32 mtp7; /* Memory Test Pattern 7 */ - u32 mtp8; /* Memory Test Pattern 8 */ - u32 mtp9; /* Memory Test Pattern 9 */ - u32 mtp10; /* Memory Test Pattern 10 */ - u8 res8_4[184]; - u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ - u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ - u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ - u8 res9[20]; - u32 capture_data_hi; /* Data Path Read Capture High */ - u32 capture_data_lo; /* Data Path Read Capture Low */ - u32 capture_ecc; /* Data Path Read Capture ECC */ - u8 res10[20]; - u32 err_detect; /* Error Detect */ - u32 err_disable; /* Error Disable */ - u32 err_int_en; - u32 capture_attributes; /* Error Attrs Capture */ - u32 capture_address; /* Error Addr Capture */ - u32 capture_ext_address; /* Error Extended Addr Capture */ - u32 err_sbe; /* Single-Bit ECC Error Management */ - u8 res11[164]; - u32 debug[32]; /* debug_1 to debug_32 */ - u8 res12[128]; -} ccsr_ddr_t; - #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 046a434719..177918b7f9 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -10,6 +10,7 @@ #ifndef __IMMAP_86xx__ #define __IMMAP_86xx__ +#include #include #include #include @@ -89,75 +90,6 @@ typedef struct ccsr_local_mcm { char res31[488]; } ccsr_local_mcm_t; -/* DDR memory controller registers(0x2000-0x3000) and (0x6000-0x7000) */ - -typedef struct ccsr_ddr { - uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ - char res1[4]; - uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ - char res2[4]; - uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ - char res3[4]; - uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ - char res4[4]; - uint cs4_bnds; /* 0x2020 - DDR Chip Select 4 Memory Bounds */ - char res5[4]; - uint cs5_bnds; /* 0x2028 - DDR Chip Select 5 Memory Bounds */ - char res6[84]; - uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ - uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ - uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ - uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - uint cs4_config; /* 0x2090 - DDR Chip Select Configuration */ - uint cs5_config; /* 0x2094 - DDR Chip Select Configuration */ - char res7[104]; - uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ - uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ - uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ - uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration 1 */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration 1 */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2 */ - uint sdram_mode_cntl; /* 0x2120 - DDR SDRAM Mode Control */ - uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data Initialization */ - char res8[4]; - uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res9[12]; - uint sdram_ocd_cntl; /* 0x2140 - DDR SDRAM OCD Control */ - uint sdram_ocd_status; /* 0x2144 - DDR SDRAM OCD Status */ - uint init_addr; /* 0x2148 - DDR training initialzation address */ - uint init_ext_addr; /* 0x214C - DDR training initialzation extended address */ - char res10[2728]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ - char res11[512]; - uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ - uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ - uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ - char res12[20]; - uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ - uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ - uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ - char res13[20]; - uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ - uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ - uint err_int_en; /* 0x2e48 - DDR Memory Error Interrupt Enable */ - uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ - uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ - uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ - char res14[164]; - uint debug_1; /* 0x2f00 */ - uint debug_2; - uint debug_3; - uint debug_4; - uint debug_5; - char res15[236]; -} ccsr_ddr_t; - - /* Daul I2C Registers(0x3000-0x4000) */ typedef struct ccsr_i2c { struct fsl_i2c i2c[2]; @@ -1225,11 +1157,11 @@ typedef struct ccsr_wdt { typedef struct immap { ccsr_local_mcm_t im_local_mcm; - ccsr_ddr_t im_ddr1; + struct ccsr_ddr im_ddr1; ccsr_i2c_t im_i2c; ccsr_duart_t im_duart; fsl_lbc_t im_lbc; - ccsr_ddr_t im_ddr2; + struct ccsr_ddr im_ddr2; char res1[4096]; ccsr_pex_t im_pex1; ccsr_pex_t im_pex2; diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c index 104987a9b6..97b84b3224 100644 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ b/board/exmeritus/hww1u1a/hww1u1a.c @@ -37,6 +37,7 @@ int checkboard(void) unsigned int gpio_low = 0; unsigned int gpio_in = 0; unsigned int i; + struct ccsr_ddr __iomem *ddr; puts("Board: HWW-1U-1A "); @@ -89,7 +90,7 @@ int checkboard(void) * and delay a while before we continue. */ if (mpc85xx_gpio_get(GPIO_RESETS)) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; puts("Debugger detected... extra device reset enabled!\n"); diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c index 974627163a..bd8560b555 100644 --- a/board/freescale/bsc9131rdb/spl_minimal.c +++ b/board/freescale/bsc9131rdb/spl_minimal.c @@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; */ static void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index 31bbf62ee5..c1ebcf88e3 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -133,16 +133,16 @@ void dsp_ddr_configure(void) *copy the ddr controller settings from PowerPC side DDR controller *to the DSP DDR controller as connected DDR memories are similar. */ - ccsr_ddr_t __iomem *pa_ddr = - (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DDR_ADDR; - ccsr_ddr_t temp_ddr; - ccsr_ddr_t __iomem *dsp_ddr = - (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; + struct ccsr_ddr __iomem *pa_ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr temp_ddr; + struct ccsr_ddr __iomem *dsp_ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR; - memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t)); + memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr)); temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS; temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN; - memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t)); + memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr)); dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN; } diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c index 0249dc587f..8f71431926 100644 --- a/board/freescale/bsc9132qds/spl_minimal.c +++ b/board/freescale/bsc9132qds/spl_minimal.c @@ -17,7 +17,8 @@ DECLARE_GLOBAL_DATA_PTR; static void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; #if CONFIG_DDR_CLK_FREQ == 100000000 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 59e9a35089..467f4f2013 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -90,7 +90,7 @@ int checkboard (void) phys_size_t fixed_sdram (void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr; uint d_init; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index 97a5d19b5e..93288c7e9c 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -168,7 +168,8 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 60f55773da..cb55e1c98c 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -231,7 +231,8 @@ int checkboard (void) #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; uint d_init; out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 2fb4257132..56863222c8 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -62,7 +62,7 @@ int checkboard (void) phys_size_t fixed_sdram (void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr= &immap->im_ddr; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr; uint d_init; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index aa99623a43..d8740ddacc 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -143,7 +143,7 @@ phys_size_t fixed_sdram(void) { #if !defined(CONFIG_SYS_RAMBOOT) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; uint d_init; ddr->cs0_bnds = 0x0000001f; diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 0cd9df1cc9..a58b5f9cd4 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -64,7 +64,7 @@ fixed_sdram(void) { #if !defined(CONFIG_SYS_RAMBOOT) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index aa2a3448c5..39a5a0f37b 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -19,7 +19,8 @@ DECLARE_GLOBAL_DATA_PTR; void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; u32 ddr_ratio; unsigned long ddr_freq_mhz; diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index 2cfcdc41f3..d8c87458e8 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -58,7 +58,8 @@ int checkboard(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index dd8c6b10fb..a0cf927038 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -68,7 +68,8 @@ int checkboard(void) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; uint d_init; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 8817103ba7..24cc776a25 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -91,7 +91,8 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); out_be32(&ddr->cs0_bnds, 0x0000007f); out_be32(&ddr->cs1_bnds, 0x008000ff); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index 8160c7b580..4906be4889 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -93,7 +93,7 @@ long int fixed_sdram (void) { #if !defined(CONFIG_SYS_RAMBOOT) volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile ccsr_ddr_t *ddr = &immap->im_ddr1; + volatile struct ccsr_ddr *ddr = &immap->im_ddr1; ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; @@ -111,7 +111,7 @@ long int fixed_sdram (void) ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; - ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL; + ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; @@ -142,7 +142,7 @@ long int fixed_sdram (void) ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; - ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL; + ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL; ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 356e8e82e7..aebd02f76c 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -24,7 +24,8 @@ */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); /* * Disable memory controller. diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index aed4569cb4..5f3ea59b8d 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -14,13 +14,14 @@ #include #include +#include #include #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR static u32 fsl_ddr_get_version(void) { - ccsr_ddr_t *ddr; + struct ccsr_ddr __iomem *ddr; u32 ver_major_minor_errata; ddr = (void *)_DDR_ADDR; diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index ff7d979d6a..8dd4a9136c 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -18,7 +18,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step) { unsigned int i; - volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; if (ctrl_num != 0) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); @@ -73,7 +74,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, void ddr_enable_ecc(unsigned int dram_size) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index c22dea5c24..988b4a4941 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -19,7 +19,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step) { unsigned int i; - ccsr_ddr_t *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; #if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 7b4e8ec93d..9f04133094 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -29,7 +29,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step) { unsigned int i, bus_width; - volatile ccsr_ddr_t *ddr; + struct ccsr_ddr __iomem *ddr; u32 temp_sdram_cfg; u32 total_gb_size_per_controller; int timeout; diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c index caffbaf019..4551ed87db 100644 --- a/drivers/ddr/fsl/mpc86xx_ddr.c +++ b/drivers/ddr/fsl/mpc86xx_ddr.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step) { unsigned int i; - volatile ccsr_ddr_t *ddr; + struct ccsr_ddr __iomem *ddr; switch (ctrl_num) { case 0: @@ -58,7 +58,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 45a7bcc080..5d6b362510 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -11,6 +11,7 @@ #include #include +#include #include /* To avoid 64-bit full-divides, we factor this here */ @@ -134,7 +135,8 @@ u32 fsl_ddr_get_intl3r(void) void board_add_ram_info(int use_default) { - ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR); + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); #if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3) u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); diff --git a/include/fsl_immap.h b/include/fsl_immap.h new file mode 100644 index 0000000000..00902cae08 --- /dev/null +++ b/include/fsl_immap.h @@ -0,0 +1,112 @@ +/* + * Common internal memory map for some Freescale SoCs + * + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_IMMAP_H +#define __FSL_IMMAP_H +/* + * DDR memory controller registers + * This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx. + */ +struct ccsr_ddr { + u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ + u8 res_04[4]; + u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ + u8 res_0c[4]; + u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ + u8 res_14[4]; + u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ + u8 res_1c[100]; + u32 cs0_config; /* Chip Select Configuration */ + u32 cs1_config; /* Chip Select Configuration */ + u32 cs2_config; /* Chip Select Configuration */ + u32 cs3_config; /* Chip Select Configuration */ + u8 res_90[48]; + u32 cs0_config_2; /* Chip Select Configuration 2 */ + u32 cs1_config_2; /* Chip Select Configuration 2 */ + u32 cs2_config_2; /* Chip Select Configuration 2 */ + u32 cs3_config_2; /* Chip Select Configuration 2 */ + u8 res_d0[48]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 sdram_data_init; /* SDRAM Data initialization */ + u8 res_12c[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res_134[20]; + u32 init_addr; /* training init addr */ + u32 init_ext_addr; /* training init extended addr */ + u8 res_150[16]; + u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ + u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ + u8 reg_168[8]; + u32 ddr_zq_cntl; /* ZQ calibration control*/ + u32 ddr_wrlvl_cntl; /* write leveling control*/ + u8 reg_178[4]; + u32 ddr_sr_cntr; /* self refresh counter */ + u32 ddr_sdram_rcw_1; /* Control Words 1 */ + u32 ddr_sdram_rcw_2; /* Control Words 2 */ + u8 reg_188[8]; + u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */ + u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ + u8 res_198[104]; + u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */ + u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */ + u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */ + u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */ + u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */ + u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */ + u8 res_218[0x908]; + u32 ddr_dsr1; /* Debug Status 1 */ + u32 ddr_dsr2; /* Debug Status 2 */ + u32 ddr_cdr1; /* Control Driver 1 */ + u32 ddr_cdr2; /* Control Driver 2 */ + u8 res_b30[200]; + u32 ip_rev1; /* IP Block Revision 1 */ + u32 ip_rev2; /* IP Block Revision 2 */ + u32 eor; /* Enhanced Optimization Register */ + u8 res_c04[252]; + u32 mtcr; /* Memory Test Control Register */ + u8 res_d04[28]; + u32 mtp1; /* Memory Test Pattern 1 */ + u32 mtp2; /* Memory Test Pattern 2 */ + u32 mtp3; /* Memory Test Pattern 3 */ + u32 mtp4; /* Memory Test Pattern 4 */ + u32 mtp5; /* Memory Test Pattern 5 */ + u32 mtp6; /* Memory Test Pattern 6 */ + u32 mtp7; /* Memory Test Pattern 7 */ + u32 mtp8; /* Memory Test Pattern 8 */ + u32 mtp9; /* Memory Test Pattern 9 */ + u32 mtp10; /* Memory Test Pattern 10 */ + u8 res_d48[184]; + u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ + u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ + u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ + u8 res_e0c[20]; + u32 capture_data_hi; /* Data Path Read Capture High */ + u32 capture_data_lo; /* Data Path Read Capture Low */ + u32 capture_ecc; /* Data Path Read Capture ECC */ + u8 res_e2c[20]; + u32 err_detect; /* Error Detect */ + u32 err_disable; /* Error Disable */ + u32 err_int_en; + u32 capture_attributes; /* Error Attrs Capture */ + u32 capture_address; /* Error Addr Capture */ + u32 capture_ext_address; /* Error Extended Addr Capture */ + u32 err_sbe; /* Single-Bit ECC Error Management */ + u8 res_e5c[164]; + u32 debug[32]; /* debug_1 to debug_32 */ + u8 res_f80[128]; +}; +#endif /* __FSL_IMMAP_H */ diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 58e6cbf289..d9afa6d024 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -18,7 +18,8 @@ DECLARE_GLOBAL_DATA_PTR; /* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = + (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); -- cgit v1.2.1 From 9ac4ffbde1a5015c9929ee8578d3811b716e2fd3 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 30 Sep 2013 14:20:51 -0700 Subject: Driver/DDR: Add Freescale DDR driver for ARM Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun --- README | 3 + drivers/ddr/fsl/Makefile | 2 +- drivers/ddr/fsl/arm_ddr_gen3.c | 213 +++++++++++++++++++++++++++++++++++++++++ drivers/ddr/fsl/main.c | 12 ++- drivers/ddr/fsl/util.c | 4 + 5 files changed, 230 insertions(+), 4 deletions(-) create mode 100644 drivers/ddr/fsl/arm_ddr_gen3.c diff --git a/README b/README index 49f4b3af2f..d6006f5018 100644 --- a/README +++ b/README @@ -450,6 +450,9 @@ The following options need to be configured: CONFIG_SYS_FSL_DDRC_GEN3 Freescale DDR3 controller. + CONFIG_SYS_FSL_DDRC_ARM_GEN3 + Freescale DDR3 controller for ARM-based SoCs. + CONFIG_SYS_FSL_DDR1 Board config to use DDR1. It can be enabled for SoCs with Freescale DDR1 or DDR2 controllers, depending on the board diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile index a328b43209..265204f311 100644 --- a/drivers/ddr/fsl/Makefile +++ b/drivers/ddr/fsl/Makefile @@ -31,4 +31,4 @@ obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o -obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o +obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c new file mode 100644 index 0000000000..bf113908fd --- /dev/null +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -0,0 +1,213 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived from mpc85xx_ddr_gen3.c, removed all workarounds + */ + +#include +#include +#include +#include +#include + +#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) +#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL +#endif + + +/* + * regs has the to-be-set values for DDR controller registers + * ctrl_num is the DDR controller number + * step: 0 goes through the initialization in one pass + * 1 sets registers and returns before enabling controller + * 2 resumes from step 1 and continues to initialize + * Dividing the initialization to two steps to deassert DDR reset signal + * to comply with JEDEC specs for RDIMMs. + */ +void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, + unsigned int ctrl_num, int step) +{ + unsigned int i, bus_width; + struct ccsr_ddr __iomem *ddr; + u32 temp_sdram_cfg; + u32 total_gb_size_per_controller; + int timeout; + + switch (ctrl_num) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); + return; + } + + if (step == 2) + goto step2; + + if (regs->ddr_eor) + out_be32(&ddr->eor, regs->ddr_eor); + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (i == 0) { + out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs0_config, regs->cs[i].config); + out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); + + } else if (i == 1) { + out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs1_config, regs->cs[i].config); + out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); + + } else if (i == 2) { + out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs2_config, regs->cs[i].config); + out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); + + } else if (i == 3) { + out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); + out_be32(&ddr->cs3_config, regs->cs[i].config); + out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); + } + } + + out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); + out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); + out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); + out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); + out_be32(&ddr->sdram_data_init, regs->ddr_data_init); + out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); + out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); + out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + + if (regs->ddr_wrlvl_cntl_2) + out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + if (regs->ddr_wrlvl_cntl_3) + out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif + + out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + out_be32(&ddr->err_disable, regs->err_disable); + out_be32(&ddr->err_int_en, regs->err_int_en); + for (i = 0; i < 32; i++) { + if (regs->debug[i]) { + debug("Write to debug_%d as %08x\n", i + 1, + regs->debug[i]); + out_be32(&ddr->debug[i], regs->debug[i]); + } + } + + /* + * For RDIMMs, JEDEC spec requires clocks to be stable before reset is + * deasserted. Clocks start when any chip select is enabled and clock + * control register is set. Because all DDR components are connected to + * one reset signal, this needs to be done in two steps. Step 1 is to + * get the clocks started. Step 2 resumes after reset signal is + * deasserted. + */ + if (step == 1) { + udelay(200); + return; + } + +step2: + /* Set, but do not enable the memory */ + temp_sdram_cfg = regs->ddr_sdram_cfg; + temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); + out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + + /* + * 500 painful micro-seconds must elapse between + * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. + */ + udelay(500); + asm volatile("dsb sy;isb"); + + /* Let the controller go */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + asm volatile("dsb sy;isb"); + + total_gb_size_per_controller = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + if (!(regs->cs[i].config & 0x80000000)) + continue; + total_gb_size_per_controller += 1 << ( + ((regs->cs[i].config >> 14) & 0x3) + 2 + + ((regs->cs[i].config >> 8) & 0x7) + 12 + + ((regs->cs[i].config >> 0) & 0x7) + 8 + + 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - + 26); /* minus 26 (count of 64M) */ + } + if (regs->cs[0].config & 0x20000000) { + /* 2-way interleaving */ + total_gb_size_per_controller <<= 1; + } + /* + * total memory / bus width = transactions needed + * transactions needed / data rate = seconds + * to add plenty of buffer, double the time + * For example, 2GB on 666MT/s 64-bit bus takes about 402ms + * Let's wait for 800ms + */ + bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) + >> SDRAM_CFG_DBW_SHIFT); + timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / + (get_ddr_freq(0) >> 20)) << 1; + total_gb_size_per_controller >>= 4; /* shift down to gb size */ + debug("total %d GB\n", total_gb_size_per_controller); + debug("Need to wait up to %d * 10ms\n", timeout); + + /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ + while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + (timeout >= 0)) { + udelay(10000); /* throttle polling rate */ + timeout--; + } + + if (timeout <= 0) + printf("Waiting for D_INIT timeout. Memory may not work.\n"); +} diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index c1cdbdf955..b4988e194c 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -15,16 +15,18 @@ #include #include #include -#include - #include +#ifdef CONFIG_PPC +#include + void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); -void fsl_ddr_set_intl3r(const unsigned int granule_size); +#endif +void fsl_ddr_set_intl3r(const unsigned int granule_size); #if defined(SPD_EEPROM_ADDRESS) || \ defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) @@ -549,7 +551,9 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, phys_size_t fsl_ddr_sdram(void) { unsigned int i; +#ifdef CONFIG_PPC unsigned int law_memctl = LAW_TRGT_IF_DDR_1; +#endif unsigned long long total_memory; fsl_ddr_info_t info; int deassert_reset; @@ -621,6 +625,7 @@ phys_size_t fsl_ddr_sdram(void) } } +#ifdef CONFIG_PPC /* program LAWs */ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { if (info.memctl_opts[i].memctl_interleaving) { @@ -681,6 +686,7 @@ phys_size_t fsl_ddr_sdram(void) law_memctl, i); } } +#endif debug("total_memory by %s = %llu\n", __func__, total_memory); diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 5d6b362510..0658261d8d 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -7,7 +7,9 @@ */ #include +#ifdef CONFIG_PPC #include +#endif #include #include @@ -79,6 +81,7 @@ unsigned int mclk_to_picos(unsigned int mclk) return get_memory_clk_period_ps() * mclk; } +#ifdef CONFIG_PPC void __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, unsigned int law_memctl, @@ -113,6 +116,7 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); +#endif void fsl_ddr_set_intl3r(const unsigned int granule_size) { -- cgit v1.2.1 From d4263b8adb5bd940c95cbaebaa0da9eaf759bfed Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 3 Jun 2013 12:39:06 -0700 Subject: powerpc/mpc8xxx: Extend DDR registers' fields Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by: York Sun --- drivers/ddr/fsl/ctrl_regs.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 5f3ea59b8d..6bf22cfbd6 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -325,10 +325,10 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, | ((twrt_mclk & 0x3) << 28) /* WRT */ | ((trrt_mclk & 0x3) << 26) /* RRT */ | ((twwt_mclk & 0x3) << 24) /* WWT */ - | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */ + | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */ | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ - | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */ + | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */ ); debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); } @@ -338,7 +338,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, - unsigned int cas_latency) + unsigned int cas_latency, + unsigned int additive_latency) { /* Extended precharge to activate interval (tRP) */ unsigned int ext_pretoact = 0; @@ -350,6 +351,8 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, unsigned int ext_refrec; /* Extended MCAS latency from READ cmd */ unsigned int ext_caslat = 0; + /* Extended additive latency */ + unsigned int ext_add_lat = 0; /* Extended last data to precharge interval (tWR) */ unsigned int ext_wrrec = 0; /* Control Adjust */ @@ -359,6 +362,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; ext_caslat = (2 * cas_latency - 1) >> 4; + ext_add_lat = additive_latency >> 4; ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + @@ -370,6 +374,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, | ((ext_acttorw & 0x1) << 22) | ((ext_refrec & 0x1F) << 16) | ((ext_caslat & 0x3) << 12) + | ((ext_add_lat & 0x1) << 10) | ((ext_wrrec & 0x1) << 8) | ((cntl_adj & 0x7) << 0) ); @@ -531,8 +536,6 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, if (rd_to_pre < 4) rd_to_pre = 4; #endif - if (additive_latency) - rd_to_pre += additive_latency; if (popts->otf_burst_chop_en) rd_to_pre += 2; /* according to UM */ @@ -1592,8 +1595,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, if (cs_en) { ddr->cs[i].bnds = (0 - | ((sa & 0xFFF) << 16)/* starting address MSB */ - | ((ea & 0xFFF) << 0) /* ending address MSB */ + | ((sa & 0xffff) << 16) /* starting address */ + | ((ea & 0xffff) << 0) /* ending address */ ); } else { /* setting bnds to 0xffffffff for inactive CS */ @@ -1618,7 +1621,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_0(ddr, popts, dimm_params); #endif - set_timing_cfg_3(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_3(ddr, popts, common_dimm, cas_latency, + additive_latency); set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); set_timing_cfg_2(ddr, popts, common_dimm, cas_latency, additive_latency); -- cgit v1.2.1 From 00ec3fd21170e463e29723976d37f8ea2316f168 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 28 Oct 2013 16:36:02 -0700 Subject: Driver/DDR: Update DDR driver to allow non-zero base address The DRAM base has been zero for Power SoCs. It could be non-zero for ARM SoCs. Use a macro instead of hard-coding to zero. Signed-off-by: York Sun --- drivers/ddr/fsl/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index b4988e194c..d0cd58925c 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -255,7 +255,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); } - current_mem_base = 0ull; + current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE; total_mem = 0; if (pinfo->memctl_opts[0].memctl_interleaving) { rank_density = pinfo->dimm_params[0][0].rank_density >> @@ -535,8 +535,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } } - total_mem = 1 + (((unsigned long long)max_end << 24ULL) - | 0xFFFFFFULL); + total_mem = 1 + (((unsigned long long)max_end << 24ULL) | + 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE; } return total_mem; -- cgit v1.2.1 From 0b66513b2706e941b55ffc6ad5aa011e10e87960 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 22 Oct 2013 12:39:02 -0700 Subject: Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 2 +- arch/powerpc/cpu/mpc8xxx/Makefile | 1 - arch/powerpc/cpu/mpc8xxx/fsl_ifc.c | 140 ----- arch/powerpc/include/asm/fsl_ifc.h | 986 -------------------------------- arch/powerpc/include/asm/immap_85xx.h | 2 +- board/freescale/bsc9132qds/bsc9132qds.c | 2 +- board/freescale/c29xpcie/c29xpcie.c | 2 +- board/freescale/p1010rdb/p1010rdb.c | 2 +- drivers/misc/Makefile | 1 + drivers/misc/fsl_ifc.c | 140 +++++ drivers/mtd/nand/fsl_ifc_nand.c | 2 +- drivers/mtd/nand/fsl_ifc_spl.c | 2 +- include/fsl_ifc.h | 986 ++++++++++++++++++++++++++++++++ 14 files changed, 1135 insertions(+), 1135 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c delete mode 100644 arch/powerpc/include/asm/fsl_ifc.h create mode 100644 drivers/misc/fsl_ifc.c create mode 100644 include/fsl_ifc.h diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b5a0242e10..3e99b079c7 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 199b33e3bd..9e4c6c9078 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -7,7 +7,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile index 395fed16b6..f66ee2e423 100644 --- a/arch/powerpc/cpu/mpc8xxx/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/Makefile @@ -25,7 +25,6 @@ obj-y += cpu.o endif obj-$(CONFIG_OF_LIBFDT) += fdt.o -obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_LBC) += fsl_lbc.o obj-$(CONFIG_SYS_SRIO) += srio.o obj-$(CONFIG_FSL_LAW) += law.o diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c deleted file mode 100644 index 2d0fb433bc..0000000000 --- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Author: Dipen Dudhat - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void print_ifc_regs(void) -{ - int i, j; - - printf("IFC Controller Registers\n"); - for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { - printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", - i, get_ifc_cspr(i), i, get_ifc_amask(i), - i, get_ifc_csor(i)); - for (j = 0; j < 4; j++) - printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); - } -} - -void init_early_memctl_regs(void) -{ -#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) - set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); - set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); - set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); - set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); - -#ifndef CONFIG_A003399_NOR_WORKAROUND -#ifdef CONFIG_SYS_CSPR0_EXT - set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); -#endif - set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); - set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); - set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); -#endif -#endif - -#ifdef CONFIG_SYS_CSPR1_EXT - set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); -#endif -#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) - set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); - set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); - set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); - set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); - - set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); - set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); - set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); -#endif - -#ifdef CONFIG_SYS_CSPR2_EXT - set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); -#endif -#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) - set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); - set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); - set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); - set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); - - set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); - set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); - set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); -#endif - -#ifdef CONFIG_SYS_CSPR3_EXT - set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); -#endif -#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) - set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); - set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); - set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); - set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); - - set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); - set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); - set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); -#endif - -#ifdef CONFIG_SYS_CSPR4_EXT - set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); -#endif -#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) - set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); - set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); - set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); - set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); - - set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); - set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); - set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); -#endif - -#ifdef CONFIG_SYS_CSPR5_EXT - set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); -#endif -#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) - set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); - set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); - set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2); - set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3); - - set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5); - set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5); - set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); -#endif - -#ifdef CONFIG_SYS_CSPR6_EXT - set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); -#endif -#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) - set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); - set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); - set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); - set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); - - set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); - set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); - set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); -#endif - -#ifdef CONFIG_SYS_CSPR7_EXT - set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); -#endif -#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) - set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); - set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); - set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); - set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); - - set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); - set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); - set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); -#endif -} diff --git a/arch/powerpc/include/asm/fsl_ifc.h b/arch/powerpc/include/asm/fsl_ifc.h deleted file mode 100644 index a945e4b2d4..0000000000 --- a/arch/powerpc/include/asm/fsl_ifc.h +++ /dev/null @@ -1,986 +0,0 @@ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - * Author: Dipen Dudhat - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_PPC_FSL_IFC_H -#define __ASM_PPC_FSL_IFC_H - -#ifdef CONFIG_FSL_IFC -#include -#include - -/* - * CSPR - Chip Select Property Register - */ -#define CSPR_BA 0xFFFF0000 -#define CSPR_BA_SHIFT 16 -#define CSPR_PORT_SIZE 0x00000180 -#define CSPR_PORT_SIZE_SHIFT 7 -/* Port Size 8 bit */ -#define CSPR_PORT_SIZE_8 0x00000080 -/* Port Size 16 bit */ -#define CSPR_PORT_SIZE_16 0x00000100 -/* Port Size 32 bit */ -#define CSPR_PORT_SIZE_32 0x00000180 -/* Write Protect */ -#define CSPR_WP 0x00000040 -#define CSPR_WP_SHIFT 6 -/* Machine Select */ -#define CSPR_MSEL 0x00000006 -#define CSPR_MSEL_SHIFT 1 -/* NOR */ -#define CSPR_MSEL_NOR 0x00000000 -/* NAND */ -#define CSPR_MSEL_NAND 0x00000002 -/* GPCM */ -#define CSPR_MSEL_GPCM 0x00000004 -/* Bank Valid */ -#define CSPR_V 0x00000001 -#define CSPR_V_SHIFT 0 - -/* Convert an address into the right format for the CSPR Registers */ -#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) - -/* - * Address Mask Register - */ -#define IFC_AMASK_MASK 0xFFFF0000 -#define IFC_AMASK_SHIFT 16 -#define IFC_AMASK(n) (IFC_AMASK_MASK << \ - (__ilog2(n) - IFC_AMASK_SHIFT)) - -/* - * Chip Select Option Register IFC_NAND Machine - */ -/* Enable ECC Encoder */ -#define CSOR_NAND_ECC_ENC_EN 0x80000000 -#define CSOR_NAND_ECC_MODE_MASK 0x30000000 -/* 4 bit correction per 520 Byte sector */ -#define CSOR_NAND_ECC_MODE_4 0x00000000 -/* 8 bit correction per 528 Byte sector */ -#define CSOR_NAND_ECC_MODE_8 0x10000000 -/* Enable ECC Decoder */ -#define CSOR_NAND_ECC_DEC_EN 0x04000000 -/* Row Address Length */ -#define CSOR_NAND_RAL_MASK 0x01800000 -#define CSOR_NAND_RAL_SHIFT 20 -#define CSOR_NAND_RAL_1 0x00000000 -#define CSOR_NAND_RAL_2 0x00800000 -#define CSOR_NAND_RAL_3 0x01000000 -#define CSOR_NAND_RAL_4 0x01800000 -/* Page Size 512b, 2k, 4k */ -#define CSOR_NAND_PGS_MASK 0x00180000 -#define CSOR_NAND_PGS_SHIFT 16 -#define CSOR_NAND_PGS_512 0x00000000 -#define CSOR_NAND_PGS_2K 0x00080000 -#define CSOR_NAND_PGS_4K 0x00100000 -/* Spare region Size */ -#define CSOR_NAND_SPRZ_MASK 0x0000E000 -#define CSOR_NAND_SPRZ_SHIFT 13 -#define CSOR_NAND_SPRZ_16 0x00000000 -#define CSOR_NAND_SPRZ_64 0x00002000 -#define CSOR_NAND_SPRZ_128 0x00004000 -#define CSOR_NAND_SPRZ_210 0x00006000 -#define CSOR_NAND_SPRZ_218 0x00008000 -#define CSOR_NAND_SPRZ_224 0x0000A000 -/* Pages Per Block */ -#define CSOR_NAND_PB_MASK 0x00000700 -#define CSOR_NAND_PB_SHIFT 8 -#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) -/* Time for Read Enable High to Output High Impedance */ -#define CSOR_NAND_TRHZ_MASK 0x0000001C -#define CSOR_NAND_TRHZ_SHIFT 2 -#define CSOR_NAND_TRHZ_20 0x00000000 -#define CSOR_NAND_TRHZ_40 0x00000004 -#define CSOR_NAND_TRHZ_60 0x00000008 -#define CSOR_NAND_TRHZ_80 0x0000000C -#define CSOR_NAND_TRHZ_100 0x00000010 -/* Buffer control disable */ -#define CSOR_NAND_BCTLD 0x00000001 - -/* - * Chip Select Option Register - NOR Flash Mode - */ -/* Enable Address shift Mode */ -#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 -/* Page Read Enable from NOR device */ -#define CSOR_NOR_PGRD_EN 0x10000000 -/* AVD Toggle Enable during Burst Program */ -#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 -/* Address Data Multiplexing Shift */ -#define CSOR_NOR_ADM_MASK 0x0003E000 -#define CSOR_NOR_ADM_SHIFT_SHIFT 13 -#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) -/* Type of the NOR device hooked */ -#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 -#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 -/* Time for Read Enable High to Output High Impedance */ -#define CSOR_NOR_TRHZ_MASK 0x0000001C -#define CSOR_NOR_TRHZ_SHIFT 2 -#define CSOR_NOR_TRHZ_20 0x00000000 -#define CSOR_NOR_TRHZ_40 0x00000004 -#define CSOR_NOR_TRHZ_60 0x00000008 -#define CSOR_NOR_TRHZ_80 0x0000000C -#define CSOR_NOR_TRHZ_100 0x00000010 -/* Buffer control disable */ -#define CSOR_NOR_BCTLD 0x00000001 - -/* - * Chip Select Option Register - GPCM Mode - */ -/* GPCM Mode - Normal */ -#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 -/* GPCM Mode - GenericASIC */ -#define CSOR_GPCM_GPMODE_ASIC 0x80000000 -/* Parity Mode odd/even */ -#define CSOR_GPCM_PARITY_EVEN 0x40000000 -/* Parity Checking enable/disable */ -#define CSOR_GPCM_PAR_EN 0x20000000 -/* GPCM Timeout Count */ -#define CSOR_GPCM_GPTO_MASK 0x0F000000 -#define CSOR_GPCM_GPTO_SHIFT 24 -#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) -/* GPCM External Access Termination mode for read access */ -#define CSOR_GPCM_RGETA_EXT 0x00080000 -/* GPCM External Access Termination mode for write access */ -#define CSOR_GPCM_WGETA_EXT 0x00040000 -/* Address Data Multiplexing Shift */ -#define CSOR_GPCM_ADM_MASK 0x0003E000 -#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 -#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) -/* Generic ASIC Parity error indication delay */ -#define CSOR_GPCM_GAPERRD_MASK 0x00000180 -#define CSOR_GPCM_GAPERRD_SHIFT 7 -#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) -/* Time for Read Enable High to Output High Impedance */ -#define CSOR_GPCM_TRHZ_MASK 0x0000001C -#define CSOR_GPCM_TRHZ_20 0x00000000 -#define CSOR_GPCM_TRHZ_40 0x00000004 -#define CSOR_GPCM_TRHZ_60 0x00000008 -#define CSOR_GPCM_TRHZ_80 0x0000000C -#define CSOR_GPCM_TRHZ_100 0x00000010 -/* Buffer control disable */ -#define CSOR_GPCM_BCTLD 0x00000001 - -/* - * Flash Timing Registers (FTIM0 - FTIM2_CSn) - */ -/* - * FTIM0 - NAND Flash Mode - */ -#define FTIM0_NAND 0x7EFF3F3F -#define FTIM0_NAND_TCCST_SHIFT 25 -#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) -#define FTIM0_NAND_TWP_SHIFT 16 -#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) -#define FTIM0_NAND_TWCHT_SHIFT 8 -#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) -#define FTIM0_NAND_TWH_SHIFT 0 -#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) -/* - * FTIM1 - NAND Flash Mode - */ -#define FTIM1_NAND 0xFFFF3FFF -#define FTIM1_NAND_TADLE_SHIFT 24 -#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) -#define FTIM1_NAND_TWBE_SHIFT 16 -#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) -#define FTIM1_NAND_TRR_SHIFT 8 -#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) -#define FTIM1_NAND_TRP_SHIFT 0 -#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) -/* - * FTIM2 - NAND Flash Mode - */ -#define FTIM2_NAND 0x1FE1F8FF -#define FTIM2_NAND_TRAD_SHIFT 21 -#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) -#define FTIM2_NAND_TREH_SHIFT 11 -#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) -#define FTIM2_NAND_TWHRE_SHIFT 0 -#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) -/* - * FTIM3 - NAND Flash Mode - */ -#define FTIM3_NAND 0xFF000000 -#define FTIM3_NAND_TWW_SHIFT 24 -#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) - -/* - * FTIM0 - NOR Flash Mode - */ -#define FTIM0_NOR 0xF03F3F3F -#define FTIM0_NOR_TACSE_SHIFT 28 -#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) -#define FTIM0_NOR_TEADC_SHIFT 16 -#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) -#define FTIM0_NOR_TAVDS_SHIFT 8 -#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) -#define FTIM0_NOR_TEAHC_SHIFT 0 -#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) -/* - * FTIM1 - NOR Flash Mode - */ -#define FTIM1_NOR 0xFF003F3F -#define FTIM1_NOR_TACO_SHIFT 24 -#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) -#define FTIM1_NOR_TRAD_NOR_SHIFT 8 -#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) -#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 -#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) -/* - * FTIM2 - NOR Flash Mode - */ -#define FTIM2_NOR 0x0F3CFCFF -#define FTIM2_NOR_TCS_SHIFT 24 -#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) -#define FTIM2_NOR_TCH_SHIFT 18 -#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) -#define FTIM2_NOR_TWPH_SHIFT 10 -#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) -#define FTIM2_NOR_TWP_SHIFT 0 -#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) - -/* - * FTIM0 - Normal GPCM Mode - */ -#define FTIM0_GPCM 0xF03F3F3F -#define FTIM0_GPCM_TACSE_SHIFT 28 -#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) -#define FTIM0_GPCM_TEADC_SHIFT 16 -#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) -#define FTIM0_GPCM_TAVDS_SHIFT 8 -#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) -#define FTIM0_GPCM_TEAHC_SHIFT 0 -#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) -/* - * FTIM1 - Normal GPCM Mode - */ -#define FTIM1_GPCM 0xFF003F00 -#define FTIM1_GPCM_TACO_SHIFT 24 -#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) -#define FTIM1_GPCM_TRAD_SHIFT 8 -#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) -/* - * FTIM2 - Normal GPCM Mode - */ -#define FTIM2_GPCM 0x0F3C00FF -#define FTIM2_GPCM_TCS_SHIFT 24 -#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) -#define FTIM2_GPCM_TCH_SHIFT 18 -#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) -#define FTIM2_GPCM_TWP_SHIFT 0 -#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) - -/* - * Ready Busy Status Register (RB_STAT) - */ -/* CSn is READY */ -#define IFC_RB_STAT_READY_CS0 0x80000000 -#define IFC_RB_STAT_READY_CS1 0x40000000 -#define IFC_RB_STAT_READY_CS2 0x20000000 -#define IFC_RB_STAT_READY_CS3 0x10000000 - -/* - * General Control Register (GCR) - */ -#define IFC_GCR_MASK 0x8000F800 -/* reset all IFC hardware */ -#define IFC_GCR_SOFT_RST_ALL 0x80000000 -/* Turnaroud Time of external buffer */ -#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 -#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 - -/* - * Common Event and Error Status Register (CM_EVTER_STAT) - */ -/* Chip select error */ -#define IFC_CM_EVTER_STAT_CSER 0x80000000 - -/* - * Common Event and Error Enable Register (CM_EVTER_EN) - */ -/* Chip select error checking enable */ -#define IFC_CM_EVTER_EN_CSEREN 0x80000000 - -/* - * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) - */ -/* Chip select error interrupt enable */ -#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 - -/* - * Common Transfer Error Attribute Register-0 (CM_ERATTR0) - */ -/* transaction type of error Read/Write */ -#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 -#define IFC_CM_ERATTR0_ERAID 0x0FF00000 -#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 - -/* - * Clock Control Register (CCR) - */ -#define IFC_CCR_MASK 0x0F0F8800 -/* Clock division ratio */ -#define IFC_CCR_CLK_DIV_MASK 0x0F000000 -#define IFC_CCR_CLK_DIV_SHIFT 24 -#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) -/* IFC Clock Delay */ -#define IFC_CCR_CLK_DLY_MASK 0x000F0000 -#define IFC_CCR_CLK_DLY_SHIFT 16 -#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) -/* Invert IFC clock before sending out */ -#define IFC_CCR_INV_CLK_EN 0x00008000 -/* Fedback IFC Clock */ -#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 - -/* - * Clock Status Register (CSR) - */ -/* Clk is stable */ -#define IFC_CSR_CLK_STAT_STABLE 0x80000000 - -/* - * IFC_NAND Machine Specific Registers - */ -/* - * NAND Configuration Register (NCFGR) - */ -/* Auto Boot Mode */ -#define IFC_NAND_NCFGR_BOOT 0x80000000 -/* Addressing Mode-ROW0+n/COL0 */ -#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 -/* Addressing Mode-ROW0+n/COL0+n */ -#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 -/* Number of loop iterations of FIR sequences for multi page operations */ -#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 -#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 -#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) -/* Number of wait cycles */ -#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF -#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 - -/* - * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) - */ -/* General purpose FCM flash command bytes CMD0-CMD7 */ -#define IFC_NAND_FCR0_CMD0 0xFF000000 -#define IFC_NAND_FCR0_CMD0_SHIFT 24 -#define IFC_NAND_FCR0_CMD1 0x00FF0000 -#define IFC_NAND_FCR0_CMD1_SHIFT 16 -#define IFC_NAND_FCR0_CMD2 0x0000FF00 -#define IFC_NAND_FCR0_CMD2_SHIFT 8 -#define IFC_NAND_FCR0_CMD3 0x000000FF -#define IFC_NAND_FCR0_CMD3_SHIFT 0 -#define IFC_NAND_FCR1_CMD4 0xFF000000 -#define IFC_NAND_FCR1_CMD4_SHIFT 24 -#define IFC_NAND_FCR1_CMD5 0x00FF0000 -#define IFC_NAND_FCR1_CMD5_SHIFT 16 -#define IFC_NAND_FCR1_CMD6 0x0000FF00 -#define IFC_NAND_FCR1_CMD6_SHIFT 8 -#define IFC_NAND_FCR1_CMD7 0x000000FF -#define IFC_NAND_FCR1_CMD7_SHIFT 0 - -/* - * Flash ROW and COL Address Register (ROWn, COLn) - */ -/* Main/spare region locator */ -#define IFC_NAND_COL_MS 0x80000000 -/* Column Address */ -#define IFC_NAND_COL_CA_MASK 0x00000FFF - -/* - * NAND Flash Byte Count Register (NAND_BC) - */ -/* Byte Count for read/Write */ -#define IFC_NAND_BC 0x000001FF - -/* - * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) - */ -/* NAND Machine specific opcodes OP0-OP14*/ -#define IFC_NAND_FIR0_OP0 0xFC000000 -#define IFC_NAND_FIR0_OP0_SHIFT 26 -#define IFC_NAND_FIR0_OP1 0x03F00000 -#define IFC_NAND_FIR0_OP1_SHIFT 20 -#define IFC_NAND_FIR0_OP2 0x000FC000 -#define IFC_NAND_FIR0_OP2_SHIFT 14 -#define IFC_NAND_FIR0_OP3 0x00003F00 -#define IFC_NAND_FIR0_OP3_SHIFT 8 -#define IFC_NAND_FIR0_OP4 0x000000FC -#define IFC_NAND_FIR0_OP4_SHIFT 2 -#define IFC_NAND_FIR1_OP5 0xFC000000 -#define IFC_NAND_FIR1_OP5_SHIFT 26 -#define IFC_NAND_FIR1_OP6 0x03F00000 -#define IFC_NAND_FIR1_OP6_SHIFT 20 -#define IFC_NAND_FIR1_OP7 0x000FC000 -#define IFC_NAND_FIR1_OP7_SHIFT 14 -#define IFC_NAND_FIR1_OP8 0x00003F00 -#define IFC_NAND_FIR1_OP8_SHIFT 8 -#define IFC_NAND_FIR1_OP9 0x000000FC -#define IFC_NAND_FIR1_OP9_SHIFT 2 -#define IFC_NAND_FIR2_OP10 0xFC000000 -#define IFC_NAND_FIR2_OP10_SHIFT 26 -#define IFC_NAND_FIR2_OP11 0x03F00000 -#define IFC_NAND_FIR2_OP11_SHIFT 20 -#define IFC_NAND_FIR2_OP12 0x000FC000 -#define IFC_NAND_FIR2_OP12_SHIFT 14 -#define IFC_NAND_FIR2_OP13 0x00003F00 -#define IFC_NAND_FIR2_OP13_SHIFT 8 -#define IFC_NAND_FIR2_OP14 0x000000FC -#define IFC_NAND_FIR2_OP14_SHIFT 2 - -/* - * Instruction opcodes to be programmed - * in FIR registers- 6bits - */ -enum ifc_nand_fir_opcodes { - IFC_FIR_OP_NOP, - IFC_FIR_OP_CA0, - IFC_FIR_OP_CA1, - IFC_FIR_OP_CA2, - IFC_FIR_OP_CA3, - IFC_FIR_OP_RA0, - IFC_FIR_OP_RA1, - IFC_FIR_OP_RA2, - IFC_FIR_OP_RA3, - IFC_FIR_OP_CMD0, - IFC_FIR_OP_CMD1, - IFC_FIR_OP_CMD2, - IFC_FIR_OP_CMD3, - IFC_FIR_OP_CMD4, - IFC_FIR_OP_CMD5, - IFC_FIR_OP_CMD6, - IFC_FIR_OP_CMD7, - IFC_FIR_OP_CW0, - IFC_FIR_OP_CW1, - IFC_FIR_OP_CW2, - IFC_FIR_OP_CW3, - IFC_FIR_OP_CW4, - IFC_FIR_OP_CW5, - IFC_FIR_OP_CW6, - IFC_FIR_OP_CW7, - IFC_FIR_OP_WBCD, - IFC_FIR_OP_RBCD, - IFC_FIR_OP_BTRD, - IFC_FIR_OP_RDSTAT, - IFC_FIR_OP_NWAIT, - IFC_FIR_OP_WFR, - IFC_FIR_OP_SBRD, - IFC_FIR_OP_UA, - IFC_FIR_OP_RB, -}; - -/* - * NAND Chip Select Register (NAND_CSEL) - */ -#define IFC_NAND_CSEL 0x0C000000 -#define IFC_NAND_CSEL_SHIFT 26 -#define IFC_NAND_CSEL_CS0 0x00000000 -#define IFC_NAND_CSEL_CS1 0x04000000 -#define IFC_NAND_CSEL_CS2 0x08000000 -#define IFC_NAND_CSEL_CS3 0x0C000000 - -/* - * NAND Operation Sequence Start (NANDSEQ_STRT) - */ -/* NAND Flash Operation Start */ -#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 -/* Automatic Erase */ -#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 -/* Automatic Program */ -#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 -/* Automatic Copyback */ -#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 -/* Automatic Read Operation */ -#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 -/* Automatic Status Read */ -#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 - -/* - * NAND Event and Error Status Register (NAND_EVTER_STAT) - */ -/* Operation Complete */ -#define IFC_NAND_EVTER_STAT_OPC 0x80000000 -/* Flash Timeout Error */ -#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 -/* Write Protect Error */ -#define IFC_NAND_EVTER_STAT_WPER 0x04000000 -/* ECC Error */ -#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 -/* RCW Load Done */ -#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 -/* Boot Loadr Done */ -#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 -/* Bad Block Indicator search select */ -#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 - -/* - * NAND Flash Page Read Completion Event Status Register - * (PGRDCMPL_EVT_STAT) - */ -#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 -/* Small Page 0-15 Done */ -#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) -/* Large Page(2K) 0-3 Done */ -#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) -/* Large Page(4K) 0-1 Done */ -#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) - -/* - * NAND Event and Error Enable Register (NAND_EVTER_EN) - */ -/* Operation complete event enable */ -#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 -/* Page read complete event enable */ -#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 -/* Flash Timeout error enable */ -#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 -/* Write Protect error enable */ -#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 -/* ECC error logging enable */ -#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 - -/* - * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) - */ -/* Enable interrupt for operation complete */ -#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 -/* Enable interrupt for Page read complete */ -#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 -/* Enable interrupt for Flash timeout error */ -#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 -/* Enable interrupt for Write protect error */ -#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 -/* Enable interrupt for ECC error*/ -#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 - -/* - * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) - */ -#define IFC_NAND_ERATTR0_MASK 0x0C080000 -/* Error on CS0-3 for NAND */ -#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 -#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 -#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 -#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 -/* Transaction type of error Read/Write */ -#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 - -/* - * NAND Flash Status Register (NAND_FSR) - */ -/* First byte of data read from read status op */ -#define IFC_NAND_NFSR_RS0 0xFF000000 -/* Second byte of data read from read status op */ -#define IFC_NAND_NFSR_RS1 0x00FF0000 - -/* - * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) - */ -/* Number of ECC errors on sector n (n = 0-15) */ -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F -#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F -#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F -#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F -#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 - -/* - * NAND Control Register (NANDCR) - */ -#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 -#define IFC_NAND_NCR_FTOCNT_SHIFT 25 -#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) - -/* - * NAND_AUTOBOOT_TRGR - */ -/* Trigger RCW load */ -#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 -/* Trigget Auto Boot */ -#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 - -/* - * NAND_MDR - */ -/* 1st read data byte when opcode SBRD */ -#define IFC_NAND_MDR_RDATA0 0xFF000000 -/* 2nd read data byte when opcode SBRD */ -#define IFC_NAND_MDR_RDATA1 0x00FF0000 - -/* - * NOR Machine Specific Registers - */ -/* - * NOR Event and Error Status Register (NOR_EVTER_STAT) - */ -/* NOR Command Sequence Operation Complete */ -#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 -/* Write Protect Error */ -#define IFC_NOR_EVTER_STAT_WPER 0x04000000 -/* Command Sequence Timeout Error */ -#define IFC_NOR_EVTER_STAT_STOER 0x01000000 - -/* - * NOR Event and Error Enable Register (NOR_EVTER_EN) - */ -/* NOR Command Seq complete event enable */ -#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 -/* Write Protect Error Checking Enable */ -#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 -/* Timeout Error Enable */ -#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 - -/* - * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) - */ -/* Enable interrupt for OPC complete */ -#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 -/* Enable interrupt for write protect error */ -#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 -/* Enable interrupt for timeout error */ -#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 - -/* - * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) - */ -/* Source ID for error transaction */ -#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 -/* AXI ID for error transation */ -#define IFC_NOR_ERATTR0_ERAID 0x000FF000 -/* Chip select corresponds to NOR error */ -#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 -#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 -#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 -#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 -/* Type of transaction read/write */ -#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 - -/* - * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) - */ -#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 -#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 - -/* - * NOR Control Register (NORCR) - */ -#define IFC_NORCR_MASK 0x0F0F0000 -/* No. of Address/Data Phase */ -#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 -#define IFC_NORCR_NUM_PHASE_SHIFT 24 -#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) -/* Sequence Timeout Count */ -#define IFC_NORCR_STOCNT_MASK 0x000F0000 -#define IFC_NORCR_STOCNT_SHIFT 16 -#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) - -/* - * GPCM Machine specific registers - */ -/* - * GPCM Event and Error Status Register (GPCM_EVTER_STAT) - */ -/* Timeout error */ -#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 -/* Parity error */ -#define IFC_GPCM_EVTER_STAT_PER 0x01000000 - -/* - * GPCM Event and Error Enable Register (GPCM_EVTER_EN) - */ -/* Timeout error enable */ -#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 -/* Parity error enable */ -#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 - -/* - * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) - */ -/* Enable Interrupt for timeout error */ -#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 -/* Enable Interrupt for Parity error */ -#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 - -/* - * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) - */ -/* Source ID for error transaction */ -#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 -/* AXI ID for error transaction */ -#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 -/* Chip select corresponds to GPCM error */ -#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 -#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 -#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 -#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 -/* Type of transaction read/Write */ -#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 - -/* - * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) - */ -/* On which beat of address/data parity error is observed */ -#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 -/* Parity Error on byte */ -#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 -/* Parity Error reported in addr or data phase */ -#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 - -/* - * GPCM Status Register (GPCM_STAT) - */ -#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ - - -#ifndef __ASSEMBLY__ -#include - -extern void print_ifc_regs(void); -extern void init_early_memctl_regs(void); - -#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) - -#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) - -#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) -#define set_ifc_ftim(i, j, v) \ - (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) - -enum ifc_chip_sel { - IFC_CS0, - IFC_CS1, - IFC_CS2, - IFC_CS3, - IFC_CS4, - IFC_CS5, - IFC_CS6, - IFC_CS7, -}; - -enum ifc_ftims { - IFC_FTIM0, - IFC_FTIM1, - IFC_FTIM2, - IFC_FTIM3, -}; - -/* - * IFC Controller NAND Machine registers - */ -struct fsl_ifc_nand { - u32 ncfgr; - u32 res1[0x4]; - u32 nand_fcr0; - u32 nand_fcr1; - u32 res2[0x8]; - u32 row0; - u32 res3; - u32 col0; - u32 res4; - u32 row1; - u32 res5; - u32 col1; - u32 res6; - u32 row2; - u32 res7; - u32 col2; - u32 res8; - u32 row3; - u32 res9; - u32 col3; - u32 res10[0x24]; - u32 nand_fbcr; - u32 res11; - u32 nand_fir0; - u32 nand_fir1; - u32 nand_fir2; - u32 res12[0x10]; - u32 nand_csel; - u32 res13; - u32 nandseq_strt; - u32 res14; - u32 nand_evter_stat; - u32 res15; - u32 pgrdcmpl_evt_stat; - u32 res16[0x2]; - u32 nand_evter_en; - u32 res17[0x2]; - u32 nand_evter_intr_en; - u32 res18[0x2]; - u32 nand_erattr0; - u32 nand_erattr1; - u32 res19[0x10]; - u32 nand_fsr; - u32 res20; - u32 nand_eccstat[4]; - u32 res21[0x20]; - u32 nanndcr; - u32 res22[0x2]; - u32 nand_autoboot_trgr; - u32 res23; - u32 nand_mdr; - u32 res24[0x5C]; -}; - -/* - * IFC controller NOR Machine registers - */ -struct fsl_ifc_nor { - u32 nor_evter_stat; - u32 res1[0x2]; - u32 nor_evter_en; - u32 res2[0x2]; - u32 nor_evter_intr_en; - u32 res3[0x2]; - u32 nor_erattr0; - u32 nor_erattr1; - u32 nor_erattr2; - u32 res4[0x4]; - u32 norcr; - u32 res5[0xEF]; -}; - -/* - * IFC controller GPCM Machine registers - */ -struct fsl_ifc_gpcm { - u32 gpcm_evter_stat; - u32 res1[0x2]; - u32 gpcm_evter_en; - u32 res2[0x2]; - u32 gpcm_evter_intr_en; - u32 res3[0x2]; - u32 gpcm_erattr0; - u32 gpcm_erattr1; - u32 gpcm_erattr2; - u32 gpcm_stat; - u32 res4[0x1F3]; -}; - -#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT -#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) -#define IFC_CSPR_REG_LEN 148 -#define IFC_AMASK_REG_LEN 144 -#define IFC_CSOR_REG_LEN 144 -#define IFC_FTIM_REG_LEN 576 - -#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ - CONFIG_SYS_FSL_IFC_BANK_COUNT -#else -#error IFC BANK count not vaild -#endif -#else -#error IFC BANK count not defined -#endif - -struct fsl_ifc_cspr { - u32 cspr_ext; - u32 cspr; - u32 res; -}; - -struct fsl_ifc_amask { - u32 amask; - u32 res[0x2]; -}; - -struct fsl_ifc_csor { - u32 csor; - u32 csor_ext; - u32 res; -}; - -struct fsl_ifc_ftim { - u32 ftim[4]; - u32 res[0x8]; -}; - -/* - * IFC Controller Registers - */ -struct fsl_ifc { - u32 ifc_rev; - u32 res1[0x2]; - struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; - struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; - struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; - struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; - u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; - u32 rb_stat; - u32 res6[0x2]; - u32 ifc_gcr; - u32 res7[0x2]; - u32 cm_evter_stat; - u32 res8[0x2]; - u32 cm_evter_en; - u32 res9[0x2]; - u32 cm_evter_intr_en; - u32 res10[0x2]; - u32 cm_erattr0; - u32 cm_erattr1; - u32 res11[0x2]; - u32 ifc_ccr; - u32 ifc_csr; - u32 res12[0x2EB]; - struct fsl_ifc_nand ifc_nand; - struct fsl_ifc_nor ifc_nor; - struct fsl_ifc_gpcm ifc_gpcm; -}; - -#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 -#undef CSPR_MSEL_NOR -#define CSPR_MSEL_NOR CSPR_MSEL_GPCM -#endif -#endif /* CONFIG_FSL_IFC */ - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_PPC_FSL_IFC_H */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 80817dcbc4..9b386ee6b2 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c index c1ebcf88e3..9377280063 100644 --- a/board/freescale/bsc9132qds/bsc9132qds.c +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c index 48c4b308be..f964d6185a 100644 --- a/board/freescale/c29xpcie/c29xpcie.c +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include "cpld.h" diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index e940d2275e..62caf676c6 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index d8ff9c6413..c77e40a2d4 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_PDSP188x) += pdsp188x.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o +obj-$(CONFIG_FSL_IFC) += fsl_ifc.o diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c new file mode 100644 index 0000000000..507c4de526 --- /dev/null +++ b/drivers/misc/fsl_ifc.c @@ -0,0 +1,140 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void print_ifc_regs(void) +{ + int i, j; + + printf("IFC Controller Registers\n"); + for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) { + printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n", + i, get_ifc_cspr(i), i, get_ifc_amask(i), + i, get_ifc_csor(i)); + for (j = 0; j < 4; j++) + printf("IFC_FTIM%d:0x%08X\n", j, get_ifc_ftim(i, j)); + } +} + +void init_early_memctl_regs(void) +{ +#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0) + set_ifc_ftim(IFC_CS0, IFC_FTIM0, CONFIG_SYS_CS0_FTIM0); + set_ifc_ftim(IFC_CS0, IFC_FTIM1, CONFIG_SYS_CS0_FTIM1); + set_ifc_ftim(IFC_CS0, IFC_FTIM2, CONFIG_SYS_CS0_FTIM2); + set_ifc_ftim(IFC_CS0, IFC_FTIM3, CONFIG_SYS_CS0_FTIM3); + +#ifndef CONFIG_A003399_NOR_WORKAROUND +#ifdef CONFIG_SYS_CSPR0_EXT + set_ifc_cspr_ext(IFC_CS0, CONFIG_SYS_CSPR0_EXT); +#endif + set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0); + set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0); + set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0); +#endif +#endif + +#ifdef CONFIG_SYS_CSPR1_EXT + set_ifc_cspr_ext(IFC_CS1, CONFIG_SYS_CSPR1_EXT); +#endif +#if defined(CONFIG_SYS_CSPR1) && defined(CONFIG_SYS_CSOR1) + set_ifc_ftim(IFC_CS1, IFC_FTIM0, CONFIG_SYS_CS1_FTIM0); + set_ifc_ftim(IFC_CS1, IFC_FTIM1, CONFIG_SYS_CS1_FTIM1); + set_ifc_ftim(IFC_CS1, IFC_FTIM2, CONFIG_SYS_CS1_FTIM2); + set_ifc_ftim(IFC_CS1, IFC_FTIM3, CONFIG_SYS_CS1_FTIM3); + + set_ifc_csor(IFC_CS1, CONFIG_SYS_CSOR1); + set_ifc_amask(IFC_CS1, CONFIG_SYS_AMASK1); + set_ifc_cspr(IFC_CS1, CONFIG_SYS_CSPR1); +#endif + +#ifdef CONFIG_SYS_CSPR2_EXT + set_ifc_cspr_ext(IFC_CS2, CONFIG_SYS_CSPR2_EXT); +#endif +#if defined(CONFIG_SYS_CSPR2) && defined(CONFIG_SYS_CSOR2) + set_ifc_ftim(IFC_CS2, IFC_FTIM0, CONFIG_SYS_CS2_FTIM0); + set_ifc_ftim(IFC_CS2, IFC_FTIM1, CONFIG_SYS_CS2_FTIM1); + set_ifc_ftim(IFC_CS2, IFC_FTIM2, CONFIG_SYS_CS2_FTIM2); + set_ifc_ftim(IFC_CS2, IFC_FTIM3, CONFIG_SYS_CS2_FTIM3); + + set_ifc_csor(IFC_CS2, CONFIG_SYS_CSOR2); + set_ifc_amask(IFC_CS2, CONFIG_SYS_AMASK2); + set_ifc_cspr(IFC_CS2, CONFIG_SYS_CSPR2); +#endif + +#ifdef CONFIG_SYS_CSPR3_EXT + set_ifc_cspr_ext(IFC_CS3, CONFIG_SYS_CSPR3_EXT); +#endif +#if defined(CONFIG_SYS_CSPR3) && defined(CONFIG_SYS_CSOR3) + set_ifc_ftim(IFC_CS3, IFC_FTIM0, CONFIG_SYS_CS3_FTIM0); + set_ifc_ftim(IFC_CS3, IFC_FTIM1, CONFIG_SYS_CS3_FTIM1); + set_ifc_ftim(IFC_CS3, IFC_FTIM2, CONFIG_SYS_CS3_FTIM2); + set_ifc_ftim(IFC_CS3, IFC_FTIM3, CONFIG_SYS_CS3_FTIM3); + + set_ifc_cspr(IFC_CS3, CONFIG_SYS_CSPR3); + set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3); + set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3); +#endif + +#ifdef CONFIG_SYS_CSPR4_EXT + set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT); +#endif +#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4) + set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0); + set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1); + set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2); + set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3); + + set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4); + set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4); + set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4); +#endif + +#ifdef CONFIG_SYS_CSPR5_EXT + set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT); +#endif +#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5) + set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0); + set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1); + set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2); + set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3); + + set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5); + set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5); + set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5); +#endif + +#ifdef CONFIG_SYS_CSPR6_EXT + set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT); +#endif +#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6) + set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0); + set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1); + set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2); + set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3); + + set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6); + set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6); + set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6); +#endif + +#ifdef CONFIG_SYS_CSPR7_EXT + set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT); +#endif +#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7) + set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0); + set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1); + set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2); + set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3); + + set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7); + set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7); + set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7); +#endif +} diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 98a09c0641..3b845b9d67 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -17,7 +17,7 @@ #include #include -#include +#include #define FSL_IFC_V1_1_0 0x01010000 #define MAX_BANKS 4 diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index d4622653fa..3c8278dafc 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include static inline int is_blank(uchar *addr, int page_size) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h new file mode 100644 index 0000000000..3e9b01b3b5 --- /dev/null +++ b/include/fsl_ifc.h @@ -0,0 +1,986 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Dipen Dudhat + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_IFC_H +#define __FSL_IFC_H + +#ifdef CONFIG_FSL_IFC +#include +#include + +/* + * CSPR - Chip Select Property Register + */ +#define CSPR_BA 0xFFFF0000 +#define CSPR_BA_SHIFT 16 +#define CSPR_PORT_SIZE 0x00000180 +#define CSPR_PORT_SIZE_SHIFT 7 +/* Port Size 8 bit */ +#define CSPR_PORT_SIZE_8 0x00000080 +/* Port Size 16 bit */ +#define CSPR_PORT_SIZE_16 0x00000100 +/* Port Size 32 bit */ +#define CSPR_PORT_SIZE_32 0x00000180 +/* Write Protect */ +#define CSPR_WP 0x00000040 +#define CSPR_WP_SHIFT 6 +/* Machine Select */ +#define CSPR_MSEL 0x00000006 +#define CSPR_MSEL_SHIFT 1 +/* NOR */ +#define CSPR_MSEL_NOR 0x00000000 +/* NAND */ +#define CSPR_MSEL_NAND 0x00000002 +/* GPCM */ +#define CSPR_MSEL_GPCM 0x00000004 +/* Bank Valid */ +#define CSPR_V 0x00000001 +#define CSPR_V_SHIFT 0 + +/* Convert an address into the right format for the CSPR Registers */ +#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000) + +/* + * Address Mask Register + */ +#define IFC_AMASK_MASK 0xFFFF0000 +#define IFC_AMASK_SHIFT 16 +#define IFC_AMASK(n) (IFC_AMASK_MASK << \ + (__ilog2(n) - IFC_AMASK_SHIFT)) + +/* + * Chip Select Option Register IFC_NAND Machine + */ +/* Enable ECC Encoder */ +#define CSOR_NAND_ECC_ENC_EN 0x80000000 +#define CSOR_NAND_ECC_MODE_MASK 0x30000000 +/* 4 bit correction per 520 Byte sector */ +#define CSOR_NAND_ECC_MODE_4 0x00000000 +/* 8 bit correction per 528 Byte sector */ +#define CSOR_NAND_ECC_MODE_8 0x10000000 +/* Enable ECC Decoder */ +#define CSOR_NAND_ECC_DEC_EN 0x04000000 +/* Row Address Length */ +#define CSOR_NAND_RAL_MASK 0x01800000 +#define CSOR_NAND_RAL_SHIFT 20 +#define CSOR_NAND_RAL_1 0x00000000 +#define CSOR_NAND_RAL_2 0x00800000 +#define CSOR_NAND_RAL_3 0x01000000 +#define CSOR_NAND_RAL_4 0x01800000 +/* Page Size 512b, 2k, 4k */ +#define CSOR_NAND_PGS_MASK 0x00180000 +#define CSOR_NAND_PGS_SHIFT 16 +#define CSOR_NAND_PGS_512 0x00000000 +#define CSOR_NAND_PGS_2K 0x00080000 +#define CSOR_NAND_PGS_4K 0x00100000 +/* Spare region Size */ +#define CSOR_NAND_SPRZ_MASK 0x0000E000 +#define CSOR_NAND_SPRZ_SHIFT 13 +#define CSOR_NAND_SPRZ_16 0x00000000 +#define CSOR_NAND_SPRZ_64 0x00002000 +#define CSOR_NAND_SPRZ_128 0x00004000 +#define CSOR_NAND_SPRZ_210 0x00006000 +#define CSOR_NAND_SPRZ_218 0x00008000 +#define CSOR_NAND_SPRZ_224 0x0000A000 +/* Pages Per Block */ +#define CSOR_NAND_PB_MASK 0x00000700 +#define CSOR_NAND_PB_SHIFT 8 +#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NAND_TRHZ_MASK 0x0000001C +#define CSOR_NAND_TRHZ_SHIFT 2 +#define CSOR_NAND_TRHZ_20 0x00000000 +#define CSOR_NAND_TRHZ_40 0x00000004 +#define CSOR_NAND_TRHZ_60 0x00000008 +#define CSOR_NAND_TRHZ_80 0x0000000C +#define CSOR_NAND_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NAND_BCTLD 0x00000001 + +/* + * Chip Select Option Register - NOR Flash Mode + */ +/* Enable Address shift Mode */ +#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000 +/* Page Read Enable from NOR device */ +#define CSOR_NOR_PGRD_EN 0x10000000 +/* AVD Toggle Enable during Burst Program */ +#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000 +/* Address Data Multiplexing Shift */ +#define CSOR_NOR_ADM_MASK 0x0003E000 +#define CSOR_NOR_ADM_SHIFT_SHIFT 13 +#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT) +/* Type of the NOR device hooked */ +#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000 +#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020 +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_NOR_TRHZ_MASK 0x0000001C +#define CSOR_NOR_TRHZ_SHIFT 2 +#define CSOR_NOR_TRHZ_20 0x00000000 +#define CSOR_NOR_TRHZ_40 0x00000004 +#define CSOR_NOR_TRHZ_60 0x00000008 +#define CSOR_NOR_TRHZ_80 0x0000000C +#define CSOR_NOR_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_NOR_BCTLD 0x00000001 + +/* + * Chip Select Option Register - GPCM Mode + */ +/* GPCM Mode - Normal */ +#define CSOR_GPCM_GPMODE_NORMAL 0x00000000 +/* GPCM Mode - GenericASIC */ +#define CSOR_GPCM_GPMODE_ASIC 0x80000000 +/* Parity Mode odd/even */ +#define CSOR_GPCM_PARITY_EVEN 0x40000000 +/* Parity Checking enable/disable */ +#define CSOR_GPCM_PAR_EN 0x20000000 +/* GPCM Timeout Count */ +#define CSOR_GPCM_GPTO_MASK 0x0F000000 +#define CSOR_GPCM_GPTO_SHIFT 24 +#define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT) +/* GPCM External Access Termination mode for read access */ +#define CSOR_GPCM_RGETA_EXT 0x00080000 +/* GPCM External Access Termination mode for write access */ +#define CSOR_GPCM_WGETA_EXT 0x00040000 +/* Address Data Multiplexing Shift */ +#define CSOR_GPCM_ADM_MASK 0x0003E000 +#define CSOR_GPCM_ADM_SHIFT_SHIFT 13 +#define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT) +/* Generic ASIC Parity error indication delay */ +#define CSOR_GPCM_GAPERRD_MASK 0x00000180 +#define CSOR_GPCM_GAPERRD_SHIFT 7 +#define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT) +/* Time for Read Enable High to Output High Impedance */ +#define CSOR_GPCM_TRHZ_MASK 0x0000001C +#define CSOR_GPCM_TRHZ_20 0x00000000 +#define CSOR_GPCM_TRHZ_40 0x00000004 +#define CSOR_GPCM_TRHZ_60 0x00000008 +#define CSOR_GPCM_TRHZ_80 0x0000000C +#define CSOR_GPCM_TRHZ_100 0x00000010 +/* Buffer control disable */ +#define CSOR_GPCM_BCTLD 0x00000001 + +/* + * Flash Timing Registers (FTIM0 - FTIM2_CSn) + */ +/* + * FTIM0 - NAND Flash Mode + */ +#define FTIM0_NAND 0x7EFF3F3F +#define FTIM0_NAND_TCCST_SHIFT 25 +#define FTIM0_NAND_TCCST(n) ((n) << FTIM0_NAND_TCCST_SHIFT) +#define FTIM0_NAND_TWP_SHIFT 16 +#define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) +#define FTIM0_NAND_TWCHT_SHIFT 8 +#define FTIM0_NAND_TWCHT(n) ((n) << FTIM0_NAND_TWCHT_SHIFT) +#define FTIM0_NAND_TWH_SHIFT 0 +#define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) +/* + * FTIM1 - NAND Flash Mode + */ +#define FTIM1_NAND 0xFFFF3FFF +#define FTIM1_NAND_TADLE_SHIFT 24 +#define FTIM1_NAND_TADLE(n) ((n) << FTIM1_NAND_TADLE_SHIFT) +#define FTIM1_NAND_TWBE_SHIFT 16 +#define FTIM1_NAND_TWBE(n) ((n) << FTIM1_NAND_TWBE_SHIFT) +#define FTIM1_NAND_TRR_SHIFT 8 +#define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) +#define FTIM1_NAND_TRP_SHIFT 0 +#define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) +/* + * FTIM2 - NAND Flash Mode + */ +#define FTIM2_NAND 0x1FE1F8FF +#define FTIM2_NAND_TRAD_SHIFT 21 +#define FTIM2_NAND_TRAD(n) ((n) << FTIM2_NAND_TRAD_SHIFT) +#define FTIM2_NAND_TREH_SHIFT 11 +#define FTIM2_NAND_TREH(n) ((n) << FTIM2_NAND_TREH_SHIFT) +#define FTIM2_NAND_TWHRE_SHIFT 0 +#define FTIM2_NAND_TWHRE(n) ((n) << FTIM2_NAND_TWHRE_SHIFT) +/* + * FTIM3 - NAND Flash Mode + */ +#define FTIM3_NAND 0xFF000000 +#define FTIM3_NAND_TWW_SHIFT 24 +#define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) + +/* + * FTIM0 - NOR Flash Mode + */ +#define FTIM0_NOR 0xF03F3F3F +#define FTIM0_NOR_TACSE_SHIFT 28 +#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT) +#define FTIM0_NOR_TEADC_SHIFT 16 +#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT) +#define FTIM0_NOR_TAVDS_SHIFT 8 +#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT) +#define FTIM0_NOR_TEAHC_SHIFT 0 +#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT) +/* + * FTIM1 - NOR Flash Mode + */ +#define FTIM1_NOR 0xFF003F3F +#define FTIM1_NOR_TACO_SHIFT 24 +#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) +#define FTIM1_NOR_TRAD_NOR_SHIFT 8 +#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT) +#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0 +#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT) +/* + * FTIM2 - NOR Flash Mode + */ +#define FTIM2_NOR 0x0F3CFCFF +#define FTIM2_NOR_TCS_SHIFT 24 +#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) +#define FTIM2_NOR_TCH_SHIFT 18 +#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) +#define FTIM2_NOR_TWPH_SHIFT 10 +#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) +#define FTIM2_NOR_TWP_SHIFT 0 +#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) + +/* + * FTIM0 - Normal GPCM Mode + */ +#define FTIM0_GPCM 0xF03F3F3F +#define FTIM0_GPCM_TACSE_SHIFT 28 +#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT) +#define FTIM0_GPCM_TEADC_SHIFT 16 +#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT) +#define FTIM0_GPCM_TAVDS_SHIFT 8 +#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT) +#define FTIM0_GPCM_TEAHC_SHIFT 0 +#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT) +/* + * FTIM1 - Normal GPCM Mode + */ +#define FTIM1_GPCM 0xFF003F00 +#define FTIM1_GPCM_TACO_SHIFT 24 +#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT) +#define FTIM1_GPCM_TRAD_SHIFT 8 +#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT) +/* + * FTIM2 - Normal GPCM Mode + */ +#define FTIM2_GPCM 0x0F3C00FF +#define FTIM2_GPCM_TCS_SHIFT 24 +#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT) +#define FTIM2_GPCM_TCH_SHIFT 18 +#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT) +#define FTIM2_GPCM_TWP_SHIFT 0 +#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT) + +/* + * Ready Busy Status Register (RB_STAT) + */ +/* CSn is READY */ +#define IFC_RB_STAT_READY_CS0 0x80000000 +#define IFC_RB_STAT_READY_CS1 0x40000000 +#define IFC_RB_STAT_READY_CS2 0x20000000 +#define IFC_RB_STAT_READY_CS3 0x10000000 + +/* + * General Control Register (GCR) + */ +#define IFC_GCR_MASK 0x8000F800 +/* reset all IFC hardware */ +#define IFC_GCR_SOFT_RST_ALL 0x80000000 +/* Turnaroud Time of external buffer */ +#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800 +#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11 + +/* + * Common Event and Error Status Register (CM_EVTER_STAT) + */ +/* Chip select error */ +#define IFC_CM_EVTER_STAT_CSER 0x80000000 + +/* + * Common Event and Error Enable Register (CM_EVTER_EN) + */ +/* Chip select error checking enable */ +#define IFC_CM_EVTER_EN_CSEREN 0x80000000 + +/* + * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN) + */ +/* Chip select error interrupt enable */ +#define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000 + +/* + * Common Transfer Error Attribute Register-0 (CM_ERATTR0) + */ +/* transaction type of error Read/Write */ +#define IFC_CM_ERATTR0_ERTYP_READ 0x80000000 +#define IFC_CM_ERATTR0_ERAID 0x0FF00000 +#define IFC_CM_ERATTR0_ESRCID 0x0000FF00 + +/* + * Clock Control Register (CCR) + */ +#define IFC_CCR_MASK 0x0F0F8800 +/* Clock division ratio */ +#define IFC_CCR_CLK_DIV_MASK 0x0F000000 +#define IFC_CCR_CLK_DIV_SHIFT 24 +#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT) +/* IFC Clock Delay */ +#define IFC_CCR_CLK_DLY_MASK 0x000F0000 +#define IFC_CCR_CLK_DLY_SHIFT 16 +#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT) +/* Invert IFC clock before sending out */ +#define IFC_CCR_INV_CLK_EN 0x00008000 +/* Fedback IFC Clock */ +#define IFC_CCR_FB_IFC_CLK_SEL 0x00000800 + +/* + * Clock Status Register (CSR) + */ +/* Clk is stable */ +#define IFC_CSR_CLK_STAT_STABLE 0x80000000 + +/* + * IFC_NAND Machine Specific Registers + */ +/* + * NAND Configuration Register (NCFGR) + */ +/* Auto Boot Mode */ +#define IFC_NAND_NCFGR_BOOT 0x80000000 +/* Addressing Mode-ROW0+n/COL0 */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000 +/* Addressing Mode-ROW0+n/COL0+n */ +#define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000 +/* Number of loop iterations of FIR sequences for multi page operations */ +#define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000 +#define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12 +#define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT) +/* Number of wait cycles */ +#define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF +#define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF000000 +#define IFC_NAND_FCR0_CMD0_SHIFT 24 +#define IFC_NAND_FCR0_CMD1 0x00FF0000 +#define IFC_NAND_FCR0_CMD1_SHIFT 16 +#define IFC_NAND_FCR0_CMD2 0x0000FF00 +#define IFC_NAND_FCR0_CMD2_SHIFT 8 +#define IFC_NAND_FCR0_CMD3 0x000000FF +#define IFC_NAND_FCR0_CMD3_SHIFT 0 +#define IFC_NAND_FCR1_CMD4 0xFF000000 +#define IFC_NAND_FCR1_CMD4_SHIFT 24 +#define IFC_NAND_FCR1_CMD5 0x00FF0000 +#define IFC_NAND_FCR1_CMD5_SHIFT 16 +#define IFC_NAND_FCR1_CMD6 0x0000FF00 +#define IFC_NAND_FCR1_CMD6_SHIFT 8 +#define IFC_NAND_FCR1_CMD7 0x000000FF +#define IFC_NAND_FCR1_CMD7_SHIFT 0 + +/* + * Flash ROW and COL Address Register (ROWn, COLn) + */ +/* Main/spare region locator */ +#define IFC_NAND_COL_MS 0x80000000 +/* Column Address */ +#define IFC_NAND_COL_CA_MASK 0x00000FFF + +/* + * NAND Flash Byte Count Register (NAND_BC) + */ +/* Byte Count for read/Write */ +#define IFC_NAND_BC 0x000001FF + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC000000 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F00000 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x00003F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x000000FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC000000 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F00000 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x00003F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x000000FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC000000 +#define IFC_NAND_FIR2_OP10_SHIFT 26 +#define IFC_NAND_FIR2_OP11 0x03F00000 +#define IFC_NAND_FIR2_OP11_SHIFT 20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT 14 +#define IFC_NAND_FIR2_OP13 0x00003F00 +#define IFC_NAND_FIR2_OP13_SHIFT 8 +#define IFC_NAND_FIR2_OP14 0x000000FC +#define IFC_NAND_FIR2_OP14_SHIFT 2 + +/* + * Instruction opcodes to be programmed + * in FIR registers- 6bits + */ +enum ifc_nand_fir_opcodes { + IFC_FIR_OP_NOP, + IFC_FIR_OP_CA0, + IFC_FIR_OP_CA1, + IFC_FIR_OP_CA2, + IFC_FIR_OP_CA3, + IFC_FIR_OP_RA0, + IFC_FIR_OP_RA1, + IFC_FIR_OP_RA2, + IFC_FIR_OP_RA3, + IFC_FIR_OP_CMD0, + IFC_FIR_OP_CMD1, + IFC_FIR_OP_CMD2, + IFC_FIR_OP_CMD3, + IFC_FIR_OP_CMD4, + IFC_FIR_OP_CMD5, + IFC_FIR_OP_CMD6, + IFC_FIR_OP_CMD7, + IFC_FIR_OP_CW0, + IFC_FIR_OP_CW1, + IFC_FIR_OP_CW2, + IFC_FIR_OP_CW3, + IFC_FIR_OP_CW4, + IFC_FIR_OP_CW5, + IFC_FIR_OP_CW6, + IFC_FIR_OP_CW7, + IFC_FIR_OP_WBCD, + IFC_FIR_OP_RBCD, + IFC_FIR_OP_BTRD, + IFC_FIR_OP_RDSTAT, + IFC_FIR_OP_NWAIT, + IFC_FIR_OP_WFR, + IFC_FIR_OP_SBRD, + IFC_FIR_OP_UA, + IFC_FIR_OP_RB, +}; + +/* + * NAND Chip Select Register (NAND_CSEL) + */ +#define IFC_NAND_CSEL 0x0C000000 +#define IFC_NAND_CSEL_SHIFT 26 +#define IFC_NAND_CSEL_CS0 0x00000000 +#define IFC_NAND_CSEL_CS1 0x04000000 +#define IFC_NAND_CSEL_CS2 0x08000000 +#define IFC_NAND_CSEL_CS3 0x0C000000 + +/* + * NAND Operation Sequence Start (NANDSEQ_STRT) + */ +/* NAND Flash Operation Start */ +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000 +/* Automatic Erase */ +#define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000 +/* Automatic Program */ +#define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000 +/* Automatic Copyback */ +#define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000 +/* Automatic Read Operation */ +#define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000 +/* Automatic Status Read */ +#define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x80000000 +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x08000000 +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER 0x04000000 +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x02000000 +/* RCW Load Done */ +#define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000 +/* Boot Loadr Done */ +#define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000 +/* Bad Block Indicator search select */ +#define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800 + +/* + * NAND Flash Page Read Completion Event Status Register + * (PGRDCMPL_EVT_STAT) + */ +#define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000 +/* Small Page 0-15 Done */ +#define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n))) +/* Large Page(2K) 0-3 Done */ +#define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4)) +/* Large Page(4K) 0-1 Done */ +#define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8)) + +/* + * NAND Event and Error Enable Register (NAND_EVTER_EN) + */ +/* Operation complete event enable */ +#define IFC_NAND_EVTER_EN_OPC_EN 0x80000000 +/* Page read complete event enable */ +#define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000 +/* Flash Timeout error enable */ +#define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000 +/* Write Protect error enable */ +#define IFC_NAND_EVTER_EN_WPER_EN 0x04000000 +/* ECC error logging enable */ +#define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000 + +/* + * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN) + */ +/* Enable interrupt for operation complete */ +#define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000 +/* Enable interrupt for Page read complete */ +#define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000 +/* Enable interrupt for Flash timeout error */ +#define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000 +/* Enable interrupt for Write protect error */ +#define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000 +/* Enable interrupt for ECC error*/ +#define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000 + +/* + * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0) + */ +#define IFC_NAND_ERATTR0_MASK 0x0C080000 +/* Error on CS0-3 for NAND */ +#define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000 +#define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000 +#define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000 +/* Transaction type of error Read/Write */ +#define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000 + +/* + * NAND Flash Status Register (NAND_FSR) + */ +/* First byte of data read from read status op */ +#define IFC_NAND_NFSR_RS0 0xFF000000 +/* Second byte of data read from read status op */ +#define IFC_NAND_NFSR_RS1 0x00FF0000 + +/* + * ECC Error Status Registers (ECCSTAT0-ECCSTAT3) + */ +/* Number of ECC errors on sector n (n = 0-15) */ +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8 +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F +#define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8 +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F +#define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8 +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F +#define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8 +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F +#define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0 + +/* + * NAND Control Register (NANDCR) + */ +#define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000 +#define IFC_NAND_NCR_FTOCNT_SHIFT 25 +#define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT) + +/* + * NAND_AUTOBOOT_TRGR + */ +/* Trigger RCW load */ +#define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000 +/* Trigget Auto Boot */ +#define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000 + +/* + * NAND_MDR + */ +/* 1st read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA0 0xFF000000 +/* 2nd read data byte when opcode SBRD */ +#define IFC_NAND_MDR_RDATA1 0x00FF0000 + +/* + * NOR Machine Specific Registers + */ +/* + * NOR Event and Error Status Register (NOR_EVTER_STAT) + */ +/* NOR Command Sequence Operation Complete */ +#define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000 +/* Write Protect Error */ +#define IFC_NOR_EVTER_STAT_WPER 0x04000000 +/* Command Sequence Timeout Error */ +#define IFC_NOR_EVTER_STAT_STOER 0x01000000 + +/* + * NOR Event and Error Enable Register (NOR_EVTER_EN) + */ +/* NOR Command Seq complete event enable */ +#define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000 +/* Write Protect Error Checking Enable */ +#define IFC_NOR_EVTER_EN_WPEREN 0x04000000 +/* Timeout Error Enable */ +#define IFC_NOR_EVTER_EN_STOEREN 0x01000000 + +/* + * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN) + */ +/* Enable interrupt for OPC complete */ +#define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000 +/* Enable interrupt for write protect error */ +#define IFC_NOR_EVTER_INTR_WPEREN 0x04000000 +/* Enable interrupt for timeout error */ +#define IFC_NOR_EVTER_INTR_STOEREN 0x01000000 + +/* + * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_NOR_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transation */ +#define IFC_NOR_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to NOR error */ +#define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010 +#define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020 +#define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030 +/* Type of transaction read/write */ +#define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2) + */ +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000 +#define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00 + +/* + * NOR Control Register (NORCR) + */ +#define IFC_NORCR_MASK 0x0F0F0000 +/* No. of Address/Data Phase */ +#define IFC_NORCR_NUM_PHASE_MASK 0x0F000000 +#define IFC_NORCR_NUM_PHASE_SHIFT 24 +#define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT) +/* Sequence Timeout Count */ +#define IFC_NORCR_STOCNT_MASK 0x000F0000 +#define IFC_NORCR_STOCNT_SHIFT 16 +#define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT) + +/* + * GPCM Machine specific registers + */ +/* + * GPCM Event and Error Status Register (GPCM_EVTER_STAT) + */ +/* Timeout error */ +#define IFC_GPCM_EVTER_STAT_TOER 0x04000000 +/* Parity error */ +#define IFC_GPCM_EVTER_STAT_PER 0x01000000 + +/* + * GPCM Event and Error Enable Register (GPCM_EVTER_EN) + */ +/* Timeout error enable */ +#define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000 +/* Parity error enable */ +#define IFC_GPCM_EVTER_EN_PER_EN 0x01000000 + +/* + * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN) + */ +/* Enable Interrupt for timeout error */ +#define IFC_GPCM_EEIER_TOERIR_EN 0x04000000 +/* Enable Interrupt for Parity error */ +#define IFC_GPCM_EEIER_PERIR_EN 0x01000000 + +/* + * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0) + */ +/* Source ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000 +/* AXI ID for error transaction */ +#define IFC_GPCM_ERATTR0_ERAID 0x000FF000 +/* Chip select corresponds to GPCM error */ +#define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000 +#define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040 +#define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080 +#define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0 +/* Type of transaction read/Write */ +#define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001 + +/* + * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2) + */ +/* On which beat of address/data parity error is observed */ +#define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00 +/* Parity Error on byte */ +#define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0 +/* Parity Error reported in addr or data phase */ +#define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001 + +/* + * GPCM Status Register (GPCM_STAT) + */ +#define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */ + + +#ifndef __ASSEMBLY__ +#include + +extern void print_ifc_regs(void); +extern void init_early_memctl_regs(void); + +#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) + +#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define set_ifc_ftim(i, j, v) \ + (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + +enum ifc_chip_sel { + IFC_CS0, + IFC_CS1, + IFC_CS2, + IFC_CS3, + IFC_CS4, + IFC_CS5, + IFC_CS6, + IFC_CS7, +}; + +enum ifc_ftims { + IFC_FTIM0, + IFC_FTIM1, + IFC_FTIM2, + IFC_FTIM3, +}; + +/* + * IFC Controller NAND Machine registers + */ +struct fsl_ifc_nand { + u32 ncfgr; + u32 res1[0x4]; + u32 nand_fcr0; + u32 nand_fcr1; + u32 res2[0x8]; + u32 row0; + u32 res3; + u32 col0; + u32 res4; + u32 row1; + u32 res5; + u32 col1; + u32 res6; + u32 row2; + u32 res7; + u32 col2; + u32 res8; + u32 row3; + u32 res9; + u32 col3; + u32 res10[0x24]; + u32 nand_fbcr; + u32 res11; + u32 nand_fir0; + u32 nand_fir1; + u32 nand_fir2; + u32 res12[0x10]; + u32 nand_csel; + u32 res13; + u32 nandseq_strt; + u32 res14; + u32 nand_evter_stat; + u32 res15; + u32 pgrdcmpl_evt_stat; + u32 res16[0x2]; + u32 nand_evter_en; + u32 res17[0x2]; + u32 nand_evter_intr_en; + u32 res18[0x2]; + u32 nand_erattr0; + u32 nand_erattr1; + u32 res19[0x10]; + u32 nand_fsr; + u32 res20; + u32 nand_eccstat[4]; + u32 res21[0x20]; + u32 nanndcr; + u32 res22[0x2]; + u32 nand_autoboot_trgr; + u32 res23; + u32 nand_mdr; + u32 res24[0x5C]; +}; + +/* + * IFC controller NOR Machine registers + */ +struct fsl_ifc_nor { + u32 nor_evter_stat; + u32 res1[0x2]; + u32 nor_evter_en; + u32 res2[0x2]; + u32 nor_evter_intr_en; + u32 res3[0x2]; + u32 nor_erattr0; + u32 nor_erattr1; + u32 nor_erattr2; + u32 res4[0x4]; + u32 norcr; + u32 res5[0xEF]; +}; + +/* + * IFC controller GPCM Machine registers + */ +struct fsl_ifc_gpcm { + u32 gpcm_evter_stat; + u32 res1[0x2]; + u32 gpcm_evter_en; + u32 res2[0x2]; + u32 gpcm_evter_intr_en; + u32 res3[0x2]; + u32 gpcm_erattr0; + u32 gpcm_erattr1; + u32 gpcm_erattr2; + u32 gpcm_stat; + u32 res4[0x1F3]; +}; + +#ifdef CONFIG_SYS_FSL_IFC_BANK_COUNT +#if (CONFIG_SYS_FSL_IFC_BANK_COUNT <= 8) +#define IFC_CSPR_REG_LEN 148 +#define IFC_AMASK_REG_LEN 144 +#define IFC_CSOR_REG_LEN 144 +#define IFC_FTIM_REG_LEN 576 + +#define IFC_CSPR_USED_LEN sizeof(struct fsl_ifc_cspr) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#define IFC_AMASK_USED_LEN sizeof(struct fsl_ifc_amask) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#define IFC_CSOR_USED_LEN sizeof(struct fsl_ifc_csor) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#define IFC_FTIM_USED_LEN sizeof(struct fsl_ifc_ftim) * \ + CONFIG_SYS_FSL_IFC_BANK_COUNT +#else +#error IFC BANK count not vaild +#endif +#else +#error IFC BANK count not defined +#endif + +struct fsl_ifc_cspr { + u32 cspr_ext; + u32 cspr; + u32 res; +}; + +struct fsl_ifc_amask { + u32 amask; + u32 res[0x2]; +}; + +struct fsl_ifc_csor { + u32 csor; + u32 csor_ext; + u32 res; +}; + +struct fsl_ifc_ftim { + u32 ftim[4]; + u32 res[0x8]; +}; + +/* + * IFC Controller Registers + */ +struct fsl_ifc { + u32 ifc_rev; + u32 res1[0x2]; + struct fsl_ifc_cspr cspr_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res2[IFC_CSPR_REG_LEN - IFC_CSPR_USED_LEN]; + struct fsl_ifc_amask amask_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res3[IFC_AMASK_REG_LEN - IFC_AMASK_USED_LEN]; + struct fsl_ifc_csor csor_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res4[IFC_CSOR_REG_LEN - IFC_CSOR_USED_LEN]; + struct fsl_ifc_ftim ftim_cs[CONFIG_SYS_FSL_IFC_BANK_COUNT]; + u8 res5[IFC_FTIM_REG_LEN - IFC_FTIM_USED_LEN]; + u32 rb_stat; + u32 res6[0x2]; + u32 ifc_gcr; + u32 res7[0x2]; + u32 cm_evter_stat; + u32 res8[0x2]; + u32 cm_evter_en; + u32 res9[0x2]; + u32 cm_evter_intr_en; + u32 res10[0x2]; + u32 cm_erattr0; + u32 cm_erattr1; + u32 res11[0x2]; + u32 ifc_ccr; + u32 ifc_csr; + u32 res12[0x2EB]; + struct fsl_ifc_nand ifc_nand; + struct fsl_ifc_nor ifc_nor; + struct fsl_ifc_gpcm ifc_gpcm; +}; + +#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 +#undef CSPR_MSEL_NOR +#define CSPR_MSEL_NOR CSPR_MSEL_GPCM +#endif +#endif /* CONFIG_FSL_IFC */ + +#endif /* __ASSEMBLY__ */ +#endif /* __FSL_IFC_H */ -- cgit v1.2.1 From 82a55c1ef87bb6c596b19e83685cc4cbf0344cb3 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 22 Nov 2013 17:39:09 +0800 Subject: net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu --- arch/powerpc/include/asm/fsl_serdes.h | 2 ++ arch/powerpc/include/asm/immap_85xx.h | 2 ++ drivers/net/fm/eth.c | 12 ++++++++++-- drivers/net/fm/fm.h | 2 ++ drivers/net/fm/init.c | 18 ++++++++++++++---- include/fm_eth.h | 18 ++++++++++++++++++ 6 files changed, 48 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index cce892ce90..404ded4580 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -62,6 +62,8 @@ enum srds_prtcl { QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ QSGMII_FM2_A, QSGMII_FM2_B, + XFI_FM1_MAC1, + XFI_FM1_MAC2, XFI_FM1_MAC9, XFI_FM1_MAC10, XFI_FM2_MAC9, diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b386ee6b2..882b0b15eb 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1621,6 +1621,8 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 +#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 +#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index cb099cd849..218a5ed175 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -557,8 +557,16 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg) num = fm_eth->num; #ifdef CONFIG_SYS_FMAN_V3 - if (fm_eth->type == FM_ETH_10G_E) - num += 8; + if (fm_eth->type == FM_ETH_10G_E) { + /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 + * 10GEC3/10GEC4 use mEMAC1/mEMAC2 + * so it needs to change the num. + */ + if (fm_eth->num >= 2) + num -= 2; + else + num += 8; + } base = ®->memac[num].fm_memac; phyregs = ®->memac[num].fm_memac_mdio; #else diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h index 3ec49a4f3b..43de114b52 100644 --- a/drivers/net/fm/fm.h +++ b/drivers/net/fm/fm.h @@ -18,9 +18,11 @@ #define RX_PORT_1G_BASE 0x08 #define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC #define RX_PORT_10G_BASE 0x10 +#define RX_PORT_10G_BASE2 0x08 #define TX_PORT_1G_BASE 0x28 #define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC #define TX_PORT_10G_BASE 0x30 +#define TX_PORT_10G_BASE2 0x28 #define MIIM_TIMEOUT 0xFFFF struct fm_muram { diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 35edd7ad94..cd787f4eed 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -64,6 +64,12 @@ struct fm_eth_info fm_info[] = { #if (CONFIG_SYS_NUM_FM1_10GEC >= 2) FM_TGEC_INFO_INITIALIZER(1, 2), #endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) + FM_TGEC_INFO_INITIALIZER2(1, 3), +#endif +#if (CONFIG_SYS_NUM_FM1_10GEC >= 4) + FM_TGEC_INFO_INITIALIZER2(1, 4), +#endif #if (CONFIG_SYS_NUM_FM2_10GEC >= 1) FM_TGEC_INFO_INITIALIZER(2, 1), #endif @@ -239,10 +245,14 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) * FM1_10GEC1 is enabled and FM1_DTSEC9 is disabled, ensure that the * dual-role MAC is not disabled, ditto for other dual-role MACs. */ - if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || - ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || - ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || - ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) + if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) || + ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) || + ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) || + ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) || + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) || + ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) || + ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) || + ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2))) #if (CONFIG_SYS_NUM_FMAN == 2) || ((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) || diff --git a/include/fm_eth.h b/include/fm_eth.h index 5a4fb70dfa..98edfcf4ad 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -22,6 +22,8 @@ enum fm_port { FM1_DTSEC10, FM1_10GEC1, FM1_10GEC2, + FM1_10GEC3, + FM1_10GEC4, FM2_DTSEC1, FM2_DTSEC2, FM2_DTSEC3, @@ -85,6 +87,22 @@ enum fm_eth_type { .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } + +#if (CONFIG_SYS_NUM_FM1_10GEC >= 3) +#define FM_TGEC_INFO_INITIALIZER2(idx, n) \ +{ \ + FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \ + .index = idx, \ + .num = n - 1, \ + .type = FM_ETH_10G_E, \ + .port = FM##idx##_10GEC##n, \ + .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \ + .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \ + .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + offsetof(struct ccsr_fman, memac[n-1-2]),\ +} +#endif + #else #define FM_DTSEC_INFO_INITIALIZER(idx, n) \ { \ -- cgit v1.2.1 From 629d6b32d6b9452b852fe79a195cca5b897fcad3 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 22 Nov 2013 17:39:10 +0800 Subject: powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu Acked-by: York Sun --- arch/powerpc/cpu/mpc85xx/Makefile | 4 + arch/powerpc/cpu/mpc85xx/speed.c | 2 +- arch/powerpc/cpu/mpc85xx/t2080_ids.c | 142 ++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/t2080_serdes.c | 208 ++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 2 + arch/powerpc/include/asm/config_mpc85xx.h | 44 +++++++ arch/powerpc/include/asm/immap_85xx.h | 16 +++ arch/powerpc/include/asm/processor.h | 2 + drivers/net/fm/Makefile | 2 + drivers/net/fm/t2080.c | 91 +++++++++++++ 10 files changed, 512 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/cpu/mpc85xx/t2080_ids.c create mode 100644 arch/powerpc/cpu/mpc85xx/t2080_serdes.c create mode 100644 drivers/net/fm/t2080.c diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 91c8402047..ef7637a49c 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -50,6 +50,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_ids.o obj-$(CONFIG_PPC_T1042) += t1040_ids.o obj-$(CONFIG_PPC_T1020) += t1040_ids.o obj-$(CONFIG_PPC_T1022) += t1040_ids.o +obj-$(CONFIG_PPC_T2080) += t2080_ids.o +obj-$(CONFIG_PPC_T2081) += t2080_ids.o obj-$(CONFIG_QE) += qe_io.o @@ -93,6 +95,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_serdes.o obj-$(CONFIG_PPC_T1042) += t1040_serdes.o obj-$(CONFIG_PPC_T1020) += t1040_serdes.o obj-$(CONFIG_PPC_T1022) += t1040_serdes.o +obj-$(CONFIG_PPC_T2080) += t2080_serdes.o +obj-$(CONFIG_PPC_T2081) += t2080_serdes.o obj-y += cpu.o obj-y += cpu_init.o diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d08a8d212d..1a58a194f9 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -122,7 +122,7 @@ void get_sys_info(sys_info_t *sys_info) sys_info->freq_processor[cpu] = freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel]; } -#ifdef CONFIG_PPC_B4860 +#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 #else diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c new file mode 100644 index 0000000000..068e1f26bf --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -0,0 +1,142 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), + SET_QP_INFO(11, 37, 1, 1), + SET_QP_INFO(12, 38, 1, 1), + SET_QP_INFO(13, 39, 1, 2), + SET_QP_INFO(14, 40, 1, 2), + SET_QP_INFO(15, 41, 1, 3), + SET_QP_INFO(16, 42, 1, 3), + SET_QP_INFO(17, 43, 1, 0), + SET_QP_INFO(18, 44, 1, 0), +}; +#endif + +#ifdef CONFIG_SYS_SRIO +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_BASE(1, 307), + SET_SRIO_LIODN_BASE(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_PME_LIODN(117), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(3, 226), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + +#ifdef CONFIG_SYS_PMAN + SET_PMAN_LIODN(1, 513), + SET_PMAN_LIODN(2, 514), + SET_PMAN_LIODN(3, 515), +#endif + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { +#ifdef CONFIG_SYS_DPAA_DCE + [FSL_HW_PORTAL_DCE] = SET_LIODN_BASE_2(618, 694), +#endif + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c new file mode 100644 index 0000000000..f2fbdebec1 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -0,0 +1,208 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, + PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} }, + {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, PCIE1, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, +#if defined(CONFIG_PPC_T2080) + {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + HIGIG_FM1_MAC9, HIGIG_FM1_MAC9, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4, + PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, + SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE3, PCIE3, PCIE3, PCIE3} }, + {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10, + XFI_FM1_MAC1, XFI_FM1_MAC2, + PCIE4, PCIE4, PCIE4, PCIE4} }, + +#elif defined(CONFIG_PPC_T2081) + {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3, + PCIE4, PCIE4, PCIE4, PCIE4} }, + {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, + SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, +#endif + {} +}; + +#ifndef CONFIG_PPC_T2081 +static const struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} }, + {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, + {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, + {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} }, + {} +}; +#endif + +static const struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, +#ifndef CONFIG_PPC_T2081 + serdes2_cfg_tbl, +#endif +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + const struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index c67be4ef29..35795c4fbe 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -75,6 +75,8 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T1020, T1020, 0), CPU_TYPE_ENTRY(T1021, T1021, 0), CPU_TYPE_ENTRY(T1022, T1022, 0), + CPU_TYPE_ENTRY(T2080, T2080, 0), + CPU_TYPE_ENTRY(T2081, T2081, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), CPU_TYPE_ENTRY(BSC9132, 9132, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 047fdf1d8c..99e16bdf63 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -718,6 +718,50 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define CONFIG_E6500 +#define CONFIG_SYS_PPC64 /* 64-bit core */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 +#define CONFIG_SYS_FSL_QMAN_V3 +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_PCI_VER_3_X +#if defined(CONFIG_PPC_T2080) +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 4 +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_FSL_SRIO_LIODN +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#elif defined(CONFIG_PPC_T2081) +#define CONFIG_SYS_NUM_FM1_DTSEC 6 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#endif +#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_PME_PLAT_CLK_DIV 1 +#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_SFP_VER_3_0 +#define CONFIG_SYS_FSL_ISBC_VER 2 + #elif defined(CONFIG_PPC_C29X) #define CONFIG_MAX_CPUS 1 #define CONFIG_FSL_SDHC_V2_3 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 882b0b15eb..672e8c6650 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,6 +1759,12 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 #endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 @@ -1821,6 +1827,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#endif +#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) +#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ +#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 +#define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ +#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 +#define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 #endif u8 res18[192]; u32 scratchrw[4]; /* Scratch Read/Write */ @@ -2818,6 +2833,7 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 +#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 81f9d38e79..831804c5c5 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1127,6 +1127,8 @@ #define SVR_T1020 0x852100 #define SVR_T1021 0x852101 #define SVR_T1022 0x852102 +#define SVR_T2080 0x853000 +#define SVR_T2081 0x853100 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index d0fd7fccee..ee5d768937 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_PPC_T1040) += t1040.o obj-$(CONFIG_PPC_T1042) += t1040.o obj-$(CONFIG_PPC_T1020) += t1040.o obj-$(CONFIG_PPC_T1022) += t1040.o +obj-$(CONFIG_PPC_T2080) += t2080.o +obj-$(CONFIG_PPC_T2081) += t2080.o obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c new file mode 100644 index 0000000000..b5c1e9f76e --- /dev/null +++ b/drivers/net/fm/t2080.c @@ -0,0 +1,91 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2, + [FM1_10GEC3] = FSL_CORENET_DEVDISR2_10GEC1_3, + [FM1_10GEC4] = FSL_CORENET_DEVDISR2_10GEC1_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1 || port == FM1_10GEC2 || + port == FM1_10GEC3 || port == FM1_10GEC4) && + ((is_serdes_configured(XAUI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC1)) || + (is_serdes_configured(XFI_FM1_MAC2)) || + (is_serdes_configured(XFI_FM1_MAC9)) || + (is_serdes_configured(XFI_FM1_MAC10)))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC10) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} -- cgit v1.2.1 From c4d0e81156a4b5108057eeaa3999e2aa27b10d4c Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 22 Nov 2013 17:39:11 +0800 Subject: powerpc/t2080qds: add support for t2080qds board The T2080QDS is a high-performance computing evaluation, development and test platform supporting the T2080 QorIQ Power Architecture processor. T2080QDS feature overview Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz Memory: - Single memory controller capable of supporting DDR3 and DDR3-LV devices - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - Four 10Gbps XFI on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) PCIE: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) SATA: - Two SATA 2.0 ports on-board SRIO: - Two Serial RapidIO 2.0 ports up to 5 GHz eSDHC: - Supports SD/SDHC/SDXC/eMMC Card I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT Signed-off-by: Shengzhou Liu [York Sun: removed Makefile blank line at EOF, fix conflicts with moving DDR driver] Acked-by: York Sun --- board/freescale/t2080qds/Makefile | 12 + board/freescale/t2080qds/ddr.c | 127 +++++ board/freescale/t2080qds/ddr.h | 85 ++++ board/freescale/t2080qds/eth_t2080qds.c | 511 +++++++++++++++++++ board/freescale/t2080qds/law.c | 34 ++ board/freescale/t2080qds/pci.c | 23 + board/freescale/t2080qds/t2080qds.c | 324 ++++++++++++ board/freescale/t2080qds/t2080qds.h | 13 + board/freescale/t2080qds/t2080qds_qixis.h | 47 ++ board/freescale/t2080qds/tlb.c | 146 ++++++ boards.cfg | 1 + include/configs/T2080QDS.h | 803 ++++++++++++++++++++++++++++++ 12 files changed, 2126 insertions(+) create mode 100644 board/freescale/t2080qds/Makefile create mode 100644 board/freescale/t2080qds/ddr.c create mode 100644 board/freescale/t2080qds/ddr.h create mode 100644 board/freescale/t2080qds/eth_t2080qds.c create mode 100644 board/freescale/t2080qds/law.c create mode 100644 board/freescale/t2080qds/pci.c create mode 100644 board/freescale/t2080qds/t2080qds.c create mode 100644 board/freescale/t2080qds/t2080qds.h create mode 100644 board/freescale/t2080qds/t2080qds_qixis.h create mode 100644 board/freescale/t2080qds/tlb.c create mode 100644 include/configs/T2080QDS.h diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t2080qds/Makefile new file mode 100644 index 0000000000..0b8747b877 --- /dev/null +++ b/board/freescale/t2080qds/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_T2080QDS) += t2080qds.o +obj-$(CONFIG_T2080QDS) += eth_t2080qds.o +obj-$(CONFIG_PCI) += pci.o +obj-y += ddr.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c new file mode 100644 index 0000000000..5db5d21622 --- /dev/null +++ b/board/freescale/t2080qds/ddr.c @@ -0,0 +1,127 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twot_en = pbsp->force_2t; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found"); + printf("for data rate %lu MT/s\n", ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twot_en = pbsp_highest->force_2t; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h new file mode 100644 index 0000000000..964eaada18 --- /dev/null +++ b/board/freescale/t2080qds/ddr.h @@ -0,0 +1,85 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ + +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0}, + {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, + {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0}, + {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, + {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t2080qds/eth_t2080qds.c new file mode 100644 index 0000000000..3613f93981 --- /dev/null +++ b/board/freescale/t2080qds/eth_t2080qds.c @@ -0,0 +1,511 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * Shengzhou Liu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/qixis.h" +#include "../common/fman.h" +#include "t2080qds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII1 0 +#define EMI1_RGMII2 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT2 6 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI2 7 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T2080QDS_MDIO_RGMII1", + "T2080QDS_MDIO_RGMII2", + "T2080QDS_MDIO_SLOT1", + "T2080QDS_MDIO_SLOT3", + "T2080QDS_MDIO_SLOT4", + "T2080QDS_MDIO_SLOT5", + "T2080QDS_MDIO_SLOT2", + "T2080QDS_MDIO_10GC", +}; + +/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ +static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; + +static const char *T2080qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = T2080qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +struct T2080qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static void T2080qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval < 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct T2080qds_mdio *priv = bus->priv; + + T2080qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct T2080qds_mdio *priv = bus->priv; + + T2080qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int T2080qds_mdio_reset(struct mii_dev *bus) +{ + struct T2080qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int T2080qds_mdio_init(char *realbusname, u8 muxval) +{ + struct T2080qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate T2080QDS MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate T2080QDS private data\n"); + free(bus); + return -1; + } + + bus->read = T2080qds_mdio_read; + bus->write = T2080qds_mdio_write; + bus->reset = T2080qds_mdio_reset; + sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + int phy; + char alias[20]; + struct fixed_link f_link; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + phy = fm_info_get_phy_address(port); + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC9: + case FM1_DTSEC10: + sprintf(alias, "phy_sgmii_s3_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case FM1_DTSEC5: + case FM1_DTSEC6: + if (mdio_mux[port] == EMI1_SLOT1) { + sprintf(alias, "phy_sgmii_s1_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot1"); + } else if (mdio_mux[port] == EMI1_SLOT2) { + sprintf(alias, "phy_sgmii_s2_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + fdt_status_okay_by_alias(fdt, "emi1_slot2"); + } + break; + default: + break; + } + + } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { + switch (srds_s1) { + case 0x66: /* XFI interface */ + case 0x6b: + case 0x6c: + case 0x6d: + case 0x71: + f_link.phy_id = port; + f_link.duplex = 1; + f_link.link_speed = 10000; + f_link.pause = 0; + f_link.asym_pause = 0; + /* no PHY for XFI */ + fdt_delprop(fdt, offset, "phy-handle"); + fdt_setprop(fdt, offset, "fixed-link", &f_link, + sizeof(f_link)); + break; + default: + break; + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +/* + * This function reads RCW to check if Serdes1{E,F,G,H} is configured + * as slot 1/2/3 and update the lane_to_slot[] array accordingly + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (srds_s1) { + case 0x51: + case 0x5f: + case 0x65: + case 0x6b: + case 0x71: + lane_to_slot[5] = 2; + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + case 0xd3: + case 0xd9: + case 0xcb: + lane_to_slot[6] = 2; + lane_to_slot[7] = 2; + break; + case 0xda: + lane_to_slot[4] = 3; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + default: + break; + } +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, idx, lane, slot, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + u32 srds_s1; + + srds_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); + T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); + T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); + + /* Set the two on-board RGMII PHY address */ + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); + else + fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); + + switch (srds_s1) { + case 0x1c: + case 0x95: + case 0xa2: + case 0x94: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x51: + case 0x5f: + case 0x65: + /* XAUI/HiGig in Slot3 */ + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0x66: + /* + * XFI does not need a PHY to work, but to avoid U-boot use + * default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to XFI + * MAC, and should not use a real XAUI PHY address, since + * MDIO can access it successfully, and then MDIO thinks + * the XAUI card is used for the XFI MAC, which will cause + * error. + */ + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + break; + case 0x6b: + fm_info_set_phy_address(FM1_10GEC1, 4); + fm_info_set_phy_address(FM1_10GEC2, 5); + fm_info_set_phy_address(FM1_10GEC3, 6); + fm_info_set_phy_address(FM1_10GEC4, 7); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x6c: + case 0x6d: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0x71: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa6: + case 0x8e: + case 0x8f: + case 0x82: + case 0x83: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + case 0xa4: + case 0x96: + case 0x8a: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + break; + case 0xd9: + case 0xd3: + case 0xcb: + /* SGMII in Slot3 */ + fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); + /* SGMII in Slot2 */ + fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); + break; + default: + puts("Invalid SerDes1 protocol for T2080QDS\n"); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + case 2: + mdio_mux[i] = EMI1_SLOT2; + fm_info_set_mdio(i, mii_dev_for_muxval( + mdio_mux[i])); + break; + }; + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC3) + mdio_mux[i] = EMI1_RGMII1; + else if (i == FM1_DTSEC4 || FM1_DTSEC10) + mdio_mux[i] = EMI1_RGMII2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + idx = i - FM1_10GEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + if (srds_s1 == 0x51) { + lane = serdes_get_first_lane(FSL_SRDS_1, + XAUI_FM1_MAC9 + idx); + } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { + lane = serdes_get_first_lane(FSL_SRDS_1, + HIGIG_FM1_MAC9 + idx); + } else { + if (i == FM1_10GEC1 || i == FM1_10GEC2) + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC9 + idx); + else + lane = serdes_get_first_lane(FSL_SRDS_1, + XFI_FM1_MAC1 + idx); + } + + if (lane < 0) + break; + mdio_mux[i] = EMI2; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + + if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || + (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || + (srds_s1 == 0x71)) { + /* As XFI is in cage intead of a slot, so + * ensure doesn't disable the corresponding port + */ + break; + } + + slot = lane_to_slot[lane]; + if (QIXIS_READ(present2) & (1 << (slot - 1))) + fm_disable_port(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t2080qds/law.c new file mode 100644 index 0000000000..74e2a53a8f --- /dev/null +++ b/board/freescale/t2080qds/law.c @@ -0,0 +1,34 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef QIXIS_BASE_PHYS + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t2080qds/pci.c new file mode 100644 index 0000000000..84a89dad4f --- /dev/null +++ b/board/freescale/t2080qds/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2007-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t2080qds/t2080qds.c new file mode 100644 index 0000000000..cac32fe73c --- /dev/null +++ b/board/freescale/t2080qds/t2080qds.c @@ -0,0 +1,324 @@ +/* + * Copyright 2009-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "t2080qds.h" +#include "t2080qds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->arch.cpu; + static const char *freq[4] = { + "100.00MHZ(from 8T49N222A)", "125.00MHz", + "156.25MHZ", "100.00MHz" + }; + + printf("Board: %sQDS, ", cpu->name); + sw = QIXIS_READ(arch); + printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4); + printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank%d\n", sw); + else if (sw == 0x8) + puts("Promjet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), + qixis_read_tag(buf), (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + puts("SERDES Reference Clocks:\n"); + sw = QIXIS_READ(brdcfg[2]); + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6], + freq[(sw >> 4) & 0x3]); + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2], + freq[sw & 0x3]); + + return 0; +} + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int brd_mux_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + switch (srds_prtcl_s1) { + case 0: + /* SerDes1 is not enabled */ + break; + case 0x1c: + case 0x95: + case 0xa2: + case 0x94: + /* SD1(A:D) => SLOT3 SGMII + * SD1(G:H) => SLOT1 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x58); + break; + case 0x51: + /* SD1(A:D) => SLOT3 XAUI + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0x15); + break; + case 0x66: + case 0x67: + /* SD1(A:D) => XFI cage + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xfe); + break; + case 0x6b: + /* SD1(A:D) => XFI cage + * SD1(E) => SLOT1 PCIe4 + * SD1(F:H) => SLOT2 SGMII + */ + QIXIS_WRITE(brdcfg[12], 0xf1); + break; + case 0x6c: + case 0x6d: + /* SD1(A:B) => XFI cage + * SD1(C:D) => SLOT3 SGMII + * SD1(E:H) => SLOT1 PCIe4 + */ + QIXIS_WRITE(brdcfg[12], 0xda); + break; + default: + printf("WARNING: unsupported for SerDes1 Protocol %d\n", + srds_prtcl_s1); + return -1; + } + + switch (srds_prtcl_s2) { + case 0: + /* SerDes2 is not enabled */ + break; + case 0x01: + case 0x02: + /* SD2(A:H) => SLOT4 PCIe1 */ + QIXIS_WRITE(brdcfg[13], 0x20); + break; + case 0x15: + case 0x16: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 PCIe2 + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0xb0); + break; + case 0x18: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:F) => SLOT5 Aurora + * SD2(G:H) => SATA1,SATA2 + */ + QIXIS_WRITE(brdcfg[13], 0x70); + break; + case 0x1f: + /* + * SD2(A:D) => SLOT4 PCIe1 + * SD2(E:H) => SLOT5 PCIe2 + */ + QIXIS_WRITE(brdcfg[13], 0xa0); + break; + case 0x29: + case 0x2d: + case 0x2e: + /* + * SD2(A:D) => SLOT4 SRIO2 + * SD2(E:H) => SLOT5 SRIO1 + */ + QIXIS_WRITE(brdcfg[13], 0x50); + break; + default: + printf("WARNING: unsupported for SerDes2 Protocol %d\n", + srds_prtcl_s2); + return -1; + } + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Disable remote I2C connection to qixis fpga */ + QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); + + brd_mux_lane_to_slot(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("SYS Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: SYS clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch (sysclk_conf & 0x0F) { + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); +#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT + /* use accurate clock measurement */ + int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); + int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); + u32 val; + + val = freq * base; + if (val) { + debug("DDR Clock measurement is: %d\n", val); + return val; + } else { + printf("Warning: DDR clock measurement is invalid, "); + printf("using value from brdcfg1.\n"); + } +#endif + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t2080qds/t2080qds.h new file mode 100644 index 0000000000..39fcef28c3 --- /dev/null +++ b/board/freescale/t2080qds/t2080qds.h @@ -0,0 +1,13 @@ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t2080qds/t2080qds_qixis.h new file mode 100644 index 0000000000..fc83da707f --- /dev/null +++ b/board/freescale/t2080qds/t2080qds_qixis.h @@ -0,0 +1,47 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T2080QDS_QIXIS_H__ +#define __T2080QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for T2080QDS */ + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e + + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */ + +#define BRDCFG12_SD3EN_MASK 0x20 +#define BRDCFG12_SD3MX_MASK 0x08 +#define BRDCFG12_SD3MX_SLOT5 0x08 +#define BRDCFG12_SD3MX_SLOT6 0x00 +#define BRDCFG12_SD4EN_MASK 0x04 +#define BRDCFG12_SD4MX_MASK 0x03 +#define BRDCFG12_SD4MX_SLOT7 0x02 +#define BRDCFG12_SD4MX_SLOT8 0x01 +#define BRDCFG12_SD4MX_AURO_SATA 0x00 +#endif diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t2080qds/tlb.c new file mode 100644 index 0000000000..62cd11033a --- /dev/null +++ b/board/freescale/t2080qds/tlb.c @@ -0,0 +1,146 @@ +/* + * Copyright 2008-2013 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) + /* + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 1, 0x80000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_512M, 1), + + /* *I*G* - PCIe 2, 0xa0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCIe 3, 0xb0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + + /* *I*G* - PCIe 4, 0xc0000000 */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +#ifdef QIXIS_BASE_PHYS + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_4K, 1), +#endif +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE + /* + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for + * fetching ucode and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, + 0, 18, BOOKE_PAGESZ_1M, 1), +#endif + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index d9b0a9af50..21e00f58af 100644 --- a/boards.cfg +++ b/boards.cfg @@ -965,6 +965,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal +Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h new file mode 100644 index 0000000000..f85ccf552f --- /dev/null +++ b/include/configs/T2080QDS.h @@ -0,0 +1,803 @@ +/* + * Copyright 2011-2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T2080 QDS board configuration file + */ + +#ifndef __T2080QDS_H +#define __T2080QDS_H + +#define CONFIG_T2080QDS +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ +#define CONFIG_MMC +#define CONFIG_SPI_FLASH +#define CONFIG_USB_EHCI +#define CONFIG_FSL_SATA_V2 +#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +/* High Level Configuration Options */ +#define CONFIG_PHYS_64BIT +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_MP /* support multiple processors */ +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +#define CONFIG_SRIO_PCIE_BOOT_MASTER +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#ifdef CONFIG_SYS_NO_FLASH +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_ENV_IS_NOWHERE +#endif +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1105) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 +#define CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CTRL_INTLV_PREFERED cacheline + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define QIXIS_BASE 0xffdf0000 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RST_FORCE_MEM 0x1 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */\ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ +#define I2C_MUX_CH_DEFAULT 0x8 + + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ +#ifdef CONFIG_SPI_FLASH +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 +#endif + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ +#define CONFIG_NET_MULTI +#define CONFIG_E1000 +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 18 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN /* RMan */ +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO or PCIE outbound window->master inbound window-> + * master LAW->the ucode address in master's memory space. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_REALTEK +#define CONFIG_PHY_TERANETICS +#define RGMII_PHY1_ADDR 0x1 +#define RGMII_PHY2_ADDR 0x2 +#define FM1_10GEC1_PHY_ADDR 0x3 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC3" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * SATA + */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +/* + * USB + */ +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * SDHC + */ +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BDI + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t2080qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t2080qds/t2080qds.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +/* + * For emulation this causes u-boot to jump to the start of the + * proof point app code automatically + */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#undef CONFIG_CMD_USB +#endif + +#endif /* __T2080QDS_H */ -- cgit v1.2.1 From f7f155e1e180e2e7743a036016ed917bba581d98 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 22 Nov 2013 17:39:12 +0800 Subject: t2080qds/ramboot: enable PBL tool for t2080qds Add the default RCW(SerDes 0x66_0x16) and PBI configure file for T2080QDS board, so we can use PBL tool to generate the ramboot image to support boot from NAND/SPI/SD. Signed-off-by: Shengzhou Liu --- board/freescale/t2080qds/t2080_pbi.cfg | 41 ++++++++++++++++++++++++++++++++++ board/freescale/t2080qds/t2080_rcw.cfg | 8 +++++++ boards.cfg | 4 ++++ include/configs/T2080QDS.h | 2 ++ 4 files changed, 55 insertions(+) create mode 100644 board/freescale/t2080qds/t2080_pbi.cfg create mode 100644 board/freescale/t2080qds/t2080_rcw.cfg diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t2080qds/t2080_pbi.cfg new file mode 100644 index 0000000000..e200d926fb --- /dev/null +++ b/board/freescale/t2080qds/t2080_pbi.cfg @@ -0,0 +1,41 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Refer doc/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#Initialize eSPI controller, default configuration is slow for eSPI to +#load data, this configuration comes from u-boot eSPI driver. +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ +094fc030 00008148 +094fd030 00008148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t2080qds/t2080_rcw.cfg new file mode 100644 index 0000000000..c2ad0fda55 --- /dev/null +++ b/board/freescale/t2080qds/t2080_rcw.cfg @@ -0,0 +1,8 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#SerDes Protocol: 0x66_0x16 +#Core/DDR: 1533Mhz/2133MT/s +12100017 15000000 00000000 00000000 +66160002 00008400 e8104000 c1000000 +00000000 00000000 00000000 000307fc +00000000 00000000 00000000 00000004 diff --git a/boards.cfg b/boards.cfg index 21e00f58af..114cc86d00 100644 --- a/boards.cfg +++ b/boards.cfg @@ -966,6 +966,10 @@ Active powerpc mpc85xx - freescale t1040qds Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal Active powerpc mpc85xx - freescale t2080qds T2080QDS T2080QDS:PPC_T2080 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SDCARD T2080QDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SPIFLASH T2080QDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_NAND T2080QDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +Active powerpc mpc85xx - freescale t2080qds T2080QDS_SRIO_PCIE_BOOT T2080QDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach diff --git a/include/configs/T2080QDS.h b/include/configs/T2080QDS.h index f85ccf552f..ad09816974 100644 --- a/include/configs/T2080QDS.h +++ b/include/configs/T2080QDS.h @@ -45,6 +45,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg #endif #define CONFIG_SRIO_PCIE_BOOT_MASTER -- cgit v1.2.1 From d19ad726bcd5d9106f7ba9c750462fcc369f1020 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 25 Nov 2013 16:49:32 -0500 Subject: Prepare v2014.01-rc1 Signed-off-by: Tom Rini --- Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 52133a5434..a2fb03798c 100644 --- a/Makefile +++ b/Makefile @@ -5,10 +5,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -VERSION = 2013 -PATCHLEVEL = 10 +VERSION = 2014 +PATCHLEVEL = 01 SUBLEVEL = -EXTRAVERSION = +EXTRAVERSION = -rc1 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else -- cgit v1.2.1 From d18d49d7ad77f1a97b9697b3761802de5b82983d Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 26 Nov 2013 17:45:25 +0000 Subject: mips: don't hardcode Malta env baudrate The baudrate passed to Linux in the environment was hardcoded at 38400. Instead pass the correct baudrate from global data, allowing Linux to correctly inherit the baudrate used by U-boot when console setup is not explicitly specified. Signed-off-by: Paul Burton --- arch/mips/lib/bootm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 1febf29865..71bb0d2a19 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -196,8 +196,10 @@ static void boot_prep_linux(bootm_headers_t *images) if (cp) linux_env_set("eth1addr", cp); - if (mips_boot_malta) - linux_env_set("modetty0", "38400n8r"); + if (mips_boot_malta) { + sprintf(env_buf, "%un8r", gd->baudrate); + linux_env_set("modetty0", env_buf); + } } static void boot_jump_linux(bootm_headers_t *images) -- cgit v1.2.1 From 72117dadcbbdffda447daa1e26b4cc4007f61160 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 26 Nov 2013 17:45:26 +0000 Subject: malta: correct UART baudrate CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in a UART at 115200 baud, thus the x16 clock rate is 115200 * 16. Previously the divider was left at 0 which led to a rate of 38400 baud regardless of CONFIG_BAUDRATE or the baudrate environment variable. Signed-off-by: Paul Burton --- include/configs/malta.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/malta.h b/include/configs/malta.h index 458c33a586..666cca99a4 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -80,7 +80,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 115200 +#define CONFIG_SYS_NS16550_CLK (115200 * 16) #define CONFIG_SYS_NS16550_COM1 CKSEG1ADDR(MALTA_GT_UART0_BASE) #define CONFIG_SYS_NS16550_COM2 CKSEG1ADDR(MALTA_MSC01_UART0_BASE) #define CONFIG_CONS_INDEX 1 -- cgit v1.2.1 From bea12b782337105feeb3aeb0875d110eed007803 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 26 Nov 2013 17:45:27 +0000 Subject: malta: enable PIIX4 SERIRQ Whilst U-boot does not require this itself, Linux currently relies upon it having been muxed and enabled by the bootloader. Thus in order to preserve compatibility with current kernels before a fix is merged in Linux we will enable the SERIRQ interrupt and mux it to its pin. Without doing this current kernels will never receive serial port interrupts and the end result is typically that userland appears to hang. Signed-off-by: Paul Burton --- arch/mips/include/asm/malta.h | 7 +++++++ board/imgtec/malta/malta.c | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/mips/include/asm/malta.h b/arch/mips/include/asm/malta.h index bd9043d51c..9e7c045aac 100644 --- a/arch/mips/include/asm/malta.h +++ b/arch/mips/include/asm/malta.h @@ -56,5 +56,12 @@ #define PCI_CFG_PIIX4_PIRQRCB 0x61 #define PCI_CFG_PIIX4_PIRQRCC 0x62 #define PCI_CFG_PIIX4_PIRQRCD 0x63 +#define PCI_CFG_PIIX4_SERIRQC 0x64 +#define PCI_CFG_PIIX4_GENCFG 0xb0 + +#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7) +#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6) + +#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16) #endif /* _MIPS_ASM_MALTA_H */ diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index a1a4c01866..d363e49919 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -171,6 +171,8 @@ struct serial_device *default_serial_console(void) void pci_init_board(void) { pci_dev_t bdf; + u32 val32; + u8 val8; switch (malta_sys_con()) { case SYSCON_GT64120: @@ -205,4 +207,14 @@ void pci_init_board(void) pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); + + /* mux SERIRQ onto SERIRQ pin */ + pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); + val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; + pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); + + /* enable SERIRQ - Linux currently depends upon this */ + pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); + val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; + pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); } -- cgit v1.2.1 From 67d4752d1dae768c7ff381272880d4aceeb62085 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 26 Nov 2013 17:45:28 +0000 Subject: malta: set CONFIG_SYS_BOOTM_LEN to 64MB Allow a larger kernel binary to be decompressed - the default 8MB can become limiting on a Malta. Signed-off-by: Paul Burton --- include/configs/malta.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/malta.h b/include/configs/malta.h index 666cca99a4..cc574ed040 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -54,6 +54,7 @@ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) +#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* * Console configuration -- cgit v1.2.1 From 2785a4ae76330dab5e792d52fc9c449ac3d1072e Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Tue, 29 Oct 2013 13:11:54 -0700 Subject: serial: zynq: Remove unused #defines Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek Series-to: trini, uboot --- drivers/serial/serial_zynq.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 050b9c0625..ff28f3c801 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -21,10 +21,6 @@ #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ -/* Some clock/baud constants */ -#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */ -#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */ - struct uart_zynq { u32 control; /* Control Register [8:0] */ u32 mode; /* Mode Register [10:0] */ -- cgit v1.2.1 From e40acc0a59319f9f3f0aba6ef10abd2dbf096ae1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 21 Nov 2013 16:10:20 +0900 Subject: Blackfin: remove executable permission of AWK script Signed-off-by: Masahiro Yamada --- arch/blackfin/cpu/bootrom-asm-offsets.awk | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 arch/blackfin/cpu/bootrom-asm-offsets.awk diff --git a/arch/blackfin/cpu/bootrom-asm-offsets.awk b/arch/blackfin/cpu/bootrom-asm-offsets.awk old mode 100755 new mode 100644 -- cgit v1.2.1