From bcfc8976e5c86afd7f14c8a32fcd33baad0b482f Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Thu, 29 Nov 2012 23:18:32 +0000 Subject: at91sam9x5: enable USB support for 9x5ek board. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Richard Genoud Acked-by: Bo Shen Signed-off-by: Andreas Bießmann --- arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 13 +++++++++++++ arch/arm/include/asm/arch-at91/at91sam9x5.h | 2 ++ board/atmel/at91sam9x5ek/at91sam9x5ek.c | 3 +++ drivers/usb/host/ohci-at91.c | 6 ++++-- 4 files changed, 22 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c index 93485523b5..0448c0b133 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c @@ -193,6 +193,19 @@ void at91_spi1_hw_init(unsigned long cs_mask) } #endif +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) +void at91_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */ + at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */ +#if defined(CONFIG_USB_OHCI_NEW) + /* port C is OHCI only */ + at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */ +#endif +} +#endif + #ifdef CONFIG_MACB void at91_macb_hw_init(void) { diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index 0e728c96dc..de0f1b1923 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -154,6 +154,8 @@ #define ATMEL_PIO_PORTS 4 #define CPU_HAS_PIO3 #define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */ +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP +#define ATMEL_ID_UHP ATMEL_ID_UHPHS /* * at91sam9x5 specific prototypes diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index edb088680d..8773e6fd39 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -295,6 +295,9 @@ int board_init(void) at91_macb_hw_init(); #endif +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) + at91_uhp_hw_init(); +#endif #ifdef CONFIG_LCD at91sam9x5ek_lcd_hw_init(); #endif diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 9532dd9ef6..efd711d489 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -41,7 +41,8 @@ int usb_cpu_init(void) writel(get_pllb_init(), &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9X5) /* Enable UPLL */ writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); @@ -81,7 +82,8 @@ int usb_cpu_stop(void) writel(0, &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ + defined(CONFIG_AT91SAM9X5) /* Disable UPLL */ writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr); while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) -- cgit v1.2.1 From 419fba0c685f968c6761a9df911f30c3c22f7559 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Thu, 29 Nov 2012 23:18:33 +0000 Subject: at91sam9x5ek: regroup FAT/DOS features MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Richard Genoud Acked-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/at91sam9x5ek.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 71f765b494..5e5f9c1169 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -90,6 +90,7 @@ #define CONFIG_CMD_NAND #define CONFIG_CMD_SF #define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @@ -142,9 +143,12 @@ /* MMC */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_CMD_FAT #define CONFIG_GENERIC_MMC #define CONFIG_GENERIC_ATMEL_MCI +#endif + +/* FAT */ +#ifdef CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif -- cgit v1.2.1 From b030e731736f4dcd3d8662bf3a3a71bed21c5c9e Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Thu, 29 Nov 2012 23:18:34 +0000 Subject: at91sam9x5ek: add USB configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Richard Genoud Acked-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/at91sam9x5ek.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 5e5f9c1169..915714f029 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -91,6 +91,13 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +/* + * define CONFIG_USB_EHCI to enable USB Hi-Speed (aka 2.0) + * NB: in this case, USB 1.1 devices won't be recognized. + */ + /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 @@ -158,6 +165,22 @@ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB_SEARCH_PHY +/* USB */ +#ifdef CONFIG_CMD_USB +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#else +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 +#endif +#define CONFIG_USB_ATMEL +#define CONFIG_USB_STORAGE +#endif + #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -- cgit v1.2.1 From ac81e1ccf7135d8004763bbf9bef1d95a03fbe92 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 5 Dec 2012 22:22:17 +0000 Subject: spi: atmel: sam9m10g45 also support WDRBT bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The at91sam9m10g45 also support WDRBT bit, add support for it Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- drivers/spi/atmel_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index c7a51f7f39..ce7d460855 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -92,7 +92,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, as->slave.cs = cs; as->regs = regs; as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS -#if defined(CONFIG_AT91SAM9X5) +#if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9M10G45) | ATMEL_SPI_MR_WDRBT #endif | ATMEL_SPI_MR_PCS(~(1 << cs) & 0xf); -- cgit v1.2.1 From 2472216caccc82f8b4bbe62421aa649eb186fefc Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Nov 2012 00:15:07 +0000 Subject: arm/km: fix memory settings On kmcoge5un we faced some serious problems with the memory during temperature tests. Reason was that we overwrite some registers for memory settings which have to leave untouched. These where registers 0x20148 , 0x2014c and 0x20154. So writing these registers is prohibited and this patch removes them from all km related config files. Even if the problem was only seen on kmcoge5un. Signed-off-by: Holger Brunck Signed-off-by: Valentin Longchamp cc: Prafulla Wadaskar --- board/keymile/km_arm/kwbimage-memphis.cfg | 6 +++--- board/keymile/km_arm/kwbimage.cfg | 6 +++--- board/keymile/km_arm/kwbimage_128M16_1.cfg | 25 ++----------------------- board/keymile/km_arm/kwbimage_256M8_1.cfg | 25 ++----------------------- 4 files changed, 10 insertions(+), 52 deletions(-) diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg index 6df2ad7902..5aa0de2528 100644 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ b/board/keymile/km_arm/kwbimage-memphis.cfg @@ -55,9 +55,9 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage #Dram initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg index b2f51936f4..e5e9942c1a 100644 --- a/board/keymile/km_arm/kwbimage.cfg +++ b/board/keymile/km_arm/kwbimage.cfg @@ -52,9 +52,9 @@ DATA 0xFFD10008 0x00001100 # MPP Control 2 Register DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register + +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage #Dram initalization DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg index bcce9073f6..5de8df70fd 100644 --- a/board/keymile/km_arm/kwbimage_128M16_1.cfg +++ b/board/keymile/km_arm/kwbimage_128M16_1.cfg @@ -98,29 +98,8 @@ DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register # bit 19-18: 1, ECC RAM WTC RAM0 # bit 31-20: ???,Reserve -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -# bit 23-0: 0x000200, Addr Config tuning -# bit 31-24: 0, Reserved - -# ??? Missing register # CPU RAM Management Control2 Register - -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -# bit 15-0: 0x1C00, Opmux Tuning -# bit 31-16: 0, Pc Dp Tuning - -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register -# bit 1-0: 1, addr clk tune -# bit 3-2: 0, reserved -# bit 5-4: 0, dtcmp clk tune -# bit 7-6: 0, reserved -# bit 9-8: 0, macdrv clk tune -# bit 11-10: 0, opmuxgm2 clk tune -# bit 15-14: 0, rf clk tune -# bit 17-16: 0, rfbypass clk tune -# bit 19-18: 0, pc dp clk tune -# bit 23-20: 0, icache clk tune -# bit 27:24: 0, dcache clk tune -# bit 31:28: 0, regfile tunin +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage # SDRAM initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg index 3e1237bbe3..d0a09f61d2 100644 --- a/board/keymile/km_arm/kwbimage_256M8_1.cfg +++ b/board/keymile/km_arm/kwbimage_256M8_1.cfg @@ -100,29 +100,8 @@ DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register # bit 19-18: 1, ECC RAM WTC RAM0 # bit 31-20: ?,Reserved -DATA 0xFFD20154 0x00000200 # CPU RAM Management Control3 Register -# bit 23-0: 0x000200, Addr Config tuning -# bit 31-24: 0, Reserved - -# ??? Missing register # CPU RAM Management Control2 Register - -DATA 0xFFD2014C 0x00001C00 # CPU RAM Management Control1 Register -# bit 15-0: 0x1C00, Opmux Tuning -# bit 31-16: 0, Pc Dp Tuning - -DATA 0xFFD20148 0x00000001 # CPU RAM Management Control0 Register -# bit 1-0: 1, addr clk tune -# bit 3-2: 0, reserved -# bit 5-4: 0, dtcmp clk tune -# bit 7-6: 0, reserved -# bit 9-8: 0, macdrv clk tune -# bit 11-10: 0, opmuxgm2 clk tune -# bit 15-14: 0, rf clk tune -# bit 17-16: 0, rfbypass clk tune -# bit 19-18: 0, pc dp clk tune -# bit 23-20: 0, icache clk tune -# bit 27:24: 0, dcache clk tune -# bit 31:28: 0, regfile tunin +# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! +# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage # SDRAM initalization DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -- cgit v1.2.1 From 06610e18260419d505f54b573c5b12bac5b29293 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Nov 2012 00:15:08 +0000 Subject: km/common: drop unneeded std* environment variables These variables are only used if CONFIG_SYS_CONSOLE_IS_IN_ENV is set. This isn't the case, so we can drop them safely. Signed-off-by: Holger Brunck cc: Valentin Longchamp cc: Prafulla Wadaskar --- include/configs/km/keymile-common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 05480d48ae..f64748e349 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -253,9 +253,6 @@ "load=tftpboot ${load_addr_r} ${u-boot}\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "stderr=serial\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ "" #endif /* CONFIG_KM_DEF_ENV */ -- cgit v1.2.1 From 37bead1a709fd14a97ea7c5fd3efc93be0fc64f5 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Fri, 2 Nov 2012 00:15:09 +0000 Subject: km/common: cosmetic change reported from checkpatch Signed-off-by: Holger Brunck cc: Valentin Longchamp cc: Prafulla Wadaskar Acked-by: Prafulla Wadaskar --- board/keymile/common/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index a90f1124fb..6f407b78f2 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -121,7 +121,7 @@ int i2c_make_abort(void) { #if defined(CONFIG_HARD_I2C) && !defined(MACH_TYPE_KM_KIRKWOOD) - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ; + immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c; /* -- cgit v1.2.1 From 136846d77f9788431d0405a7291e93f9996bb016 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 2 Nov 2012 00:15:10 +0000 Subject: arm/km: remove duplicate code This patch removes 2 small portions of board specific code that are duplicated with common ARM code and thus unnecessary. These 2 portions of code concern the mach id that is given by u-boot to the Linux kernel to identify the system's MACH. The first one was the possibility to change the MACH thanks to the 'mach_id' enviroment variable. This is possible thanks to the 'machid' env variable (see arch/arm/lib/bootm.c:boot_jump_linux()). The seconde one is the setting of the bi_arch_number. This is already done in arch/arm/lib/board.c:board_init_f() since km_arm.h does #define CONFIG_MACH_TYPE. Signed-off-by: Valentin Longchamp cc: Holger Brunck cc: Prafulla Wadaskar Acked-by: Prafulla Wadaskar --- board/keymile/km_arm/km_arm.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 0c4dddc617..262b8d2cf1 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -193,15 +193,6 @@ void set_bootcount_addr(void) int misc_init_r(void) { - char *str; - int mach_type; - - str = getenv("mach_type"); - if (str != NULL) { - mach_type = simple_strtoul(str, NULL, 10); - printf("Overwriting MACH_TYPE with %d!!!\n", mach_type); - gd->bd->bi_arch_number = mach_type; - } #if defined(CONFIG_KM_MGCOGE3UN) char *wait_for_ne; wait_for_ne = getenv("waitforne"); @@ -258,11 +249,6 @@ int board_early_init_f(void) int board_init(void) { - /* - * arch number of board - */ - gd->bd->bi_arch_number = MACH_TYPE_KM_KIRKWOOD; - /* address of boot parameters */ gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; -- cgit v1.2.1 From 0a16ea593355d1a0fd415286089961f9c9ad1614 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 26 Nov 2012 11:27:35 +0000 Subject: mv88e61xx: refactor PHY and SWITCH level-code Signed-off-by: Albert ARIBAUD --- drivers/net/phy/mv88e61xx.c | 495 ++++++++++++++++++++++++++++---------------- drivers/net/phy/mv88e61xx.h | 39 ++-- include/netdev.h | 21 +- 3 files changed, 358 insertions(+), 197 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 483a920fca..e8da66d63f 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -26,6 +26,14 @@ #include #include "mv88e61xx.h" +/* + * Uncomment either of the following line for local debug control; + * otherwise global debug control will apply. + */ + +/* #undef DEBUG */ +/* #define DEBUG */ + #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE /* Chip Address mode * The Switch support two modes of operation @@ -52,7 +60,8 @@ static int mv88e61xx_busychk_multic(char *name, u32 devaddr) return 0; } -static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +static void mv88e61xx_switch_write(char *name, u32 phy_adr, + u32 reg_ofs, u16 data) { u16 mii_dev_addr; @@ -70,7 +79,8 @@ static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) 15)); } -static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +static void mv88e61xx_switch_read(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data) { u16 mii_dev_addr; @@ -90,110 +100,51 @@ static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) } #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ -static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, - u32 max_prtnum, u32 ports_ofs) -{ - u32 prt; - u16 reg; - char *name = swconfig->name; - u32 cpu_port = swconfig->cpuport; - u32 port_mask = swconfig->ports_enabled; - enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg; - - /* be sure all ports are disabled */ - for (prt = 0; prt < max_prtnum; prt++) { - RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®); - reg &= ~0x3; - WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg); - - if (!(cpu_port & (1 << prt))) - continue; - /* Set CPU port VID to 0x1 */ - RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®); - reg &= ~0xfff; - reg |= 0x1; - WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg); - } - - /* Setting Port default priority for all ports to zero */ - for (prt = 0; prt < max_prtnum; prt++) { - RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®); - reg &= ~0xc000; - WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg); - } - /* Setting VID and VID map for all ports except CPU port */ - for (prt = 0; prt < max_prtnum; prt++) { - /* only for enabled ports */ - if ((1 << prt) & port_mask) { - /* skip CPU port */ - if ((1 << prt) & cpu_port) { - /* - * Set Vlan map table for cpu_port to see - * all ports - */ - RD_PHY(name, (ports_ofs + prt), - MV88E61XX_PRT_VMAP_REG, ®); - reg &= ~((1 << max_prtnum) - 1); - reg |= port_mask & ~(1 << prt); - WR_PHY(name, (ports_ofs + prt), - MV88E61XX_PRT_VMAP_REG, reg); - } else { - - /* - * set Ports VLAN Mapping. - * port prt <--> cpu_port VLAN #prt+1. - */ - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VID_REG, ®); - reg &= ~0x0fff; - reg |= (prt + 1); - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VID_REG, reg); - - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VMAP_REG, ®); - if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) { - /* - * all any port can send frames to all other ports - * ref: sec 3.2.1.1 of datasheet - */ - reg |= 0x03f; - reg &= ~(1 << prt); - } else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) { - /* - * all other ports can send frames to CPU port only - * ref: sec 3.2.1.2 of datasheet - */ - reg &= ~((1 << max_prtnum) - 1); - reg |= cpu_port; - } - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_VMAP_REG, reg); - } - } - } +/* + * Convenience macros for switch device/port reads/writes + * These macros output valid 'mv88e61xx' U_BOOT_CMDs + */ - /* - * enable only appropriate ports to forwarding mode - * and disable the others - */ - for (prt = 0; prt < max_prtnum; prt++) { - if ((1 << prt) & port_mask) { - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, ®); - reg |= 0x3; - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, reg); - } else { - /* Disable port */ - RD_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, ®); - reg &= ~0x3; - WR_PHY(name, ports_ofs + prt, - MV88E61XX_PRT_CTRL_REG, reg); - } - } +#ifndef DEBUG +#define WR_SWITCH_REG wr_switch_reg +#define RD_SWITCH_REG rd_switch_reg +#define WR_SWITCH_PORT_REG(n, p, r, d) \ + WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) +#define RD_SWITCH_PORT_REG(n, p, r, d) \ + RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) +#else +static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data) +{ + printf("mv88e61xx %s dev %02x reg %02x write %04x\n", + name, dev_adr, reg_ofs, data); + wr_switch_reg(name, dev_adr, reg_ofs, data); } +static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data) +{ + rd_switch_reg(name, dev_adr, reg_ofs, data); + printf("mv88e61xx %s dev %02x reg %02x read %04x\n", + name, dev_adr, reg_ofs, *data); +} +static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, + u16 data) +{ + printf("mv88e61xx %s port %02x reg %02x write %04x\n", + name, prt_adr, reg_ofs, data); + wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); +} +static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, + u16 *data) +{ + rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); + printf("mv88e61xx %s port %02x reg %02x read %04x\n", + name, prt_adr, reg_ofs, *data); +} +#endif + +/* + * Local functions to read/write registers on the switch PHYs. + * NOTE! This goes through switch, not direct miiphy, writes and reads! + */ /* * Make sure SMIBusy bit cleared before another @@ -204,7 +155,7 @@ static int mv88e61xx_busychk(char *name) u16 reg = 0; u32 timeout = MV88E61XX_PHY_TIMEOUT; do { - RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, + rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, ®); if (timeout-- == 0) { printf("SMI busy timeout\n"); @@ -214,34 +165,110 @@ static int mv88e61xx_busychk(char *name) return 0; } +static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy, + u32 reg, u16 data) +{ + /* write switch data reg then cmd reg then check completion */ + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, + data); + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, + (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg)); + return mv88e61xx_busychk(name); +} + +static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy, + u32 reg, u16 *data) +{ + /* write switch cmd reg, check for completion */ + wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, + (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg)); + if (mv88e61xx_busychk(name)) + return -1; + /* read switch data reg and return success */ + rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data); + return 0; +} + +/* + * Convenience macros for switch PHY reads/writes + */ + +#ifndef DEBUG +#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write +#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read +#else +static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr, + u32 reg_ofs, u16 data) +{ + int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data); + if (r) + printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n", + name, phy_adr, reg_ofs); + else + printf("mv88e61xx %s phy %02x reg %02x write %04x\n", + name, phy_adr, reg_ofs, data); + return r; +} +static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data) +{ + int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data); + if (r) + printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n", + name, phy_adr, reg_ofs); + else + printf("mv88e61xx %s phy %02x reg %02x read %04x\n", + name, phy_adr, reg_ofs, *data); + return r; +} +#endif + +static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 port_mask = swconfig->ports_enabled; + + /* apply internal vlan config */ + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* take vlan map from swconfig */ + u8 vlanmap = swconfig->vlancfg[prt]; + /* remove disabled ports from vlan map */ + vlanmap &= swconfig->ports_enabled; + /* apply vlan map to port */ + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VMAP_REG, ®); + reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); + reg |= vlanmap; + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } +} + /* * Power up the specified port and reset PHY */ -static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt) +static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy) { char *name = swconfig->name; - /* Write Copper Specific control reg1 (0x14) for- + /* Write Copper Specific control reg1 (0x10) for- * Enable Phy power up * Energy Detect on (sense&Xmit NLP Periodically * reset other settings default */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (0x9410 | (prt << 5))); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360)) return -1; /* Write PHY ctrl reg (0x0) to apply * Phy reset (set bit 15 low) * reset other default values */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (0x9400 | (prt << 5))); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140)) return -1; return 0; @@ -256,48 +283,26 @@ static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt) * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s * Link status */ -static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt) +static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy) { char *name = swconfig->name; - u16 reg; if (swconfig->led_init != MV88E61XX_LED_INIT_EN) return 0; /* set page address to 3 */ - reg = 3; - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 22)); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003)) return -1; - /* set LED Func Ctrl reg */ - reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 16)); - - if (mv88e61xx_busychk(name)) + /* + * set LED Func Ctrl reg + * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink + */ + if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001)) return -1; /* set page address to 0 */ - reg = 0; - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 22)); - - if (mv88e61xx_busychk(name)) + if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000)) return -1; return 0; @@ -312,23 +317,15 @@ static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt) * This is optional settings may be needed on some boards * for PHY<->magnetics h/w tuning */ -static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt) +static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy) { char *name = swconfig->name; - u16 reg; if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) return 0; - reg = 0x0f; /*Reverse MDIP/N[3:0] bits */ - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg); - WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST | - 1 << MV88E61XX_MODE_OFST | - 1 << MV88E61XX_OP_OFST | - prt << MV88E61XX_ADDR_OFST | 20)); - - if (mv88e61xx_busychk(name)) + /*Reverse MDIP/N[3:0] bits */ + if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f)) return -1; return 0; @@ -343,6 +340,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) u16 reg; char *idstr; char *name = swconfig->name; + int time; if (miiphy_set_current_dev(name)) { printf("%s failed\n", __FUNCTION__); @@ -354,7 +352,7 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) printf("Invalid cpu port config, using default port5\n"); } - RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, ®); + RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®); switch (reg &= 0xfff0) { case 0x1610: idstr = "88E6161"; @@ -373,46 +371,183 @@ int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) break; } - /* Port based VLANs configuration */ - if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT) - || (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER)) - mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM, - MV88E61XX_PRT_OFST); - else { - printf("Unsupported mode %s failed\n", __FUNCTION__); - return -1; + /* be sure all ports are disabled */ + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®); + reg &= ~0x3; + WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); } + /* wait 2 ms for queues to drain */ + udelay(2000); + + /* reset switch */ + RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®); + reg |= 0x8000; + WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg); + + /* wait up to 1 second for switch reset complete */ + for (time = 1000; time; time--) { + RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR, + ®); + if ((reg & 0xc800) == 0xc800) + break; + udelay(1000); + } + if (!time) + return -1; + + /* Port based VLANs configuration */ + mv88e61xx_port_vlan_config(swconfig); + if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 9.5 of chip datasheet-02 */ - WR_PHY(name, MV88E61XX_PRT_OFST + 5, - MV88E61XX_RGMII_TIMECTRL_REG, 0x18); - WR_PHY(name, MV88E61XX_PRT_OFST + 4, - MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + /*Force port link down */ + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10); + /* configure port RGMII delay */ + WR_SWITCH_PORT_REG(name, 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7); + RD_SWITCH_PORT_REG(name, 5, + MV88E61XX_RGMII_TIMECTRL_REG, ®); + WR_SWITCH_PORT_REG(name, 5, + MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18); + WR_SWITCH_PORT_REG(name, 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + /* Force port to RGMII FDX 1000Base then up */ + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e); + WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); } for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { - if (!((1 << prt) & swconfig->cpuport)) { - if (mv88361xx_led_init(swconfig, prt)) + /* configure port's PHY */ + if (!((1 << prt) & swconfig->cpuport)) { + /* port 4 has phy 6, not 4 */ + int phy = (prt == 4) ? 6 : prt; + if (mv88361xx_powerup(swconfig, phy)) return -1; - if (mv88361xx_reverse_mdipn(swconfig, prt)) + if (mv88361xx_reverse_mdipn(swconfig, phy)) return -1; - if (mv88361xx_powerup(swconfig, prt)) + if (mv88361xx_led_init(swconfig, phy)) return -1; } + /* set port VID to port+1 except for cpu port */ + if (!((1 << prt) & swconfig->cpuport)) { + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VID_REG, ®); + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_VID_REG, + (reg & ~1023) | (prt+1)); + } + /*Program port state */ - RD_PHY(name, MV88E61XX_PRT_OFST + prt, - MV88E61XX_PRT_CTRL_REG, ®); - WR_PHY(name, MV88E61XX_PRT_OFST + prt, - MV88E61XX_PRT_CTRL_REG, - reg | (swconfig->portstate & 0x03)); + RD_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_CTRL_REG, ®); + WR_SWITCH_PORT_REG(name, prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } printf("%s Initialized on %s\n", idstr, name); return 0; } + +#ifdef CONFIG_MV88E61XX_CMD +static int +do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char *name, *endp; + int write = 0; + enum { dev, prt, phy } target = dev; + u32 addrlo, addrhi, addr; + u32 reglo, reghi, reg; + u16 data, rdata; + + if (argc < 7) + return -1; + + name = argv[1]; + + if (strcmp(argv[2], "phy") == 0) + target = phy; + else if (strcmp(argv[2], "port") == 0) + target = prt; + else if (strcmp(argv[2], "dev") != 0) + return 1; + + addrlo = simple_strtoul(argv[3], &endp, 16); + + if (!*endp) { + addrhi = addrlo; + } else { + while (*endp < '0' || *endp > '9') + endp++; + addrhi = simple_strtoul(endp, NULL, 16); + } + + reglo = simple_strtoul(argv[5], &endp, 16); + if (!*endp) { + reghi = reglo; + } else { + while (*endp < '0' || *endp > '9') + endp++; + reghi = simple_strtoul(endp, NULL, 16); + } + + if (strcmp(argv[6], "write") == 0) + write = 1; + else if (strcmp(argv[6], "read") != 0) + return 1; + + data = simple_strtoul(argv[7], NULL, 16); + + for (addr = addrlo; addr <= addrhi; addr++) { + for (reg = reglo; reg <= reghi; reg++) { + if (write) { + if (target == phy) + mv88e61xx_switch_miiphy_write( + name, addr, reg, data); + else if (target == prt) + wr_switch_reg(name, + addr+MV88E61XX_PRT_OFST, + reg, data); + else + wr_switch_reg(name, addr, reg, data); + } else { + if (target == phy) + mv88e61xx_switch_miiphy_read( + name, addr, reg, &rdata); + else if (target == prt) + rd_switch_reg(name, + addr+MV88E61XX_PRT_OFST, + reg, &rdata); + else + rd_switch_reg(name, addr, reg, &rdata); + printf("%s %s %s %02x %s %02x %s %04x\n", + argv[0], argv[1], argv[2], addr, + argv[4], reg, argv[6], rdata); + if (write && argc == 7 && rdata != data) + return 1; + } + } + } + return 0; +} + +U_BOOT_CMD(mv88e61xx, 8, 0, do_switch, + "Read or write mv88e61xx switch registers", + " dev|port|phy reg write \n" + " dev|port|phy reg read []\n" + " - read/write switch device, port or phy at (addr,reg)\n" + " addr=0..0x1C for dev, 0..5 for port or phy.\n" + " reg=0..0x1F.\n" + " data=0..0xFFFF (tested if present against actual read).\n" + " All numeric parameters are assumed to be hex.\n" + " and < arguments can be ranges (x..y)" +); +#endif /* CONFIG_MV88E61XX_CMD */ diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h index 57762b6861..55ded7e032 100644 --- a/drivers/net/phy/mv88e61xx.h +++ b/drivers/net/phy/mv88e61xx.h @@ -28,35 +28,50 @@ #include #define MV88E61XX_CPU_PORT 0x5 -#define MV88E61XX_MAX_PORTS_NUM 0x6 #define MV88E61XX_PHY_TIMEOUT 100000 -#define MV88E61XX_PRT_STS_REG 0x1 +/* port dev-addr (= port + 0x10) */ +#define MV88E61XX_PRT_OFST 0x10 +/* port registers */ +#define MV88E61XX_PCS_CTRL_REG 0x1 #define MV88E61XX_PRT_CTRL_REG 0x4 #define MV88E61XX_PRT_VMAP_REG 0x6 #define MV88E61XX_PRT_VID_REG 0x7 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A -#define MV88E61XX_PRT_OFST 0x10 +/* global registers dev-addr */ +#define MV88E61XX_GLBREG_DEVADR 0x1B +/* global registers */ +#define MV88E61XX_SGSR 0x00 +#define MV88E61XX_SGCR 0x04 + +/* global 2 registers dev-addr */ +#define MV88E61XX_GLB2REG_DEVADR 0x1C +/* global 2 registers */ #define MV88E61XX_PHY_CMD 0x18 #define MV88E61XX_PHY_DATA 0x19 -#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A -#define MV88E61XX_GLB2REG_DEVADR 0x1C +/* global 2 phy commands */ +#define MV88E61XX_PHY_WRITE_CMD 0x9400 +#define MV88E61XX_PHY_READ_CMD 0x9800 #define MV88E61XX_BUSY_OFST 15 #define MV88E61XX_MODE_OFST 12 -#define MV88E61XX_OP_OFST 10 +#define MV88E61XX_OP_OFST 10 #define MV88E61XX_ADDR_OFST 5 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE static int mv88e61xx_busychk_multic(char *name, u32 devaddr); -static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data); -static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data); -#define WR_PHY mv88e61xx_wr_phy -#define RD_PHY mv88e61xx_rd_phy +static void mv88e61xx_switch_write(char *name, u32 phy_adr, + u32 reg_ofs, u16 data); +static void mv88e61xx_switch_read(char *name, u32 phy_adr, + u32 reg_ofs, u16 *data); +#define wr_switch_reg mv88e61xx_switch_write +#define rd_switch_reg mv88e61xx_switch_read #else -#define WR_PHY miiphy_write -#define RD_PHY miiphy_read +/* switch appears a s simple PHY and can thus use miiphy */ +#define wr_switch_reg miiphy_write +#define rd_switch_reg miiphy_read #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ #endif /* _MV88E61XX_H */ diff --git a/include/netdev.h b/include/netdev.h index b8d303d089..7f158d433b 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -163,10 +163,9 @@ static inline int pci_eth_init(bd_t *bis) * the stuct and enums here are used to specify switch configuration params */ #if defined(CONFIG_MV88E61XX_SWITCH) -enum mv88e61xx_cfg_vlan { - MV88E61XX_VLANCFG_DEFAULT, - MV88E61XX_VLANCFG_ROUTER -}; + +/* constants for any 88E61xx switch */ +#define MV88E61XX_MAX_PORTS_NUM 6 enum mv88e61xx_cfg_mdip { MV88E61XX_MDIP_NOCHANGE, @@ -192,7 +191,7 @@ enum mv88e61xx_cfg_prtstt { struct mv88e61xx_config { char *name; - enum mv88e61xx_cfg_vlan vlancfg; + u8 vlancfg[MV88E61XX_MAX_PORTS_NUM]; enum mv88e61xx_cfg_rgmiid rgmii_delay; enum mv88e61xx_cfg_prtstt portstate; enum mv88e61xx_cfg_ledinit led_init; @@ -201,6 +200,18 @@ struct mv88e61xx_config { u8 cpuport; }; +/* + * Common mappings for Internal VLANs + * These mappings consider that all ports are useable; the driver + * will mask inexistent/unused ports. + */ + +/* Switch mode : routes any port to any port */ +#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F } + +/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */ +#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F } + int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig); #endif /* CONFIG_MV88E61XX_SWITCH */ -- cgit v1.2.1 From 9d86f0c30bd7e6a7f7a93bc7f12b69ef48a4de19 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 26 Nov 2012 11:27:36 +0000 Subject: kirkwood: make MPP arrays static const This saves stack and code memory for local copy, and consumes initialized data memory. For 22 of the 29 kirkwood-based boards, this results in a global saving of about 30 bytes. For 7 of them, it results in an increase of 6 to 14 bytes. Signed-off-by: Albert ARIBAUD --- arch/arm/cpu/arm926ejs/kirkwood/mpp.c | 2 +- arch/arm/include/asm/arch-kirkwood/mpp.h | 2 +- board/LaCie/net2big_v2/net2big_v2.c | 2 +- board/LaCie/netspace_v2/netspace_v2.c | 2 +- board/Marvell/dreamplug/dreamplug.c | 2 +- board/Marvell/guruplug/guruplug.c | 2 +- board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c | 2 +- board/Marvell/openrd/openrd.c | 2 +- board/Marvell/rd6281a/rd6281a.c | 2 +- board/Marvell/sheevaplug/sheevaplug.c | 2 +- board/Seagate/dockstar/dockstar.c | 2 +- board/buffalo/lsxl/lsxl.c | 2 +- board/cloudengines/pogo_e02/pogo_e02.c | 2 +- board/d-link/dns325/dns325.c | 2 +- board/iomega/iconnect/iconnect.c | 2 +- board/karo/tk71/tk71.c | 2 +- board/keymile/km_arm/km_arm.c | 2 +- board/raidsonic/ib62x0/ib62x0.c | 2 +- drivers/spi/kirkwood_spi.c | 12 +++++------- 19 files changed, 23 insertions(+), 25 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c index 03eb2de520..0ba6f098cb 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c @@ -31,7 +31,7 @@ static u32 kirkwood_variant(void) #define MPP_CTRL(i) (KW_MPP_BASE + (i* 4)) #define MPP_NR_REGS (1 + MPP_MAX/8) -void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save) +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save) { u32 mpp_ctrl[MPP_NR_REGS]; unsigned int variant_mask; diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h index 8ceea7bb88..48d1477fff 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/include/asm/arch-kirkwood/mpp.h @@ -312,6 +312,6 @@ #define MPP_MAX 49 -void kirkwood_mpp_conf(u32 *mpp_list, u32 *mpp_save); +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save); #endif diff --git a/board/LaCie/net2big_v2/net2big_v2.c b/board/LaCie/net2big_v2/net2big_v2.c index 0e06c29153..e524f3511d 100644 --- a/board/LaCie/net2big_v2/net2big_v2.c +++ b/board/LaCie/net2big_v2/net2big_v2.c @@ -39,7 +39,7 @@ int board_early_init_f(void) NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c index 101a80a70a..0aa5345ddc 100644 --- a/board/LaCie/netspace_v2/netspace_v2.c +++ b/board/LaCie/netspace_v2/netspace_v2.c @@ -39,7 +39,7 @@ int board_early_init_f(void) NETSPACE_V2_OE_LOW, NETSPACE_V2_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/Marvell/dreamplug/dreamplug.c b/board/Marvell/dreamplug/dreamplug.c index d6497aaa07..0caf34ff0a 100644 --- a/board/Marvell/dreamplug/dreamplug.c +++ b/board/Marvell/dreamplug/dreamplug.c @@ -46,7 +46,7 @@ int board_early_init_f(void) DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, /* SPI Flash */ MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c index f5c1c3cfd9..3a52ab2744 100644 --- a/board/Marvell/guruplug/guruplug.c +++ b/board/Marvell/guruplug/guruplug.c @@ -43,7 +43,7 @@ int board_early_init_f(void) GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c index 43852f6b24..fb57faa52b 100644 --- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c +++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c @@ -45,7 +45,7 @@ int board_early_init_f(void) MV88F6281GTW_GE_OE_LOW, MV88F6281GTW_GE_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c index d48f05a048..c59a32611c 100644 --- a/board/Marvell/openrd/openrd.c +++ b/board/Marvell/openrd/openrd.c @@ -48,7 +48,7 @@ int board_early_init_f(void) OPENRD_OE_LOW, OPENRD_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c index 1fd7677dcb..adaa6a1a69 100644 --- a/board/Marvell/rd6281a/rd6281a.c +++ b/board/Marvell/rd6281a/rd6281a.c @@ -44,7 +44,7 @@ int board_early_init_f(void) RD6281A_OE_LOW, RD6281A_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 688d3086d4..16efe645d1 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -43,7 +43,7 @@ int board_early_init_f(void) SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/Seagate/dockstar/dockstar.c b/board/Seagate/dockstar/dockstar.c index fc88520b2d..4f1f899b90 100644 --- a/board/Seagate/dockstar/dockstar.c +++ b/board/Seagate/dockstar/dockstar.c @@ -47,7 +47,7 @@ int board_early_init_f(void) DOCKSTAR_OE_LOW, DOCKSTAR_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index 57776fb077..f2980204c8 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -76,7 +76,7 @@ int board_early_init_f(void) * Multi-Purpose Pins Functionality configuration * These strappings are taken from the original vendor uboot port. */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_SPI_SCn, MPP1_SPI_MOSI, MPP2_SPI_SCK, diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c index bac9ce55a8..3b1c8ec2ad 100644 --- a/board/cloudengines/pogo_e02/pogo_e02.c +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -45,7 +45,7 @@ int board_early_init_f(void) POGO_E02_OE_LOW, POGO_E02_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 11260fe5f6..41879017e8 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -44,7 +44,7 @@ int board_early_init_f(void) DNS325_OE_LOW, DNS325_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 8cfb4e6620..c54c95d288 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -41,7 +41,7 @@ int board_early_init_f(void) ICONNECT_OE_LOW, ICONNECT_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c index 96410d77d6..7a4e7b3286 100644 --- a/board/karo/tk71/tk71.c +++ b/board/karo/tk71/tk71.c @@ -47,7 +47,7 @@ int board_early_init_f(void) TK71_OE_LOW, TK71_OE_HIGH); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 262b8d2cf1..eda9199bbe 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -54,7 +54,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MASK_RBI_DEFECT_16 0x01 /* Multi-Purpose Pins Functionality configuration */ -u32 kwmpp_config[] = { +static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index 5f0f3961d3..cf4ca51fcb 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -45,7 +45,7 @@ int board_early_init_f(void) /* Set SATA activity LEDs to default off */ writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG); /* Multi-Purpose Pins Functionality configuration */ - u32 kwmpp_config[] = { + static const u32 kwmpp_config[] = { MPP0_NF_IO2, MPP1_NF_IO3, MPP2_NF_IO4, diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index a7cda751bd..de81064b9d 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -41,7 +41,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, { struct spi_slave *slave; u32 data; - u32 kwspi_mpp_config[] = { 0, 0 }; + static const u32 kwspi_mpp_config[2][2] = { + { MPP0_SPI_SCn, 0 }, /* if cs == 0 */ + { MPP7_SPI_SCn, 0 } /* if cs != 0 */ + }; if (!spi_cs_is_valid(bus, cs)) return NULL; @@ -68,12 +71,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, writel(KWSPI_IRQMASK, &spireg->irq_mask); /* program mpp registers to select SPI_CSn */ - if (cs) { - kwspi_mpp_config[0] = MPP7_SPI_SCn; - } else { - kwspi_mpp_config[0] = MPP0_SPI_SCn; - } - kirkwood_mpp_conf(kwspi_mpp_config, cs_spi_mpp_back); + kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back); return slave; } -- cgit v1.2.1 From 7202e8ae5132deae7a9e6f310c3278f2da388471 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Mon, 26 Nov 2012 11:27:37 +0000 Subject: ARM: lacie_kw: add support for WIRELESS_SPACE Signed-off-by: Albert ARIBAUD --- board/LaCie/wireless_space/Makefile | 46 +++++++ board/LaCie/wireless_space/kwbimage.cfg | 82 ++++++++++++ board/LaCie/wireless_space/wireless_space.c | 176 +++++++++++++++++++++++++ boards.cfg | 1 + include/configs/wireless_space.h | 194 ++++++++++++++++++++++++++++ 5 files changed, 499 insertions(+) create mode 100644 board/LaCie/wireless_space/Makefile create mode 100644 board/LaCie/wireless_space/kwbimage.cfg create mode 100644 board/LaCie/wireless_space/wireless_space.c create mode 100644 include/configs/wireless_space.h diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile new file mode 100644 index 0000000000..b43c3d3bfe --- /dev/null +++ b/board/LaCie/wireless_space/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2011 Simon Guinot +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o ../common/common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg new file mode 100644 index 0000000000..0daf5b5393 --- /dev/null +++ b/board/LaCie/wireless_space/kwbimage.cfg @@ -0,0 +1,82 @@ +# +# Copyright (C) 2012 Albert ARIBAUD +# +# Based on netspace_v2 kwbimage.cfg: +# Copyright (C) 2011 Simon Guinot +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # Boot from NAND flash +NAND_PAGE_SIZE 800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Values taken from image original LaCie U-Boot header dump! + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1B1B1B9B + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register + +DATA 0xFFD01404 0x37743000 # DDR Controller Control Low + +DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) + +DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) + +DATA 0xFFD01410 0x0000CCCC # DDR Address Control + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control + +DATA 0xFFD01418 0x00000000 # DDR Operation + +DATA 0xFFD0141C 0x00000662 # DDR Mode + +DATA 0xFFD01420 0x00000004 # DDR Extended Mode + +DATA 0xFFD01424 0x0000F07F # DDR Controller Control High + +DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) + +DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 +DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E40F # CPU ODT Control +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x66666666 +DATA 0xFFD10000 0x01112222 +DATA 0xFFD1000C 0x00000000 +DATA 0xFFD10104 0x00000000 +DATA 0xFFD10100 0x40000000 +# End of Header extension +DATA 0x0 0x0 diff --git a/board/LaCie/wireless_space/wireless_space.c b/board/LaCie/wireless_space/wireless_space.c new file mode 100644 index 0000000000..208065899f --- /dev/null +++ b/board/LaCie/wireless_space/wireless_space.c @@ -0,0 +1,176 @@ +/* + * Copyright (C) 2011 Simon Guinot + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/common.h" +#include "netdev.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO configuration: start FAN at low speed, USB and HDD */ + +#define WIRELESS_SPACE_OE_LOW 0xFF006808 +#define WIRELESS_SPACE_OE_HIGH 0x0000F989 +#define WIRELESS_SPACE_OE_VAL_LOW 0x00010080 +#define WIRELESS_SPACE_OE_VAL_HIGH 0x00000240 + +#define WIRELESS_SPACE_REAR_BUTTON 13 +#define WIRELESS_SPACE_FRONT_BUTTON 43 + +const u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, /* Fan speed (bit 1) */ + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP13_GPIO, /* Red led */ + MPP14_GPIO, /* USB fuse */ + MPP15_SATA0_ACTn, + MPP16_GPIO, /* SATA 0 power */ + MPP17_GPIO, /* SATA 1 power */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, /* Gigabit Ethernet 1 */ + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GE1_8, + MPP29_GE1_9, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GE1_14, + MPP35_GE1_15, + MPP36_GPIO, /* Fan speed (bit 2) */ + MPP37_GPIO, /* Fan speed (bit 0) */ + MPP38_GPIO, /* Fan power */ + MPP39_GPIO, /* Fan rotation fail */ + MPP40_GPIO, /* Ethernet switch link */ + MPP41_GPIO, /* USB enable host vbus */ + MPP42_GPIO, /* LED clock control */ + MPP43_GPIO, /* WPS button (0=Pushed, 1=Released) */ + MPP44_GPIO, /* Red LED on/off */ + MPP45_GPIO, /* Red LED timer blink (on=off=100ms) */ + MPP46_GPIO, /* Green LED on/off */ + MPP47_GPIO, /* LED (blue, green) SATA activity blink */ + MPP48_GPIO, /* Blue LED on/off */ + 0 +}; + +struct mv88e61xx_config swcfg = { + .name = "egiga0", + .vlancfg = MV88E61XX_VLANCFG_ROUTER, + .rgmii_delay = MV88E61XX_RGMII_DELAY_EN, + .led_init = MV88E61XX_LED_INIT_EN, + .mdip = MV88E61XX_MDIP_NOCHANGE, + .portstate = MV88E61XX_PORTSTT_FORWARDING, + .cpuport = 0x20, + .ports_enabled = 0x3F, +}; + +int board_early_init_f(void) +{ + /* Gpio configuration */ + kw_config_gpio(WIRELESS_SPACE_OE_VAL_LOW, WIRELESS_SPACE_OE_VAL_HIGH, + WIRELESS_SPACE_OE_LOW, WIRELESS_SPACE_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + /* Machine number */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR) + if (!getenv("ethaddr")) { + uchar mac[6]; + if (lacie_read_mac_address(mac) == 0) + eth_setenv_enetaddr("ethaddr", mac); + } +#endif + return 0; +} +#endif + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) +/* Configure and initialize PHY */ +void reset_phy(void) +{ + /* configure switch on egiga0 */ + mv88e61xx_switch_initialize(&swcfg); +} +#endif + +#if defined(CONFIG_KIRKWOOD_GPIO) && defined(CONFIG_WIRELESS_SPACE_CMD) +/* Return GPIO button status */ +static int +do_ws(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (strcmp(argv[1], "button") == 0) { + if (strcmp(argv[2], "rear") == 0) + /* invert GPIO result for intuitive while/until use */ + return !kw_gpio_get_value(WIRELESS_SPACE_REAR_BUTTON); + else if (strcmp(argv[2], "front") == 0) + return kw_gpio_get_value(WIRELESS_SPACE_FRONT_BUTTON); + else + return -1; + } else { + return -1; + } +} + +U_BOOT_CMD(ws, 3, 0, do_ws, + "Return GPIO button status 0=off 1=on", + "- ws button rear|front: test buttons' states\n" +); +#endif diff --git a/boards.cfg b/boards.cfg index 388e4a4461..1477f919ab 100644 --- a/boards.cfg +++ b/boards.cfg @@ -171,6 +171,7 @@ netspace_lite_v2 arm arm926ejs netspace_v2 LaCie netspace_max_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MAX_V2 netspace_mini_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_MINI_V2 netspace_v2 arm arm926ejs netspace_v2 LaCie kirkwood lacie_kw:NETSPACE_V2 +wireless_space arm arm926ejs wireless_space LaCie kirkwood dreamplug arm arm926ejs - Marvell kirkwood guruplug arm arm926ejs - Marvell kirkwood mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood diff --git a/include/configs/wireless_space.h b/include/configs/wireless_space.h new file mode 100644 index 0000000000..eb20492896 --- /dev/null +++ b/include/configs/wireless_space.h @@ -0,0 +1,194 @@ +/* + * Copyright (C) 2011 Albert ARIBAUD + * + * Based on the netspace_v2 code which is + * Copyright (C) 2011 Simon Guinot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CONFIG_WIRELESS_SPACE_H +#define _CONFIG_WIRELESS_SPACE_H + +/* + * Machine number definition + */ +#define MACH_TYPE_WIRELESS_SPACE 2500 /* is missing in mach-types.h */ +#define CONFIG_MACH_TYPE MACH_TYPE_WIRELESS_SPACE +#define CONFIG_IDENT_STRING " Wireless Space" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD /* SoC Family Name */ +/* SoC name */ +#define CONFIG_KW88F6281 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH /* no NOR or SPI flash */ +#include +#define CONFIG_CMD_ENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB + +/* + * Core clock definition + */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +/* + * SDRAM configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* + * Different SDRAM configuration and size for some of the boards derived + * from the Network Space v2 + */ + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* Remove or override few declarations from mv-common.h */ +#undef CONFIG_RBTREE +#undef CONFIG_SYS_IDE_MAXBUS +#undef CONFIG_SYS_IDE_MAXDEVICE +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "ws> " + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MISC_INIT_R /* misc_init_r() initializes MAC address */ +#define CONFIG_MVGBE_PORTS {1, 0} /* enable only egiga0... */ +#define PORT_SERIAL_CONTROL_VALUE 0x00A4260E /* ... tied to the switch... */ +#define CONFIG_PHY_BASE_ADR 0xa /* ... through a 'fake' PHY */ +#define CONFIG_MII +#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN +#define CONFIG_NETCONSOLE +#define CONFIG_MV88E61XX_SWITCH +#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define CONFIG_MV88E61XX_CMD +#define CONFIG_CMD_TFTPPUT +#endif /* CONFIG_CMD_NET */ + +/* + * SATA Driver configuration + */ +#ifdef CONFIG_MVSATA_IDE +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET +#endif /* CONFIG_MVSATA_IDE */ + +/* + * Enable GPI0 support + */ +#define CONFIG_KIRKWOOD_GPIO + +/* + * Enable I2C support + */ +#ifdef CONFIG_CMD_I2C +/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ +#endif /* CONFIG_CMD_I2C */ + +/* + * Partition support + */ +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION + +/* + * File systems support + */ +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER + +/* + * Console configuration + */ +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* + * Enable device tree support + */ +#define CONFIG_OF_LIBFDT + +/* + * Environment variables configurations + */ + +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ +#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ + +/* + * Board-specific command to make using buttons etc easier + */ + +#define CONFIG_WIRELESS_SPACE_CMD + +/* + * Default environment variables + */ +#define CONFIG_PREBOOT + +#define CONFIG_BOOTARGS "console=ttyS0,115200" + +#define CONFIG_BOOTCOMMAND \ + "if run usbload || run diskload; then bootm; fi" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" \ + "bootfile=uImage\0" \ + "loadaddr=0x800000\0" \ + "autoload=no\0" \ + "netconsole=" \ + "set stdin $stdin,nc; " \ + "set stdout $stdout,nc; " \ + "set stderr $stderr,nc;\0" \ + "diskload=ide reset && " \ + "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ + "usbload=usb start && " \ + "fatload usb 0:1 $loadaddr /boot/$bootfile\0" \ + "preboot=" \ + "dhcp && run netconsole\0" + +#endif /* _CONFIG_WIRELESS_SPACE_H */ -- cgit v1.2.1 From 23c9946a3bfc23e3ede8995437d6b0e3b7b1335c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 4 Oct 2012 06:54:25 +0000 Subject: lsxl: unset ncip for rescue mode Instead of using the serverip we get from the DHCP server, implicitly use the broadcast address, which is automatically set when no ncip environment variable is set. That way it isn't necessary to use a special DHCP configuration to set the netconsole peer. Signed-off-by: Michael Walle Cc: Prafulla Wadaskar --- board/buffalo/lsxl/lsxl.c | 5 ++--- include/configs/lsxl.h | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index f2980204c8..83eea04cbc 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -49,9 +49,8 @@ * you can do this only with a working network connection. Therefore, a random * ethernet address is generated if none is set and a DHCP request is sent. * After a successful DHCP response is received, the network settings are - * configured and the ncip parameter is set to the serverip. Eg. for a working - * resuce mode, you should set 'next-server' to the host where the netconsole - * client is started. + * configured and the ncip is unset. Therefore, all netconsole packets are + * broadcasted. * Additionally, the bootsource is set to 'rescue'. */ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 8097f28ccc..59f151a375 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -146,7 +146,7 @@ "config_nc_dhcp=setenv autoload_old ${autoload}; " \ "setenv autoload no " \ "&& bootp " \ - "&& setenv ncip ${serverip} " \ + "&& setenv ncip " \ "&& setenv autoload ${autoload_old}; " \ "setenv autoload_old\0" \ "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ -- cgit v1.2.1 From 3e75e69668bd5be89aad835f1e990badf921f2e4 Mon Sep 17 00:00:00 2001 From: Luke Lowrey Date: Mon, 25 Jun 2012 06:37:09 +0000 Subject: arch-kirkwood: Ethernet port macro returning incorrect address Modified the arch-kirkwood header so KWGBE_PORT_SERIAL_CONTROL1_REG(x) returns the correct address. Originally calling KWGBE_PORT_SERIAL_CONTROL1_REG(1) returned the address for port 0 and vice versa. Doesn't have any knock on effects to the u-boot code as the only time they're used is to do the same function to both addresses Signed-off-by: Luke Lowrey Acked-by: Prafulla Wadaskar Acked-by: Heiko Schocher --- arch/arm/include/asm/arch-kirkwood/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index 57bfe8e78b..009a6bb8f3 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -33,7 +33,7 @@ | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ - ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) + ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c) #define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) #define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) -- cgit v1.2.1 From bfbfab94fd0b38ca780e6dda99657b0c848c9bb9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Mon, 29 Oct 2012 13:58:55 +0000 Subject: mv-common.h: increase malloc arena to 4MiB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This will fix the following error: ---8<--- UBIFS error (pid 0): ubifs_mount: Error reading superblock on volume 'ubi:root' errno=-12! --->8--- Signed-off-by: Andreas Bießmann Cc: prafulla@marvell.com Cc: dimax.main@gmail.com Tested-by: Alex Xol --- include/configs/mv-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 7086d1d0e8..405a842f72 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -92,7 +92,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */ /* * Other required minimal configurations -- cgit v1.2.1 From 44df5e8d30a276985b40bb32a69584f5a7fac9a0 Mon Sep 17 00:00:00 2001 From: Arun Mankuzhi Date: Fri, 30 Nov 2012 13:01:14 +0000 Subject: arm: move flush_dcache_all() to just before disable cache In Cortex-A15 architecture, when we run cache invalidate the cache clean operation executes automatically. So if there are any dirty cache lines before disabling the L2 cache these will be synchronized with the main memory when invalidate_dcache_all() runs in the last part of U-boot The two functions after flush_dcache_all is using the stack. So this data will be on the cache. After disable when invalidate is called the data will be flushed from cache to memory. This corrupts the stack in invalida_dcache_all. So this change is required to avoid the u-boot hang. So flush has to be done just before clearing CR_C bit Signed-off-by: Arun Mankuzhi Signed-off-by: Simon Glass --- arch/arm/lib/cache-cp15.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6edf815d4d..1cab27c226 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -153,8 +153,11 @@ static void cache_disable(uint32_t cache_bit) return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; - flush_dcache_all(); } + reg = get_cr(); + cp_delay(); + if (cache_bit == (CR_C | CR_M)) + flush_dcache_all(); set_cr(reg & ~cache_bit); } #endif -- cgit v1.2.1 From 724cdffca179057f4ebdf413ad764ea70b0e8ed2 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 30 Nov 2012 13:01:15 +0000 Subject: arm: Keep track of the tlb size as well as its location It may be necessary to know where the TLB area ends as well as where it starts. This allows board code to complete a secure memory erase without destroying the page tables. Signed-off-by: Gabe Black Signed-off-by: Simon Glass --- arch/arm/include/asm/global_data.h | 1 + arch/arm/lib/board.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 2b9af93806..41a26edfb5 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -73,6 +73,7 @@ typedef struct global_data { unsigned long reloc_off; #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; + unsigned long tlb_size; #endif const void *fdt_blob; /* Our device tree, NULL if none */ void **jt; /* jump table */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 0459d0ce9f..c214bba881 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -348,13 +348,14 @@ void board_init_f(ulong bootflag) #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* reserve TLB table */ - addr -= (4096 * 4); + gd->tlb_size = 4096 * 4; + addr -= gd->tlb_size; /* round down to next 64 kB limit */ addr &= ~(0x10000 - 1); gd->tlb_addr = addr; - debug("TLB table at: %08lx\n", addr); + debug("TLB table from %08lx to %08lx\n", addr, addr + gd->tlb_size); #endif /* round down to next 4 kB limit */ -- cgit v1.2.1 From eae78c3406e8b53950ab716567157aa836a5f398 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 30 Nov 2012 13:01:16 +0000 Subject: arm: Move fdt check earlier so that board_early_init_f() can use it We want to use the fdt inside board_early_init_f(), so check for its presence earlier in the pre-reloc init sequence. So far ARM and microblaze are the only only ones that use CONFIG_OF_CONTROL. Microblaze does not have the same init loop, and in particular does not have the board_early_init_f() call. So a patch for microblaze would have no meaning. Signed-off-by: Simon Glass --- arch/arm/lib/board.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index c214bba881..864b53380b 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -233,12 +233,11 @@ int power_init_board(void) init_fnc_t *init_sequence[] = { arch_cpu_init, /* basic arch cpu dependent setup */ - -#if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, -#endif #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt, +#endif +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, #endif timer_init, /* initialize timer */ #ifdef CONFIG_BOARD_POSTCLK_INIT -- cgit v1.2.1 From 06fd853890f23491605bfd6c9ab0116b79e15aaa Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 30 Nov 2012 13:01:17 +0000 Subject: arm: Add CONFIG_DELAY_ENVIRONMENT to delay environment loading This option delays loading of the environment until later, so that only the default environment will be available to U-Boot. This can address the security risk of untrusted data being used during boot. Any time you load untrusted data you expose yourself to a bug in the code. The attacker gets to choose the data so can sometimes carefully craft it to exploit a bug. We try to avoid touching user-controlled data during a verified boot unless strictly necessary. Since the default environment is good enough in this case (or you would just change it), this gets around the problem by just not loading the environment. When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a run-time way of enabling loading of the environment. Add this to the fdt as /config/delay-environment. Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/ Signed-off-by: Doug Anderson Signed-off-by: Simon Glass Reviewed-by: Doug Anderson --- README | 9 +++++++++ arch/arm/lib/board.c | 29 +++++++++++++++++++++++++++-- 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/README b/README index 653ef6aa4a..ef8571c898 100644 --- a/README +++ b/README @@ -2378,6 +2378,15 @@ CBFS (Coreboot Filesystem) support run-time determined information about the hardware to the environment. These will be named board_name, board_rev. + CONFIG_DELAY_ENVIRONMENT + + Normally the environment is loaded when the board is + intialised so that it is available to U-Boot. This inhibits + that so that the environment is not available until + explicitly loaded later by U-Boot code. With CONFIG_OF_CONTROL + this is instead controlled by the value of + /config/load-environment. + - DataFlash Support: CONFIG_HAS_DATAFLASH diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 864b53380b..a1eb7993ad 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -40,6 +40,7 @@ #include #include +#include #include #include #include @@ -467,7 +468,28 @@ static char *failed = "*** failed ***\n"; #endif /* - ************************************************************************ + * Tell if it's OK to load the environment early in boot. + * + * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see + * if this is OK (defaulting to saying it's not OK). + * + * NOTE: Loading the environment early can be a bad idea if security is + * important, since no verification is done on the environment. + * + * @return 0 if environment should not be loaded, !=0 if it is ok to load + */ +static int should_load_env(void) +{ +#ifdef CONFIG_OF_CONTROL + return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 0); +#elif defined CONFIG_DELAY_ENVIRONMENT + return 0; +#else + return 1; +#endif +} + +/************************************************************************ * * This is the next part if the initialization sequence: we are now * running from RAM and have a "normal" C environment, i. e. global @@ -570,7 +592,10 @@ void board_init_r(gd_t *id, ulong dest_addr) #endif /* initialize environment */ - env_relocate(); + if (should_load_env()) + env_relocate(); + else + set_default_env(NULL); #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) arm_pci_init(); -- cgit v1.2.1 From b2b92f53157d9afe73b413516834e062448a2fce Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 30 Nov 2012 13:01:18 +0000 Subject: Document the CONFIG_DISPLAY_BOARDINFO option Add a short note about this in the README. Signed-off-by: Simon Glass --- README | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README b/README index ef8571c898..d57ee91ca3 100644 --- a/README +++ b/README @@ -3457,6 +3457,11 @@ use the "saveenv" command to store a valid environment. space for already greatly restricted images, including but not limited to NAND_SPL configurations. +- CONFIG_DISPLAY_BOARDINFO + Display information about the board that U-Boot is running on + when U-Boot starts up. The board function checkboard() is called + to do this. + Low Level (hardware related) configuration options: --------------------------------------------------- -- cgit v1.2.1 From e2e3e2b1be703e0c93d0e49cac9a0dd2e1ba8f6e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 30 Nov 2012 13:01:19 +0000 Subject: arm: Add CONFIG_DISPLAY_BOARDINFO_LATE to display board info on LCD This option displays board info after stdio is running, so that it will appear on the LCD. If it is displayed earlier, the board info will appear on the serial console but not on the LCD. Here follows a blow-by-blow description. 1a. Without CONFIG_DISPLAY_BOARDINFO_LATE, on serial: U-Boot 2011.12-02550-g037e1c5-dirty (Nov 15 2012 - 14:29:42) for SMDK5250 CPU: S5PC520 @ 1700MHz Board: Google Snow, rev 0 I2C: ready DRAM: 2 GiB Elpida DDR3 @ 800MHz MMC: S5P MSHC0: 0, S5P MSHC1: 1 SF: Detected W25Q32 with page size 4 KiB, total 4 MiB *** Warning - bad CRC, using default environment In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # 1b. Without CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info is missing): In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # 2a. With CONFIG_DISPLAY_BOARDINFO_LATE, on serial: U-Boot 2011.12-02550-g037e1c5 (Nov 15 2012 - 14:27:40) for SMDK5250 CPU: S5PC520 @ 1700MHz I2C: ready DRAM: 2 GiB Elpida DDR3 @ 800MHz MMC: S5P MSHC0: 0, S5P MSHC1: 1 SF: Detected W25Q32 with page size 4 KiB, total 4 MiB *** Warning - bad CRC, using default environment Model: Google Snow In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # 2b. With CONFIG_DISPLAY_BOARDINFO_LATE, on LCD (note machine info is present): Model: Google Snow In: mkbp-keyb Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 SMDK5250 # Since the LCD is all that a typical user sees, it is useful to display the model there. We may be able to rearrange things some other way one day, but at present this seems like a convenient way of getting the required behaviour. Signed-off-by: Simon Glass --- README | 5 +++++ arch/arm/lib/board.c | 19 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/README b/README index d57ee91ca3..9c261680d4 100644 --- a/README +++ b/README @@ -3462,6 +3462,11 @@ use the "saveenv" command to store a valid environment. when U-Boot starts up. The board function checkboard() is called to do this. +- CONFIG_DISPLAY_BOARDINFO_LATE + Similar to the previous option, but display this information + later, once stdio is running and output goes to the LCD, if + present. + Low Level (hardware related) configuration options: --------------------------------------------------- diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index a1eb7993ad..ec5c35f131 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -489,6 +489,16 @@ static int should_load_env(void) #endif } +#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL) +static void display_fdt_model(const void *blob) +{ + const char *model; + + model = (char *)fdt_getprop(blob, 0, "model", NULL); + printf("Model: %s\n", model ? model : ""); +} +#endif + /************************************************************************ * * This is the next part if the initialization sequence: we are now @@ -612,6 +622,15 @@ void board_init_r(gd_t *id, ulong dest_addr) console_init_r(); /* fully init console as a device */ +#ifdef CONFIG_DISPLAY_BOARDINFO_LATE +# ifdef CONFIG_OF_CONTROL + /* Put this here so it appears on the LCD, now it is ready */ + display_fdt_model(gd->fdt_blob); +# else + checkboard(); +# endif +#endif + #if defined(CONFIG_ARCH_MISC_INIT) /* miscellaneous arch dependent initialisations */ arch_misc_init(); -- cgit v1.2.1 From 15a33e49decc81f34b35998a61757bfe2becae83 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 30 Nov 2012 13:01:20 +0000 Subject: Add option to display customised memory information Some boards want to report more than just memory size. For example, it might be useful to display the memory type (DDR2, DDR3) or manufacturer. Add a weak function to support this requirement, accessed through a new 'meminfo' command. Any example of the DRAM: output is below, just for illustration: SMDK5250 # meminfo DRAM: 2 GiB Elpida DDR3 @ 800MHz Signed-off-by: Simon Glass --- README | 1 + common/cmd_mem.c | 27 +++++++++++++++++++++++++++ include/common.h | 9 +++++++++ include/config_cmd_all.h | 1 + 4 files changed, 38 insertions(+) diff --git a/README b/README index 9c261680d4..a9a92d7f83 100644 --- a/README +++ b/README @@ -849,6 +849,7 @@ The following options need to be configured: CONFIG_CMD_LOADS loads CONFIG_CMD_MD5SUM print md5 message digest (requires CONFIG_CMD_MEMORY and CONFIG_MD5) + CONFIG_CMD_MEMINFO * Display detailed memory information CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, loop, loopw, mtest CONFIG_CMD_MISC Misc functions like sleep etc diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 4d64cfffde..0f3ffc84ff 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -33,6 +33,9 @@ #include #endif #include +#include + +DECLARE_GLOBAL_DATA_PTR; static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); @@ -1203,6 +1206,22 @@ U_BOOT_CMD( #endif +#ifdef CONFIG_CMD_MEMINFO +__weak void board_show_dram(ulong size) +{ + puts("DRAM: "); + print_size(size, "\n"); +} + +static int do_mem_info(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + board_show_dram(gd->ram_size); + + return 0; +} +#endif + U_BOOT_CMD( base, 2, 1, do_mem_base, "print or set address offset", @@ -1243,3 +1262,11 @@ U_BOOT_CMD( "[.b, .w, .l] address value delay(ms)" ); #endif /* CONFIG_MX_CYCLIC */ + +#ifdef CONFIG_CMD_MEMINFO +U_BOOT_CMD( + meminfo, 3, 1, do_mem_info, + "display memory information", + "" +); +#endif diff --git a/include/common.h b/include/common.h index 2f2578bef5..4ad17eafb9 100644 --- a/include/common.h +++ b/include/common.h @@ -311,6 +311,15 @@ int mac_read_from_eeprom(void); extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +/** + * Show the DRAM size in a board-specific way + * + * This is used by boards to display DRAM information in their own way. + * + * @param size Size of DRAM (which should be displayed along with other info) + */ +void board_show_dram(ulong size); + /* common/flash.c */ void flash_perror (int); diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index e82f6421c0..2a82e19c78 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -56,6 +56,7 @@ #define CONFIG_CMD_LICENSE /* console license display */ #define CONFIG_CMD_LOADB /* loadb */ #define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMINFO /* meminfo */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ #define CONFIG_CMD_MFSL /* FSL support for Microblaze */ #define CONFIG_CMD_MII /* MII support */ -- cgit v1.2.1 From fe34f8dc8ca719d83a4bc67a35e15dfc780559e9 Mon Sep 17 00:00:00 2001 From: Tom Wai-Hong Tam Date: Fri, 30 Nov 2012 13:01:21 +0000 Subject: arm: Make interrupts.o and reset.o in libarm also appear in SPL SPL u-boot may call do_reset() which depends on interrupts.o and reset.o. So make them also appear in SPL. Signed-off-by: Tom Wai-Hong Tam Signed-off-by: Simon Glass --- arch/arm/lib/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 07baee2ec6..57111afd90 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -42,14 +42,15 @@ ifndef CONFIG_SPL_BUILD COBJS-y += board.o COBJS-y += bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o -COBJS-y += interrupts.o -COBJS-y += reset.o SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o else COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o endif +COBJS-y += interrupts.o +COBJS-y += reset.o + COBJS-y += cache.o COBJS-y += cache-cp15.o -- cgit v1.2.1 From 2f8d8d6b3aedcea36db84872a4174eb8d5903f8f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 30 Nov 2012 13:01:22 +0000 Subject: arm: Move bootstage record for board_init_f() to after arch_cpu_init() The timer may be inited in arch_cpu_init() so it is not safe to make a bootstage mark before this is called. Arrange the code to fix this. Note: The question was raised as to why we don't keep all archs in sync. PowerPC doesn't have specific bootstage markers at present (although it does use boot progress). I hope that the generic board series will solve this problem in general, but in the meantime this is a real problem, and only in ARM. We now get a correct time for board_init_f: Timer summary in microseconds: Mark Elapsed Stage 0 0 reset 100,000 100,000 spl_start 848,530 748,530 board_init_f 907,301 58,771 board_init_r 910,478 3,177 board_init Signed-off-by: Simon Glass --- arch/arm/lib/board.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index ec5c35f131..404ef4dceb 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -232,8 +232,17 @@ int __power_init_board(void) int power_init_board(void) __attribute__((weak, alias("__power_init_board"))); + /* Record the board_init_f() bootstage (after arch_cpu_init()) */ +static int mark_bootstage(void) +{ + bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); + + return 0; +} + init_fnc_t *init_sequence[] = { arch_cpu_init, /* basic arch cpu dependent setup */ + mark_bootstage, #ifdef CONFIG_OF_CONTROL fdtdec_check_fdt, #endif @@ -277,8 +286,6 @@ void board_init_f(ulong bootflag) void *new_fdt = NULL; size_t fdt_size = 0; - bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); - memset((void *)gd, 0, sizeof(gd_t)); gd->mon_len = _bss_end_ofs; -- cgit v1.2.1 From 80e409508b9bba8c372cdd44565a3d472b10e904 Mon Sep 17 00:00:00 2001 From: Taylor Hutt Date: Fri, 30 Nov 2012 13:01:23 +0000 Subject: arm: Tabify code for MMC initialization The two modified lines were indented with spaces. They are now indented with tabs. Signed-off-by: Taylor Hutt Signed-off-by: Simon Glass --- arch/arm/lib/board.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 404ef4dceb..cfe32cc926 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -599,8 +599,8 @@ void board_init_r(gd_t *id, ulong dest_addr) #endif #ifdef CONFIG_GENERIC_MMC - puts("MMC: "); - mmc_initialize(gd->bd); + puts("MMC: "); + mmc_initialize(gd->bd); #endif #ifdef CONFIG_HAS_DATAFLASH -- cgit v1.2.1 From 0e29a2481468e238f3925343aad78d9fa6e1d4f0 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Fri, 28 Dec 2012 02:51:53 +0000 Subject: OMAP3: igep00x0: add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_NAND_SUPPORT When booting an IGEPv2 board from NAND with SPL, U-Boot hangs trying to read the OMAP General Purpose Memory Controller (GPMC). The reason is that the GPMC initialization function is called inside spl_board_init() and this function is only executed when CONFIG_SPL_BOARD_INIT is defined. Signed-off-by: Javier Martinez Canillas Acked-by: Enric Balletbo i Serra --- include/configs/igep00x0.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 43dd06e246..0617a58a26 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -312,6 +312,7 @@ #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT -- cgit v1.2.1 From 94bcfe524cab9574f799bd2b7df9c7de2b81465a Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 2 Jan 2013 07:59:24 +0000 Subject: Makefile: remove MLO.byteswap on clobber On clobber, do a cleanup even for SPL build else, we'd have MLO.byteswap remaining for certain platforms like am33xx SPL builds Signed-off-by: Nishanth Menon --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a7b6cd1cba..4e64622967 100644 --- a/Makefile +++ b/Makefile @@ -869,7 +869,7 @@ clobber: tidy @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map} @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst} - @rm -f $(obj)MLO + @rm -f $(obj)MLO MLO.byteswap @rm -f $(obj)SPL @rm -f $(obj)tools/xway-swap-bytes @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c -- cgit v1.2.1 From 7de0fe1ac330399afc1873e11061668a93cf4fb9 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 7 Jan 2013 01:35:20 +0000 Subject: serial/ns16550: add an option to avoid hanging on broken platforms Some platforms (e.g. IGEPv2 board) has a broken ns16550 UART that does not set the TEMT bit when the transmitter is empty in SPL. This makes U-Boot to hang while waiting for TEMT to be set. Add a new option to avoid this: CONFIG_SYS_NS16550_BROKEN_TEMT 16550 UART set the Transmitter Empty (TEMT) Bit when all output has finished and the transmitter is totally empty. U-Boot waits for this bit to be set to initialize the serial console. On some broken platforms this bit is not set in SPL making U-Boot to hang while waiting for TEMT. Define this option to avoid it. Signed-off-by: Javier Martinez Canillas --- README | 8 ++++++++ drivers/serial/ns16550.c | 2 ++ 2 files changed, 10 insertions(+) diff --git a/README b/README index 653ef6aa4a..98dbe98c2e 100644 --- a/README +++ b/README @@ -616,6 +616,14 @@ The following options need to be configured: boot loader that has already initialized the UART. Define this variable to flush the UART at init time. + CONFIG_SYS_NS16550_BROKEN_TEMT + + 16550 UART set the Transmitter Empty (TEMT) Bit when all output + has finished and the transmitter is totally empty. U-Boot waits + for this bit to be set to initialize the serial console. On some + broken platforms this bit is not set in SPL making U-Boot to + hang while waiting for TEMT. Define this option to avoid it. + - Console Interface: Depending on board, define exactly one serial port diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index bbd91ca247..87a0917086 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -36,8 +36,10 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) { +#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT)) while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) ; +#endif serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ -- cgit v1.2.1 From 039cbaefcf57338cc9b6a3c656db64e7907838db Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 7 Jan 2013 01:35:21 +0000 Subject: OMAP3: igep00x0: add CONFIG_SYS_NS16550_BROKEN_TEMT IGEP board PC16550D (ns16550) UART doesn't set the Transmitter Empty (TEMT) Bit in SPL. This makes U-Boot to hang while waiting for TEMT. Add the CONFIG_SYS_NS16550_BROKEN_TEMT config option to avoid this issue. Signed-off-by: Javier Martinez Canillas --- include/configs/igep00x0.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 0617a58a26..f8131b1baf 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -67,6 +67,9 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +/* define to avoid U-Boot to hang while waiting for TEMT */ +#define CONFIG_SYS_NS16550_BROKEN_TEMT + /* select serial console configuration */ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -- cgit v1.2.1