From 1903bb91c4dde49a1a44bd6b769527165c8a4d34 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 2 Jun 2016 18:46:09 +0200 Subject: sunxi: Enable ALDO3 and ALDO4 in Wobo_i5_defconfig These are used for the usb wifi and if we leave the enabling up to the kernel, we get hit by the axp209 issues with enabling ldo3 or 4 post boot and the systems hangs as soon as it is enabled. Signed-off-by: Hans de Goede --- configs/Wobo_i5_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index fc43cc5fb1..17ed968597 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -11,3 +11,5 @@ CONFIG_SPL=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y +CONFIG_AXP_ALDO3_VOLT=3300 +CONFIG_AXP_ALDO4_VOLT=3300 -- cgit v1.2.1 From fd2aa39a619ce011414f6cb6efb0232136e300c7 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 5 Jun 2016 14:40:44 +0200 Subject: sunxi: Add INITIAL_USB_SCAN_DELAY to Mele_A1000G_quad_defconfig The Mele_A1000G_quad has an onboard usb <-> sata conversion which needs longer then the usb-spec allows to connect after getting power. Signed-off-by: Hans de Goede --- configs/Mele_A1000G_quad_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index b3f825e33f..2ac2596dce 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN6I=y CONFIG_DRAM_ZQ=120 +CONFIG_INITIAL_USB_SCAN_DELAY=2000 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad" -- cgit v1.2.1 From bca4c3c5fcb3d170308e621dadcc5555a1aca1b8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 5 Jun 2016 16:53:04 +0200 Subject: sunxi: musb: Properly turn of musb controller before booting Turn of the clock and assert the reset when musb_stop gets called, so that the os gets the musb controller in a pristine state. This fixes a spurious VBus error interrupt triggering as soon as the Linux musb driver loads. Signed-off-by: Hans de Goede --- drivers/usb/musb-new/sunxi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c index 3081afca0e..c016a0bb54 100644 --- a/drivers/usb/musb-new/sunxi.c +++ b/drivers/usb/musb-new/sunxi.c @@ -340,9 +340,16 @@ int musb_usb_probe(struct udevice *dev) int musb_usb_remove(struct udevice *dev) { struct musb_host_data *host = dev_get_priv(dev); + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; musb_stop(host->host); + sunxi_usb_phy_exit(0); +#ifdef CONFIG_SUNXI_GEN_SUN6I + clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_GATE_OFFSET_USB0); +#endif + clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_USB0); + return 0; } -- cgit v1.2.1 From 5bc88cc2be3a962005b6e5768e06ca8f6ffcb88d Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Tue, 31 May 2016 01:48:05 +0300 Subject: sunxi: Downclock AHB1 to 100MHz on Allwinner A64 Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test). For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x: 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1 However the FEL mode uses more conservative settings (100MHz for AHB1): 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3190 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0 It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level. Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too). Signed-off-by: Siarhei Siamashka Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index f2990db928..c2e72f5a86 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -222,7 +222,12 @@ struct sunxi_ccm_reg { #define CCM_PLL11_CTRL_UPD (0x1 << 30) #define CCM_PLL11_CTRL_EN (0x1 << 31) +#if defined(CONFIG_MACH_SUN50I) +/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ +#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ +#else #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ +#endif #define AXI_GATE_OFFSET_DRAM 0 -- cgit v1.2.1 From 1a83fb4a17d959d7b037999ab7ed7e62429abe34 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Tue, 31 May 2016 01:48:06 +0300 Subject: sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80 Since the SRAM C corruption issue is now resolved on Allwinner A64, it is possible to move the stack top to the address 0x1A000 on both A64 and A80. The boot ROM can load SPL binaries with up to 32 KiB size on A64 (the 24 KiB SPL size limitation only affects A10/A20), and this patch also ensures the availability of 8 KiB stack. Signed-off-by: Siarhei Siamashka Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- include/configs/sunxi-common.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index b33cfb86f8..94275a7183 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -100,7 +100,7 @@ * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. */ #define CONFIG_SYS_INIT_RAM_ADDR 0x10000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ +#define CONFIG_SYS_INIT_RAM_SIZE 0xA000 /* 40 KiB */ #else #define CONFIG_SYS_INIT_RAM_ADDR 0x0 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ @@ -213,8 +213,7 @@ #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ #if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I) -/* FIXME: 40 KiB instead of 32 KiB ? */ -#define LOW_LEVEL_SRAM_STACK 0x00018000 +#define LOW_LEVEL_SRAM_STACK 0x0001A000 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #else /* end of 32 KiB in sram */ -- cgit v1.2.1