From 534992827756c3a1ab49823ca487702a954fe433 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Tue, 31 May 2016 15:39:06 +0800 Subject: board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot We should use unified setup_ddr_tlbs() for spl boot and non-spl boot to make sure 'M' bit is set for DDR TLB to maintain cache coherence. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- board/freescale/b4860qds/ddr.c | 8 +++----- board/freescale/t102xqds/ddr.c | 5 ++--- board/freescale/t102xrdb/ddr.c | 4 ++-- board/freescale/t104xrdb/ddr.c | 7 ++----- board/freescale/t208xqds/ddr.c | 5 ++--- board/freescale/t208xrdb/ddr.c | 6 +++--- board/freescale/t4qds/ddr.c | 7 +++---- board/freescale/t4rdb/ddr.c | 5 ++--- 8 files changed, 19 insertions(+), 28 deletions(-) diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index eb10a6f364..31b186ea8c 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -179,15 +179,13 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c index 2d4d10f351..fa1394d9f0 100644 --- a/board/freescale/t102xqds/ddr.c +++ b/board/freescale/t102xqds/ddr.c @@ -172,14 +172,13 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index adf9fd5f78..b13692bb4a 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -234,12 +234,12 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); #endif dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index cf79d2ddb2..22d6a5f617 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -124,15 +124,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index f1aff5481e..f96470f020 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -108,13 +108,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; return dram_size; } diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 053f128e5b..f6c8ca30ac 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -101,12 +101,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 62d58c5b1f..d533924a0d 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,13 +117,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index 27b37b5cc4..230f031a3b 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -110,13 +110,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; return dram_size; } -- cgit v1.2.1