From 4ba73a5ac7d2ece1d17bb1c109d694ce306ac1af Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:36:53 +0200 Subject: sunxi: mksunxiboot: Fix loading of files with a size which is not a multiple of 4 We should not be aligning the amount of bytes which we try to read from the disk, this leads to trying to read more bytes then there are which fails. file_size is already aligned to BLOCK_SIZE before being stored in img.header.length, so there is no need for load_size at all. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- tools/mksunxiboot.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c index da7c9f0ddc..1f0fbae8e1 100644 --- a/tools/mksunxiboot.c +++ b/tools/mksunxiboot.c @@ -77,7 +77,7 @@ int main(int argc, char *argv[]) { int fd_in, fd_out; struct boot_img img; - unsigned file_size, load_size; + unsigned file_size; int count; if (argc < 2) { @@ -101,8 +101,6 @@ int main(int argc, char *argv[]) if (file_size > SRAM_LOAD_MAX_SIZE) { fprintf(stderr, "ERROR: File too large!\n"); return EXIT_FAILURE; - } else { - load_size = ALIGN(file_size, sizeof(int)); } fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666); @@ -113,8 +111,8 @@ int main(int argc, char *argv[]) /* read file to buffer to calculate checksum */ lseek(fd_in, 0, SEEK_SET); - count = read(fd_in, img.code, load_size); - if (count != load_size) { + count = read(fd_in, img.code, file_size); + if (count != file_size) { perror("Reading input image"); return EXIT_FAILURE; } @@ -126,7 +124,7 @@ int main(int argc, char *argv[]) & 0x00FFFFFF); memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */ img.header.length = - ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE); + ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE); gen_check_sum(&img.header); count = write(fd_out, &img, img.header.length); -- cgit v1.2.1 From 9e5f80d823e3fd2a685b10ecf02009e34b86cff9 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:36:54 +0200 Subject: sunxi: Fix u-boot-spl.lds to refer to .vectors Adjust the u-boot-spl.lds linker script to match the changes made in the 41623c91b09a0c865fab41acdaff30f060f29ad6 "arm: move exception handling out of start.S files" commit. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds index 5008028aae..c1ae227f06 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -27,6 +27,7 @@ SECTIONS .text : { __start = .; + *(.vectors) arch/arm/cpu/armv7/start.o (.text) *(.text*) } > .sram -- cgit v1.2.1 From b6ae6765c5a9e5daa3799e4d65562d3184712506 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:36:55 +0200 Subject: sunxi: Remove mmc DMA support The DMA code in sunxi_mmc.c is broken. mmc_trans_data_by_dma() allocates the dma descriptors on the stack, and then exits while the dma transfer is in progress, so the dma engine is reading stack memory which at that point may be re-used. So far we've gotten away with this by luck, but recent u-boot changes have shifted the stack start address by 16 bytes, which combined with dma alignment now exposes this problem. Since we end up just busy waiting for the dma engine anyway, this commit fixes things by simply removing the dma code, resulting in smaller bug-free code. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/mmc/sunxi_mmc.c | 141 ++--------------------------------------- include/configs/sunxi-common.h | 1 - 2 files changed, 7 insertions(+), 135 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index eb7b1158d6..d4e574fe19 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -16,28 +16,6 @@ #include #include -struct sunxi_mmc_des { - u32 reserved1_1:1; - u32 dic:1; /* disable interrupt on completion */ - u32 last_des:1; /* 1-this data buffer is the last buffer */ - u32 first_des:1; /* 1-data buffer is the first buffer, - 0-data buffer contained in the next - descriptor is 1st buffer */ - u32 des_chain:1; /* 1-the 2nd address in the descriptor is the - next descriptor address */ - u32 end_of_ring:1; /* 1-last descriptor flag when using dual - data buffer in descriptor */ - u32 reserved1_2:24; - u32 card_err_sum:1; /* transfer error flag */ - u32 own:1; /* des owner:1-idma owns it, 0-host owns it */ -#define SDXC_DES_NUM_SHIFT 16 -#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) - u32 data_buf1_sz:16; - u32 data_buf2_sz:16; - u32 buf_addr_ptr1; - u32 buf_addr_ptr2; -}; - struct sunxi_mmc_host { unsigned mmc_no; uint32_t *mclkreg; @@ -189,6 +167,7 @@ static int mmc_core_init(struct mmc *mmc) /* Reset controller */ writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + udelay(1000); return 0; } @@ -204,6 +183,9 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) unsigned timeout_msecs = 2000; unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); + /* Always read / write data through the CPU */ + setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); + for (i = 0; i < (byte_cnt >> 2); i++) { while (readl(&mmchost->reg->status) & status_bit) { if (!timeout_msecs--) @@ -220,85 +202,6 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) return 0; } -static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data) -{ - struct sunxi_mmc_host *mmchost = mmc->priv; - unsigned byte_cnt = data->blocksize * data->blocks; - unsigned char *buff; - unsigned des_idx = 0; - unsigned buff_frag_num = - (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT; - unsigned remain; - unsigned i, rval; - ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num); - - buff = data->flags & MMC_DATA_READ ? - (unsigned char *)data->dest : (unsigned char *)data->src; - remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1); - - flush_cache((unsigned long)buff, (unsigned long)byte_cnt); - for (i = 0; i < buff_frag_num; i++, des_idx++) { - memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des)); - pdes[des_idx].des_chain = 1; - pdes[des_idx].own = 1; - pdes[des_idx].dic = 1; - if (buff_frag_num > 1 && i != buff_frag_num - 1) - pdes[des_idx].data_buf1_sz = 0; /* 0 == max_len */ - else - pdes[des_idx].data_buf1_sz = remain; - - pdes[des_idx].buf_addr_ptr1 = - (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN; - if (i == 0) - pdes[des_idx].first_des = 1; - - if (i == buff_frag_num - 1) { - pdes[des_idx].dic = 0; - pdes[des_idx].last_des = 1; - pdes[des_idx].end_of_ring = 1; - pdes[des_idx].buf_addr_ptr2 = 0; - } else { - pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1]; - } - } - flush_cache((unsigned long)pdes, - sizeof(struct sunxi_mmc_des) * (des_idx + 1)); - - rval = readl(&mmchost->reg->gctrl); - /* Enable DMA */ - writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE, - &mmchost->reg->gctrl); - /* Reset iDMA */ - writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac); - /* Enable iDMA */ - writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE, - &mmchost->reg->dmac); - rval = readl(&mmchost->reg->idie) & - ~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ); - if (data->flags & MMC_DATA_WRITE) - rval |= SUNXI_MMC_IDIE_TXIRQ; - else - rval |= SUNXI_MMC_IDIE_RXIRQ; - writel(rval, &mmchost->reg->idie); - writel((u32) pdes, &mmchost->reg->dlba); - writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3), - &mmchost->reg->ftrglevel); - - return 0; -} - -static void mmc_enable_dma_accesses(struct mmc *mmc, int dma) -{ - struct sunxi_mmc_host *mmchost = mmc->priv; - - unsigned int gctrl = readl(&mmchost->reg->gctrl); - if (dma) - gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB; - else - gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB; - writel(gctrl, &mmchost->reg->gctrl); -} - static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, unsigned int done_bit, const char *what) { @@ -327,7 +230,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, unsigned int timeout_msecs; int error = 0; unsigned int status = 0; - unsigned int usedma = 0; unsigned int bytecnt = 0; if (mmchost->fatal_err) @@ -378,20 +280,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, bytecnt = data->blocksize * data->blocks; debug("trans data %d bytes\n", bytecnt); -#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD) - if (bytecnt > 64) { -#else - if (0) { -#endif - usedma = 1; - mmc_enable_dma_accesses(mmc, 1); - ret = mmc_trans_data_by_dma(mmc, data); - writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); - } else { - mmc_enable_dma_accesses(mmc, 0); - writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); - ret = mmc_trans_data_by_cpu(mmc, data); - } + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + ret = mmc_trans_data_by_cpu(mmc, data); if (ret) { error = readl(&mmchost->reg->rint) & \ SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; @@ -405,7 +295,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, goto out; if (data) { - timeout_msecs = usedma ? 120 * bytecnt : 120; + timeout_msecs = 120; debug("cacl timeout %x msec\n", timeout_msecs); error = mmc_rint_wait(mmc, timeout_msecs, data->blocks > 1 ? @@ -442,23 +332,6 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, debug("mmc resp 0x%08x\n", cmd->response[0]); } out: - if (data && usedma) { - /* IDMASTAREG - * IDST[0] : idma tx int - * IDST[1] : idma rx int - * IDST[2] : idma fatal bus error - * IDST[4] : idma descriptor invalid - * IDST[5] : idma error summary - * IDST[8] : idma normal interrupt sumary - * IDST[9] : idma abnormal interrupt sumary - */ - status = readl(&mmchost->reg->idst); - writel(status, &mmchost->reg->idst); - writel(0, &mmchost->reg->idie); - writel(0, &mmchost->reg->dmac); - writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE, - &mmchost->reg->gctrl); - } if (error < 0) { writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); mmc_update_clk(mmc); diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d72d62f14..fd02d0dc83 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -70,7 +70,6 @@ #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI #define CONFIG_MMC_SUNXI_SLOT 0 -#define CONFIG_MMC_SUNXI_USE_DMA #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ -- cgit v1.2.1 From c7e79dec85f324565cee03f5be1d1a7765481573 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:36:56 +0200 Subject: sunxi: Implement reset_cpu There is no way to reset the cpu, so use the watchdog for this. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/board.c | 7 +++++++ arch/arm/include/asm/arch-sunxi/timer.h | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c94489ee..c80b42121c 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -56,6 +56,13 @@ int gpio_init(void) void reset_cpu(ulong addr) { + static const struct sunxi_wdog *wdog = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set the watchdog for its shortest interval (.5s) and wait */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); + while (1); } /* do some early init */ diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h index 6aacfd7b39..58e14fd0f7 100644 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -11,6 +11,11 @@ #ifndef _SUNXI_TIMER_H_ #define _SUNXI_TIMER_H_ +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) +#define WDT_MODE_EN (0x1 << 0) +#define WDT_MODE_RESET_EN (0x1 << 1) + #ifndef __ASSEMBLY__ #include -- cgit v1.2.1 From 745325a97d172a71dea4ec7528224ed63973d601 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:36:57 +0200 Subject: sunxi: Add sun4i support Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family, and add the Cubieboard board which uses the A10 SoC. Compared to sun7 only the DRAM controller is a bit different: -Controller reset bits are inverted, but only for Rev. A -Different hpcr values -No MBUS on sun4i -Various other initialization changes Signed-off-by: Henrik Nordstrom Signed-off-by: Stefan Roese Signed-off-by: Oliver Schinagl Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/Makefile | 2 + arch/arm/cpu/armv7/sunxi/cpu_info.c | 7 ++++ arch/arm/cpu/armv7/sunxi/dram.c | 81 +++++++++++++++++++++++++++++++++++-- board/sunxi/Makefile | 1 + board/sunxi/dram_cubieboard.c | 31 ++++++++++++++ boards.cfg | 1 + include/configs/sun4i.h | 23 +++++++++++ 7 files changed, 143 insertions(+), 3 deletions(-) create mode 100644 board/sunxi/dram_cubieboard.c create mode 100644 include/configs/sun4i.h diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index a64bfa18e0..856d353528 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -11,6 +11,7 @@ obj-y += timer.o obj-y += board.o obj-y += clock.o obj-y += pinmux.o +obj-$(CONFIG_SUN4I) += clock_sun4i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o ifndef CONFIG_SPL_BUILD @@ -18,6 +19,7 @@ obj-y += cpu_info.o endif ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SUN4I) += dram.o obj-$(CONFIG_SUN7I) += dram.o ifdef CONFIG_SPL_FEL obj-y += start.o diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index b4c3d5c6dd..b4b5089fec 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -13,7 +13,14 @@ #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { +#ifdef CONFIG_SUN4I + puts("CPU: Allwinner A10 (SUN4I)\n"); +#elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); +#else +#warning Please update cpu_info.c with correct CPU information + puts("CPU: SUNXI Family\n"); +#endif return 0; } #endif diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index b43c4b41d3..1de752904b 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -53,16 +53,37 @@ static void mctl_ddr3_reset(void) struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; - clrbits_le32(&dram->mcr, DRAM_MCR_RESET); - udelay(2); - setbits_le32(&dram->mcr, DRAM_MCR_RESET); +#ifdef CONFIG_SUN4I + struct sunxi_timer_reg *timer = + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + u32 reg_val; + + writel(0, &timer->cpu_cfg); + reg_val = readl(&timer->cpu_cfg); + + if ((reg_val & CPU_CFG_CHIP_VER_MASK) != + CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) { + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(2); + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + } else +#endif + { + clrbits_le32(&dram->mcr, DRAM_MCR_RESET); + udelay(2); + setbits_le32(&dram->mcr, DRAM_MCR_RESET); + } } static void mctl_set_drive(void) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; +#ifdef CONFIG_SUN7I clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), +#else + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), +#endif DRAM_MCR_MODE_EN(0x3) | 0xffc); } @@ -134,6 +155,16 @@ static void mctl_enable_dllx(u32 phase) } static u32 hpcr_value[32] = { +#ifdef CONFIG_SUN4I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x5031, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x1031, 0x0301, 0x0301, 0x0731 +#endif #ifdef CONFIG_SUN7I 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, @@ -223,22 +254,32 @@ static void mctl_setup_dram_clock(u32 clk) clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); #endif +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) /* setup MBUS clock */ reg_val = CCM_MBUS_CTRL_GATE | CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) | CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) | CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); writel(reg_val, &ccm->mbus_clk_cfg); +#endif /* * open DRAMC AHB & DLL register clock * close it first */ +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif udelay(22); /* then open it */ +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); +#else + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); +#endif udelay(22); } @@ -385,6 +426,13 @@ static void dramc_clock_output_en(u32 on) else clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT); #endif +#ifdef CONFIG_SUN4I + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + if (on) + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); + else + clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT); +#endif } static const u16 tRFC_table[2][6] = { @@ -421,11 +469,19 @@ unsigned long dramc_init(struct dram_para *para) mctl_setup_dram_clock(para->clock); /* reset external DRAM */ +#ifndef CONFIG_SUN7I + mctl_ddr3_reset(); +#endif mctl_set_drive(); /* dram clock off */ dramc_clock_output_en(0); +#ifdef CONFIG_SUN4I + /* select dram controller 1 */ + writel(DRAM_CSEL_MAGIC, &dram->csel); +#endif + mctl_itm_disable(); mctl_enable_dll0(para->tpr3); @@ -482,6 +538,9 @@ unsigned long dramc_init(struct dram_para *para) mctl_ddr3_reset(); else setbits_le32(&dram->mcr, DRAM_MCR_RESET); +#else + /* dram clock on */ + dramc_clock_output_en(1); #endif udelay(1); @@ -490,6 +549,22 @@ unsigned long dramc_init(struct dram_para *para) mctl_enable_dllx(para->tpr3); +#ifdef CONFIG_SUN4I + /* set odt impedance divide ratio */ + reg_val = ((para->zq) >> 8) & 0xfffff; + reg_val |= ((para->zq) & 0xff) << 20; + reg_val |= (para->zq) & 0xf0000000; + writel(reg_val, &dram->zqcr0); +#endif + +#ifdef CONFIG_SUN4I + /* set I/O configure register */ + reg_val = 0x00cc0000; + reg_val |= (para->odt_en) & 0x3; + reg_val |= ((para->odt_en) & 0x3) << 30; + writel(reg_val, &dram->iocr); +#endif + /* set refresh period */ dramc_set_autorefresh_cycle(para->clock, para->type - 2, density); diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index cbf8f086a9..4902d70834 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -10,4 +10,5 @@ # obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o diff --git a/board/sunxi/dram_cubieboard.c b/board/sunxi/dram_cubieboard.c new file mode 100644 index 0000000000..399028ca96 --- /dev/null +++ b/board/sunxi/dram_cubieboard.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include +#include + +static struct dram_para dram_para = { + .clock = 480, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 6, + .zq = 123, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x30926692, + .tpr1 = 0x1090, + .tpr2 = 0x1a0c8, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0, + .emr2 = 0, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/boards.cfg b/boards.cfg index 6f8d168cf1..af241283c7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -377,6 +377,7 @@ Active arm armv7 rmobile renesas lager Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL Hans de Goede Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h new file mode 100644 index 0000000000..6560b65b38 --- /dev/null +++ b/include/configs/sun4i.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * + * Configuration settings for the Allwinner A10 (sun4i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A10 specific configuration + */ +#define CONFIG_SUN4I /* sun4i SoC generation */ + +#define CONFIG_SYS_PROMPT "sun4i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ -- cgit v1.2.1 From f84269c5c0ac3944532fce6fcadaeb7912d014e8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:36:58 +0200 Subject: sunxi: Add sun5i support Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based boards. The only differences compared to the already supported sun4i and sun7i families are all in the DRAM controller initialization: -Different hcpr values -Different MBUS settings -Some other small initialization changes Signed-off-by: Henrik Nordstrom Signed-off-by: Stefan Roese Signed-off-by: Oliver Schinagl Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 12 ++++++++++++ arch/arm/cpu/armv7/sunxi/cpu_info.c | 8 ++++++++ arch/arm/cpu/armv7/sunxi/dram.c | 21 +++++++++++++++++++++ board/sunxi/Makefile | 2 ++ board/sunxi/dram_a13_oli_micro.c | 32 ++++++++++++++++++++++++++++++++ board/sunxi/dram_r7dongle.c | 31 +++++++++++++++++++++++++++++++ boards.cfg | 2 ++ include/configs/sun5i.h | 23 +++++++++++++++++++++++ include/configs/sunxi-common.h | 2 ++ 10 files changed, 135 insertions(+) create mode 100644 board/sunxi/dram_a13_oli_micro.c create mode 100644 board/sunxi/dram_r7dongle.c create mode 100644 include/configs/sun5i.h diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 856d353528..6c706393d3 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,6 +12,7 @@ obj-y += board.o obj-y += clock.o obj-y += pinmux.o obj-$(CONFIG_SUN4I) += clock_sun4i.o +obj-$(CONFIG_SUN5I) += clock_sun4i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o ifndef CONFIG_SPL_BUILD @@ -20,6 +21,7 @@ endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SUN4I) += dram.o +obj-$(CONFIG_SUN5I) += dram.o obj-$(CONFIG_SUN7I) += dram.o ifdef CONFIG_SPL_FEL obj-y += start.o diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index c80b42121c..0118f5b418 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -47,9 +47,21 @@ u32 spl_boot_mode(void) int gpio_init(void) { +#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(23), 1); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(20), 1); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); + sunxi_gpio_set_pull(SUNXI_GPG(4), 1); +#else +#error Unsupported console port number. Please fix pin mux settings in board.c +#endif return 0; } diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index b4b5089fec..5cf35acc1e 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -15,6 +15,14 @@ int print_cpuinfo(void) { #ifdef CONFIG_SUN4I puts("CPU: Allwinner A10 (SUN4I)\n"); +#elif defined CONFIG_SUN5I + u32 val = readl(SUNXI_SID_BASE + 0x08); + switch ((val >> 12) & 0xf) { + case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break; + case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break; + case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break; + default: puts("CPU: Allwinner A1X (SUN5I)\n"); + } #elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); #else diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c index 1de752904b..0f1ceecc1d 100644 --- a/arch/arm/cpu/armv7/sunxi/dram.c +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -155,6 +155,16 @@ static void mctl_enable_dllx(u32 phase) } static u32 hpcr_value[32] = { +#ifdef CONFIG_SUN5I + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0, + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0 +#endif #ifdef CONFIG_SUN4I 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0x0301, 0, 0, @@ -257,9 +267,15 @@ static void mctl_setup_dram_clock(u32 clk) #if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) /* setup MBUS clock */ reg_val = CCM_MBUS_CTRL_GATE | +#ifdef CONFIG_SUN7I CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) | CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) | CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); +#else /* defined(CONFIG_SUN5I) */ + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) | + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) | + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2)); +#endif writel(reg_val, &ccm->mbus_clk_cfg); #endif @@ -468,6 +484,11 @@ unsigned long dramc_init(struct dram_para *para) /* setup DRAM relative clock */ mctl_setup_dram_clock(para->clock); +#ifdef CONFIG_SUN5I + /* Disable any pad power save control */ + writel(0, &dram->ppwrsctl); +#endif + /* reset external DRAM */ #ifndef CONFIG_SUN7I mctl_ddr3_reset(); diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 4902d70834..708363290a 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -10,5 +10,7 @@ # obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o +obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o +obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o diff --git a/board/sunxi/dram_a13_oli_micro.c b/board/sunxi/dram_a13_oli_micro.c new file mode 100644 index 0000000000..8154ea2ca9 --- /dev/null +++ b/board/sunxi/dram_a13_oli_micro.c @@ -0,0 +1,32 @@ +/* this file is generated, don't edit it yourself */ + +#include +#include + +static struct dram_para dram_para = { + .clock = 408, + .type = 3, + .rank_num = 1, + .density = 2048, + .io_width = 16, + .bus_width = 16, + .cas = 9, + .zq = 123, + .odt_en = 0, + .size = 256, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0, + .emr2 = 0x10, + .emr3 = 0, + +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/board/sunxi/dram_r7dongle.c b/board/sunxi/dram_r7dongle.c new file mode 100644 index 0000000000..59343cb2a5 --- /dev/null +++ b/board/sunxi/dram_r7dongle.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include +#include + +static struct dram_para dram_para = { + .clock = 384, + .type = 3, + .rank_num = 1, + .density = 2048, + .io_width = 8, + .bus_width = 32, + .cas = 9, + .zq = 123, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0x04, + .emr2 = 0x10, + .emr3 = 0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/boards.cfg b/boards.cfg index af241283c7..20ad48868d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -377,9 +377,11 @@ Active arm armv7 rmobile renesas lager Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL Hans de Goede Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - +Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h new file mode 100644 index 0000000000..43f0d67345 --- /dev/null +++ b/include/configs/sun5i.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom + * + * Configuration settings for the Allwinner A13 (sun5i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_SUN5I /* sun5i SoC generation */ + +#define CONFIG_SYS_PROMPT "sun5i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index fd02d0dc83..1d1c87d000 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -161,7 +161,9 @@ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS +#ifndef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 1 /* UART0 */ +#endif #ifdef CONFIG_SUNXI_GMAC #define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ -- cgit v1.2.1 From b70ed300b0dcf23e46265904ddc4fbf9a72b99b8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 9 Jun 2014 11:36:59 +0200 Subject: net: Rename and cleanup sunxi (Allwinner) emac driver There have been 3 versions of the sunxi_emac support patch during its development. Somehow version 2 ended up in upstream u-boot where as the u-boot-sunxi git repo got version 3. This bumps the version in upstream u-boot to version 3 of the patch: - Initialize MII clock earlier so mii access to allow independent use - Name change from WEMAC to EMAC to match mainline kernel & chip manual - Cosmetic code cleanup Signed-off-by: Stefan Roese Signed-off-by: Henrik Nordstrom Signed-off-by: Oliver Schinagl Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/net/Makefile | 2 +- drivers/net/sunxi_emac.c | 521 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/sunxi_wemac.c | 525 ---------------------------------------------- include/netdev.h | 2 +- 4 files changed, 523 insertions(+), 527 deletions(-) create mode 100644 drivers/net/sunxi_emac.c delete mode 100644 drivers/net/sunxi_wemac.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 6226cb259f..7cc6b6fc08 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DNET) += dnet.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o +obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o obj-$(CONFIG_ENC28J60) += enc28j60.o obj-$(CONFIG_EP93XX) += ep93xx_eth.o obj-$(CONFIG_ETHOC) += ethoc.o @@ -51,7 +52,6 @@ obj-$(CONFIG_RTL8169) += rtl8169.o obj-$(CONFIG_SH_ETHER) += sh_eth.o obj-$(CONFIG_SMC91111) += smc91111.o obj-$(CONFIG_SMC911X) += smc911x.o -obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c new file mode 100644 index 0000000000..5a06d68af7 --- /dev/null +++ b/drivers/net/sunxi_emac.c @@ -0,0 +1,521 @@ +/* + * sunxi_emac.c -- Allwinner A10 ethernet driver + * + * (C) Copyright 2012, Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* EMAC register */ +struct emac_regs { + u32 ctl; /* 0x00 */ + u32 tx_mode; /* 0x04 */ + u32 tx_flow; /* 0x08 */ + u32 tx_ctl0; /* 0x0c */ + u32 tx_ctl1; /* 0x10 */ + u32 tx_ins; /* 0x14 */ + u32 tx_pl0; /* 0x18 */ + u32 tx_pl1; /* 0x1c */ + u32 tx_sta; /* 0x20 */ + u32 tx_io_data; /* 0x24 */ + u32 tx_io_data1;/* 0x28 */ + u32 tx_tsvl0; /* 0x2c */ + u32 tx_tsvh0; /* 0x30 */ + u32 tx_tsvl1; /* 0x34 */ + u32 tx_tsvh1; /* 0x38 */ + u32 rx_ctl; /* 0x3c */ + u32 rx_hash0; /* 0x40 */ + u32 rx_hash1; /* 0x44 */ + u32 rx_sta; /* 0x48 */ + u32 rx_io_data; /* 0x4c */ + u32 rx_fbc; /* 0x50 */ + u32 int_ctl; /* 0x54 */ + u32 int_sta; /* 0x58 */ + u32 mac_ctl0; /* 0x5c */ + u32 mac_ctl1; /* 0x60 */ + u32 mac_ipgt; /* 0x64 */ + u32 mac_ipgr; /* 0x68 */ + u32 mac_clrt; /* 0x6c */ + u32 mac_maxf; /* 0x70 */ + u32 mac_supp; /* 0x74 */ + u32 mac_test; /* 0x78 */ + u32 mac_mcfg; /* 0x7c */ + u32 mac_mcmd; /* 0x80 */ + u32 mac_madr; /* 0x84 */ + u32 mac_mwtd; /* 0x88 */ + u32 mac_mrdd; /* 0x8c */ + u32 mac_mind; /* 0x90 */ + u32 mac_ssrr; /* 0x94 */ + u32 mac_a0; /* 0x98 */ + u32 mac_a1; /* 0x9c */ +}; + +/* SRAMC register */ +struct sunxi_sramc_regs { + u32 ctrl0; + u32 ctrl1; +}; + +/* 0: Disable 1: Aborted frame enable(default) */ +#define EMAC_TX_AB_M (0x1 << 0) +/* 0: CPU 1: DMA(default) */ +#define EMAC_TX_TM (0x1 << 1) + +#define EMAC_TX_SETUP (0) + +/* 0: DRQ asserted 1: DRQ automatically(default) */ +#define EMAC_RX_DRQ_MODE (0x1 << 1) +/* 0: CPU 1: DMA(default) */ +#define EMAC_RX_TM (0x1 << 2) +/* 0: Normal(default) 1: Pass all Frames */ +#define EMAC_RX_PA (0x1 << 4) +/* 0: Normal(default) 1: Pass Control Frames */ +#define EMAC_RX_PCF (0x1 << 5) +/* 0: Normal(default) 1: Pass Frames with CRC Error */ +#define EMAC_RX_PCRCE (0x1 << 6) +/* 0: Normal(default) 1: Pass Frames with Length Error */ +#define EMAC_RX_PLE (0x1 << 7) +/* 0: Normal 1: Pass Frames length out of range(default) */ +#define EMAC_RX_POR (0x1 << 8) +/* 0: Not accept 1: Accept unicast Packets(default) */ +#define EMAC_RX_UCAD (0x1 << 16) +/* 0: Normal(default) 1: DA Filtering */ +#define EMAC_RX_DAF (0x1 << 17) +/* 0: Not accept 1: Accept multicast Packets(default) */ +#define EMAC_RX_MCO (0x1 << 20) +/* 0: Disable(default) 1: Enable Hash filter */ +#define EMAC_RX_MHF (0x1 << 21) +/* 0: Not accept 1: Accept Broadcast Packets(default) */ +#define EMAC_RX_BCO (0x1 << 22) +/* 0: Disable(default) 1: Enable SA Filtering */ +#define EMAC_RX_SAF (0x1 << 24) +/* 0: Normal(default) 1: Inverse Filtering */ +#define EMAC_RX_SAIF (0x1 << 25) + +#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ + EMAC_RX_MCO | EMAC_RX_BCO) + +/* 0: Disable 1: Enable Receive Flow Control(default) */ +#define EMAC_MAC_CTL0_RFC (0x1 << 2) +/* 0: Disable 1: Enable Transmit Flow Control(default) */ +#define EMAC_MAC_CTL0_TFC (0x1 << 3) + +#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) + +/* 0: Disable 1: Enable MAC Frame Length Checking(default) */ +#define EMAC_MAC_CTL1_FLC (0x1 << 1) +/* 0: Disable(default) 1: Enable Huge Frame */ +#define EMAC_MAC_CTL1_HF (0x1 << 2) +/* 0: Disable(default) 1: Enable MAC Delayed CRC */ +#define EMAC_MAC_CTL1_DCRC (0x1 << 3) +/* 0: Disable 1: Enable MAC CRC(default) */ +#define EMAC_MAC_CTL1_CRC (0x1 << 4) +/* 0: Disable 1: Enable MAC PAD Short frames(default) */ +#define EMAC_MAC_CTL1_PC (0x1 << 5) +/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ +#define EMAC_MAC_CTL1_VC (0x1 << 6) +/* 0: Disable(default) 1: Enable MAC auto detect Short frames */ +#define EMAC_MAC_CTL1_ADP (0x1 << 7) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_PRE (0x1 << 8) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_LPE (0x1 << 9) +/* 0: Disable(default) 1: Enable no back off */ +#define EMAC_MAC_CTL1_NB (0x1 << 12) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_BNB (0x1 << 13) +/* 0: Disable(default) 1: Enable */ +#define EMAC_MAC_CTL1_ED (0x1 << 14) + +#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ + EMAC_MAC_CTL1_PC) + +#define EMAC_MAC_IPGT 0x15 + +#define EMAC_MAC_NBTB_IPG1 0xc +#define EMAC_MAC_NBTB_IPG2 0x12 + +#define EMAC_MAC_CW 0x37 +#define EMAC_MAC_RM 0xf + +#define EMAC_MAC_MFL 0x0600 + +/* Receive status */ +#define EMAC_CRCERR (0x1 << 4) +#define EMAC_LENERR (0x3 << 5) + +#define DMA_CPU_TRRESHOLD 2000 + +struct emac_eth_dev { + u32 speed; + u32 duplex; + u32 phy_configured; + int link_printed; +}; + +struct emac_rxhdr { + s16 rx_len; + u16 rx_status; +}; + +static void emac_inblk_32bit(void *reg, void *data, int count) +{ + int cnt = (count + 3) >> 2; + + if (cnt) { + u32 *buf = data; + + do { + u32 x = readl(reg); + *buf++ = x; + } while (--cnt); + } +} + +static void emac_outblk_32bit(void *reg, void *data, int count) +{ + int cnt = (count + 3) >> 2; + + if (cnt) { + const u32 *buf = data; + + do { + writel(*buf++, reg); + } while (--cnt); + } +} + +/* Read a word from phyxcer */ +static int emac_phy_read(const char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + /* issue the phy address and reg */ + writel(addr << 8 | reg, ®s->mac_madr); + + /* pull up the phy io line */ + writel(0x1, ®s->mac_mcmd); + + /* Wait read complete */ + mdelay(1); + + /* push down the phy io line */ + writel(0x0, ®s->mac_mcmd); + + /* and write data */ + *value = readl(®s->mac_mrdd); + + return 0; +} + +/* Write a word to phyxcer */ +static int emac_phy_write(const char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev = eth_get_dev_by_name(devname); + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + /* issue the phy address and reg */ + writel(addr << 8 | reg, ®s->mac_madr); + + /* pull up the phy io line */ + writel(0x1, ®s->mac_mcmd); + + /* Wait write complete */ + mdelay(1); + + /* push down the phy io line */ + writel(0x0, ®s->mac_mcmd); + + /* and write data */ + writel(value, ®s->mac_mwtd); + + return 0; +} + +static void emac_setup(struct eth_device *dev) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + u32 reg_val; + u16 phy_val; + u32 duplex_flag; + + /* Set up TX */ + writel(EMAC_TX_SETUP, ®s->tx_mode); + + /* Set up RX */ + writel(EMAC_RX_SETUP, ®s->rx_ctl); + + /* Set MAC */ + /* Set MAC CTL0 */ + writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); + + /* Set MAC CTL1 */ + emac_phy_read(dev->name, 1, 0, &phy_val); + debug("PHY SETUP, reg 0 value: %x\n", phy_val); + duplex_flag = !!(phy_val & (1 << 8)); + + reg_val = 0; + if (duplex_flag) + reg_val = (0x1 << 0); + writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); + + /* Set up IPGT */ + writel(EMAC_MAC_IPGT, ®s->mac_ipgt); + + /* Set up IPGR */ + writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); + + /* Set up Collison window */ + writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); + + /* Set up Max Frame Length */ + writel(EMAC_MAC_MFL, ®s->mac_maxf); +} + +static void emac_reset(struct eth_device *dev) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + debug("resetting device\n"); + + /* RESET device */ + writel(0, ®s->ctl); + udelay(200); + + writel(1, ®s->ctl); + udelay(200); +} + +static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + struct emac_eth_dev *priv = dev->priv; + u16 phy_reg; + + /* Init EMAC */ + + /* Flush RX FIFO */ + setbits_le32(®s->rx_ctl, 0x8); + udelay(1); + + /* Init MAC */ + + /* Soft reset MAC */ + clrbits_le32(®s->mac_ctl0, 0x1 << 15); + + /* Clear RX counter */ + writel(0x0, ®s->rx_fbc); + udelay(1); + + /* Set up EMAC */ + emac_setup(dev); + + writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 | + dev->enetaddr[2], ®s->mac_a1); + writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 | + dev->enetaddr[5], ®s->mac_a0); + + mdelay(1); + + emac_reset(dev); + + /* PHY POWER UP */ + emac_phy_read(dev->name, 1, 0, &phy_reg); + emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11))); + mdelay(1); + + emac_phy_read(dev->name, 1, 0, &phy_reg); + + priv->speed = miiphy_speed(dev->name, 0); + priv->duplex = miiphy_duplex(dev->name, 0); + + /* Print link status only once */ + if (!priv->link_printed) { + printf("ENET Speed is %d Mbps - %s duplex connection\n", + priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); + priv->link_printed = 1; + } + + /* Set EMAC SPEED depend on PHY */ + clrsetbits_le32(®s->mac_supp, 1 << 8, + ((phy_reg & (0x1 << 13)) >> 13) << 8); + + /* Set duplex depend on phy */ + clrsetbits_le32(®s->mac_ctl1, 1 << 0, + ((phy_reg & (0x1 << 8)) >> 8) << 0); + + /* Enable RX/TX */ + setbits_le32(®s->ctl, 0x7); + + return 0; +} + +static void sunxi_emac_eth_halt(struct eth_device *dev) +{ + /* Nothing to do here */ +} + +static int sunxi_emac_eth_recv(struct eth_device *dev) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + struct emac_rxhdr rxhdr; + u32 rxcount; + u32 reg_val; + int rx_len; + int rx_status; + int good_packet; + + /* Check packet ready or not */ + + /* Race warning: The first packet might arrive with + * the interrupts disabled, but the second will fix + */ + rxcount = readl(®s->rx_fbc); + if (!rxcount) { + /* Had one stuck? */ + rxcount = readl(®s->rx_fbc); + if (!rxcount) + return 0; + } + + reg_val = readl(®s->rx_io_data); + if (reg_val != 0x0143414d) { + /* Disable RX */ + clrbits_le32(®s->ctl, 0x1 << 2); + + /* Flush RX FIFO */ + setbits_le32(®s->rx_ctl, 0x1 << 3); + while (readl(®s->rx_ctl) & (0x1 << 3)) + ; + + /* Enable RX */ + setbits_le32(®s->ctl, 0x1 << 2); + + return 0; + } + + /* A packet ready now + * Get status/length + */ + good_packet = 1; + + emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); + + rx_len = rxhdr.rx_len; + rx_status = rxhdr.rx_status; + + /* Packet Status check */ + if (rx_len < 0x40) { + good_packet = 0; + debug("RX: Bad Packet (runt)\n"); + } + + /* rx_status is identical to RSR register. */ + if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { + good_packet = 0; + if (rx_status & EMAC_CRCERR) + printf("crc error\n"); + if (rx_status & EMAC_LENERR) + printf("length error\n"); + } + + /* Move data from EMAC */ + if (good_packet) { + if (rx_len > DMA_CPU_TRRESHOLD) { + printf("Received packet is too big (len=%d)\n", rx_len); + } else { + emac_inblk_32bit((void *)®s->rx_io_data, + NetRxPackets[0], rx_len); + + /* Pass to upper layer */ + NetReceive(NetRxPackets[0], rx_len); + return rx_len; + } + } + + return 0; +} + +static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len) +{ + struct emac_regs *regs = (struct emac_regs *)dev->iobase; + + /* Select channel 0 */ + writel(0, ®s->tx_ins); + + /* Write packet */ + emac_outblk_32bit((void *)®s->tx_io_data, packet, len); + + /* Set TX len */ + writel(len, ®s->tx_pl0); + + /* Start translate from fifo to phy */ + setbits_le32(®s->tx_ctl0, 1); + + return 0; +} + +int sunxi_emac_initialize(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_sramc_regs *sram = + (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; + struct emac_regs *regs = + (struct emac_regs *)SUNXI_EMAC_BASE; + struct eth_device *dev; + struct emac_eth_dev *priv; + int pin; + + dev = malloc(sizeof(*dev)); + if (dev == NULL) + return -ENOMEM; + + priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + memset(dev, 0, sizeof(*dev)); + memset(priv, 0, sizeof(struct emac_eth_dev)); + + /* Map SRAM to EMAC */ + setbits_le32(&sram->ctrl1, 0x5 << 2); + + /* Configure pin mux settings for MII Ethernet */ + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC); + + /* Set up clock gating */ + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC); + + /* Set MII clock */ + clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); + + dev->iobase = (int)regs; + dev->priv = priv; + dev->init = sunxi_emac_eth_init; + dev->halt = sunxi_emac_eth_halt; + dev->send = sunxi_emac_eth_send; + dev->recv = sunxi_emac_eth_recv; + strcpy(dev->name, "emac"); + + eth_register(dev); + + miiphy_register(dev->name, emac_phy_read, emac_phy_write); + + return 0; +} diff --git a/drivers/net/sunxi_wemac.c b/drivers/net/sunxi_wemac.c deleted file mode 100644 index 699a381582..0000000000 --- a/drivers/net/sunxi_wemac.c +++ /dev/null @@ -1,525 +0,0 @@ -/* - * sunxi_wemac.c -- Allwinner A10 ethernet driver - * - * (C) Copyright 2012, Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* EMAC register */ -struct wemac_regs { - u32 ctl; /* 0x00 */ - u32 tx_mode; /* 0x04 */ - u32 tx_flow; /* 0x08 */ - u32 tx_ctl0; /* 0x0c */ - u32 tx_ctl1; /* 0x10 */ - u32 tx_ins; /* 0x14 */ - u32 tx_pl0; /* 0x18 */ - u32 tx_pl1; /* 0x1c */ - u32 tx_sta; /* 0x20 */ - u32 tx_io_data; /* 0x24 */ - u32 tx_io_data1; /* 0x28 */ - u32 tx_tsvl0; /* 0x2c */ - u32 tx_tsvh0; /* 0x30 */ - u32 tx_tsvl1; /* 0x34 */ - u32 tx_tsvh1; /* 0x38 */ - u32 rx_ctl; /* 0x3c */ - u32 rx_hash0; /* 0x40 */ - u32 rx_hash1; /* 0x44 */ - u32 rx_sta; /* 0x48 */ - u32 rx_io_data; /* 0x4c */ - u32 rx_fbc; /* 0x50 */ - u32 int_ctl; /* 0x54 */ - u32 int_sta; /* 0x58 */ - u32 mac_ctl0; /* 0x5c */ - u32 mac_ctl1; /* 0x60 */ - u32 mac_ipgt; /* 0x64 */ - u32 mac_ipgr; /* 0x68 */ - u32 mac_clrt; /* 0x6c */ - u32 mac_maxf; /* 0x70 */ - u32 mac_supp; /* 0x74 */ - u32 mac_test; /* 0x78 */ - u32 mac_mcfg; /* 0x7c */ - u32 mac_mcmd; /* 0x80 */ - u32 mac_madr; /* 0x84 */ - u32 mac_mwtd; /* 0x88 */ - u32 mac_mrdd; /* 0x8c */ - u32 mac_mind; /* 0x90 */ - u32 mac_ssrr; /* 0x94 */ - u32 mac_a0; /* 0x98 */ - u32 mac_a1; /* 0x9c */ -}; - -/* SRAMC register */ -struct sunxi_sramc_regs { - u32 ctrl0; - u32 ctrl1; -}; - -/* 0: Disable 1: Aborted frame enable(default) */ -#define EMAC_TX_AB_M (0x1 << 0) -/* 0: CPU 1: DMA(default) */ -#define EMAC_TX_TM (0x1 << 1) - -#define EMAC_TX_SETUP (0) - -/* 0: DRQ asserted 1: DRQ automatically(default) */ -#define EMAC_RX_DRQ_MODE (0x1 << 1) -/* 0: CPU 1: DMA(default) */ -#define EMAC_RX_TM (0x1 << 2) -/* 0: Normal(default) 1: Pass all Frames */ -#define EMAC_RX_PA (0x1 << 4) -/* 0: Normal(default) 1: Pass Control Frames */ -#define EMAC_RX_PCF (0x1 << 5) -/* 0: Normal(default) 1: Pass Frames with CRC Error */ -#define EMAC_RX_PCRCE (0x1 << 6) -/* 0: Normal(default) 1: Pass Frames with Length Error */ -#define EMAC_RX_PLE (0x1 << 7) -/* 0: Normal 1: Pass Frames length out of range(default) */ -#define EMAC_RX_POR (0x1 << 8) -/* 0: Not accept 1: Accept unicast Packets(default) */ -#define EMAC_RX_UCAD (0x1 << 16) -/* 0: Normal(default) 1: DA Filtering */ -#define EMAC_RX_DAF (0x1 << 17) -/* 0: Not accept 1: Accept multicast Packets(default) */ -#define EMAC_RX_MCO (0x1 << 20) -/* 0: Disable(default) 1: Enable Hash filter */ -#define EMAC_RX_MHF (0x1 << 21) -/* 0: Not accept 1: Accept Broadcast Packets(default) */ -#define EMAC_RX_BCO (0x1 << 22) -/* 0: Disable(default) 1: Enable SA Filtering */ -#define EMAC_RX_SAF (0x1 << 24) -/* 0: Normal(default) 1: Inverse Filtering */ -#define EMAC_RX_SAIF (0x1 << 25) - -#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \ - EMAC_RX_MCO | EMAC_RX_BCO) - -/* 0: Disable 1: Enable Receive Flow Control(default) */ -#define EMAC_MAC_CTL0_RFC (0x1 << 2) -/* 0: Disable 1: Enable Transmit Flow Control(default) */ -#define EMAC_MAC_CTL0_TFC (0x1 << 3) - -#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC) - -/* 0: Disable 1: Enable MAC Frame Length Checking(default) */ -#define EMAC_MAC_CTL1_FLC (0x1 << 1) -/* 0: Disable(default) 1: Enable Huge Frame */ -#define EMAC_MAC_CTL1_HF (0x1 << 2) -/* 0: Disable(default) 1: Enable MAC Delayed CRC */ -#define EMAC_MAC_CTL1_DCRC (0x1 << 3) -/* 0: Disable 1: Enable MAC CRC(default) */ -#define EMAC_MAC_CTL1_CRC (0x1 << 4) -/* 0: Disable 1: Enable MAC PAD Short frames(default) */ -#define EMAC_MAC_CTL1_PC (0x1 << 5) -/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */ -#define EMAC_MAC_CTL1_VC (0x1 << 6) -/* 0: Disable(default) 1: Enable MAC auto detect Short frames */ -#define EMAC_MAC_CTL1_ADP (0x1 << 7) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_PRE (0x1 << 8) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_LPE (0x1 << 9) -/* 0: Disable(default) 1: Enable no back off */ -#define EMAC_MAC_CTL1_NB (0x1 << 12) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_BNB (0x1 << 13) -/* 0: Disable(default) 1: Enable */ -#define EMAC_MAC_CTL1_ED (0x1 << 14) - -#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \ - EMAC_MAC_CTL1_PC) - -#define EMAC_MAC_IPGT 0x15 - -#define EMAC_MAC_NBTB_IPG1 0xC -#define EMAC_MAC_NBTB_IPG2 0x12 - -#define EMAC_MAC_CW 0x37 -#define EMAC_MAC_RM 0xF - -#define EMAC_MAC_MFL 0x0600 - -/* Receive status */ -#define EMAC_CRCERR (1 << 4) -#define EMAC_LENERR (3 << 5) - -#define DMA_CPU_TRRESHOLD 2000 - -struct wemac_eth_dev { - u32 speed; - u32 duplex; - u32 phy_configured; - int link_printed; -}; - -struct wemac_rxhdr { - s16 rx_len; - u16 rx_status; -}; - -static void wemac_inblk_32bit(void *reg, void *data, int count) -{ - int cnt = (count + 3) >> 2; - - if (cnt) { - u32 *buf = data; - - do { - u32 x = readl(reg); - *buf++ = x; - } while (--cnt); - } -} - -static void wemac_outblk_32bit(void *reg, void *data, int count) -{ - int cnt = (count + 3) >> 2; - - if (cnt) { - const u32 *buf = data; - - do { - writel(*buf++, reg); - } while (--cnt); - } -} - -/* - * Read a word from phyxcer - */ -static int wemac_phy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - struct eth_device *dev = eth_get_dev_by_name(devname); - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - /* issue the phy address and reg */ - writel(addr << 8 | reg, ®s->mac_madr); - - /* pull up the phy io line */ - writel(0x1, ®s->mac_mcmd); - - /* Wait read complete */ - mdelay(1); - - /* push down the phy io line */ - writel(0x0, ®s->mac_mcmd); - - /* and write data */ - *value = readl(®s->mac_mrdd); - - return 0; -} - -/* - * Write a word to phyxcer - */ -static int wemac_phy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - struct eth_device *dev = eth_get_dev_by_name(devname); - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - /* issue the phy address and reg */ - writel(addr << 8 | reg, ®s->mac_madr); - - /* pull up the phy io line */ - writel(0x1, ®s->mac_mcmd); - - /* Wait write complete */ - mdelay(1); - - /* push down the phy io line */ - writel(0x0, ®s->mac_mcmd); - - /* and write data */ - writel(value, ®s->mac_mwtd); - - return 0; -} - -static void emac_setup(struct eth_device *dev) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - u32 reg_val; - u16 phy_val; - u32 duplex_flag; - - /* Set up TX */ - writel(EMAC_TX_SETUP, ®s->tx_mode); - - /* Set up RX */ - writel(EMAC_RX_SETUP, ®s->rx_ctl); - - /* Set MAC */ - /* Set MAC CTL0 */ - writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0); - - /* Set MAC CTL1 */ - wemac_phy_read(dev->name, 1, 0, &phy_val); - debug("PHY SETUP, reg 0 value: %x\n", phy_val); - duplex_flag = !!(phy_val & (1 << 8)); - - reg_val = 0; - if (duplex_flag) - reg_val = (0x1 << 0); - writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1); - - /* Set up IPGT */ - writel(EMAC_MAC_IPGT, ®s->mac_ipgt); - - /* Set up IPGR */ - writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr); - - /* Set up Collison window */ - writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt); - - /* Set up Max Frame Length */ - writel(EMAC_MAC_MFL, ®s->mac_maxf); -} - -static void wemac_reset(struct eth_device *dev) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - debug("resetting device\n"); - - /* RESET device */ - writel(0, ®s->ctl); - udelay(200); - - writel(1, ®s->ctl); - udelay(200); -} - -static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - struct wemac_eth_dev *priv = dev->priv; - u16 phy_reg; - - /* Init EMAC */ - - /* Flush RX FIFO */ - setbits_le32(®s->rx_ctl, 0x8); - udelay(1); - - /* Init MAC */ - - /* Soft reset MAC */ - clrbits_le32(®s->mac_ctl0, 1 << 15); - - /* Set MII clock */ - clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2); - - /* Clear RX counter */ - writel(0x0, ®s->rx_fbc); - udelay(1); - - /* Set up EMAC */ - emac_setup(dev); - - writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 | - dev->enetaddr[2], ®s->mac_a1); - writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 | - dev->enetaddr[5], ®s->mac_a0); - - mdelay(1); - - wemac_reset(dev); - - /* PHY POWER UP */ - wemac_phy_read(dev->name, 1, 0, &phy_reg); - wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11))); - mdelay(1); - - wemac_phy_read(dev->name, 1, 0, &phy_reg); - - priv->speed = miiphy_speed(dev->name, 0); - priv->duplex = miiphy_duplex(dev->name, 0); - - /* Print link status only once */ - if (!priv->link_printed) { - printf("ENET Speed is %d Mbps - %s duplex connection\n", - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); - priv->link_printed = 1; - } - - /* Set EMAC SPEED depend on PHY */ - clrsetbits_le32(®s->mac_supp, 1 << 8, - ((phy_reg & (1 << 13)) >> 13) << 8); - - /* Set duplex depend on phy */ - clrsetbits_le32(®s->mac_ctl1, 1 << 0, - ((phy_reg & (1 << 8)) >> 8) << 0); - - /* Enable RX/TX */ - setbits_le32(®s->ctl, 0x7); - - return 0; -} - -static void sunxi_wemac_eth_halt(struct eth_device *dev) -{ - /* Nothing to do here */ -} - -static int sunxi_wemac_eth_recv(struct eth_device *dev) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - struct wemac_rxhdr rxhdr; - u32 rxcount; - u32 reg_val; - int rx_len; - int rx_status; - int good_packet; - - /* Check packet ready or not */ - - /* - * Race warning: The first packet might arrive with - * the interrupts disabled, but the second will fix - */ - rxcount = readl(®s->rx_fbc); - if (!rxcount) { - /* Had one stuck? */ - rxcount = readl(®s->rx_fbc); - if (!rxcount) - return 0; - } - - reg_val = readl(®s->rx_io_data); - if (reg_val != 0x0143414d) { - /* Disable RX */ - clrbits_le32(®s->ctl, 1 << 2); - - /* Flush RX FIFO */ - setbits_le32(®s->rx_ctl, 1 << 3); - while (readl(®s->rx_ctl) & (1 << 3)) - ; - - /* Enable RX */ - setbits_le32(®s->ctl, 1 << 2); - - return 0; - } - - /* - * A packet ready now - * Get status/length - */ - good_packet = 1; - - wemac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr)); - - rx_len = rxhdr.rx_len; - rx_status = rxhdr.rx_status; - - /* Packet Status check */ - if (rx_len < 0x40) { - good_packet = 0; - debug("RX: Bad Packet (runt)\n"); - } - - /* rx_status is identical to RSR register. */ - if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) { - good_packet = 0; - if (rx_status & EMAC_CRCERR) - printf("crc error\n"); - if (rx_status & EMAC_LENERR) - printf("length error\n"); - } - - /* Move data from WEMAC */ - if (good_packet) { - if (rx_len > DMA_CPU_TRRESHOLD) { - printf("Received packet is too big (len=%d)\n", rx_len); - } else { - wemac_inblk_32bit((void *)®s->rx_io_data, - NetRxPackets[0], rx_len); - - /* Pass to upper layer */ - NetReceive(NetRxPackets[0], rx_len); - return rx_len; - } - } - - return 0; -} - -static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len) -{ - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase; - - /* Select channel 0 */ - writel(0, ®s->tx_ins); - - /* Write packet */ - wemac_outblk_32bit((void *)®s->tx_io_data, packet, len); - - /* Set TX len */ - writel(len, ®s->tx_pl0); - - /* Start translate from fifo to phy */ - setbits_le32(®s->tx_ctl0, 1); - - return 0; -} - -int sunxi_wemac_initialize(void) -{ - struct sunxi_ccm_reg *const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_sramc_regs *sram = - (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; - struct eth_device *dev; - struct wemac_eth_dev *priv; - int pin; - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - return -ENOMEM; - - priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev)); - if (!priv) { - free(dev); - return -ENOMEM; - } - - memset(dev, 0, sizeof(*dev)); - memset(priv, 0, sizeof(struct wemac_eth_dev)); - - /* Map SRAM to EMAC */ - setbits_le32(&sram->ctrl1, 0x5 << 2); - - /* Configure pin mux settings for MII Ethernet */ - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) - sunxi_gpio_set_cfgpin(pin, 2); - - /* Set up clock gating */ - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC); - - dev->iobase = SUNXI_EMAC_BASE; - dev->priv = priv; - dev->init = sunxi_wemac_eth_init; - dev->halt = sunxi_wemac_eth_halt; - dev->send = sunxi_wemac_eth_send; - dev->recv = sunxi_wemac_eth_recv; - strcpy(dev->name, "wemac"); - - eth_register(dev); - - miiphy_register(dev->name, wemac_phy_read, wemac_phy_write); - - return 0; -} diff --git a/include/netdev.h b/include/netdev.h index 63481eca22..e45dd7abec 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -78,8 +78,8 @@ int sh_eth_initialize(bd_t *bis); int skge_initialize(bd_t *bis); int smc91111_initialize(u8 dev_num, int base_addr); int smc911x_initialize(u8 dev_num, int base_addr); +int sunxi_emac_initialize(bd_t *bis); int sunxi_gmac_initialize(bd_t *bis); -int sunxi_wemac_initialize(bd_t *bis); int tsi108_eth_initialize(bd_t *bis); int uec_standard_init(bd_t *bis); int uli526x_initialize(bd_t *bis); -- cgit v1.2.1 From c26fb9db0ed7d524bde1206ed49a63e50125d329 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:37:00 +0200 Subject: sunxi: Add emac glue, enable emac on the cubieboard Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/board.c | 8 ++++++++ boards.cfg | 2 +- include/configs/sunxi-common.h | 5 +++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 0118f5b418..1e506b5176 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -117,6 +117,14 @@ int cpu_eth_init(bd_t *bis) { int rc; +#ifdef CONFIG_SUNXI_EMAC + rc = sunxi_emac_initialize(bis); + if (rc < 0) { + printf("sunxi: failed to initialize emac\n"); + return rc; + } +#endif + #ifdef CONFIG_SUNXI_GMAC rc = sunxi_gmac_initialize(bis); if (rc < 0) { diff --git a/boards.cfg b/boards.cfg index 20ad48868d..a6d70dfbf3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -378,7 +378,7 @@ Active arm armv7 s5pc1xx samsung goni Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede -Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL Hans de Goede +Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC Hans de Goede Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1d1c87d000..3f04890526 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -165,6 +165,11 @@ #define CONFIG_CONS_INDEX 1 /* UART0 */ #endif +/* Ethernet support */ +#ifdef CONFIG_SUNXI_EMAC +#define CONFIG_MII /* MII PHY management */ +#endif + #ifdef CONFIG_SUNXI_GMAC #define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ #define CONFIG_DW_AUTONEG -- cgit v1.2.1 From ef7e723ba184a5664e6e27f1b92cd8fc2042d695 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Mon, 9 Jun 2014 11:37:01 +0200 Subject: sunxi: Add support for using MII phy-s with the GMAC nic Many A20 boards (ie Cubieboard2, A20-OLinuXino_MICRO) use an 100 Mbit MII phy together with the GMAC nic found in the A20 SoC, add support for this (this will get used when we add these boards in a later patch). Signed-off-by: Chen-Yu Tsai Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- board/sunxi/gmac.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index e48328d9e8..e7ff95285c 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -16,17 +16,28 @@ int sunxi_gmac_initialize(bd_t *bis) setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); /* Set MII clock */ +#ifdef CONFIG_RGMII setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | CCM_GMAC_CTRL_GPIT_RGMII); +#else + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | + CCM_GMAC_CTRL_GPIT_MII); +#endif /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { +#ifdef CONFIG_RGMII /* skip unused pins in RGMII mode */ if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) continue; +#endif sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); sunxi_gpio_set_drv(pin, 3); } +#ifdef CONFIG_RGMII return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); +#else + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); +#endif } -- cgit v1.2.1 From db53073037813858e7f375fc3402960285b1407c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 9 Jun 2014 11:37:02 +0200 Subject: sunxi: Add Ian Campbell and Hans de Goede as cubietruck board-maintainers Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- boards.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards.cfg b/boards.cfg index a6d70dfbf3..759d331d19 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,8 +379,8 @@ Active arm armv7 s5pc1xx samsung smdkc100 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC Hans de Goede -Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - -Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - -- cgit v1.2.1 From 799aff38dfc1b2d860ec8430572f9402d3ce9881 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Sun, 6 Jul 2014 20:03:20 +0100 Subject: sunxi: Avoid unused variable warning. Mark rc as __maybe_unused since it is infact unused on systems with neither EMAC nor GMAC. Signed-off-by: Ian Campbell Acked-by: Tom Rini --- arch/arm/cpu/armv7/sunxi/board.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 1e506b5176..538ffa70a3 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -24,6 +24,8 @@ #include #include +#include + #ifdef CONFIG_SPL_BUILD /* Pointer to the global data structure for SPL */ DECLARE_GLOBAL_DATA_PTR; @@ -115,7 +117,7 @@ void enable_caches(void) */ int cpu_eth_init(bd_t *bis) { - int rc; + __maybe_unused int rc; #ifdef CONFIG_SUNXI_EMAC rc = sunxi_emac_initialize(bis); -- cgit v1.2.1 From 0db2bbdc04c7ba41861e686acb815fce5a227a01 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 13 Jun 2014 22:55:48 +0200 Subject: mvtwsi: convert to CONFIG_SYS_I2C framework Note this has only been tested on Allwinner sunxi devices (support for which gets introduced by a later patch). The kirkwood changes have been compile tested using the wireless_space board config, the orion5x changes have been compile tested using the edminiv2 board config. Signed-off-by: Hans de Goede Acked-by: Heiko Schocher --- arch/arm/include/asm/arch-kirkwood/config.h | 3 +- drivers/i2c/Makefile | 2 +- drivers/i2c/mvtwsi.c | 70 +++++++++++++---------------- include/configs/edminiv2.h | 3 +- 4 files changed, 37 insertions(+), 41 deletions(-) diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 7a688e46b0..f7bfa0e74d 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -129,7 +129,8 @@ */ #ifdef CONFIG_CMD_I2C #ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI #endif #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index e33586d8a6..61e9f3c240 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o obj-$(CONFIG_DW_I2C) += designware_i2c.o -obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_I2C_MXS) += mxs_i2c.o obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o @@ -19,6 +18,7 @@ obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o +obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 5ba0e03862..c8b5425a01 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -220,11 +220,10 @@ static int twsi_stop(int status) /* * Reset controller. - * Called at end of i2c_init unsuccessful i2c transactions. * Controller reset also resets the baud rate and slave address, so - * re-establish them. + * they must be re-established afterwards. */ -static void twsi_reset(u8 baud_rate, u8 slave_address) +static void twsi_reset(struct i2c_adapter *adap) { /* ensure controller will be enabled by any twsi*() function */ twsi_control_flags = MVTWSI_CONTROL_TWSIEN; @@ -232,23 +231,17 @@ static void twsi_reset(u8 baud_rate, u8 slave_address) writel(0, &twsi->soft_reset); /* wait 2 ms -- this is what the Marvell LSP does */ udelay(20000); - /* set baud rate */ - writel(baud_rate, &twsi->baudrate); - /* set slave address even though we don't use it */ - writel(slave_address, &twsi->slave_address); - writel(0, &twsi->xtnd_slave_addr); - /* assert STOP but don't care for the result */ - (void) twsi_stop(0); } /* * I2C init called by cmd_i2c when doing 'i2c reset'. * Sets baud to the highest possible value not exceeding requested one. */ -void i2c_init(int requested_speed, int slaveadd) +static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap, + unsigned int requested_speed) { - int tmp_speed, highest_speed, n, m; - int baud = 0x44; /* baudrate at controller reset */ + unsigned int tmp_speed, highest_speed, n, m; + unsigned int baud = 0x44; /* baudrate at controller reset */ /* use actual speed to collect progressively higher values */ highest_speed = 0; @@ -263,8 +256,21 @@ void i2c_init(int requested_speed, int slaveadd) } } } + writel(baud, &twsi->baudrate); + return 0; +} + +static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ /* reset controller */ - twsi_reset(baud, slaveadd); + twsi_reset(adap); + /* set speed */ + twsi_i2c_set_bus_speed(adap, speed); + /* set slave address even though we don't use it */ + writel(slaveadd, &twsi->slave_address); + writel(0, &twsi->xtnd_slave_addr); + /* assert STOP but don't care for the result */ + (void) twsi_stop(0); } /* @@ -294,7 +300,7 @@ static int i2c_begin(int expected_start_status, u8 addr) * I2C probe called by cmd_i2c when doing 'i2c probe'. * Begin read, nak data byte, end. */ -int i2c_probe(uchar chip) +static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) { u8 dummy_byte; int status; @@ -320,12 +326,13 @@ int i2c_probe(uchar chip) * cmd_eeprom, so we have to choose here, and for the moment that'll be * a repeated start without a preceding stop. */ -int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) { int status; /* begin i2c write to send the address bytes */ - status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + status = i2c_begin(MVTWSI_STATUS_START, (chip << 1)); /* send addr bytes */ while ((status == 0) && alen--) status = twsi_send(addr >> (8*alen), @@ -333,7 +340,7 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) /* begin i2c read to receive eeprom data bytes */ if (status == 0) status = i2c_begin( - MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1); + MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1); /* prepare ACK if at least one byte must be received */ if (length > 0) twsi_control_flags |= MVTWSI_CONTROL_ACK; @@ -355,12 +362,13 @@ int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c * Begin write, send address byte(s), send data bytes, end. */ -int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) { int status; /* begin i2c write to send the eeprom adress bytes then data bytes */ - status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + status = i2c_begin(MVTWSI_STATUS_START, (chip << 1)); /* send addr bytes */ while ((status == 0) && alen--) status = twsi_send(addr >> (8*alen), @@ -374,21 +382,7 @@ int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) return status; } -/* - * Bus set routine: we only support bus 0. - */ -int i2c_set_bus_num(unsigned int bus) -{ - if (bus > 0) { - return -1; - } - return 0; -} - -/* - * Bus get routine: hard-return bus 0. - */ -unsigned int i2c_get_bus_num(void) -{ - return 0; -} +U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, + twsi_i2c_read, twsi_i2c_write, + twsi_i2c_set_bus_speed, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 8b9f66a29c..77717a84ae 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -187,7 +187,8 @@ * I2C related stuff */ #ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MVTWSI +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI #define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE #define CONFIG_SYS_I2C_SLAVE 0x0 #define CONFIG_SYS_I2C_SPEED 100000 -- cgit v1.2.1 From 6620377e4b8be3c232c59d673efcd673c30bc69f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 13 Jun 2014 22:55:49 +0200 Subject: sunxi: Add i2c support Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede Acked-by: Ian Campbell Acked-By: Prafulla Wadaskar Acked-by: Heiko Schocher [ ijc -- updated u-boot-spl-fel.lds ] --- arch/arm/cpu/armv7/sunxi/board.c | 6 ++++++ arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 5 +++++ arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 5 +++++ arch/arm/include/asm/arch-sunxi/i2c.h | 15 +++++++++++++++ board/sunxi/board.c | 7 +++++++ drivers/i2c/mvtwsi.c | 18 ++++++++++++++++++ include/configs/sunxi-common.h | 8 ++++++++ 7 files changed, 64 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/i2c.h diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 538ffa70a3..701f9195e2 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -11,6 +11,7 @@ */ #include +#include #include #include #include @@ -93,11 +94,16 @@ void s_init(void) clock_init(); timer_init(); gpio_init(); + i2c_init_board(); #ifdef CONFIG_SPL_BUILD gd = &gdata; preloader_console_init(); +#ifdef CONFIG_SPL_I2C_SUPPORT + /* Needed early by sunxi_board_init if PMU is enabled */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif sunxi_board_init(); #endif } diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds index 364e35c32f..928b7c19e0 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -26,6 +26,11 @@ SECTIONS *(.data*) } + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + . = ALIGN(4); . = .; diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds index c1ae227f06..53f0cbd2b7 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -38,6 +38,11 @@ SECTIONS . = ALIGN(4); .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } > .sram + . = ALIGN(4); __image_copy_end = .; _end = .; diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h new file mode 100644 index 0000000000..dc5406b213 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -0,0 +1,15 @@ +/* + * Copyright 2014 - Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SUNXI_I2C_H_ +#define _SUNXI_I2C_H_ + +#include + +#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE +/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ +#define CONFIG_SYS_TCLK 24000000 + +#endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index b05d0b9b18..543b8098e9 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -106,6 +106,13 @@ int board_mmc_init(bd_t *bis) } #endif +void i2c_init_board(void) +{ + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0); + clock_twi_onoff(0, 1); +} + #ifdef CONFIG_SPL_BUILD void sunxi_board_init(void) { diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index c8b5425a01..ab3ffa0fc1 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -22,6 +22,8 @@ #include #elif defined(CONFIG_KIRKWOOD) #include +#elif defined(CONFIG_SUNXI) +#include #else #error Driver mvtwsi not supported by SoC or board #endif @@ -30,6 +32,20 @@ * TWSI register structure */ +#ifdef CONFIG_SUNXI + +struct mvtwsi_registers { + u32 slave_address; + u32 xtnd_slave_addr; + u32 data; + u32 control; + u32 status; + u32 baudrate; + u32 soft_reset; +}; + +#else + struct mvtwsi_registers { u32 slave_address; u32 data; @@ -43,6 +59,8 @@ struct mvtwsi_registers { u32 soft_reset; }; +#endif + /* * Control register fields */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 3f04890526..42b0d2e51b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -161,6 +161,14 @@ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS +/* I2C */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_CMD_I2C + #ifndef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 1 /* UART0 */ #endif -- cgit v1.2.1 From 14bc66bd9a1d8073a12c6e785ab379909f620356 Mon Sep 17 00:00:00 2001 From: Henrik Nordstrom Date: Fri, 13 Jun 2014 22:55:50 +0200 Subject: sunxi: Add axp209 pmic support Add support for the x-powers axp209 pmic which is found on most A10, A13 and A20 boards. And enable AXP209 support for the Cubietruck and Cubieboard boards. Signed-off-by: Henrik Nordstrom Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- board/sunxi/board.c | 22 ++++++ boards.cfg | 6 +- drivers/power/Makefile | 1 + drivers/power/axp209.c | 167 +++++++++++++++++++++++++++++++++++++++++ include/axp209.h | 14 ++++ include/configs/sun4i.h | 1 + include/configs/sun5i.h | 1 + include/configs/sun7i.h | 1 + include/configs/sunxi-common.h | 5 ++ 9 files changed, 215 insertions(+), 3 deletions(-) create mode 100644 drivers/power/axp209.c create mode 100644 include/axp209.h diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 543b8098e9..8375711d1e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -12,6 +12,9 @@ */ #include +#ifdef CONFIG_AXP209_POWER +#include +#endif #include #include #include @@ -116,12 +119,31 @@ void i2c_init_board(void) #ifdef CONFIG_SPL_BUILD void sunxi_board_init(void) { + int power_failed = 0; unsigned long ramsize; +#ifdef CONFIG_AXP209_POWER + power_failed |= axp209_init(); + power_failed |= axp209_set_dcdc2(1400); + power_failed |= axp209_set_dcdc3(1250); + power_failed |= axp209_set_ldo2(3000); + power_failed |= axp209_set_ldo3(2800); + power_failed |= axp209_set_ldo4(2800); +#endif + printf("DRAM:"); ramsize = sunxi_dram_init(); printf(" %lu MiB\n", ramsize >> 20); if (!ramsize) hang(); + + /* + * Only clock up the CPU to full speed if we are reasonably + * assured it's being powered with suitable core voltage + */ + if (!power_failed) + clock_set_pll1(CONFIG_CLK_FULL_SPEED); + else + printf("Failed to set core voltage! Can't set CPU frequency\n"); } #endif diff --git a/boards.cfg b/boards.cfg index 759d331d19..8e6afe7876 100644 --- a/boards.cfg +++ b/boards.cfg @@ -378,9 +378,9 @@ Active arm armv7 s5pc1xx samsung goni Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede -Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC Hans de Goede -Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede -Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede +Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 53ff97d745..063ac8f9d6 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c new file mode 100644 index 0000000000..9798e5bf7c --- /dev/null +++ b/drivers/power/axp209.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2012 + * Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +enum axp209_reg { + AXP209_POWER_STATUS = 0x00, + AXP209_CHIP_VERSION = 0x03, + AXP209_DCDC2_VOLTAGE = 0x23, + AXP209_DCDC3_VOLTAGE = 0x27, + AXP209_LDO24_VOLTAGE = 0x28, + AXP209_LDO3_VOLTAGE = 0x29, + AXP209_IRQ_STATUS5 = 0x4c, + AXP209_SHUTDOWN = 0x32, +}; + +#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0) + +#define AXP209_IRQ5_PEK_UP (1 << 6) +#define AXP209_IRQ5_PEK_DOWN (1 << 5) + +#define AXP209_POWEROFF (1 << 7) + +static int axp209_write(enum axp209_reg reg, u8 val) +{ + return i2c_write(0x34, reg, 1, &val, 1); +} + +static int axp209_read(enum axp209_reg reg, u8 *val) +{ + return i2c_read(0x34, reg, 1, val, 1); +} + +static u8 axp209_mvolt_to_cfg(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int axp209_set_dcdc2(int mvolt) +{ + int rc; + u8 cfg, current; + + cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); + + /* Do we really need to be this gentle? It has built-in voltage slope */ + while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, ¤t)) == 0 && + current != cfg) { + if (current < cfg) + current++; + else + current--; + + rc = axp209_write(AXP209_DCDC2_VOLTAGE, current); + if (rc) + break; + } + + return rc; +} + +int axp209_set_dcdc3(int mvolt) +{ + u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); + + return axp209_write(AXP209_DCDC3_VOLTAGE, cfg); +} + +int axp209_set_ldo2(int mvolt) +{ + int rc; + u8 cfg, reg; + + cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100); + + rc = axp209_read(AXP209_LDO24_VOLTAGE, ®); + if (rc) + return rc; + + /* LDO2 configuration is in upper 4 bits */ + reg = (reg & 0x0f) | (cfg << 4); + return axp209_write(AXP209_LDO24_VOLTAGE, reg); +} + +int axp209_set_ldo3(int mvolt) +{ + u8 cfg; + + if (mvolt == -1) + cfg = 0x80; /* determined by LDO3IN pin */ + else + cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); + + return axp209_write(AXP209_LDO3_VOLTAGE, cfg); +} + +int axp209_set_ldo4(int mvolt) +{ + int rc; + static const int vindex[] = { + 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500, + 2700, 2800, 3000, 3100, 3200, 3300 + }; + u8 cfg, reg; + + /* Translate mvolt to register cfg value, requested <= selected */ + for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--); + + rc = axp209_read(AXP209_LDO24_VOLTAGE, ®); + if (rc) + return rc; + + /* LDO4 configuration is in lower 4 bits */ + reg = (reg & 0xf0) | (cfg << 0); + return axp209_write(AXP209_LDO24_VOLTAGE, reg); +} + +int axp209_init(void) +{ + u8 ver; + int rc; + + rc = axp209_read(AXP209_CHIP_VERSION, &ver); + if (rc) + return rc; + + /* Low 4 bits is chip version */ + ver &= 0x0f; + + if (ver != 0x1) + return -1; + + return 0; +} + +int axp209_poweron_by_dc(void) +{ + u8 v; + + if (axp209_read(AXP209_POWER_STATUS, &v)) + return 0; + + return (v & AXP209_POWER_STATUS_ON_BY_DC); +} + +int axp209_power_button(void) +{ + u8 v; + + if (axp209_read(AXP209_IRQ_STATUS5, &v)) + return 0; + + axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN); + + return v & AXP209_IRQ5_PEK_DOWN; +} diff --git a/include/axp209.h b/include/axp209.h new file mode 100644 index 0000000000..21efce64bb --- /dev/null +++ b/include/axp209.h @@ -0,0 +1,14 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +extern int axp209_set_dcdc2(int mvolt); +extern int axp209_set_dcdc3(int mvolt); +extern int axp209_set_ldo2(int mvolt); +extern int axp209_set_ldo3(int mvolt); +extern int axp209_set_ldo4(int mvolt); +extern int axp209_init(void); +extern int axp209_poweron_by_dc(void); +extern int axp209_power_button(void); diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 6560b65b38..037f9952f8 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -12,6 +12,7 @@ * A10 specific configuration */ #define CONFIG_SUN4I /* sun4i SoC generation */ +#define CONFIG_CLK_FULL_SPEED 1008000000 #define CONFIG_SYS_PROMPT "sun4i# " diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index 43f0d67345..c6138b7cd4 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -12,6 +12,7 @@ * High Level Configuration Options */ #define CONFIG_SUN5I /* sun5i SoC generation */ +#define CONFIG_CLK_FULL_SPEED 1008000000 #define CONFIG_SYS_PROMPT "sun5i# " diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 9b693f7039..d9be1046b0 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -13,6 +13,7 @@ * A20 specific configuration */ #define CONFIG_SUN7I /* sun7i SoC generation */ +#define CONFIG_CLK_FULL_SPEED 912000000 #define CONFIG_SYS_PROMPT "sun7i# " diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 42b0d2e51b..40833885f7 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -169,6 +169,11 @@ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_CMD_I2C +/* PMU */ +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER +#define CONFIG_SPL_POWER_SUPPORT +#endif + #ifndef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 1 /* UART0 */ #endif -- cgit v1.2.1 From 24289208354c143967968755cff5c825a12e3f90 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 13 Jun 2014 22:55:51 +0200 Subject: sunxi: Add axp152 pmic support Add support for the x-powers axp152 pmic which is found on most A10s boards and enable it for the r7-tv-dongle board. Signed-off-by: Henrik Nordstrom Signed-off-by: Ian Campbell Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- board/sunxi/board.c | 10 ++++++ boards.cfg | 2 +- drivers/power/Makefile | 1 + drivers/power/axp152.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/axp152.h | 10 ++++++ 5 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 drivers/power/axp152.c create mode 100644 include/axp152.h diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 8375711d1e..8607eb3aa3 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -12,6 +12,9 @@ */ #include +#ifdef CONFIG_AXP152_POWER +#include +#endif #ifdef CONFIG_AXP209_POWER #include #endif @@ -122,6 +125,13 @@ void sunxi_board_init(void) int power_failed = 0; unsigned long ramsize; +#ifdef CONFIG_AXP152_POWER + power_failed = axp152_init(); + power_failed |= axp152_set_dcdc2(1400); + power_failed |= axp152_set_dcdc3(1500); + power_failed |= axp152_set_dcdc4(1250); + power_failed |= axp152_set_ldo2(3000); +#endif #ifdef CONFIG_AXP209_POWER power_failed |= axp209_init(); power_failed |= axp209_set_dcdc2(1400); diff --git a/boards.cfg b/boards.cfg index 8e6afe7876..58873b6fa0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -381,7 +381,7 @@ Active arm armv7 sunxi - sunxi Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede -Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL Hans de Goede +Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 063ac8f9d6..dc64e4d32b 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o diff --git a/drivers/power/axp152.c b/drivers/power/axp152.c new file mode 100644 index 0000000000..fa4ea050a5 --- /dev/null +++ b/drivers/power/axp152.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2012 + * Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include + +enum axp152_reg { + AXP152_CHIP_VERSION = 0x3, + AXP152_DCDC2_VOLTAGE = 0x23, + AXP152_DCDC3_VOLTAGE = 0x27, + AXP152_DCDC4_VOLTAGE = 0x2B, + AXP152_LDO2_VOLTAGE = 0x2A, + AXP152_SHUTDOWN = 0x32, +}; + +#define AXP152_POWEROFF (1 << 7) + +static int axp152_write(enum axp152_reg reg, u8 val) +{ + return i2c_write(0x30, reg, 1, &val, 1); +} + +static int axp152_read(enum axp152_reg reg, u8 *val) +{ + return i2c_read(0x30, reg, 1, val, 1); +} + +static u8 axp152_mvolt_to_target(int mvolt, int min, int max, int div) +{ + if (mvolt < min) + mvolt = min; + else if (mvolt > max) + mvolt = max; + + return (mvolt - min) / div; +} + +int axp152_set_dcdc2(int mvolt) +{ + int rc; + u8 current, target; + + target = axp152_mvolt_to_target(mvolt, 700, 2275, 25); + + /* Do we really need to be this gentle? It has built-in voltage slope */ + while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, ¤t)) == 0 && + current != target) { + if (current < target) + current++; + else + current--; + rc = axp152_write(AXP152_DCDC2_VOLTAGE, current); + if (rc) + break; + } + return rc; +} + +int axp152_set_dcdc3(int mvolt) +{ + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25); + + return axp152_write(AXP152_DCDC3_VOLTAGE, target); +} + +int axp152_set_dcdc4(int mvolt) +{ + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 25); + + return axp152_write(AXP152_DCDC4_VOLTAGE, target); +} + +int axp152_set_ldo2(int mvolt) +{ + u8 target = axp152_mvolt_to_target(mvolt, 700, 3500, 100); + + return axp152_write(AXP152_LDO2_VOLTAGE, target); +} + +int axp152_init(void) +{ + u8 ver; + int rc; + + rc = axp152_read(AXP152_CHIP_VERSION, &ver); + if (rc) + return rc; + + if (ver != 0x05) + return -1; + + return 0; +} diff --git a/include/axp152.h b/include/axp152.h new file mode 100644 index 0000000000..3e5ccbd0d8 --- /dev/null +++ b/include/axp152.h @@ -0,0 +1,10 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * SPDX-License-Identifier: GPL-2.0+ + */ +int axp152_set_dcdc2(int mvolt); +int axp152_set_dcdc3(int mvolt); +int axp152_set_dcdc4(int mvolt); +int axp152_set_ldo2(int mvolt); +int axp152_init(void); -- cgit v1.2.1 From ae5de5a19df2d25ccf0e58bf59b74ebdb18612a2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 13 Jun 2014 22:55:52 +0200 Subject: sunxi: Fix reset hang on sun5i Do the same as the Linux kernel does, this fixes the SoC hanging on reset about 50% of the time. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/board.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 701f9195e2..8f2cef332f 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -77,7 +77,11 @@ void reset_cpu(ulong addr) /* Set the watchdog for its shortest interval (.5s) and wait */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); - while (1); + + while (1) { + /* sun5i sometimes gets stuck without this */ + writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); + } } /* do some early init */ -- cgit v1.2.1 From b41d7d05b7a7ab56d961c144ca93b15de0fc4308 Mon Sep 17 00:00:00 2001 From: Jonathan Liu Date: Sat, 14 Jun 2014 08:59:09 +0200 Subject: sunxi: use random parts of SID to set ethaddr Similar to the USB NIC found on OMAP5uEVM, PandaBoard and BeagleBoard-XM boards, the sunxi SoCs have a NIC onboard without an embedded MAC address. Just like the omap used on these boards, the sunxi SoCs do have a unique chip id, in the form of the 128 bit SID register: http://linux-sunxi.org/SID_Register_Guide So mimick the BeagleBoard-XM board code (commit 548a64d8) and use the chip id to generate a unique fixed MAC address. We check for the SID not being all 0, since some early A20 batches shipped without having there SID programmed. Note we use specific parts of the 128 bits, since some parts indicate the SoC family / revision, and thus are fixed. The algorithm for this was taken from the linux-sunxi.org kernels. Signed-off-by: Jonathan Liu [hdegoede@redhat.com: Expanded the commit message with some more info] Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- board/sunxi/board.c | 28 ++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 2 ++ 2 files changed, 30 insertions(+) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 8607eb3aa3..2179e234e2 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -19,9 +19,12 @@ #include #endif #include +#include #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -157,3 +160,28 @@ void sunxi_board_init(void) printf("Failed to set core voltage! Can't set CPU frequency\n"); } #endif + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + if (!getenv("ethaddr")) { + uint32_t reg_val = readl(SUNXI_SID_BASE); + + if (reg_val) { + uint8_t mac_addr[6]; + + mac_addr[0] = 0x02; /* Non OUI / registered MAC address */ + mac_addr[1] = (reg_val >> 0) & 0xff; + reg_val = readl(SUNXI_SID_BASE + 0x0c); + mac_addr[2] = (reg_val >> 24) & 0xff; + mac_addr[3] = (reg_val >> 16) & 0xff; + mac_addr[4] = (reg_val >> 8) & 0xff; + mac_addr[5] = (reg_val >> 0) & 0xff; + + eth_setenv_enetaddr("ethaddr", mac_addr); + } + } + + return 0; +} +#endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 40833885f7..13e72d5f02 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -207,6 +207,8 @@ #define CONFIG_ENV_IS_NOWHERE #endif +#define CONFIG_MISC_INIT_R + #ifndef CONFIG_SPL_BUILD #include #endif -- cgit v1.2.1 From 5c58f8b685fbb201fd93af2a010eecd26c78bb4e Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 5 Jun 2014 19:00:14 +0100 Subject: sunxi: add Cubieboard2 support This is a sun7i (A20) based followup to the sun4i (A10) Cubieboard. It has GMAC using MII mode. Signed-off-by: Ian Campbell Acked-by: Hans de Goede --- board/sunxi/Makefile | 1 + board/sunxi/dram_cubieboard2.c | 31 +++++++++++++++++++++++++++++++ boards.cfg | 2 ++ 3 files changed, 34 insertions(+) create mode 100644 board/sunxi/dram_cubieboard2.c diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 708363290a..62acb8ff27 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -12,5 +12,6 @@ obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o +obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o diff --git a/board/sunxi/dram_cubieboard2.c b/board/sunxi/dram_cubieboard2.c new file mode 100644 index 0000000000..9e753677c5 --- /dev/null +++ b/board/sunxi/dram_cubieboard2.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include +#include + +static struct dram_para dram_para = { + .clock = 480, + .type = 3, + .rank_num = 1, + .density = 4096, + .io_width = 16, + .bus_width = 32, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 1024, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0x0, + .tpr4 = 0x1, + .tpr5 = 0x0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0x0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/boards.cfg b/boards.cfg index 58873b6fa0..035b5c720f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -379,6 +379,8 @@ Active arm armv7 s5pc1xx samsung smdkc100 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,CONS_INDEX=2 Hans de Goede Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,AXP209_POWER,SUNXI_EMAC Hans de Goede +Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC Ian Campbell :Hans de Goede +Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC Ian Campbell :Hans de Goede Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII Ian Campbell :Hans de Goede Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER Hans de Goede -- cgit v1.2.1 From abce2c6220c1f8f4b66e464adc1074e04a8f19eb Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 5 Jun 2014 19:00:15 +0100 Subject: sunxi: add gpio driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well as providing the common gpio API (gpio_request/free, direction in/out, get/set etc). Signed-off-by: Chen-Yu Tsai Signed-off-by: Hans de Goede Signed-off-by: Ma Haijun Signed-off-by: Oliver Schinagl Signed-off-by: Ian Campbell Cc: Henrik Nordström Cc: Tom Cubie Acked-by: Hans de Goede --- arch/arm/include/asm/arch-sunxi/gpio.h | 2 + drivers/gpio/Makefile | 1 + drivers/gpio/sunxi_gpio.c | 102 +++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 4 ++ 4 files changed, 109 insertions(+) create mode 100644 drivers/gpio/sunxi_gpio.c diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 892479c183..f7f3d8c41a 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -143,5 +143,7 @@ int sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgpin(u32 pin); int sunxi_gpio_set_drv(u32 pin, u32 val); int sunxi_gpio_set_pull(u32 pin, u32 val); +int sunxi_name_to_gpio(const char *name); +#define name_to_gpio(name) sunxi_name_to_gpio(name) #endif /* _SUNXI_GPIO_H */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 4e001e12bd..86813b9326 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -34,3 +34,4 @@ obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o oby-$(CONFIG_SX151X) += sx151x.o +obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c new file mode 100644 index 0000000000..0c50a8f332 --- /dev/null +++ b/drivers/gpio/sunxi_gpio.c @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom + * + * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c: + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static int sunxi_gpio_output(u32 pin, u32 val) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + dat = readl(&pio->dat); + if (val) + dat |= 0x1 << num; + else + dat &= ~(0x1 << num); + + writel(dat, &pio->dat); + + return 0; +} + +static int sunxi_gpio_input(u32 pin) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + + dat = readl(&pio->dat); + dat >>= num; + + return dat & 0x1; +} + +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT); + + return sunxi_gpio_input(gpio); +} + +int gpio_direction_output(unsigned gpio, int value) +{ + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT); + + return sunxi_gpio_output(gpio, value); +} + +int gpio_get_value(unsigned gpio) +{ + return sunxi_gpio_input(gpio); +} + +int gpio_set_value(unsigned gpio, int value) +{ + return sunxi_gpio_output(gpio, value); +} + +int sunxi_name_to_gpio(const char *name) +{ + int group = 0; + int groupsize = 9 * 32; + long pin; + char *eptr; + if (*name == 'P' || *name == 'p') + name++; + if (*name >= 'A') { + group = *name - (*name > 'a' ? 'a' : 'A'); + groupsize = 32; + name++; + } + + pin = simple_strtol(name, &eptr, 10); + if (!*name || *eptr) + return -1; + if (pin < 0 || pin > groupsize || group >= 9) + return -1; + return group * 32 + pin; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 13e72d5f02..845b004a27 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -178,6 +178,10 @@ #define CONFIG_CONS_INDEX 1 /* UART0 */ #endif +/* GPIO */ +#define CONFIG_SUNXI_GPIO +#define CONFIG_CMD_GPIO + /* Ethernet support */ #ifdef CONFIG_SUNXI_EMAC #define CONFIG_MII /* MII PHY management */ -- cgit v1.2.1 From 7c48b015100eeff0e1bbb766394f7beca23afb48 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Thu, 5 Jun 2014 19:00:16 +0100 Subject: sunxi: use setbits_le32 to enable the DMA clock Signed-off-by: Ian Campbell Acked-by: Hans de Goede --- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 5a7da3c6bf..b8b16cff95 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -36,8 +36,7 @@ void clock_init_safe(void) CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, &ccm->cpu_ahb_apb0_cfg); #ifdef CONFIG_SUN7I - writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0), - &ccm->ahb_gate0); + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA); #endif writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); } -- cgit v1.2.1 From 2b25721645677de68ffdfd93dfa6fe5a8a389893 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 8 May 2014 15:10:48 +0200 Subject: ARM: zynq: Enable generic board for Xilinx Zynq Enable CONFIG_SYS_GENERIC_BOARD for all Zynq boards. Signed-off-by: Michal Simek Tested-by: Masahiro Yamada [on ZC706 board] --- include/configs/zynq-common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index fa252c0b13..690cacbc94 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -339,4 +339,6 @@ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_GENERIC_BOARD + #endif /* __CONFIG_ZYNQ_COMMON_H */ -- cgit v1.2.1 From 03606ff42eb11a6beacc766a78819561abe930b1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 15 May 2014 09:40:14 +0200 Subject: ARM: zynq: Show ECC status on the same line as DRAM size Without this patch is DRAM size one line below DRAM: which is not nice Origin: I2C: ready DRAM: Memory: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Fixed by this patch: I2C: ready DRAM: ECC disabled 1 GiB MMC: zynq_sdhci: 0 Signed-off-by: Michal Simek Tested-by: Masahiro Yamada --- arch/arm/cpu/armv7/zynq/ddrc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index e0ed3bfb43..1ea086d520 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -34,7 +34,7 @@ void zynq_ddrc_init(void) /* ECC is enabled when memory is in 16bit mode and it is enabled */ if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) && (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) { - puts("Memory: ECC enabled\n"); + puts("ECC enabled "); /* * Clear the first 1MB because it is not initialized from * first stage bootloader. To get ECC to work all memory has @@ -42,6 +42,6 @@ void zynq_ddrc_init(void) */ memset((void *)0, 0, 1 * 1024 * 1024); } else { - puts("Memory: ECC disabled\n"); + puts("ECC disabled "); } } -- cgit v1.2.1 From 327474915a413be98950deeeba27c3d17e5134bc Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 29 May 2014 14:46:13 +0900 Subject: zynq: disable -Wstrict-prototypes option for ps7_init.c The files ps7_init.c and ps7_init.h are supposed to be generated by hw projects such as Vivado, PlanAhead and then to be copied into board/xilinx/zynq directory. But some prototypes in them cause annoying warning messages: CC spl/board/xilinx/zynq/ps7_init.o In file included from board/xilinx/zynq/ps7_init.c:50:0: board/xilinx/zynq/ps7_init.h:137:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.h:138:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.h:139:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.h:145:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.c:12602:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.c:12723:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.c:12742:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.c:12761:1: warning: function declaration isn't a prototype [-Wstrict-prototypes] board/xilinx/zynq/ps7_init.c:12854:6: warning: function declaration isn't a prototype [-Wstrict-prototypes] The prototypes should be int ps7_init(void); int ps7_post_config(void); int ps7_debug(void); rather than int ps7_init(); int ps7_post_config(); int ps7_debug(); We do not want to be bothered because of automatically generated files. But we cannot touch the external projects for now. What we can do is to disable -Wstrict-prototypes for ps7_init.c Signed-off-by: Masahiro Yamada Cc: Michal Simek Tested-by: Michal Simek Signed-off-by: Michal Simek --- board/xilinx/zynq/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile index fd93f6317b..71c0c351f9 100644 --- a/board/xilinx/zynq/Makefile +++ b/board/xilinx/zynq/Makefile @@ -10,3 +10,6 @@ obj-y := board.o # Please copy ps7_init.c/h from hw project to this directory obj-$(CONFIG_SPL_BUILD) += \ $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o) + +# Suppress "warning: function declaration isn't a prototype" +CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes -- cgit v1.2.1 From 172437472af18ec6b40cd2fec558302c7cf117ce Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 24 Jun 2014 17:01:08 +0900 Subject: net: sh-eth: Add support R8A7794 R8A7794 has the same sh-ether IP core as other SH/rmobile. This patch adds support of R8A7794. Signed-off-by: Nobuhiro Iwamatsu --- drivers/net/sh_eth.c | 5 +++-- drivers/net/sh_eth.h | 6 ++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 81e8ddbbc7..451c33e1a1 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -413,7 +413,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7794) sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); #endif /* Configure phy */ @@ -439,7 +440,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752) sh_eth_write(eth, 1, RTRATE); #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ - defined(CONFIG_R8A7791) + defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794) val = ECMR_RTM; #endif } else if (phy->speed == 10) { diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index d0d9aaa703..e325a39aac 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -358,7 +358,8 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R8A7740) #define SH_ETH_TYPE_GETHER #define BASE_IO_ADDR 0xE9A00000 -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7794) #define SH_ETH_TYPE_ETHER #define BASE_IO_ADDR 0xEE700200 #elif defined(CONFIG_R7S72100) @@ -569,7 +570,8 @@ enum FELIC_MODE_BIT { ECMR_PRM = 0x00000001, #ifdef CONFIG_CPU_SH7724 ECMR_RTM = 0x00000010, -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7794) ECMR_RTM = 0x00000004, #endif -- cgit v1.2.1 From 2f972a3c62f775dd662f1710416a065f5f001dd5 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 24 Jun 2014 17:03:20 +0900 Subject: serial: sh: Add support R8A7794 This adds the preset value to register for R8A7794. Signed-off-by: Nobuhiro Iwamatsu --- drivers/serial/serial_sh.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index f5e9854d13..341997c8ec 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -226,7 +226,8 @@ struct uart_port { # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ # define SCIF_ORER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ -#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) +#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ + defined(CONFIG_R8A7794) # define SCIF_ORER 0x0001 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ #else -- cgit v1.2.1 From fafcfc5a98709c8e5547d0e327fd14f3da065d4f Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 24 Jun 2014 17:10:02 +0900 Subject: arm: rmobile: Add support R8A7794 Renesas R8A7794 is CPU with Cortex-A15. This supports the basic register definition and GPIO and framework of PFC. Signed-off-by: Hisashi Nakamura Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/Makefile | 1 + arch/arm/cpu/armv7/rmobile/cpu_info.c | 1 + arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c | 1513 ++++++++++++++++++++++ arch/arm/include/asm/arch-rmobile/gpio.h | 3 + arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h | 176 +++ arch/arm/include/asm/arch-rmobile/r8a7794.h | 14 + arch/arm/include/asm/arch-rmobile/rcar-base.h | 4 +- arch/arm/include/asm/arch-rmobile/rmobile.h | 2 + 8 files changed, 1712 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c create mode 100644 arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h create mode 100644 arch/arm/include/asm/arch-rmobile/r8a7794.h diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile index fad004ca64..dd7de41082 100644 --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -13,5 +13,6 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o +obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c index 7a7c97d791..b98137e86a 100644 --- a/arch/arm/cpu/armv7/rmobile/cpu_info.c +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -53,6 +53,7 @@ static const struct { { 0x40, "R8A7740" }, { 0x45, "R8A7790" }, { 0x47, "R8A7791" }, + { 0x4C, "R8A7794" }, { 0x0, "CPU" }, }; diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c new file mode 100644 index 0000000000..e123663333 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c @@ -0,0 +1,1513 @@ +/* + * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c + * This file is r8a7794 processor support - PFC hardware block. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_26_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) + +#define CPU_28_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ + PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) + +/* + * GP_0_0_DATA -> GP_6_25_DATA + * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31] + * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28], + * GP6[29]),GP6[30],GP6[31]) + */ +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT(fn, pfx##_0_, sfx), \ + CPU_26_PORT(fn, pfx##_1_, sfx), \ + CPU_32_PORT(fn, pfx##_2_, sfx), \ + CPU_32_PORT(fn, pfx##_3_, sfx), \ + CPU_32_PORT(fn, pfx##_4_, sfx), \ + CPU_28_PORT(fn, pfx##_5_, sfx), \ + CPU_26_PORT(fn, pfx##_6_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, + FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, + FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, + FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, + FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, + FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, + FN_IP2_17_16, + + /* GPSR1 */ + FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, + FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, + FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, + FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, + FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, + + /* GPSR2 */ + FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, + FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, + FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, + FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, + FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, + FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, + FN_IP6_5_4, FN_IP6_7_6, + + /* GPSR3 */ + FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, + FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, + FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, + FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, + FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, + FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, + FN_IP8_22_20, + + /* GPSR4 */ + FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, + FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, + FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, + FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, + FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, + FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, + FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, + + /* GPSR5 */ + FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, + FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, + FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, + FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, + FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, + FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, + + /* GPSR6 */ + FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, + FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, + FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, + FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, + FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, + FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, + FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, + FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, + FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, + FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, + FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, + FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, + FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, + FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, + FN_ADIDATA, FN_AD_DI, + + /* IPSR7 */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, + FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, + FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, + FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, + FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, + FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, + FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, + FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, + FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, + + /* IPSR8 */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, + FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, + FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, + FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, + FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, + FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, + FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, + FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, + FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, + FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, + FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, + FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, + FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, + FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, + FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, + FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, + FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, + FN_ADICLK_B, FN_AD_CLK_B, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + /* MOD_SEL */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, + FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, + FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, + FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, + FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, + FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, + FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, + FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, + FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, + FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, + FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, + + /* MOD_SEL2 */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, + FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, + FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, + FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, + FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, + FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, + FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, + FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, + FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, + FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, + FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, + FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, + FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, + FN_SEL_RDS_2, FN_SEL_RDS_3, + + /* MOD_SEL3 */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, + FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, + FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, + FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, + FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, + FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, + FN_SEL_SSI9_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, + + USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, + + SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, + SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, + + SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, + SD1_DATA2_MARK, SD1_DATA3_MARK, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, + DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, + CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, + AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, + VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, + AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, + VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, + AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, + I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, + VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, + AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, + IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, + I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, + VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, + ADIDATA_MARK, AD_DI_MARK, + + /* IPSR7 */ + ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, + AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, + MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, + AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, + CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, + ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, + AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, + MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, + ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, + SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, + IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, + VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, + SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, + AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, + SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, + DREQ0_N_MARK, SCIFB1_RXD_MARK, + + /* IPSR8 */ + ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, + AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, + I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, + HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, + AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, + SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, + HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, + AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, + HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, + I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, + AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, + SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, + CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, + DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, + I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, + TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, + I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, + FMCLK_C_MARK, RDS_CLK_MARK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, + CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, + DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, + SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, + SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, + SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, + DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, + DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, + AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, + MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, + PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, + ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, + PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + PINMUX_DATA(A2_MARK, FN_A2), + PINMUX_DATA(WE0_N_MARK, FN_WE0_N), + PINMUX_DATA(WE1_N_MARK, FN_WE1_N), + PINMUX_DATA(DACK0_MARK, FN_DACK0), + PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), + PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), + PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), + PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), + PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), + PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), + PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), + PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), + PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), + PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), + PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), + PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), + PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), + PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), + PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), + PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), + PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), + PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), + PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), + PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), + PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), + PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), + PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), + PINMUX_IPSR_DATA(IP6_5_4, QPOLA), + PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), + PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), + PINMUX_IPSR_DATA(IP6_7_6, QPOLB), + PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), + PINMUX_IPSR_DATA(IP6_8, VI0_CLK), + PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), + PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), + PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), + PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), + PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), + PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), + PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), + PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), + PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), + PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), + PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), + PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), + PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), + PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), + PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), + PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), + PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), + PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), + PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), + PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), + PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), + PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), + PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), + PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), + + /* IPSR7 */ + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), + PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), + PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), + PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), + PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), + PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), + PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), + PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), + PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), + PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), + PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), + PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), + PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), + PINMUX_IPSR_DATA(IP7_31, DREQ0_N), + PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), + + /* IPSR8 */ + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), + PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), + PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), + PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), + PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), + PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), + PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), + PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), + PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), + PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), + PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), + PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), + PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), + PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), + PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), + PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_19_17, PWM5), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), + PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), + PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), + PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), + PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), + PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), + PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), + PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), + PINMUX_IPSR_DATA(IP8_28_26, IRQ5), + PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), + PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), + PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), + PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), + PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), + PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), + PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), + PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), + PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), + PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), + PINMUX_IPSR_DATA(IP11_20_18, IRQ8), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), + PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), + PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), + PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), + PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), + PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), + PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0), + GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN), + GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD), + GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2), + GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP), + GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0), + GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3), + + /* + * From IPSR0 to IPSR5 have been removed because they does not use + */ + + /* IPSR6 */ + GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), + GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), + GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP), + GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), + GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK), + GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV), + GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2), + GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2), + GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5), + GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5), + GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB), + GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C), + GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA), + GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER), + GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C), + GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N), + GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B), + GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0), + GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK), + GPIO_FN(ADIDATA), GPIO_FN(AD_DI), + + /* IPSR7 */ + GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B), + GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP), + GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2), + GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1), + GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3), + GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2), + GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1), + GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D), + GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5), + GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4), + GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6), + GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B), + GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C), + GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B), + GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C), + GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B), + GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B), + GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0), + GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E), + GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N), + GPIO_FN(SCIFB1_RXD), + + /* IPSR8 */ + GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B), + GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B), + GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C), + GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B), + GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C), + GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B), + GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D), + GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B), + GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D), + GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B), + GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS), + GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C), + GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK), + GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA), + GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK), + GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL), + GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0), + GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B), + GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5), + GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D), + GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD), + GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B), + GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK), + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C), + GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5), + GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1), + GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B), + GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13), + GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C), + GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14), + GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C), + GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15), + GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C), + GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B), + GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7), + GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D), + GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129), + GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B), + GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129), + GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B), + GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B), + GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B), + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + GP_0_31_FN, FN_IP2_17_16, + GP_0_30_FN, FN_IP2_15_14, + GP_0_29_FN, FN_IP2_13_12, + GP_0_28_FN, FN_IP2_11_10, + GP_0_27_FN, FN_IP2_9_8, + GP_0_26_FN, FN_IP2_7_6, + GP_0_25_FN, FN_IP2_5_4, + GP_0_24_FN, FN_IP2_3_2, + GP_0_23_FN, FN_IP2_1_0, + GP_0_22_FN, FN_IP1_31_30, + GP_0_21_FN, FN_IP1_29_28, + GP_0_20_FN, FN_IP1_27, + GP_0_19_FN, FN_IP1_26, + GP_0_18_FN, FN_A2, + GP_0_17_FN, FN_IP1_24, + GP_0_16_FN, FN_IP1_23_22, + GP_0_15_FN, FN_IP1_21_20, + GP_0_14_FN, FN_IP1_19_18, + GP_0_13_FN, FN_IP1_17_15, + GP_0_12_FN, FN_IP1_14_13, + GP_0_11_FN, FN_IP1_12_11, + GP_0_10_FN, FN_IP1_10_8, + GP_0_9_FN, FN_IP1_7_6, + GP_0_8_FN, FN_IP1_5_4, + GP_0_7_FN, FN_IP1_3_2, + GP_0_6_FN, FN_IP1_1_0, + GP_0_5_FN, FN_IP0_31_30, + GP_0_4_FN, FN_IP0_29_28, + GP_0_3_FN, FN_IP0_27_26, + GP_0_2_FN, FN_IP0_25, + GP_0_1_FN, FN_IP0_24, + GP_0_0_FN, FN_IP0_23_22, } + }, + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_FN, FN_DACK0, + GP_1_24_FN, FN_IP7_31, + GP_1_23_FN, FN_IP4_1_0, + GP_1_22_FN, FN_WE1_N, + GP_1_21_FN, FN_WE0_N, + GP_1_20_FN, FN_IP3_31, + GP_1_19_FN, FN_IP3_30, + GP_1_18_FN, FN_IP3_29_27, + GP_1_17_FN, FN_IP3_26_24, + GP_1_16_FN, FN_IP3_23_21, + GP_1_15_FN, FN_IP3_20_18, + GP_1_14_FN, FN_IP3_17_15, + GP_1_13_FN, FN_IP3_14_13, + GP_1_12_FN, FN_IP3_12, + GP_1_11_FN, FN_IP3_11, + GP_1_10_FN, FN_IP3_10, + GP_1_9_FN, FN_IP3_9_8, + GP_1_8_FN, FN_IP3_7_6, + GP_1_7_FN, FN_IP3_5_4, + GP_1_6_FN, FN_IP3_3_2, + GP_1_5_FN, FN_IP3_1_0, + GP_1_4_FN, FN_IP2_31_30, + GP_1_3_FN, FN_IP2_29_27, + GP_1_2_FN, FN_IP2_26_24, + GP_1_1_FN, FN_IP2_23_21, + GP_1_0_FN, FN_IP2_20_18, } + }, + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + GP_2_31_FN, FN_IP6_7_6, + GP_2_30_FN, FN_IP6_5_4, + GP_2_29_FN, FN_IP6_3_2, + GP_2_28_FN, FN_IP6_1_0, + GP_2_27_FN, FN_IP5_31_30, + GP_2_26_FN, FN_IP5_29_28, + GP_2_25_FN, FN_IP5_27_26, + GP_2_24_FN, FN_IP5_25_24, + GP_2_23_FN, FN_IP5_23_22, + GP_2_22_FN, FN_IP5_21_20, + GP_2_21_FN, FN_IP5_19_18, + GP_2_20_FN, FN_IP5_17_16, + GP_2_19_FN, FN_IP5_15_14, + GP_2_18_FN, FN_IP5_13_12, + GP_2_17_FN, FN_IP5_11_9, + GP_2_16_FN, FN_IP5_8_6, + GP_2_15_FN, FN_IP5_5_4, + GP_2_14_FN, FN_IP5_3_2, + GP_2_13_FN, FN_IP5_1_0, + GP_2_12_FN, FN_IP4_31_30, + GP_2_11_FN, FN_IP4_29_28, + GP_2_10_FN, FN_IP4_27_26, + GP_2_9_FN, FN_IP4_25_23, + GP_2_8_FN, FN_IP4_22_20, + GP_2_7_FN, FN_IP4_19_18, + GP_2_6_FN, FN_IP4_17_16, + GP_2_5_FN, FN_IP4_15_14, + GP_2_4_FN, FN_IP4_13_12, + GP_2_3_FN, FN_IP4_11_10, + GP_2_2_FN, FN_IP4_9_8, + GP_2_1_FN, FN_IP4_7_5, + GP_2_0_FN, FN_IP4_4_2 } + }, + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + GP_3_31_FN, FN_IP8_22_20, + GP_3_30_FN, FN_IP8_19_17, + GP_3_29_FN, FN_IP8_16_15, + GP_3_28_FN, FN_IP8_14_12, + GP_3_27_FN, FN_IP8_11_9, + GP_3_26_FN, FN_IP8_8_6, + GP_3_25_FN, FN_IP8_5_3, + GP_3_24_FN, FN_IP8_2_0, + GP_3_23_FN, FN_IP7_29_27, + GP_3_22_FN, FN_IP7_26_24, + GP_3_21_FN, FN_IP7_23_21, + GP_3_20_FN, FN_IP7_20_18, + GP_3_19_FN, FN_IP7_17_15, + GP_3_18_FN, FN_IP7_14_12, + GP_3_17_FN, FN_IP7_11_9, + GP_3_16_FN, FN_IP7_8_6, + GP_3_15_FN, FN_IP7_5_3, + GP_3_14_FN, FN_IP7_2_0, + GP_3_13_FN, FN_IP6_31_29, + GP_3_12_FN, FN_IP6_28_26, + GP_3_11_FN, FN_IP6_25_23, + GP_3_10_FN, FN_IP6_22_20, + GP_3_9_FN, FN_IP6_19_17, + GP_3_8_FN, FN_IP6_16, + GP_3_7_FN, FN_IP6_15, + GP_3_6_FN, FN_IP6_14, + GP_3_5_FN, FN_IP6_13, + GP_3_4_FN, FN_IP6_12, + GP_3_3_FN, FN_IP6_11, + GP_3_2_FN, FN_IP6_10, + GP_3_1_FN, FN_IP6_9, + GP_3_0_FN, FN_IP6_8 } + }, + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + GP_4_31_FN, FN_IP11_17_16, + GP_4_30_FN, FN_IP11_15_14, + GP_4_29_FN, FN_IP11_13_11, + GP_4_28_FN, FN_IP11_10_8, + GP_4_27_FN, FN_IP11_7_6, + GP_4_26_FN, FN_IP11_5_3, + GP_4_25_FN, FN_IP11_2_0, + GP_4_24_FN, FN_IP10_31_30, + GP_4_23_FN, FN_IP10_29_27, + GP_4_22_FN, FN_IP10_26_24, + GP_4_21_FN, FN_IP10_23_21, + GP_4_20_FN, FN_IP10_20_18, + GP_4_19_FN, FN_IP10_17_15, + GP_4_18_FN, FN_IP10_14_12, + GP_4_17_FN, FN_IP10_11_9, + GP_4_16_FN, FN_IP10_8_6, + GP_4_15_FN, FN_IP10_5_3, + GP_4_14_FN, FN_IP10_2_0, + GP_4_13_FN, FN_IP9_30_28, + GP_4_12_FN, FN_IP9_27_25, + GP_4_11_FN, FN_IP9_24_22, + GP_4_10_FN, FN_IP9_21_19, + GP_4_9_FN, FN_IP9_18_17, + GP_4_8_FN, FN_IP9_16_15, + GP_4_7_FN, FN_IP9_14_12, + GP_4_6_FN, FN_IP9_11_9, + GP_4_5_FN, FN_IP9_8_6, + GP_4_4_FN, FN_IP9_5_3, + GP_4_3_FN, FN_IP9_2_0, + GP_4_2_FN, FN_IP8_31_29, + GP_4_1_FN, FN_IP8_28_26, + GP_4_0_FN, FN_IP8_25_23 } + }, + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_FN, FN_USB1_OVC, + GP_5_26_FN, FN_USB1_PWEN, + GP_5_25_FN, FN_USB0_OVC, + GP_5_24_FN, FN_USB0_PWEN, + GP_5_23_FN, FN_IP13_26_24, + GP_5_22_FN, FN_IP13_23_21, + GP_5_21_FN, FN_IP13_20_18, + GP_5_20_FN, FN_IP13_17_15, + GP_5_19_FN, FN_IP13_14_12, + GP_5_18_FN, FN_IP13_11_9, + GP_5_17_FN, FN_IP13_8_6, + GP_5_16_FN, FN_IP13_5_3, + GP_5_15_FN, FN_IP13_2_0, + GP_5_14_FN, FN_IP12_29_27, + GP_5_13_FN, FN_IP12_26_24, + GP_5_12_FN, FN_IP12_23_21, + GP_5_11_FN, FN_IP12_20_18, + GP_5_10_FN, FN_IP12_17_15, + GP_5_9_FN, FN_IP12_14_13, + GP_5_8_FN, FN_IP12_12_11, + GP_5_7_FN, FN_IP12_10_9, + GP_5_6_FN, FN_IP12_8_6, + GP_5_5_FN, FN_IP12_5_3, + GP_5_4_FN, FN_IP12_2_0, + GP_5_3_FN, FN_IP11_29_27, + GP_5_2_FN, FN_IP11_26_24, + GP_5_1_FN, FN_IP11_23_21, + GP_5_0_FN, FN_IP11_20_18 } + }, + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_FN, FN_IP0_21_20, + GP_6_24_FN, FN_IP0_19_18, + GP_6_23_FN, FN_IP0_17, + GP_6_22_FN, FN_IP0_16, + GP_6_21_FN, FN_IP0_15, + GP_6_20_FN, FN_IP0_14, + GP_6_19_FN, FN_IP0_13, + GP_6_18_FN, FN_IP0_12, + GP_6_17_FN, FN_IP0_11, + GP_6_16_FN, FN_IP0_10, + GP_6_15_FN, FN_IP0_9_8, + GP_6_14_FN, FN_IP0_0, + GP_6_13_FN, FN_SD1_DATA3, + GP_6_12_FN, FN_SD1_DATA2, + GP_6_11_FN, FN_SD1_DATA1, + GP_6_10_FN, FN_SD1_DATA0, + GP_6_9_FN, FN_SD1_CMD, + GP_6_8_FN, FN_SD1_CLK, + GP_6_7_FN, FN_SD0_WP, + GP_6_6_FN, FN_SD0_CD, + GP_6_5_FN, FN_SD0_DATA3, + GP_6_4_FN, FN_SD0_DATA2, + GP_6_3_FN, FN_SD0_DATA1, + GP_6_2_FN, FN_SD0_DATA0, + GP_6_1_FN, FN_SD0_CMD, + GP_6_0_FN, FN_SD0_CLK } + }, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, + 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, + 2, 2) { + /* IP6_31_29 [3] */ + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, + FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, + /* IP6_28_26 [3] */ + FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, + FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, + /* IP6_25_23 [3] */ + FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, + FN_AVB_COL, 0, 0, 0, + /* IP6_22_20 [3] */ + FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, + FN_AVB_RX_ER, 0, 0, 0, + /* IP6_19_17 [3] */ + FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, + FN_AVB_RXD7, 0, 0, 0, + /* IP6_16 [1] */ + FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, + /* IP6_15 [1] */ + FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, + /* IP6_14 [1] */ + FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, + /* IP6_13 [1] */ + FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, + /* IP6_12 [1] */ + FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, + /* IP6_11 [1] */ + FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, + /* IP6_10 [1] */ + FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, + /* IP6_9 [1] */ + FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, + /* IP6_8 [1] */ + FN_VI0_CLK, FN_AVB_RX_CLK, + /* IP6_7_6 [2] */ + FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, + /* IP6_5_4 [2] */ + FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, + /* IP6_3_2 [2] */ + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + /* IP6_1_0 [2] */ + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, + 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { + /* IP7_31 [1] */ + FN_DREQ0_N, FN_SCIFB1_RXD, + /* IP7_30 [1] */ + 0, 0, + /* IP7_29_27 [3] */ + FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, + FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, + /* IP7_26_24 [3] */ + FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, + FN_SSI_SCK6_B, 0, 0, 0, + /* IP7_23_21 [3] */ + FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, + FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, + /* IP7_20_18 [3] */ + FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, + FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, + /* IP7_17_15 [3] */ + FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, + FN_SSI_SCK5_B, 0, 0, 0, + /* IP7_14_12 [3] */ + FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, + FN_AVB_TXD4, FN_ADICHS2, 0, 0, + /* IP7_11_9 [3] */ + FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, + FN_AVB_TXD3, FN_ADICHS1, 0, 0, + /* IP7_8_6 [3] */ + FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, + FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, + /* IP7_5_3 [3] */ + FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, + FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, + /* IP7_2_0 [3] */ + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, + FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, + 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { + /* IP8_31_29 [3] */ + FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, + FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + /* IP8_28_26 [3] */ + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, + FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, + /* IP8_25_23 [3] */ + FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, + FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, + /* IP8_22_20 [3] */ + FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, + FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, + /* IP8_19_17 [3] */ + FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, + FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, + /* IP8_16_15 [2] */ + FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, + /* IP8_14_12 [3] */ + FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, + FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, + /* IP8_11_9 [3] */ + FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, + /* IP8_8_6 [3] */ + FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, + FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, + /* IP8_5_3 [3] */ + FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, + FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, + /* IP8_2_0 [3] */ + FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, + FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } + }, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, + 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { + /* IP11_31_30 [2] */ + 0, 0, 0, 0, + /* IP11_29_27 [3] */ + FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, + FN_AD_CLK_B, 0, 0, 0, + /* IP11_26_24 [3] */ + FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, + FN_AD_DO_B, 0, 0, 0, + /* IP11_23_21 [3] */ + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, + FN_AD_DI_B, FN_PCMWE_N, 0, 0, + /* IP11_20_18 [3] */ + FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, + FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, + /* IP11_17_16 [2] */ + FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, + /* IP11_15_14 [2] */ + FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, + /* IP11_13_11 [3] */ + FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, + /* IP11_10_8 [3] */ + FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, + FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, + /* IP11_7_6 [2] */ + FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_CAN_DEBUGOUT13, + /* IP11_5_3 [3] */ + FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, + FN_CAN_DEBUGOUT12, 0, 0, 0, + /* IP11_2_0 [3] */ + FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, + FN_CAN_DEBUGOUT11, 0, 0, 0, } + }, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ + + { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, + 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, + 2, 1) { + /* SEL_ADG [2] */ + FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, + /* SEL_ADI [1] */ + FN_SEL_ADI_0, FN_SEL_ADI_1, + /* SEL_CAN [2] */ + FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, + /* SEL_DARC [3] */ + FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, + FN_SEL_DARC_4, 0, 0, 0, + /* SEL_DR0 [1] */ + FN_SEL_DR0_0, FN_SEL_DR0_1, + /* SEL_DR1 [1] */ + FN_SEL_DR1_0, FN_SEL_DR1_1, + /* SEL_DR2 [1] */ + FN_SEL_DR2_0, FN_SEL_DR2_1, + /* SEL_DR3 [1] */ + FN_SEL_DR3_0, FN_SEL_DR3_1, + /* SEL_ETH [1] */ + FN_SEL_ETH_0, FN_SEL_ETH_1, + /* SLE_FSN [1] */ + FN_SEL_FSN_0, FN_SEL_FSN_1, + /* SEL_IC200 [3] */ + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, + FN_SEL_I2C00_4, 0, 0, 0, + /* SEL_I2C01 [3] */ + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, + FN_SEL_I2C01_4, 0, 0, 0, + /* SEL_I2C02 [3] */ + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + FN_SEL_I2C02_4, 0, 0, 0, + /* SEL_I2C03 [3] */ + FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, + FN_SEL_I2C03_4, 0, 0, 0, + /* SEL_I2C04 [3] */ + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, + FN_SEL_I2C04_4, 0, 0, 0, + /* SEL_IIC00 [2] */ + FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, + /* SEL_AVB [1] */ + FN_SEL_AVB_0, FN_SEL_AVB_1, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, + 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, + 2, 2, 2, 1, 1, 2) { + /* SEL_IEB [2] */ + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, + /* SEL_LBS [1] */ + FN_SEL_LBS_0, FN_SEL_LBS_1, + /* SEL_MSI1 [1] */ + FN_SEL_MSI1_0, FN_SEL_MSI1_1, + /* SEL_MSI2 [1] */ + FN_SEL_MSI2_0, FN_SEL_MSI2_1, + /* SEL_RAD [1] */ + FN_SEL_RAD_0, FN_SEL_RAD_1, + /* SEL_RCN [1] */ + FN_SEL_RCN_0, FN_SEL_RCN_1, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, FN_SEL_RSP_1, + /* SEL_SCIFA0 [2] */ + FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, + FN_SEL_SCIFA0_3, + /* SEL_SCIFA1 [2] */ + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, + /* SEL_SCIFA2 [1] */ + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, + /* SEL_SCIFA3 [1] */ + FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, + /* SEL_SCIFA4 [2] */ + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, + FN_SEL_SCIFA4_3, + /* SEL_SCIFA5 [2] */ + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, + FN_SEL_SCIFA5_3, + /* SEL_SPDM [1] */ + FN_SEL_SPDM_0, FN_SEL_SPDM_1, + /* SEL_TMU [1] */ + FN_SEL_TMU_0, FN_SEL_TMU_1, + /* SEL_TSIF0 [2] */ + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* SEL_CAN0 [2] */ + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + /* SEL_CAN1 [2] */ + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + /* SEL_HSCIF1 [1] */ + FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, + /* SEL_RDS [2] */ + FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } + }, + { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, + 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { + /* SEL_SCIF0 [2] */ + FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, + /* SEL_SCIF1 [2] */ + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, + /* SEL_SCIF2 [2] */ + FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, + /* SEL_SCIF3 [1] */ + FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, + /* SEL_SCIF4 [3] */ + FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, + FN_SEL_SCIF4_4, 0, 0, 0, + /* SEL_SCIF5 [2] */ + FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, + /* SEL_SSI1 [1] */ + FN_SEL_SSI1_0, FN_SEL_SSI1_1, + /* SEL_SSI2 [1] */ + FN_SEL_SSI2_0, FN_SEL_SSI2_1, + /* SEL_SSI4 [1] */ + FN_SEL_SSI4_0, FN_SEL_SSI4_1, + /* SEL_SSI5 [1] */ + FN_SEL_SSI5_0, FN_SEL_SSI5_1, + /* SEL_SSI6 [1] */ + FN_SEL_SSI6_0, FN_SEL_SSI6_1, + /* SEL_SSI7 [1] */ + FN_SEL_SSI7_0, FN_SEL_SSI7_1, + /* SEL_SSI8 [1] */ + FN_SEL_SSI8_0, FN_SEL_SSI8_1, + /* SEL_SSI9 [1] */ + FN_SEL_SSI9_0, FN_SEL_SSI9_1, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, + /* RESEVED [1] */ + 0, 0, } + }, + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_27_IN, GP_5_27_OUT, + GP_5_26_IN, GP_5_26_OUT, + GP_5_25_IN, GP_5_25_OUT, + GP_5_24_IN, GP_5_24_OUT, + GP_5_23_IN, GP_5_23_OUT, + GP_5_22_IN, GP_5_22_OUT, + GP_5_21_IN, GP_5_21_OUT, + GP_5_20_IN, GP_5_20_OUT, + GP_5_19_IN, GP_5_19_OUT, + GP_5_18_IN, GP_5_18_OUT, + GP_5_17_IN, GP_5_17_OUT, + GP_5_16_IN, GP_5_16_OUT, + GP_5_15_IN, GP_5_15_OUT, + GP_5_14_IN, GP_5_14_OUT, + GP_5_13_IN, GP_5_13_OUT, + GP_5_12_IN, GP_5_12_OUT, + GP_5_11_IN, GP_5_11_OUT, + GP_5_10_IN, GP_5_10_OUT, + GP_5_9_IN, GP_5_9_OUT, + GP_5_8_IN, GP_5_8_OUT, + GP_5_7_IN, GP_5_7_OUT, + GP_5_6_IN, GP_5_6_OUT, + GP_5_5_IN, GP_5_5_OUT, + GP_5_4_IN, GP_5_4_OUT, + GP_5_3_IN, GP_5_3_OUT, + GP_5_2_IN, GP_5_2_OUT, + GP_5_1_IN, GP_5_1_OUT, + GP_5_0_IN, GP_5_0_OUT, } + }, + { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_6_25_IN, GP_6_25_OUT, + GP_6_24_IN, GP_6_24_OUT, + GP_6_23_IN, GP_6_23_OUT, + GP_6_22_IN, GP_6_22_OUT, + GP_6_21_IN, GP_6_21_OUT, + GP_6_20_IN, GP_6_20_OUT, + GP_6_19_IN, GP_6_19_OUT, + GP_6_18_IN, GP_6_18_OUT, + GP_6_17_IN, GP_6_17_OUT, + GP_6_16_IN, GP_6_16_OUT, + GP_6_15_IN, GP_6_15_OUT, + GP_6_14_IN, GP_6_14_OUT, + GP_6_13_IN, GP_6_13_OUT, + GP_6_12_IN, GP_6_12_OUT, + GP_6_11_IN, GP_6_11_OUT, + GP_6_10_IN, GP_6_10_OUT, + GP_6_9_IN, GP_6_9_OUT, + GP_6_8_IN, GP_6_8_OUT, + GP_6_7_IN, GP_6_7_OUT, + GP_6_6_IN, GP_6_6_OUT, + GP_6_5_IN, GP_6_5_OUT, + GP_6_4_IN, GP_6_4_OUT, + GP_6_3_IN, GP_6_3_OUT, + GP_6_2_IN, GP_6_2_OUT, + GP_6_1_IN, GP_6_1_OUT, + GP_6_0_IN, GP_6_0_OUT, } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + 0, 0, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { + 0, 0, 0, 0, + GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA, + GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, + GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, + GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, + GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, + GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, + GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } + }, + { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { + 0, 0, 0, 0, + 0, 0, GP_6_25_DATA, GP_6_24_DATA, + GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA, + GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA, + GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA, + GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA, + GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, + GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } + }, + { }, +}; + +static struct pinmux_info r8a7794_pinmux_info = { + .name = "r8a7794_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_FN_AD_CLK_B, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7794_pinmux_init(void) +{ + register_pinmux(&r8a7794_pinmux_info); +} diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h index 560e9f42d9..d25ea61e26 100644 --- a/arch/arm/include/asm/arch-rmobile/gpio.h +++ b/arch/arm/include/asm/arch-rmobile/gpio.h @@ -13,6 +13,9 @@ void r8a7790_pinmux_init(void); #elif defined(CONFIG_R8A7791) #include "r8a7791-gpio.h" void r8a7791_pinmux_init(void); +#elif defined(CONFIG_R8A7794) +#include "r8a7794-gpio.h" +void r8a7794_pinmux_init(void); #endif #endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h new file mode 100644 index 0000000000..a45a67c4d6 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h @@ -0,0 +1,176 @@ +#ifndef __ASM_R8A7794_H__ +#define __ASM_R8A7794_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23, + GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27, + GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19, + GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23, + GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27, + GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27, + GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15, + GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19, + GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23, + GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27, + + GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3, + GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7, + GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11, + GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15, + GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19, + GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23, + GPIO_GP_6_24, GPIO_GP_6_25, + + GPIO_FN_A2, GPIO_FN_WE0_N, GPIO_FN_WE1_N, GPIO_FN_DACK0, + GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN, + GPIO_FN_USB1_OVC, GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, + GPIO_FN_SD0_DATA0, GPIO_FN_SD0_DATA1, GPIO_FN_SD0_DATA2, + GPIO_FN_SD0_DATA3, GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, + GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0, + GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3, + + /* + * From IPSR0 to IPSR5 have been removed because they does not use. + */ + + /* IPSR6 */ + GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE, GPIO_FN_CC50_STATE28, + GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE, + GPIO_FN_CC50_STATE29, GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, + GPIO_FN_CC50_STATE30, GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, + GPIO_FN_CC50_STATE31, GPIO_FN_VI0_CLK, GPIO_FN_AVB_RX_CLK, + GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_AVB_RX_DV, GPIO_FN_VI0_DATA1_VI0_B1, + GPIO_FN_AVB_RXD0, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_AVB_RXD1, + GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_AVB_RXD2, GPIO_FN_VI0_DATA4_VI0_B4, + GPIO_FN_AVB_RXD3, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_AVB_RXD4, + GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA7_VI0_B7, + GPIO_FN_AVB_RXD6, GPIO_FN_VI0_CLKENB, GPIO_FN_I2C3_SCL, + GPIO_FN_SCIFA5_RXD_C, GPIO_FN_IETX_C, GPIO_FN_AVB_RXD7, + GPIO_FN_VI0_FIELD, GPIO_FN_I2C3_SDA, GPIO_FN_SCIFA5_TXD_C, + GPIO_FN_IECLK_C, GPIO_FN_AVB_RX_ER, GPIO_FN_VI0_HSYNC_N, + GPIO_FN_SCIF0_RXD_B, GPIO_FN_I2C0_SCL_C, GPIO_FN_IERX_C, + GPIO_FN_AVB_COL, GPIO_FN_VI0_VSYNC_N, GPIO_FN_SCIF0_TXD_B, + GPIO_FN_I2C0_SDA_C, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_AVB_TX_EN, + GPIO_FN_ETH_MDIO, GPIO_FN_VI0_G0, GPIO_FN_MSIOF2_RXD_B, + GPIO_FN_IIC0_SCL_D, GPIO_FN_AVB_TX_CLK, GPIO_FN_ADIDATA, GPIO_FN_AD_DI, + + /* IPSR7 */ + GPIO_FN_ETH_CRS_DV, GPIO_FN_VI0_G1, GPIO_FN_MSIOF2_TXD_B, + GPIO_FN_IIC0_SDA_D, GPIO_FN_AVB_TXD0, GPIO_FN_ADICS_SAMP, GPIO_FN_AD_DO, + GPIO_FN_ETH_RX_ER, GPIO_FN_VI0_G2, GPIO_FN_MSIOF2_SCK_B, + GPIO_FN_CAN0_RX_B, GPIO_FN_AVB_TXD1, GPIO_FN_ADICLK, GPIO_FN_AD_CLK, + GPIO_FN_ETH_RXD0, GPIO_FN_VI0_G3, GPIO_FN_MSIOF2_SYNC_B, + GPIO_FN_CAN0_TX_B, GPIO_FN_AVB_TXD2, GPIO_FN_ADICHS0, GPIO_FN_AD_NCS_N, + GPIO_FN_ETH_RXD1, GPIO_FN_VI0_G4, GPIO_FN_MSIOF2_SS1_B, + GPIO_FN_SCIF4_RXD_D, GPIO_FN_AVB_TXD3, GPIO_FN_ADICHS1, + GPIO_FN_ETH_LINK, GPIO_FN_VI0_G5, GPIO_FN_MSIOF2_SS2_B, + GPIO_FN_SCIF4_TXD_D, GPIO_FN_AVB_TXD4, GPIO_FN_ADICHS2, + GPIO_FN_ETH_REFCLK, GPIO_FN_VI0_G6, GPIO_FN_SCIF2_SCK_C, + GPIO_FN_AVB_TXD5, GPIO_FN_SSI_SCK5_B, GPIO_FN_ETH_TXD1, GPIO_FN_VI0_G7, + GPIO_FN_SCIF2_RXD_C, GPIO_FN_IIC1_SCL_D, GPIO_FN_AVB_TXD6, + GPIO_FN_SSI_WS5_B, GPIO_FN_ETH_TX_EN, GPIO_FN_VI0_R0, + GPIO_FN_SCIF2_TXD_C, GPIO_FN_IIC1_SDA_D, GPIO_FN_AVB_TXD7, + GPIO_FN_SSI_SDATA5_B, GPIO_FN_ETH_MAGIC, GPIO_FN_VI0_R1, + GPIO_FN_SCIF3_SCK_B, GPIO_FN_AVB_TX_ER, GPIO_FN_SSI_SCK6_B, + GPIO_FN_ETH_TXD0, GPIO_FN_VI0_R2, GPIO_FN_SCIF3_RXD_B, + GPIO_FN_I2C4_SCL_E, GPIO_FN_AVB_GTX_CLK, GPIO_FN_SSI_WS6_B, + GPIO_FN_DREQ0_N, GPIO_FN_SCIFB1_RXD, + + /* IPSR8 */ + GPIO_FN_ETH_MDC, GPIO_FN_VI0_R3, GPIO_FN_SCIF3_TXD_B, + GPIO_FN_I2C4_SDA_E, GPIO_FN_AVB_MDC, GPIO_FN_SSI_SDATA6_B, + GPIO_FN_HSCIF0_HRX, GPIO_FN_VI0_R4, GPIO_FN_I2C1_SCL_C, + GPIO_FN_AUDIO_CLKA_B, GPIO_FN_AVB_MDIO, GPIO_FN_SSI_SCK78_B, + GPIO_FN_HSCIF0_HTX, GPIO_FN_VI0_R5, GPIO_FN_I2C1_SDA_C, + GPIO_FN_AUDIO_CLKB_B, GPIO_FN_AVB_LINK, GPIO_FN_SSI_WS78_B, + GPIO_FN_HSCIF0_HCTS_N, GPIO_FN_VI0_R6, GPIO_FN_SCIF0_RXD_D, + GPIO_FN_I2C0_SCL_E, GPIO_FN_AVB_MAGIC, GPIO_FN_SSI_SDATA7_B, + GPIO_FN_HSCIF0_HRTS_N, GPIO_FN_VI0_R7, GPIO_FN_SCIF0_TXD_D, + GPIO_FN_I2C0_SDA_E, GPIO_FN_AVB_PHY_INT, GPIO_FN_SSI_SDATA8_B, + GPIO_FN_HSCIF0_HSCK, GPIO_FN_SCIF_CLK_B, GPIO_FN_AVB_CRS, + GPIO_FN_AUDIO_CLKC_B, GPIO_FN_I2C0_SCL, GPIO_FN_SCIF0_RXD_C, + GPIO_FN_PWM5, GPIO_FN_TCLK1_B, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN1_RX_D, + GPIO_FN_TPUTO0_B, GPIO_FN_I2C0_SDA, GPIO_FN_SCIF0_TXD_C, GPIO_FN_TPUTO0, + GPIO_FN_CAN_CLK, GPIO_FN_DVC_MUTE, GPIO_FN_CAN1_TX_D, GPIO_FN_I2C1_SCL, + GPIO_FN_SCIF4_RXD, GPIO_FN_PWM5_B, GPIO_FN_DU1_DR0, GPIO_FN_RIF1_SYNC_B, + GPIO_FN_TS_SDATA_D, GPIO_FN_TPUTO1_B, GPIO_FN_I2C1_SDA, + GPIO_FN_SCIF4_TXD, GPIO_FN_IRQ5, GPIO_FN_DU1_DR1, GPIO_FN_RIF1_CLK_B, + GPIO_FN_TS_SCK_D, GPIO_FN_BPFCLK_C, GPIO_FN_MSIOF0_RXD, + GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2, + GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK, + + /* + * From IPSR9 to IPSR10 have been removed because they does not use. + */ + + /* IPSR11 */ + GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C, + GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5, + GPIO_FN_SCIFA3_TXD, GPIO_FN_I2C3_SDA_C, GPIO_FN_DU1_DOTCLKOUT1, + GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SCK6, GPIO_FN_SCIFA1_SCK_B, + GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_SSI_WS6, + GPIO_FN_SCIFA1_RXD_B, GPIO_FN_I2C4_SCL_C, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, + GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_SDATA6, GPIO_FN_SCIFA1_TXD_B, + GPIO_FN_I2C4_SDA_C, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + GPIO_FN_CAN_DEBUGOUT15, GPIO_FN_SSI_SCK78, GPIO_FN_SCIFA2_SCK_B, + GPIO_FN_IIC0_SDA_C, GPIO_FN_DU1_DISP, GPIO_FN_SSI_WS78, + GPIO_FN_SCIFA2_RXD_B, GPIO_FN_IIC0_SCL_C, GPIO_FN_DU1_CDE, + GPIO_FN_SSI_SDATA7, GPIO_FN_SCIFA2_TXD_B, GPIO_FN_IRQ8, + GPIO_FN_AUDIO_CLKA_D, GPIO_FN_CAN_CLK_D, GPIO_FN_PCMOE_N, + GPIO_FN_SSI_SCK0129, GPIO_FN_MSIOF1_RXD_B, GPIO_FN_SCIF5_RXD_D, + GPIO_FN_ADIDATA_B, GPIO_FN_AD_DI_B, GPIO_FN_PCMWE_N, GPIO_FN_SSI_WS0129, + GPIO_FN_MSIOF1_TXD_B, GPIO_FN_SCIF5_TXD_D, GPIO_FN_ADICS_SAMP_B, + GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B, + GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B, + + /* + * From IPSR12 to IPSR13 have been removed because they does not use. + */ +}; + +#endif /* __ASM_R8A7794_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h new file mode 100644 index 0000000000..94276ddc75 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h @@ -0,0 +1,14 @@ +/* + * arch/arm/include/asm/arch-rmobile/r8a7794.h + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 +*/ + +#ifndef __ASM_ARCH_R8A7794_H +#define __ASM_ARCH_R8A7794_H + +#include "rcar-base.h" + +#endif /* __ASM_ARCH_R8A7794_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index 41240f3320..027e9b1b14 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -10,7 +10,7 @@ #define __ASM_ARCH_RCAR_BASE_H /* - * R-Car (R8A7790/R8A7791) I/O Addresses + * R-Car (R8A7790/R8A7791/R8A7794) I/O Addresses */ #define RWDT_BASE 0xE6020000 #define SWDT_BASE 0xE6030000 @@ -116,7 +116,7 @@ #define SYS_AXI_SAT1_BASE 0xFF8009C0 #define SYS_AXI_SDM0_BASE 0xFF800A00 #define SYS_AXI_SDM1_BASE 0xFF800A40 -#define SYS_AXI_TRAB_BASE 0xFF800B00 +#define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */ #define SYS_AXI_UDM0_BASE 0xFF800B80 #define SYS_AXI_UDM1_BASE 0xFF800BC0 diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h index ebddd7a8fe..2cc38e1b5b 100644 --- a/arch/arm/include/asm/arch-rmobile/rmobile.h +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -10,6 +10,8 @@ #include #elif defined(CONFIG_R8A7791) #include +#elif defined(CONFIG_R8A7794) +#include #else #error "SOC Name not defined" #endif -- cgit v1.2.1 From cff2f5f09ee8ab45b86eed7228bacbce6eca9f01 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 26 Jun 2014 10:23:30 +0900 Subject: arm: rmobile: Add support Alt board The alt board has R8A7794, 1GB DDR3-SDRAM, USB, Ethernet, QSPI, MMC, SDHI and more. This commit supports the following functions: - DDR3-SDRAM - SCIF - I2C - Ethernet - QSPI Signed-off-by: Hisashi Nakamura Signed-off-by: Nobuhiro Iwamatsu --- board/renesas/alt/Makefile | 9 + board/renesas/alt/alt.c | 173 +++++++++ board/renesas/alt/qos.c | 944 +++++++++++++++++++++++++++++++++++++++++++++ board/renesas/alt/qos.h | 12 + boards.cfg | 1 + include/configs/alt.h | 166 ++++++++ 6 files changed, 1305 insertions(+) create mode 100644 board/renesas/alt/Makefile create mode 100644 board/renesas/alt/alt.c create mode 100644 board/renesas/alt/qos.c create mode 100644 board/renesas/alt/qos.h create mode 100644 include/configs/alt.h diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile new file mode 100644 index 0000000000..9ed12bd87d --- /dev/null +++ b/board/renesas/alt/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/alt/Makefile +# +# Copyright (C) 2014 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := alt.o qos.o diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c new file mode 100644 index 0000000000..9d8e8f96be --- /dev/null +++ b/board/renesas/alt/alt.c @@ -0,0 +1,173 @@ +/* + * board/renesas/alt/alt.c + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* QoS */ + qos_init(); +} + +#define MSTPSR1 0xE6150038 +#define SMSTPCR1 0xE6150134 +#define TMU0_MSTP125 (1 << 25) + +#define MSTPSR7 0xE61501C4 +#define SMSTPCR7 0xE615014C +#define SCIF0_MSTP719 (1 << 19) + +#define MSTPSR8 0xE61509A0 +#define SMSTPCR8 0xE6150990 +#define ETHER_MSTP813 (1 << 13) + +#define mstp_setbits(type, addr, saddr, set) \ + out_##type((saddr), in_##type(addr) | (set)) +#define mstp_clrbits(type, addr, saddr, clear) \ + out_##type((saddr), in_##type(addr) & ~(clear)) +#define mstp_setbits_le32(addr, saddr, set) \ + mstp_setbits(le32, addr, saddr, set) +#define mstp_clrbits_le32(addr, saddr, clear) \ + mstp_clrbits(le32, addr, saddr, clear) + +int board_early_init_f(void) +{ + /* TMU */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + return 0; +} + +void arch_preboot_os(void) +{ + /* Disable TMU0 */ + mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7794_pinmux_init(); + + /* Ether Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ8, NULL); + + /* PHY reset */ + gpio_request(GPIO_GP_1_24, NULL); + gpio_direction_output(GPIO_GP_1_24, 0); + mdelay(20); + gpio_set_value(GPIO_GP_1_24, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = ALT_SDRAM_BASE; + gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE; +} + +int board_late_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(1); /* PowerIC connected to ch3 */ + i2c_init(400000, 0); + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c new file mode 100644 index 0000000000..ea51f3f532 --- /dev/null +++ b/board/renesas/alt/qos.c @@ -0,0 +1,944 @@ +/* + * board/renesas/alt/qos.c + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include +#include +#include +#include +#include + +/* QoS version 0.10 */ + +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x1F0D0B0A, &s3c->s3crorr); + writel(0x1F0D0B09, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x0000202A, &qos_addr->dbtmval2); + writel(0x00001FBD, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x00002043, &qos_addr->dbtmval2); + writel(0x00002030, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002031, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20001000, CCI_400_MAXOT_1); + writel(0x20001000, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} diff --git a/board/renesas/alt/qos.h b/board/renesas/alt/qos.h new file mode 100644 index 0000000000..9a6c0461be --- /dev/null +++ b/board/renesas/alt/qos.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2013 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/boards.cfg b/boards.cfg index 6f8d168cf1..82b3291e10 100644 --- a/boards.cfg +++ b/boards.cfg @@ -372,6 +372,7 @@ Active arm armv7 omap5 ti dra7xx Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu :Tetsuyuki Kobayashi +Active arm armv7 rmobile renesas alt alt - Nobuhiro Iwamatsu Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga diff --git a/include/configs/alt.h b/include/configs/alt.h new file mode 100644 index 0000000000..9eec4bc231 --- /dev/null +++ b/include/configs/alt.h @@ -0,0 +1,166 @@ +/* + * include/configs/alt.h + * This file is alt board configuration. + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ALT_H +#define __ALT_H + +#undef DEBUG +#define CONFIG_ARMV7 +#define CONFIG_R8A7794 +#define CONFIG_RMOBILE +#define CONFIG_RMOBILE_BOARD_STRING "Alt" +#define CONFIG_SH_GPIO_PFC + +#include + +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_RUN +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#define CONFIG_SYS_THUMB_BUILD +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_OF_LIBFDT +#define BOARD_LATE_INIT + +#define CONFIG_BAUDRATE 38400 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_TMU_TIMER + +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define ALT_SDRAM_BASE 0x40000000 +#define ALT_SDRAM_SIZE (1024u * 1024 * 1024) +#define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE 512 +#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF2 +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +#define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ + 504 * 1024 * 1024) +#undef CONFIG_SYS_ALT_MEMTEST +#undef CONFIG_SYS_MEMTEST_SCRATCH +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +#define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE) +#define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0) +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_ADDR 0xC0000 +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_low=0x40e00000\0" \ + "bootm_size=0x100000\0" \ + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +#endif /* __ALT_H */ -- cgit v1.2.1 From 7a0227534dfc17c96bb02529fb69971d079a85f0 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 22 May 2014 14:37:10 +0530 Subject: drivers: net: cpsw: add support for using second port as ethernet Add support for using the second slave port of cpsw to be used as primary ethernet. Signed-off-by: Mugunthan V N --- drivers/net/cpsw.c | 8 +++++--- include/cpsw.h | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index bd5fba21ce..8ec5161ec6 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -211,6 +211,8 @@ struct cpdma_chan { #define chan_read(chan, fld) __raw_readl((chan)->fld) #define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) +#define for_active_slave(slave, priv) \ + slave = (priv)->slaves + (priv)->data.active_slave; if (slave) #define for_each_slave(slave, priv) \ for (slave = (priv)->slaves; slave != (priv)->slaves + \ (priv)->data.slaves; slave++) @@ -609,7 +611,7 @@ static int cpsw_update_link(struct cpsw_priv *priv) int link = 0; struct cpsw_slave *slave; - for_each_slave(slave, priv) + for_active_slave(slave, priv) cpsw_slave_update_link(slave, priv, &link); priv->mdio_link = readl(&mdio_regs->link); return link; @@ -785,7 +787,7 @@ static int cpsw_init(struct eth_device *dev, bd_t *bis) ALE_SECURE); cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << priv->host_port); - for_each_slave(slave, priv) + for_active_slave(slave, priv) cpsw_slave_init(slave, priv); cpsw_update_link(priv); @@ -1013,7 +1015,7 @@ int cpsw_register(struct cpsw_platform_data *data) cpsw_mdio_init(dev->name, data->mdio_base, data->mdio_div); priv->bus = miiphy_get_dev_by_name(dev->name); - for_each_slave(slave, priv) + for_active_slave(slave, priv) cpsw_phy_init(dev, slave); return 1; diff --git a/include/cpsw.h b/include/cpsw.h index a73843d2f7..547b40c57b 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -44,6 +44,7 @@ struct cpsw_platform_data { struct cpsw_slave_data *slave_data; void (*control)(int enabled); u32 host_port_num; + u32 active_slave; u8 version; }; -- cgit v1.2.1 From e5ff845bff6dfc6e4d1d8b75fb817a8bc7635b2f Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 22 May 2014 14:37:11 +0530 Subject: ARM: DRA7xx: Add cpsw second port pinmux Add cpsw second slave port pinmux to use it as primary ethernet port Signed-off-by: Mugunthan V N --- board/ti/dra7xx/mux_data.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 38de9d5a8b..56cda07ed7 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -51,6 +51,18 @@ const struct pad_conf_entry core_padconf_array_essential[] = { {RGMII0_RXD2, (IEN | M0) }, {RGMII0_RXD1, (IEN | M0) }, {RGMII0_RXD0, (IEN | M0) }, + {VIN2A_D12, (M3) }, + {VIN2A_D13, (M3) }, + {VIN2A_D14, (M3) }, + {VIN2A_D15, (M3) }, + {VIN2A_D16, (M3) }, + {VIN2A_D17, (M3) }, + {VIN2A_D18, (IEN | M3)}, + {VIN2A_D19, (IEN | M3)}, + {VIN2A_D20, (IEN | M3)}, + {VIN2A_D21, (IEN | M3)}, + {VIN2A_D22, (IEN | M3)}, + {VIN2A_D23, (IEN | M3)}, {GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */ {GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */ {GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */ -- cgit v1.2.1 From 4c8014b9429b593c28fbf0384a6c7ded8587806a Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Thu, 22 May 2014 14:37:12 +0530 Subject: ARM: dra7_evm: Add Ethernet support for dra72x platform Set the active_slave to 1 as slave 1 is pinned out in dra72x base board Signed-off-by: Mugunthan V N --- board/ti/dra7xx/evm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 073d15127c..955c16fe74 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -157,6 +157,8 @@ int spl_start_uboot(void) #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) +extern u32 *const omap_si_rev; + static void cpsw_control(int enabled) { /* VTP can be added here */ @@ -183,7 +185,7 @@ static struct cpsw_platform_data cpsw_data = { .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, - .slaves = 1, + .slaves = 2, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, @@ -254,6 +256,9 @@ int board_eth_init(bd_t *bis) ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); + if (*omap_si_rev == DRA722_ES1_0) + cpsw_data.active_slave = 1; + ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); -- cgit v1.2.1 From 5c44dd6bbd42775a93b9938510d398f0e26dbcc2 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Jun 2014 16:06:28 -0400 Subject: power/pmic.h: Add prototype for power_init_board. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As this is a weak function that we may override, provide a prototype for it. Cc: Łukasz Majewski Signed-off-by: Tom Rini --- include/power/pmic.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/power/pmic.h b/include/power/pmic.h index a62e6c90a5..afbc5aab7e 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -79,6 +79,7 @@ struct pmic { }; int pmic_init(unsigned char bus); +int power_init_board(void); int pmic_dialog_init(unsigned char bus); int check_reg(struct pmic *p, u32 reg); struct pmic *pmic_alloc(void); -- cgit v1.2.1 From 7aa5598aac3faf9188559f7a50940df11c30b656 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 23 Jun 2014 16:06:29 -0400 Subject: tps65218/am43xx_evm: Add power framework support to TPS65218 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add in an init function for the drivers/power framework so we can dump and read the registers via i2c. Cc: Łukasz Majewski Signed-off-by: Tom Rini --- board/ti/am43xx/board.c | 14 ++++++++++++++ drivers/power/pmic/pmic_tps65218.c | 22 ++++++++++++++++++++++ include/configs/am43xx_evm.h | 2 ++ include/power/tps65218.h | 1 + 4 files changed, 39 insertions(+) diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 054a452eac..f6577769e7 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -19,6 +19,7 @@ #include #include #include "board.h" +#include #include #include #include @@ -484,6 +485,19 @@ void sdram_init(void) } #endif +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS65218\n"); + + return 0; +} + int board_init(void) { gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c index 0952456379..dbc7a73a72 100644 --- a/drivers/power/pmic/pmic_tps65218.c +++ b/drivers/power/pmic/pmic_tps65218.c @@ -7,6 +7,8 @@ #include #include +#include +#include #include /** @@ -95,3 +97,23 @@ int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel) return 0; } + +int power_tps65218_init(unsigned char bus) +{ + static const char name[] = "TPS65218_PMIC"; + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = name; + p->interface = PMIC_I2C; + p->number_of_regs = TPS65218_PMIC_NUM_OF_REGS; + p->hw.i2c.addr = TPS65218_CHIP_PM; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + return 0; +} diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 974ce986e9..e26204025f 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -33,6 +33,8 @@ #define CONFIG_SYS_I2C_MULTI_EEPROMS /* Power */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C #define CONFIG_POWER_TPS65218 /* SPL defines. */ diff --git a/include/power/tps65218.h b/include/power/tps65218.h index 67aa2f8c8d..f8f33b8b16 100644 --- a/include/power/tps65218.h +++ b/include/power/tps65218.h @@ -60,4 +60,5 @@ enum { int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, uchar mask); int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); +int power_tps65218_init(unsigned char bus); #endif /* __POWER_TPS65218_H__ */ -- cgit v1.2.1 From 67ac6ffaeefb93ff294f976cbb03479f84aa0b1a Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 4 Jul 2014 15:03:25 +0300 Subject: mtd: nand: davinci: add opportunity to write keystone U-boot image The Keystone SoCs use the same NAND driver as Davinci. This patch adds opportunity to write Keystone U-boot image to NAND device using appropriate RBL ECC layout. This is needed only if RBL boots U-boot from NAND device and that's supposed that raw u-boot partition is used only for writing image. The main problem is that default Davinci ECC layout is different from Keystone RBL layout. To read U-boot image the RBL needs that image was written using RBL ECC layout. The BBT table is written using default Davinci layout and has to be updated using one. The BBT can be updated only while erasing chip or by forced bad block assigning, so erase function has to use native ecc layout in order to be able to write BBT correctly. So if we're writing to NAND U-boot address we use RBL layout for others we use default ECC layout. Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no reasons to use ECC layout commands. It was added by mistake. Signed-off-by: Ivan Khoronzhuk --- drivers/mtd/nand/davinci_nand.c | 196 ++++++++++++++++++++++++++++++++++++++++ include/configs/k2hk_evm.h | 4 +- 2 files changed, 199 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index 5d425092f4..a079b1e5cf 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -305,6 +305,189 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { #endif }; +#if defined CONFIG_KEYSTONE_RBL_NAND +#if defined(CONFIG_SYS_NAND_PAGE_2K) +static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = { + .eccbytes = 40, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {.offset = 2, .length = 4, }, + {.offset = 16, .length = 6, }, + {.offset = 32, .length = 6, }, + {.offset = 48, .length = 6, }, + }, +#elif defined(CONFIG_SYS_NAND_PAGE_4K) + .eccbytes = 80, + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, + 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, + 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, + }, + .oobfree = { + {.offset = 2, .length = 4, }, + {.offset = 16, .length = 6, }, + {.offset = 32, .length = 6, }, + {.offset = 48, .length = 6, }, + {.offset = 64, .length = 6, }, + {.offset = 80, .length = 6, }, + {.offset = 96, .length = 6, }, + {.offset = 112, .length = 6, }, + }, +#endif +}; + +#ifdef CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 +#elif defined(CONFIG_SYS_NAND_PAGE_4K) +#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 +#endif + +/** + * nand_davinci_write_page - write one page + * @mtd: MTD device structure + * @chip: NAND chip descriptor + * @buf: the data to write + * @oob_required: must write chip->oob_poi to OOB + * @page: page number to write + * @cached: cached programming + * @raw: use _raw version of write_page + */ +static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required, + int page, int cached, int raw) +{ + int status; + int ret = 0; + struct nand_ecclayout *saved_ecc_layout; + + /* save current ECC layout and assign Keystone RBL ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + saved_ecc_layout = chip->ecc.layout; + chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; + mtd->oobavail = chip->ecc.layout->oobavail; + } + + chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); + + if (unlikely(raw)) + status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required); + else + status = chip->ecc.write_page(mtd, chip, buf, oob_required); + + if (status < 0) { + ret = status; + goto err; + } + + chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); + status = chip->waitfunc(mtd, chip); + + /* + * See if operation failed and additional status checks are + * available. + */ + if ((status & NAND_STATUS_FAIL) && (chip->errstat)) + status = chip->errstat(mtd, chip, FL_WRITING, status, page); + + if (status & NAND_STATUS_FAIL) { + ret = -EIO; + goto err; + } + +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE + /* Send command to read back the data */ + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + if (chip->verify_buf(mtd, buf, mtd->writesize)) { + ret = -EIO; + goto err; + } + + /* Make sure the next page prog is preceded by a status read */ + chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); +#endif +err: + /* restore ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = saved_ecc_layout; + mtd->oobavail = saved_ecc_layout->oobavail; + } + + return ret; +} + +/** + * nand_davinci_read_page_hwecc - hardware ECC based page read function + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @oob_required: caller requires OOB data read to chip->oob_poi + * @page: page number to read + * + * Not for syndrome calculating ECC controllers which need a special oob layout. + */ +static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + int i, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint32_t *eccpos; + uint8_t *p = buf; + uint8_t *ecc_code = chip->buffers->ecccode; + uint8_t *ecc_calc = chip->buffers->ecccalc; + struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; + + /* save current ECC layout and assign Keystone RBL ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; + mtd->oobavail = chip->ecc.layout->oobavail; + } + + eccpos = chip->ecc.layout->eccpos; + + /* Read the OOB area first */ + chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + + for (i = 0; i < chip->ecc.total; i++) + ecc_code[i] = chip->oob_poi[eccpos[i]]; + + for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { + int stat; + + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + + /* restore ECC layout */ + if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + chip->ecc.layout = saved_ecc_layout; + mtd->oobavail = saved_ecc_layout->oobavail; + } + + return 0; +} +#endif /* CONFIG_KEYSTONE_RBL_NAND */ + static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) { u32 val; @@ -604,6 +787,19 @@ static void nand_flash_init(void) void davinci_nand_init(struct nand_chip *nand) { +#if defined CONFIG_KEYSTONE_RBL_NAND + int i; + struct nand_ecclayout *layout; + + layout = &nand_keystone_rbl_4bit_layout_oobfirst; + layout->oobavail = 0; + for (i = 0; layout->oobfree[i].length && + i < ARRAY_SIZE(layout->oobfree); i++) + layout->oobavail += layout->oobfree[i].length; + + nand->write_page = nand_davinci_write_page; + nand->ecc.read_page = nand_davinci_read_page_hwecc; +#endif nand->chip_delay = 0; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT nand->bbt_options |= NAND_BBT_USE_FLASH; diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 858329f958..3f877418cd 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -135,7 +135,8 @@ /* NAND Configuration */ #define CONFIG_NAND_DAVINCI -#define CONFIG_CMD_NAND_ECCLAYOUT +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET #define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST @@ -155,6 +156,7 @@ #define CONFIG_MTD_DEVICE #define CONFIG_RBTREE #define CONFIG_LZO +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" #define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ "1024k(bootloader)ro,512k(params)ro," \ "-(ubifs)" -- cgit v1.2.1 From 0e7f2dbac6ead25798f81c9f6d5f80b7666916f6 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 4 Jul 2014 15:03:26 +0300 Subject: keystone: add support for NAND gpheader image Add support for NAND gpheader image. TI Keystone2 ROM bootloader expects 8 bytes of trailing zeroes in the nand u-boot image. So add zeros at the end of the nand gph image. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Makefile b/Makefile index 686cab1460..76533135f2 100644 --- a/Makefile +++ b/Makefile @@ -914,6 +914,12 @@ OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_u-boot-nand.gph = -A $(ARCH) -T gpimage -C none \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot +u-boot-nand.gph: u-boot.bin FORCE + $(call if_changed,mkimage) + @dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@ + ifneq ($(CONFIG_SUNXI),) OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff -- cgit v1.2.1 From c6ac7e3bdc195a7dd39b5bf699deceedb9444c0c Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 4 Jul 2014 15:03:27 +0300 Subject: k2hk_evm: add script to automate NAND flash process Add script to automate NAND flash process. As for now the board has two burn scripts - burn to boot from SPI NOR flash and burn to boot from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi. Also update README to contain NAND burn U-boot process description. Signed-off-by: Ivan Khoronzhuk Acked-by: Murali Karicheri --- board/ti/k2hk_evm/README | 28 +++++++++++++++++++++++++++- include/configs/k2hk_evm.h | 4 +++- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README index bfeb05b4a4..7426b8dc97 100644 --- a/board/ti/k2hk_evm/README +++ b/board/ti/k2hk_evm/README @@ -38,11 +38,13 @@ board configuration file: include/configs/k2hk_evm.h Supported boot modes: - SPI NOR boot + - AEMIF NAND boot Supported image formats:- - u-boot.bin: for loading and running u-boot.bin through Texas instruments code composure studio (CCS) - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot Build instructions: =================== @@ -55,6 +57,10 @@ To build u-boot-spi.gph >make k2hk_evm_config >make u-boot-spi.gph +To build u-boot-nand.gph + >make k2hk_evm_config + >make u-boot-nand.gph + Load and Run U-Boot on K2HK EVM using CCS ========================================= @@ -115,8 +121,28 @@ instructions:- 5. At the U-Boot console type following to setup u-boot environment variables. setenv addr_uboot 0x87000000 setenv filesize - run burn_uboot + run burn_uboot_spi Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch to "SPI Little Endian Boot mode" as per instruction at http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. 6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. + +AEMIF NAND Flash programming instructions +====================================== +U-Boot image can be flashed to first 1024KB of the NAND flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv filesize + run burn_uboot_nand + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "ARM NAND Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 3f877418cd..63e02495e1 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -221,8 +221,10 @@ "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ - "burn_uboot=sf probe; sf erase 0 0x100000; " \ + "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ "sf write ${addr_uboot} 0 ${filesize}\0" \ + "burn_uboot_nand=nand erase 0 0x100000; " \ + "nand write ${addr_uboot} 0 ${filesize}\0" \ "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ -- cgit v1.2.1 From c4f80f500356a8e0a71debe5bbe6e9a0d6d5d62e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 7 Jul 2014 21:40:16 -0400 Subject: am335x_evm / gumstix pepper: Correct DDR settings As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: Jeroen Hofstee Cc: Ash Charles Signed-off-by: Tom Rini Tested-By: Ash Charles --- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 ---- board/gumstix/pepper/board.c | 30 +++-------------------------- board/ti/am335x/board.c | 30 +++-------------------------- 3 files changed, 6 insertions(+), 58 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 4d899528f5..97bbfe2e65 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -33,11 +33,7 @@ #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a #define MT47H128M16RT25E_RATIO 0x80 -#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 -#define MT47H128M16RT25E_WR_DQS 0x00 -#define MT47H128M16RT25E_PHY_WRLVL 0x00 -#define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c index 75aac49fd0..f644f8188b 100644 --- a/board/gumstix/pepper/board.c +++ b/board/gumstix/pepper/board.c @@ -34,41 +34,17 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_SPL_BUILD static const struct ddr_data ddr2_data = { - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | - (MT47H128M16RT25E_RD_DQS<<20) | - (MT47H128M16RT25E_RD_DQS<<10) | - (MT47H128M16RT25E_RD_DQS<<0)), - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | - (MT47H128M16RT25E_WR_DQS<<20) | - (MT47H128M16RT25E_WR_DQS<<10) | - (MT47H128M16RT25E_WR_DQS<<0)), - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | - (MT47H128M16RT25E_PHY_WRLVL<<20) | - (MT47H128M16RT25E_PHY_WRLVL<<10) | - (MT47H128M16RT25E_PHY_WRLVL<<0)), - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | - (MT47H128M16RT25E_PHY_GATELVL<<20) | - (MT47H128M16RT25E_PHY_GATELVL<<10) | - (MT47H128M16RT25E_PHY_GATELVL<<0)), - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | - (MT47H128M16RT25E_PHY_WR_DATA<<20) | - (MT47H128M16RT25E_PHY_WR_DATA<<10) | - (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = { diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index da780edb89..d81eec90b4 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -84,41 +84,17 @@ static int read_eeprom(struct am335x_baseboard_id *header) #ifndef CONFIG_SKIP_LOWLEVEL_INIT static const struct ddr_data ddr2_data = { - .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | - (MT47H128M16RT25E_RD_DQS<<20) | - (MT47H128M16RT25E_RD_DQS<<10) | - (MT47H128M16RT25E_RD_DQS<<0)), - .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | - (MT47H128M16RT25E_WR_DQS<<20) | - (MT47H128M16RT25E_WR_DQS<<10) | - (MT47H128M16RT25E_WR_DQS<<0)), - .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | - (MT47H128M16RT25E_PHY_WRLVL<<20) | - (MT47H128M16RT25E_PHY_WRLVL<<10) | - (MT47H128M16RT25E_PHY_WRLVL<<0)), - .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | - (MT47H128M16RT25E_PHY_GATELVL<<20) | - (MT47H128M16RT25E_PHY_GATELVL<<10) | - (MT47H128M16RT25E_PHY_GATELVL<<0)), - .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | - (MT47H128M16RT25E_PHY_FIFO_WE<<20) | - (MT47H128M16RT25E_PHY_FIFO_WE<<10) | - (MT47H128M16RT25E_PHY_FIFO_WE<<0)), - .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | - (MT47H128M16RT25E_PHY_WR_DATA<<20) | - (MT47H128M16RT25E_PHY_WR_DATA<<10) | - (MT47H128M16RT25E_PHY_WR_DATA<<0)), + .datardsratio0 = MT47H128M16RT25E_RD_DQS, + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; static const struct emif_regs ddr2_emif_reg_data = { -- cgit v1.2.1 From e6f9d419c86d311b19c27ae12d2d7dd921c06058 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20Bie=C3=9Fmann?= Date: Wed, 9 Jul 2014 17:10:34 +0200 Subject: tricorder: convert to generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann Cc: Thomas Weber --- include/configs/tricorder.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 80985a2655..847e099512 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -35,6 +35,8 @@ #include /* get chip and board defs */ #include +#define CONFIG_SYS_GENERIC_BOARD + /* Display CPU and Board information */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v1.2.1 From fb2fcb798a524858780b7a8c7ea8a21d104c36b1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Jul 2014 17:18:09 +0200 Subject: ARM: omap: Fix GPMC init for OMAP3 platforms Commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform) broke NAND on OMAP3 based platforms. I noticed this while testing the latest 2014.07-rc version on the TAO3530 board. NAND detection did not work with this error message: NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC was not initialized for NAND at all. This patch now fixes this issue. Tested on TAO3530 board. Signed-off-by: Stefan Roese Cc: Pekon Gupta Cc: Tom Rini Acked-by: Pekon Gupta --- arch/arm/cpu/armv7/omap-common/mem-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index 5bc7e1f19b..ba26cd1fdb 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -89,7 +89,7 @@ void gpmc_init(void) }; u32 size = GPMC_SIZE_16M; u32 base = CONFIG_SYS_FLASH_BASE; -#elif defined(CONFIG_NAND) +#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) /* configure GPMC for NAND */ const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, -- cgit v1.2.1 From 6d3bbdb0e718aba1e63086d27392f36c81f338fe Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Jul 2014 17:18:10 +0200 Subject: ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c These functions have been merged into the common GPMC init code with this commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform). The file is not compiled any more. So remove it as well. Signed-off-by: Stefan Roese Cc: Pekon Gupta Cc: Tom Rini Acked-by: Pekon Gupta --- arch/arm/cpu/armv7/omap3/mem.c | 139 ----------------------------------------- 1 file changed, 139 deletions(-) delete mode 100644 arch/arm/cpu/armv7/omap3/mem.c diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c deleted file mode 100644 index 1832affa5b..0000000000 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, - * - * Author : - * Manikandan Pillai - * - * Initial Code from: - * Richard Woodruff - * Syed Mohammed Khasim - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -struct gpmc *gpmc_cfg; - -#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif /* CONFIG_CMD_NAND */ - -#if defined(CONFIG_CMD_ONENAND) -static const u32 gpmc_onenand[GPMC_MAX_REG] = { - ONENAND_GPMC_CONFIG1, - ONENAND_GPMC_CONFIG2, - ONENAND_GPMC_CONFIG3, - ONENAND_GPMC_CONFIG4, - ONENAND_GPMC_CONFIG5, - ONENAND_GPMC_CONFIG6, 0 -}; -#endif /* CONFIG_CMD_ONENAND */ - -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in guessing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(u32 cs) -{ - u32 val1, val2, addr; - u32 pattern = 0x12345678; - - addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); - - writel(0x0, addr + 0x400); /* clear pos A */ - writel(pattern, addr); /* pattern to pos B */ - writel(0x0, addr + 4); /* remove pattern off the bus */ - val1 = readl(addr + 0x400); /* get pos A value */ - val2 = readl(addr); /* get val2 */ - writel(0x0, addr + 0x400); /* clear pos A */ - - if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ - return 0; - else - return 1; -} - -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - - /* - * Enable the config. size is the CS size and goes in - * bits 11:8. We set bit 6 to enable this CS and the base - * address goes into bits 5:0. - */ - writel((size << 8) | (GPMC_CS_ENABLE << 6) | - ((base >> 24) & GPMC_BASEADDR_MASK), - &cs->config7); - sdelay(2000); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; -#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND) - const u32 *gpmc_config = NULL; - u32 base = 0; - u32 size = 0; -#endif - u32 config = 0; - - /* global settings */ - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - - config = readl(&gpmc_cfg->config); - config &= (~0xf00); - writel(config, &gpmc_cfg->config); - - /* - * Disable the GPMC0 config set by ROM code - * It conflicts with our MPDB (both at 0x08000000) - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - -#if defined(CONFIG_CMD_NAND) /* CS 0 */ - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif - -#if defined(CONFIG_CMD_ONENAND) - gpmc_config = gpmc_onenand; - base = PISMO1_ONEN_BASE; - size = PISMO1_ONEN_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif -} -- cgit v1.2.1 From 188948e884794a562fca5c2dcdcb6f2c03ea4e7b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Jul 2014 17:18:11 +0200 Subject: ARM: omap: tao3530: Convert to generic board Use generic board setup functions by defining CONFIG_SYS_GENERIC_BOARD. Signed-off-by: Stefan Roese Cc: Tom Rini --- include/configs/tao3530.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 1b0fee9a80..62613e1eaa 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -22,6 +22,7 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define MACH_TYPE_OMAP3_TAO3530 2836 -- cgit v1.2.1 From 04b7ce0773da133140f6f7ef70b37933eae36ad3 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 19:48:39 +0300 Subject: ARM: keystone2: psc: use common PSC base Use common keystone2 Power Sleep controller base address instead of directly deciding which keystone2 SoC is used in psc module. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/psc.c | 42 ++++++++++------------ arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 1 - arch/arm/include/asm/arch-keystone/hardware.h | 3 ++ 3 files changed, 22 insertions(+), 24 deletions(-) diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c index c844dc84d5..fa5422f2e8 100644 --- a/arch/arm/cpu/armv7/keystone/psc.c +++ b/arch/arm/cpu/armv7/keystone/psc.c @@ -16,10 +16,6 @@ #define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr)) #define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr)) -#ifdef CONFIG_SOC_K2HK -#define DEVICE_PSC_BASE K2HK_PSC_BASE -#endif - int psc_delay(void) { udelay(10); @@ -55,7 +51,7 @@ int psc_wait(u32 domain_num) retry = 0; do { - ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT); + ptstat = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PSTAT); ptstat = ptstat & (1 << domain_num); } while ((ptstat != 0) && ((retry += psc_delay()) < PSC_PTSTAT_TIMEOUT_LIMIT)); @@ -71,7 +67,7 @@ u32 psc_get_domain_num(u32 mod_num) u32 domain_num; /* Get the power domain associated with the module number */ - domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE + + domain_num = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); domain_num = PSC_REG_MDCFG_GET_PD(domain_num); @@ -106,7 +102,7 @@ int psc_set_state(u32 mod_num, u32 state) * Get the power domain associated with the module number, and reset * isolation functionality */ - v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num)); + v = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); domain_num = PSC_REG_MDCFG_GET_PD(v); reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v); @@ -123,24 +119,24 @@ int psc_set_state(u32 mod_num, u32 state) * change is made if the new state is power down. */ if (state == PSC_REG_VAL_MDCTL_NEXT_ON) { - pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + + pdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_ON); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num), pdctl); } /* Set the next state for the module to enabled/disabled */ - mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state); mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso); - DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); + DEVICE_REG32_W(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); /* Trigger the enable */ - ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD); + ptcmd = DEVICE_REG32_R(KS2_PSC_BASE + PSC_REG_PTCMD); ptcmd |= (u32)(1< Date: Wed, 9 Jul 2014 19:48:40 +0300 Subject: keystone: ddr3: add ddr3.h to hold ddr3 API It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/ddr3.c | 6 +-- arch/arm/include/asm/arch-keystone/ddr3.h | 55 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-keystone/hardware.h | 39 ------------------- board/ti/k2hk_evm/board.c | 3 +- board/ti/k2hk_evm/ddr3.c | 27 +++++++------ 5 files changed, 76 insertions(+), 54 deletions(-) create mode 100644 arch/arm/include/asm/arch-keystone/ddr3.h diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index 4875db76a3..bb16551eb2 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -7,10 +7,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include +#include -void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) { unsigned int tmp; @@ -57,7 +57,7 @@ void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) ; } -void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) { __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h new file mode 100644 index 0000000000..05b7e2920d --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -0,0 +1,55 @@ +/* + * DDR3 + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DDR3_H_ +#define _DDR3_H_ + +#include + +struct ddr3_phy_config { + unsigned int pllcr; + unsigned int pgcr1_mask; + unsigned int pgcr1_val; + unsigned int ptr0; + unsigned int ptr1; + unsigned int ptr2; + unsigned int ptr3; + unsigned int ptr4; + unsigned int dcr_mask; + unsigned int dcr_val; + unsigned int dtpr0; + unsigned int dtpr1; + unsigned int dtpr2; + unsigned int mr0; + unsigned int mr1; + unsigned int mr2; + unsigned int dtcr; + unsigned int pgcr2; + unsigned int zq0cr1; + unsigned int zq1cr1; + unsigned int zq2cr1; + unsigned int pir_v1; + unsigned int pir_v2; +}; + +struct ddr3_emif_config { + unsigned int sdcfg; + unsigned int sdtim1; + unsigned int sdtim2; + unsigned int sdtim3; + unsigned int sdtim4; + unsigned int zqcfg; + unsigned int sdrfc; +}; + +void ddr3_init(void); +void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); +void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 4e49143ec6..f8f986ca60 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -22,42 +22,6 @@ typedef volatile unsigned int dv_reg; typedef volatile unsigned int *dv_reg_p; -struct ddr3_phy_config { - unsigned int pllcr; - unsigned int pgcr1_mask; - unsigned int pgcr1_val; - unsigned int ptr0; - unsigned int ptr1; - unsigned int ptr2; - unsigned int ptr3; - unsigned int ptr4; - unsigned int dcr_mask; - unsigned int dcr_val; - unsigned int dtpr0; - unsigned int dtpr1; - unsigned int dtpr2; - unsigned int mr0; - unsigned int mr1; - unsigned int mr2; - unsigned int dtcr; - unsigned int pgcr2; - unsigned int zq0cr1; - unsigned int zq1cr1; - unsigned int zq2cr1; - unsigned int pir_v1; - unsigned int pir_v2; -}; - -struct ddr3_emif_config { - unsigned int sdcfg; - unsigned int sdtim1; - unsigned int sdtim2; - unsigned int sdtim3; - unsigned int sdtim4; - unsigned int zqcfg; - unsigned int sdrfc; -}; - #endif #define BIT(x) (1 << (x)) @@ -149,9 +113,6 @@ static inline int cpu_revision(void) void share_all_segments(int priv_id); int cpu_to_bus(u32 *ptr, u32 length); -void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); -void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); -void init_ddr3(void); void sdelay(unsigned long); #endif diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index ef90f9d821..f910ebe032 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -63,7 +64,7 @@ static struct pll_init_data pll_config[] = { int dram_init(void) { - init_ddr3(); + ddr3_init(); gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index 6092eb8fe3..0085f291b5 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -228,7 +229,7 @@ struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); -void init_ddr3(void) +void ddr3_init(void) { char dimm_name[32]; @@ -239,22 +240,26 @@ void init_ddr3(void) if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { init_pll(&ddr3a_400); if (cpu_revision() > 0) { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); } else { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_32); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); } } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { init_pll(&ddr3a_333); if (cpu_revision() > 0) { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_64); } else { - init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); - init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_32); } } else { printf("Unknown SO-DIMM. Cannot configure DDR3\n"); @@ -263,6 +268,6 @@ void init_ddr3(void) } init_pll(&ddr3b_333); - init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); - init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); + ddr3_init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); + ddr3_init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); } -- cgit v1.2.1 From 101eec50f021a354487a511dc1f72691404b2b48 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 19:48:41 +0300 Subject: keystone2: ddr: add DDR3 PHY configs updated for PG 2.0 Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/ddr3.c | 19 +++++++ arch/arm/include/asm/arch-keystone/ddr3.h | 1 + arch/arm/include/asm/arch-keystone/hardware.h | 2 + board/ti/k2hk_evm/ddr3.c | 80 ++++++++++++++++++++++++++- 4 files changed, 100 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index bb16551eb2..b711b810cb 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -8,6 +8,7 @@ */ #include +#include #include void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) @@ -67,3 +68,21 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); } + +void ddr3_reset_ddrphy(void) +{ + u32 tmp; + + /* Assert DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; + writel(tmp, K2HK_DDR3APLLCTL1); + + /* wait 10us to catch the reset */ + udelay(10); + + /* Release DDR3A PHY reset */ + tmp = readl(K2HK_DDR3APLLCTL1); + tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; + __raw_writel(tmp, K2HK_DDR3APLLCTL1); +} diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h index 05b7e2920d..4d229a25fa 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -49,6 +49,7 @@ struct ddr3_emif_config { }; void ddr3_init(void); +void ddr3_reset_ddrphy(void); void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index f8f986ca60..db2d36bfb6 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -80,6 +80,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3_PMCTL_OFFSET 0x38 #define KS2_DDR3_ZQCFG_OFFSET 0xC8 +#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 + #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index 0085f291b5..b604266837 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -188,6 +188,61 @@ static struct ddr3_phy_config ddr3phy_1333_64 = { .pir_v2 = 0x0000FF81ul, }; /******************************************************/ + +/* DDR PHY Configs Updated for PG 2.0 + * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ +static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + int get_dimm_params(char *dimm_name) { u8 spd_params[256]; @@ -240,7 +295,18 @@ void ddr3_init(void) if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { init_pll(&ddr3a_400); if (cpu_revision() > 0) { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1600_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1600_64A); + } + ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); @@ -253,7 +319,17 @@ void ddr3_init(void) } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { init_pll(&ddr3a_333); if (cpu_revision() > 0) { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1333_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + &ddr3phy_1333_64A); + } ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); } else { -- cgit v1.2.1 From 35c547c2bc59dd63cdf76f81abe26f68e9eaf7fb Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 19:48:42 +0300 Subject: ARM: keystone2: keystone_nav: make it dependent on keystone driver This driver is needed in case if keystone driver is used. Currently only keystone_net driver uses it. So to avoid redundant code compilation make the keystone_nav dependent on keystone net driver. It also leads to compilation errors for boards that does't use it. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index c4af252110..02ecf7e22c 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -10,7 +10,7 @@ obj-y += psc.o obj-y += clock.o obj-y += cmd_clock.o obj-y += cmd_mon.o -obj-y += keystone_nav.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o obj-y += msmc.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-y += ddr3.o -- cgit v1.2.1 From 4984bce41fe78da160ccdad573b09b40e277ec7a Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 19:48:43 +0300 Subject: keystone2: move cpu_to_bus() to keystone.c The SoC related common functions in board.c should be placed to a common keystone.c arch file. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Makefile | 1 + arch/arm/cpu/armv7/keystone/keystone.c | 28 ++++++++++++++++++++++++++++ board/ti/k2hk_evm/board.c | 14 -------------- 3 files changed, 29 insertions(+), 14 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/keystone.c diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index 02ecf7e22c..64e42a6e23 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o obj-y += msmc.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-y += ddr3.o +obj-y += keystone.o diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c new file mode 100644 index 0000000000..48c869064e --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/keystone.c @@ -0,0 +1,28 @@ +/* + * Keystone EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +/** + * cpu_to_bus - swap bytes of the 32-bit data if the device is BE + * @ptr - array of data + * @length - lenght of data array + */ +int cpu_to_bus(u32 *ptr, u32 length) +{ + u32 i; + + if (!(readl(K2HK_DEVSTAT) & 0x1)) + for (i = 0; i < length; i++, ptr++) + *ptr = cpu_to_be32(*ptr); + + return 0; +} diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index f910ebe032..3333eb067c 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -23,8 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -u32 device_big_endian; - unsigned int external_clk[ext_clk_count] = { [sys_clk] = 122880000, [alt_core_clk] = 125000000, @@ -136,18 +134,6 @@ int board_eth_init(bd_t *bis) } #endif -/* Byte swap the 32-bit data if the device is BE */ -int cpu_to_bus(u32 *ptr, u32 length) -{ - u32 i; - - if (device_big_endian) - for (i = 0; i < length; i++, ptr++) - *ptr = __swab32(*ptr); - - return 0; -} - #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { -- cgit v1.2.1 From 7b26c1f608d3ef18b11ff0a07476155af4a6ab95 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 19:48:44 +0300 Subject: keystone2: add possibility to turn off all dsps By default all DSPs are turned off, for another case option to turn off them is added in this commit. Also add command to turn off itself. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/keystone.c | 59 ++++++++++++++++++++++ arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 5 +- arch/arm/include/asm/arch-keystone/hardware.h | 6 +++ arch/arm/include/asm/arch-keystone/mon.h | 15 ++++++ 4 files changed, 83 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-keystone/mon.h diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c index 48c869064e..1c8c038455 100644 --- a/arch/arm/cpu/armv7/keystone/keystone.c +++ b/arch/arm/cpu/armv7/keystone/keystone.c @@ -9,6 +9,9 @@ #include #include +#include +#include +#include #include /** @@ -26,3 +29,59 @@ int cpu_to_bus(u32 *ptr, u32 length) return 0; } + +static int turn_off_myself(void) +{ + printf("Turning off ourselves\r\n"); + mon_power_off(0); + + psc_disable_module(KS2_LPSC_TETRIS); + psc_disable_domain(KS2_TETRIS_PWR_DOMAIN); + + asm volatile ("isb\n" + "dsb\n" + "wfi\n"); + + printf("What! Should not see that\n"); + return 0; +} + +static void turn_off_all_dsps(int num_dsps) +{ + int i; + + for (i = 0; i < num_dsps; i++) { + if (psc_disable_module(i + KS2_LPSC_GEM_0)) + printf("Cannot disable module for #%d DSP", i); + + if (psc_disable_domain(i + 8)) + printf("Cannot disable domain for #%d DSP", i); + } +} + +int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + return turn_off_myself(); +} + +U_BOOT_CMD( + killme, 1, 0, do_killme_cmd, + "turn off main ARM core", + "turn off main ARM core. Should not live after that :(\n" +); + +int misc_init_r(void) +{ + char *env; + long ks2_debug = 0; + + env = getenv("ks2_debug"); + + if (env) + ks2_debug = simple_strtol(env, NULL, 0); + + if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0) + turn_off_all_dsps(KS2_NUM_DSPS); + + return 0; +} diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 2cac633131..5e2f659e94 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -68,7 +68,6 @@ #define K2HK_LPSC_VUSR0 12 #define K2HK_LPSC_CHIP_SRSS 13 #define K2HK_LPSC_MSMC 14 -#define K2HK_LPSC_GEM_0 15 #define K2HK_LPSC_GEM_1 16 #define K2HK_LPSC_GEM_2 17 #define K2HK_LPSC_GEM_3 18 @@ -105,7 +104,6 @@ #define K2HK_LPSC_VUSR1 49 #define K2HK_LPSC_XGE 50 #define K2HK_LPSC_ARM_SREFLEX 51 -#define K2HK_LPSC_TETRIS 52 /* DDR3A definitions */ #define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000 @@ -137,4 +135,7 @@ /* MSMC control */ #define K2HK_MSMC_CTRL_BASE 0x0bc00000 +/* Number of DSP cores */ +#define KS2_NUM_DSPS 8 + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index db2d36bfb6..0dcc31a645 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -87,11 +87,17 @@ typedef volatile unsigned int *dv_reg_p; /* PSC */ #define KS2_PSC_BASE 0x02350000 +#define KS2_LPSC_GEM_0 15 +#define KS2_LPSC_TETRIS 52 +#define KS2_TETRIS_PWR_DOMAIN 31 /* AEMIF */ #define KS2_AEMIF_CNTRL_BASE 0x21000a00 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE +/* Flag from ks2_debug options to check if DSPs need to stay ON */ +#define DBG_LEAVE_DSPS_ON 0x1 + #ifdef CONFIG_SOC_K2HK #include #endif diff --git a/arch/arm/include/asm/arch-keystone/mon.h b/arch/arm/include/asm/arch-keystone/mon.h new file mode 100644 index 0000000000..33a28764bc --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/mon.h @@ -0,0 +1,15 @@ +/* + * K2HK: secure kernel command header file + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MON_H_ +#define _MON_H_ + +int mon_power_off(int core_id); + +#endif -- cgit v1.2.1 From 3d315386255f6d944c0ccb4c7c8819ce604429ab Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 23:44:44 +0300 Subject: k2hk: use common KS2_ prefix for all hardware definitions Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and add KS2_ prefix where it's needed. It requires to change names also in places where they're used. Align lines and remove redundant definitions in kardware-k2hk.h at the same time. Using common KS2_ prefix helps resolve redundant redefinitions and adds opportunity to use KS2_ definition across a project not thinking about what SoC should be used. It's more convenient and we don't need to worry about the SoC type in common files, hardware.h will think about that. The hardware.h decides definitions of what SoC to use. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/clock.c | 24 +-- arch/arm/cpu/armv7/keystone/ddr3.c | 8 +- arch/arm/cpu/armv7/keystone/init.c | 4 +- arch/arm/cpu/armv7/keystone/keystone.c | 2 +- arch/arm/cpu/armv7/keystone/msmc.c | 2 +- arch/arm/include/asm/arch-keystone/clock-k2hk.h | 2 +- arch/arm/include/asm/arch-keystone/clock_defs.h | 2 +- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 202 ++++++++++----------- arch/arm/include/asm/arch-keystone/hardware.h | 4 +- board/ti/k2hk_evm/ddr3.c | 24 +-- include/configs/k2hk_evm.h | 12 +- 11 files changed, 138 insertions(+), 148 deletions(-) diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index bfa4c9d8f6..f905fdcf0d 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -29,11 +29,11 @@ struct pll_regs { }; static const struct pll_regs pll_regs[] = { - [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1}, - [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1}, - [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1}, - [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1}, - [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1}, + [CORE_PLL] = { KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = { KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = { KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3A_PLL] = { KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, + [DDR3B_PLL] = { KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, }; /* Fout = Fref * NF(mult) / NR(prediv) / OD */ @@ -47,7 +47,7 @@ static unsigned long pll_freq_get(int pll) ret = external_clk[sys_clk]; if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { /* PLL mode */ - tmp = __raw_readl(K2HK_MAINPLLCTL0); + tmp = __raw_readl(KS2_MAINPLLCTL0); prediv = (tmp & PLL_DIV_MASK) + 1; mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | (pllctl_reg_read(pll, mult) & @@ -61,19 +61,19 @@ static unsigned long pll_freq_get(int pll) switch (pll) { case PASS_PLL: ret = external_clk[pa_clk]; - reg = K2HK_PASSPLLCTL0; + reg = KS2_PASSPLLCTL0; break; case TETRIS_PLL: ret = external_clk[tetris_clk]; - reg = K2HK_ARMPLLCTL0; + reg = KS2_ARMPLLCTL0; break; case DDR3A_PLL: ret = external_clk[ddr3a_clk]; - reg = K2HK_DDR3APLLCTL0; + reg = KS2_DDR3APLLCTL0; break; case DDR3B_PLL: ret = external_clk[ddr3b_clk]; - reg = K2HK_DDR3BPLLCTL0; + reg = KS2_DDR3BPLLCTL0; break; default: return 0; @@ -214,7 +214,7 @@ void init_pll(const struct pll_init_data *data) * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass) * only applicable for Kepler */ - clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN); + clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */ setbits_le32(pll_regs[data->pll].reg1 , PLL_PLLRST | PLLCTL_ENSAT); @@ -255,7 +255,7 @@ void init_pll(const struct pll_init_data *data) * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass) * only applicable for Kepler */ - setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN); + setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); } else { setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT); /* diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c index b711b810cb..2391e794e8 100644 --- a/arch/arm/cpu/armv7/keystone/ddr3.c +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -74,15 +74,15 @@ void ddr3_reset_ddrphy(void) u32 tmp; /* Assert DDR3A PHY reset */ - tmp = readl(K2HK_DDR3APLLCTL1); + tmp = readl(KS2_DDR3APLLCTL1); tmp |= KS2_DDR3_PLLCTRL_PHY_RESET; - writel(tmp, K2HK_DDR3APLLCTL1); + writel(tmp, KS2_DDR3APLLCTL1); /* wait 10us to catch the reset */ udelay(10); /* Release DDR3A PHY reset */ - tmp = readl(K2HK_DDR3APLLCTL1); + tmp = readl(KS2_DDR3APLLCTL1); tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET; - __raw_writel(tmp, K2HK_DDR3APLLCTL1); + __raw_writel(tmp, KS2_DDR3APLLCTL1); } diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index 4df5ae1cae..f4c293aa89 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -15,8 +15,8 @@ void chip_configuration_unlock(void) { - __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0); - __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1); + __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0); + __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1); } int arch_cpu_init(void) diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c index 1c8c038455..11a9357db4 100644 --- a/arch/arm/cpu/armv7/keystone/keystone.c +++ b/arch/arm/cpu/armv7/keystone/keystone.c @@ -23,7 +23,7 @@ int cpu_to_bus(u32 *ptr, u32 length) { u32 i; - if (!(readl(K2HK_DEVSTAT) & 0x1)) + if (!(readl(KS2_DEVSTAT) & 0x1)) for (i = 0; i < length; i++, ptr++) *ptr = cpu_to_be32(*ptr); diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c index f3f1621d20..af858fa758 100644 --- a/arch/arm/cpu/armv7/keystone/msmc.c +++ b/arch/arm/cpu/armv7/keystone/msmc.c @@ -58,7 +58,7 @@ struct msms_regs { void share_all_segments(int priv_id) { - struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE; + struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; int j; for (j = 0; j < 8; j++) { diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h index 6a69a8d2be..ed1225c298 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h @@ -56,7 +56,7 @@ enum clk_e { sys_clk3_clk }; -#define K2HK_CLK1_6 sys_clk0_6_clk +#define KS2_CLK1_6 sys_clk0_6_clk /* PLL identifiers */ enum pll_type_e { diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h index b251aff383..e545341ca7 100644 --- a/arch/arm/include/asm/arch-keystone/clock_defs.h +++ b/arch/arm/include/asm/arch-keystone/clock_defs.h @@ -50,7 +50,7 @@ struct pllctl_regs { }; static struct pllctl_regs *pllctl_regs[] = { - (struct pllctl_regs *)(CLOCK_BASE + 0x100) + (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100) }; #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 5e2f659e94..e7dff059b8 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -6,134 +6,124 @@ * * SPDX-License-Identifier: GPL-2.0+ */ + #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define K2HK_PLL_CNTRL_BASE 0x02310000 -#define CLOCK_BASE K2HK_PLL_CNTRL_BASE -#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8) -#define KS2_RSTCTRL_KEY 0x5a69 -#define KS2_RSTCTRL_MASK 0xffff0000 -#define KS2_RSTCTRL_SWRST 0xfffe0000 +#define KS2_PLL_CNTRL_BASE 0x02310000 +#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 -#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 -#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) -#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) -#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) +#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) -#define ARM_PLL_EN BIT(13) +#define KS2_ARM_PLL_EN BIT(13) -#define K2HK_SPI0_BASE 0x21000400 -#define K2HK_SPI1_BASE 0x21000600 -#define K2HK_SPI2_BASE 0x21000800 -#define K2HK_SPI_BASE K2HK_SPI0_BASE +#define KS2_SPI0_BASE 0x21000400 +#define KS2_SPI1_BASE 0x21000600 +#define KS2_SPI2_BASE 0x21000800 +#define KS2_SPI_BASE KS2_SPI0_BASE /* Chip configuration unlock codes and registers */ -#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) -#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) -#define KEYSTONE_KICK0_MAGIC 0x83e70b13 -#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0 +#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KS2_KICK0_MAGIC 0x83e70b13 +#define KS2_KICK1_MAGIC 0x95a4f1e0 /* PA SS Registers */ -#define KS2_PASS_BASE 0x02000000 +#define KS2_PASS_BASE 0x02000000 /* PLL control registers */ -#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) -#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) -#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) -#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) -#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) -#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) -#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) -#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) -#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) -#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) +#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) +#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) +#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) /* Power and Sleep Controller (PSC) Domains */ -#define K2HK_LPSC_MOD 0 -#define K2HK_LPSC_DUMMY1 1 -#define K2HK_LPSC_USB 2 -#define K2HK_LPSC_EMIF25_SPI 3 -#define K2HK_LPSC_TSIP 4 -#define K2HK_LPSC_DEBUGSS_TRC 5 -#define K2HK_LPSC_TETB_TRC 6 -#define K2HK_LPSC_PKTPROC 7 -#define KS2_LPSC_PA K2HK_LPSC_PKTPROC -#define K2HK_LPSC_SGMII 8 -#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII -#define K2HK_LPSC_CRYPTO 9 -#define K2HK_LPSC_PCIE 10 -#define K2HK_LPSC_SRIO 11 -#define K2HK_LPSC_VUSR0 12 -#define K2HK_LPSC_CHIP_SRSS 13 -#define K2HK_LPSC_MSMC 14 -#define K2HK_LPSC_GEM_1 16 -#define K2HK_LPSC_GEM_2 17 -#define K2HK_LPSC_GEM_3 18 -#define K2HK_LPSC_GEM_4 19 -#define K2HK_LPSC_GEM_5 20 -#define K2HK_LPSC_GEM_6 21 -#define K2HK_LPSC_GEM_7 22 -#define K2HK_LPSC_EMIF4F_DDR3A 23 -#define K2HK_LPSC_EMIF4F_DDR3B 24 -#define K2HK_LPSC_TAC 25 -#define K2HK_LPSC_RAC 26 -#define K2HK_LPSC_RAC_1 27 -#define K2HK_LPSC_FFTC_A 28 -#define K2HK_LPSC_FFTC_B 29 -#define K2HK_LPSC_FFTC_C 30 -#define K2HK_LPSC_FFTC_D 31 -#define K2HK_LPSC_FFTC_E 32 -#define K2HK_LPSC_FFTC_F 33 -#define K2HK_LPSC_AI2 34 -#define K2HK_LPSC_TCP3D_0 35 -#define K2HK_LPSC_TCP3D_1 36 -#define K2HK_LPSC_TCP3D_2 37 -#define K2HK_LPSC_TCP3D_3 38 -#define K2HK_LPSC_VCP2X4_A 39 -#define K2HK_LPSC_CP2X4_B 40 -#define K2HK_LPSC_VCP2X4_C 41 -#define K2HK_LPSC_VCP2X4_D 42 -#define K2HK_LPSC_VCP2X4_E 43 -#define K2HK_LPSC_VCP2X4_F 44 -#define K2HK_LPSC_VCP2X4_G 45 -#define K2HK_LPSC_VCP2X4_H 46 -#define K2HK_LPSC_BCP 47 -#define K2HK_LPSC_DXB 48 -#define K2HK_LPSC_VUSR1 49 -#define K2HK_LPSC_XGE 50 -#define K2HK_LPSC_ARM_SREFLEX 51 +#define KS2_LPSC_MOD 0 +#define KS2_LPSC_DUMMY1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_SRIO 11 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_GEM_1 16 +#define KS2_LPSC_GEM_2 17 +#define KS2_LPSC_GEM_3 18 +#define KS2_LPSC_GEM_4 19 +#define KS2_LPSC_GEM_5 20 +#define KS2_LPSC_GEM_6 21 +#define KS2_LPSC_GEM_7 22 +#define KS2_LPSC_EMIF4F_DDR3A 23 +#define KS2_LPSC_EMIF4F_DDR3B 24 +#define KS2_LPSC_TAC 25 +#define KS2_LPSC_RAC 26 +#define KS2_LPSC_RAC_1 27 +#define KS2_LPSC_FFTC_A 28 +#define KS2_LPSC_FFTC_B 29 +#define KS2_LPSC_FFTC_C 30 +#define KS2_LPSC_FFTC_D 31 +#define KS2_LPSC_FFTC_E 32 +#define KS2_LPSC_FFTC_F 33 +#define KS2_LPSC_AI2 34 +#define KS2_LPSC_TCP3D_0 35 +#define KS2_LPSC_TCP3D_1 36 +#define KS2_LPSC_TCP3D_2 37 +#define KS2_LPSC_TCP3D_3 38 +#define KS2_LPSC_VCP2X4_A 39 +#define KS2_LPSC_CP2X4_B 40 +#define KS2_LPSC_VCP2X4_C 41 +#define KS2_LPSC_VCP2X4_D 42 +#define KS2_LPSC_VCP2X4_E 43 +#define KS2_LPSC_VCP2X4_F 44 +#define KS2_LPSC_VCP2X4_G 45 +#define KS2_LPSC_VCP2X4_H 46 +#define KS2_LPSC_BCP 47 +#define KS2_LPSC_DXB 48 +#define KS2_LPSC_VUSR1 49 +#define KS2_LPSC_XGE 50 +#define KS2_LPSC_ARM_SREFLEX 51 /* DDR3A definitions */ -#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000 -#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000 -#define K2HK_DDR3A_DDRPHYC 0x02329000 +#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 +#define KS2_DDR3A_DDRPHYC 0x02329000 /* DDR3B definitions */ -#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000 -#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000 -#define K2HK_DDR3B_DDRPHYC 0x02328000 +#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 +#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 +#define KS2_DDR3B_DDRPHYC 0x02328000 /* Queue manager */ -#define DEVICE_QM_MANAGER_BASE 0x02a02000 -#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000 -#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000 -#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 -#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000 -#define DEVICE_QM_NUM_LINKRAMS 2 -#define DEVICE_QM_NUM_MEMREGIONS 20 - -#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000 -#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400 -#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800 -#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000 - -#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24 -#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32 -#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9 +#define KS2_QM_MANAGER_BASE 0x02a02000 +#define KS2_QM_DESC_SETUP_BASE 0x02a03000 +#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 /* MSMC control */ -#define K2HK_MSMC_CTRL_BASE 0x0bc00000 +#define KS2_MSMC_CTRL_BASE 0x0bc00000 /* Number of DSP cores */ #define KS2_NUM_DSPS 8 diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 0dcc31a645..133edadc2a 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -105,7 +105,7 @@ typedef volatile unsigned int *dv_reg_p; #ifndef __ASSEMBLY__ static inline int cpu_is_k2hk(void) { - unsigned int jtag_id = __raw_readl(JTAG_ID_REG); + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); unsigned int part_no = (jtag_id >> 12) & 0xffff; return (part_no == 0xb981) ? 1 : 0; @@ -113,7 +113,7 @@ static inline int cpu_is_k2hk(void) static inline int cpu_revision(void) { - unsigned int jtag_id = __raw_readl(JTAG_ID_REG); + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); unsigned int rev = (jtag_id >> 28) & 0xf; return rev; diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c index b604266837..31e9c31ea2 100644 --- a/board/ti/k2hk_evm/ddr3.c +++ b/board/ti/k2hk_evm/ddr3.c @@ -299,20 +299,20 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_64A_pg2); } else { /* PG 1.1 */ - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_64A); } - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); } else { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); } @@ -323,18 +323,18 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_64A_pg2); } else { /* PG 1.1 */ - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_64A); } - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); } else { - ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); - ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32); } } else { @@ -344,6 +344,6 @@ void ddr3_init(void) } init_pll(&ddr3b_333); - ddr3_init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); - ddr3_init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); + ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); + ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); } diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 63e02495e1..bacf3bca9d 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -73,7 +73,7 @@ #define CONFIG_SYS_NS16550_REG_SIZE -4 #define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE #define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE -#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6) +#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 @@ -83,16 +83,16 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI #define CONFIG_SYS_SPI0 -#define CONFIG_SYS_SPI_BASE K2HK_SPI_BASE +#define CONFIG_SYS_SPI_BASE KS2_SPI_BASE #define CONFIG_SYS_SPI0_NUM_CS 4 #define CONFIG_SYS_SPI1 -#define CONFIG_SYS_SPI1_BASE K2HK_SPI1_BASE +#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE #define CONFIG_SYS_SPI1_NUM_CS 4 #define CONFIG_SYS_SPI2 #define CONFIG_SYS_SPI2_NUM_CS 4 -#define CONFIG_SYS_SPI2_BASE K2HK_SPI2_BASE +#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE #define CONFIG_CMD_SPI -#define CONFIG_SYS_SPI_CLK clk_get_rate(K2HK_LPSC_EMIF25_SPI) +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED @@ -264,6 +264,6 @@ /* we may include files below only after all above definitions */ #include #include -#define CONFIG_SYS_HZ_CLOCK clk_get_rate(K2HK_CLK1_6) +#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) #endif /* __CONFIG_K2HK_EVM_H */ -- cgit v1.2.1 From 0bedbb81351193f1507ad127b6b26e19a93c2c42 Mon Sep 17 00:00:00 2001 From: Murali Karicheri Date: Wed, 9 Jul 2014 23:44:45 +0300 Subject: keystone2: add env option to do unitrd dt fixup With latest v3.13 kernel, unitrd dt fixup is not needed. However for older kernel versions such as v3.8/v3.10, it is needed. So to work with both, add a u-boot env variable that can be set to do dt fixup for older kernels. Signed-off-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/board.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index 3333eb067c..646ecb37e7 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -157,11 +157,14 @@ void ft_board_setup(void *blob, bd_t *bd) u64 size[2]; char name[32], *env, *endp; int lpae, nodeoffset; + int unitrd_fixup = 0; u32 ddr3a_size; int nbanks; env = getenv("mem_lpae"); lpae = env && simple_strtol(env, NULL, 0); + env = getenv("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); ddr3a_size = 0; if (lpae) { @@ -204,10 +207,11 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, start, size, nbanks); /* Fix up the initrd */ - if (lpae) { + if (lpae && unitrd_fixup) { u64 initrd_start, initrd_end; u32 *prop1, *prop2; int err; + nodeoffset = fdt_path_offset(blob, "/chosen"); if (nodeoffset >= 0) { prop1 = (u32 *)fdt_getprop(blob, nodeoffset, -- cgit v1.2.1 From e595107ebbdeb3e50351e703cce08eb07f70c614 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 23:44:46 +0300 Subject: ARM: keystone2: move K2HK board files to common KS2 board directory This patch moves K2HK board directory to a common Keystone II board directory. The Board related common functions are moved to a common keystone board file. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/k2hk_evm/Makefile | 9 -- board/ti/k2hk_evm/README | 148 ------------------ board/ti/k2hk_evm/board.c | 292 ----------------------------------- board/ti/k2hk_evm/ddr3.c | 349 ------------------------------------------ board/ti/ks2_evm/Makefile | 10 ++ board/ti/ks2_evm/README_K2HK | 148 ++++++++++++++++++ board/ti/ks2_evm/board.c | 229 +++++++++++++++++++++++++++ board/ti/ks2_evm/board.h | 19 +++ board/ti/ks2_evm/board_k2hk.c | 81 ++++++++++ board/ti/ks2_evm/ddr3_k2hk.c | 349 ++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 2 +- include/configs/k2hk_evm.h | 1 + 12 files changed, 838 insertions(+), 799 deletions(-) delete mode 100644 board/ti/k2hk_evm/Makefile delete mode 100644 board/ti/k2hk_evm/README delete mode 100644 board/ti/k2hk_evm/board.c delete mode 100644 board/ti/k2hk_evm/ddr3.c create mode 100644 board/ti/ks2_evm/Makefile create mode 100644 board/ti/ks2_evm/README_K2HK create mode 100644 board/ti/ks2_evm/board.c create mode 100644 board/ti/ks2_evm/board.h create mode 100644 board/ti/ks2_evm/board_k2hk.c create mode 100644 board/ti/ks2_evm/ddr3_k2hk.c diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/k2hk_evm/Makefile deleted file mode 100644 index 3645f2feb0..0000000000 --- a/board/ti/k2hk_evm/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# K2HK-EVM: board Makefile -# (C) Copyright 2012-2014 -# Texas Instruments Incorporated, -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += board.o -obj-y += ddr3.o diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README deleted file mode 100644 index 7426b8dc97..0000000000 --- a/board/ti/k2hk_evm/README +++ /dev/null @@ -1,148 +0,0 @@ -U-Boot port for Texas Instruments XTCIEVMK2X -============================================ - -Author: Murali Karicheri - -This README has information on the u-boot port for XTCIEVMK2X EVM board. -Documentation for this board can be found at - http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx - -The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. -More details on these SoCs are available at company websites - K2K: http://www.ti.com/product/tci6638k2k - K2H: http://www.ti.com/product/tci6638k2h - -Board configuration: -==================== - -Some of the peripherals that are configured by u-boot are:- - -1. 2GB DDR3 (can support 8GB SO DIMM as well) -2. 512M NAND (over ti emif16 bus) -3. 6MB MSM SRAM (part of the SoC) -4. two 1GBit Ethernet ports (SoC supports upto 4) -5. two UART ports -6. three i2c interfaces -7. three spi interfaces (only 1 interface supported in driver) - -There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. -To bring up SMP Linux on this board, there is a boot monitor -code that will be installed in MSMC SRAM. There is command available -to install this image from u-boot. - -The port related files can be found at following folders - keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ - K2HK evm board files: board/ti/k2hk_evm/ - -board configuration file: include/configs/k2hk_evm.h - -Supported boot modes: - - SPI NOR boot - - AEMIF NAND boot - -Supported image formats:- - - u-boot.bin: for loading and running u-boot.bin through Texas instruments - code composure studio (CCS) - - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot - - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot - -Build instructions: -=================== - -To build u-boot.bin - >make k2hk_evm_config - >make u-boot-spi.gph - -To build u-boot-spi.gph - >make k2hk_evm_config - >make u-boot-spi.gph - -To build u-boot-nand.gph - >make k2hk_evm_config - >make u-boot-nand.gph - -Load and Run U-Boot on K2HK EVM using CCS -========================================= - -Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin -on EVM. See instructions at below link for installing CCS on a Windows PC. -http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# -Installing_Code_Composer_Studio -Use u-boot.bin from the build folder for loading annd running u-boot binary -on EVM. Follow instructions at -http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup -to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" -and Power ON the EVM. Follow instructions to connect serial port of EVM to -PC and start TeraTerm or Hyper Terminal. - -Start CCS on a Windows machine and Launch Target -configuration as instructed at http://processors.wiki.ti.com/index.php/ -MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. -The instructions provided in the above link uses a script for -loading the u-boot binary on the target EVM. Instead do the following:- - -1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D - isconnected: Unknown)" at the debug window (This is created once Target - configuration is launched) and select "Connect Target". -2. Once target connect is successful, choose Tools->Load Memory option from the - top level menu. At the Load Memory window, choose the file u-boot.bin - through "Browse" button and click "next >" button. In the next window, enter - Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" - button. -3. Click View -> Registers from the top level menu to view registers window. -4. From Registers, window expand "Core Registers" to view PC. Edit PC value - to be 0xc001000. From the "Run" top level menu, select "Free Run" -5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as - below and type any key to stop autoboot as instructed := - -U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) - -I2C: ready -Detected SO-DIMM [SQR-SD3T-2G1333SED] -DRAM: 1.1 GiB -NAND: 512 MiB -Net: K2HK_EMAC -Warning: K2HK_EMAC using MAC address from net device -, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 -Hit any key to stop autoboot: 0 - -SPI NOR Flash programming instructions -====================================== -U-Boot image can be flashed to first 512KB of the NOR flash using following -instructions:- - -1. Start CCS and run U-boot as described above. -2. Suspend Target. Select Run -> Suspend from top level menu - CortexA15_1 (Free Running)" -3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM - using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. - setenv addr_uboot 0x87000000 - setenv filesize - run burn_uboot_spi - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch - to "SPI Little Endian Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. - -AEMIF NAND Flash programming instructions -====================================== -U-Boot image can be flashed to first 1024KB of the NAND flash using following -instructions:- - -1. Start CCS and run U-boot as described above. -2. Suspend Target. Select Run -> Suspend from top level menu - CortexA15_1 (Free Running)" -3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 - through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM - using CCS", but using address 0x87000000. -4. Free Run the target as desribed earlier (step 4) to get u-boot prompt -5. At the U-Boot console type following to setup u-boot environment variables. - setenv filesize - run burn_uboot_nand - Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch - to "ARM NAND Boot mode" as per instruction at - http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. -6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c deleted file mode 100644 index 646ecb37e7..0000000000 --- a/board/ti/k2hk_evm/board.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * K2HK EVM : Board initialization - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int external_clk[ext_clk_count] = { - [sys_clk] = 122880000, - [alt_core_clk] = 125000000, - [pa_clk] = 122880000, - [tetris_clk] = 125000000, - [ddr3a_clk] = 100000000, - [ddr3b_clk] = 100000000, - [mcm_clk] = 312500000, - [pcie_clk] = 100000000, - [sgmii_srio_clk] = 156250000, - [xgmii_clk] = 156250000, - [usb_clk] = 100000000, - [rp1_clk] = 123456789 /* TODO: cannot find - what is that */ -}; - -static struct aemif_config aemif_configs[] = { - { /* CS0 */ - .mode = AEMIF_MODE_NAND, - .wr_setup = 0xf, - .wr_strobe = 0x3f, - .wr_hold = 7, - .rd_setup = 0xf, - .rd_strobe = 0x3f, - .rd_hold = 7, - .turn_around = 3, - .width = AEMIF_WIDTH_8, - }, - -}; - -static struct pll_init_data pll_config[] = { - CORE_PLL_1228, - PASS_PLL_983, - TETRIS_PLL_1200, -}; - -int dram_init(void) -{ - ddr3_init(); - - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_MAX_RAM_BANK_SIZE); - aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); - return 0; -} - -#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET -struct eth_priv_t eth_priv_cfg[] = { - { - .int_name = "K2HK_EMAC", - .rx_flow = 22, - .phy_addr = 0, - .slave_port = 1, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - }, - { - .int_name = "K2HK_EMAC1", - .rx_flow = 23, - .phy_addr = 1, - .slave_port = 2, - .sgmii_link_type = SGMII_LINK_MAC_PHY, - }, - { - .int_name = "K2HK_EMAC2", - .rx_flow = 24, - .phy_addr = 2, - .slave_port = 3, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - }, - { - .int_name = "K2HK_EMAC3", - .rx_flow = 25, - .phy_addr = 3, - .slave_port = 4, - .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, - }, -}; - -int get_eth_env_param(char *env_name) -{ - char *env; - int res = -1; - - env = getenv(env_name); - if (env) - res = simple_strtol(env, NULL, 0); - - return res; -} - -int board_eth_init(bd_t *bis) -{ - int j; - int res; - char link_type_name[32]; - - for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t)); - j++) { - sprintf(link_type_name, "sgmii%d_link_type", j); - res = get_eth_env_param(link_type_name); - if (res >= 0) - eth_priv_cfg[j].sgmii_link_type = res; - - keystone2_emac_initialize(ð_priv_cfg[j]); - } - - return 0; -} -#endif - -#if defined(CONFIG_BOARD_EARLY_INIT_F) -int board_early_init_f(void) -{ - init_plls(ARRAY_SIZE(pll_config), pll_config); - return 0; -} -#endif - -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - - return 0; -} - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -#define K2_DDR3_START_ADDR 0x80000000 -void ft_board_setup(void *blob, bd_t *bd) -{ - u64 start[2]; - u64 size[2]; - char name[32], *env, *endp; - int lpae, nodeoffset; - int unitrd_fixup = 0; - u32 ddr3a_size; - int nbanks; - - env = getenv("mem_lpae"); - lpae = env && simple_strtol(env, NULL, 0); - env = getenv("uinitrd_fixup"); - unitrd_fixup = env && simple_strtol(env, NULL, 0); - - ddr3a_size = 0; - if (lpae) { - env = getenv("ddr3a_size"); - if (env) - ddr3a_size = simple_strtol(env, NULL, 10); - if ((ddr3a_size != 8) && (ddr3a_size != 4)) - ddr3a_size = 0; - } - - nbanks = 1; - start[0] = bd->bi_dram[0].start; - size[0] = bd->bi_dram[0].size; - - /* adjust memory start address for LPAE */ - if (lpae) { - start[0] -= K2_DDR3_START_ADDR; - start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; - } - - if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { - size[1] = ((u64)ddr3a_size - 2) << 30; - start[1] = 0x880000000; - nbanks++; - } - - /* reserve memory at start of bank */ - sprintf(name, "mem_reserve_head"); - env = getenv(name); - if (env) { - start[0] += ustrtoul(env, &endp, 0); - size[0] -= ustrtoul(env, &endp, 0); - } - - sprintf(name, "mem_reserve"); - env = getenv(name); - if (env) - size[0] -= ustrtoul(env, &endp, 0); - - fdt_fixup_memory_banks(blob, start, size, nbanks); - - /* Fix up the initrd */ - if (lpae && unitrd_fixup) { - u64 initrd_start, initrd_end; - u32 *prop1, *prop2; - int err; - - nodeoffset = fdt_path_offset(blob, "/chosen"); - if (nodeoffset >= 0) { - prop1 = (u32 *)fdt_getprop(blob, nodeoffset, - "linux,initrd-start", NULL); - prop2 = (u32 *)fdt_getprop(blob, nodeoffset, - "linux,initrd-end", NULL); - if (prop1 && prop2) { - initrd_start = __be32_to_cpu(*prop1); - initrd_start -= K2_DDR3_START_ADDR; - initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; - initrd_start = __cpu_to_be64(initrd_start); - initrd_end = __be32_to_cpu(*prop2); - initrd_end -= K2_DDR3_START_ADDR; - initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; - initrd_end = __cpu_to_be64(initrd_end); - - err = fdt_delprop(blob, nodeoffset, - "linux,initrd-start"); - if (err < 0) - puts("error deleting initrd-start\n"); - - err = fdt_delprop(blob, nodeoffset, - "linux,initrd-end"); - if (err < 0) - puts("error deleting initrd-end\n"); - - err = fdt_setprop(blob, nodeoffset, - "linux,initrd-start", - &initrd_start, - sizeof(initrd_start)); - if (err < 0) - puts("error adding initrd-start\n"); - - err = fdt_setprop(blob, nodeoffset, - "linux,initrd-end", - &initrd_end, - sizeof(initrd_end)); - if (err < 0) - puts("error adding linux,initrd-end\n"); - } - } - } -} - -void ft_board_setup_ex(void *blob, bd_t *bd) -{ - int lpae; - char *env; - u64 *reserve_start, size; - - env = getenv("mem_lpae"); - lpae = env && simple_strtol(env, NULL, 0); - - if (lpae) { - /* - * the initrd and other reserved memory areas are - * embedded in in the DTB itslef. fix up these addresses - * to 36 bit format - */ - reserve_start = (u64 *)((char *)blob + - fdt_off_mem_rsvmap(blob)); - while (1) { - *reserve_start = __cpu_to_be64(*reserve_start); - size = __cpu_to_be64(*(reserve_start + 1)); - if (size) { - *reserve_start -= K2_DDR3_START_ADDR; - *reserve_start += - CONFIG_SYS_LPAE_SDRAM_BASE; - *reserve_start = - __cpu_to_be64(*reserve_start); - } else { - break; - } - reserve_start += 2; - } - } -} -#endif diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c deleted file mode 100644 index 31e9c31ea2..0000000000 --- a/board/ti/k2hk_evm/ddr3.c +++ /dev/null @@ -1,349 +0,0 @@ -/* - * Keystone2: DDR3 initialization - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1600_64A = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_64 = { - .sdcfg = 0x6200CE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001869ul, -}; - -static struct ddr3_phy_config ddr3phy_1600_32 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_32 = { - .sdcfg = 0x6200DE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001869ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64A = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_64 = { - .sdcfg = 0x62008C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001457ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_32 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_32 = { - .sdcfg = 0x62009C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xf0073200ul, - .sdrfc = 0x00001457ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; -/******************************************************/ - -/* DDR PHY Configs Updated for PG 2.0 - * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ -static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x32868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x32857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -int get_dimm_params(char *dimm_name) -{ - u8 spd_params[256]; - int ret; - int old_bus; - - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); - - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - ret = i2c_read(0x53, 0, 1, spd_params, 256); - - i2c_set_bus_num(old_bus); - - dimm_name[0] = '\0'; - - if (ret) { - puts("Cannot read DIMM params\n"); - return 1; - } - - /* - * We need to convert spd data to dimm parameters - * and to DDR3 EMIF and PHY regirsters values. - * For now we just return DIMM type string value. - * Caller may use this value to choose appropriate - * a pre-set DDR3 configuration - */ - - strncpy(dimm_name, (char *)&spd_params[0x80], 18); - dimm_name[18] = '\0'; - - return 0; -} - -struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); -struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); -struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); -struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); - -void ddr3_init(void) -{ - char dimm_name[32]; - - get_dimm_params(dimm_name); - - printf("Detected SO-DIMM [%s]\n", dimm_name); - - if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { - init_pll(&ddr3a_400); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A_pg2); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A); - } - - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_64); - printf("DRAM: Capacity 8 GiB (includes reported below)\n"); - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_32); - printf("DRAM: Capacity 4 GiB (includes reported below)\n"); - } - } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { - init_pll(&ddr3a_333); - if (cpu_revision() > 0) { - if (cpu_revision() > 1) { - /* PG 2.0 */ - /* Reset DDR3A PHY after PLL enabled */ - ddr3_reset_ddrphy(); - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A_pg2); - } else { - /* PG 1.1 */ - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A); - } - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_64); - } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); - ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_32); - } - } else { - printf("Unknown SO-DIMM. Cannot configure DDR3\n"); - while (1) - ; - } - - init_pll(&ddr3b_333); - ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); - ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); -} diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile new file mode 100644 index 0000000000..58d77dcae5 --- /dev/null +++ b/board/ti/ks2_evm/Makefile @@ -0,0 +1,10 @@ +# +# KS2-EVM: board Makefile +# (C) Copyright 2012-2014 +# Texas Instruments Incorporated, +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o +obj-$(CONFIG_K2HK_EVM) += board_k2hk.o +obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o diff --git a/board/ti/ks2_evm/README_K2HK b/board/ti/ks2_evm/README_K2HK new file mode 100644 index 0000000000..7426b8dc97 --- /dev/null +++ b/board/ti/ks2_evm/README_K2HK @@ -0,0 +1,148 @@ +U-Boot port for Texas Instruments XTCIEVMK2X +============================================ + +Author: Murali Karicheri + +This README has information on the u-boot port for XTCIEVMK2X EVM board. +Documentation for this board can be found at + http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx + +The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. +More details on these SoCs are available at company websites + K2K: http://www.ti.com/product/tci6638k2k + K2H: http://www.ti.com/product/tci6638k2h + +Board configuration: +==================== + +Some of the peripherals that are configured by u-boot are:- + +1. 2GB DDR3 (can support 8GB SO DIMM as well) +2. 512M NAND (over ti emif16 bus) +3. 6MB MSM SRAM (part of the SoC) +4. two 1GBit Ethernet ports (SoC supports upto 4) +5. two UART ports +6. three i2c interfaces +7. three spi interfaces (only 1 interface supported in driver) + +There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. +To bring up SMP Linux on this board, there is a boot monitor +code that will be installed in MSMC SRAM. There is command available +to install this image from u-boot. + +The port related files can be found at following folders + keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ + K2HK evm board files: board/ti/k2hk_evm/ + +board configuration file: include/configs/k2hk_evm.h + +Supported boot modes: + - SPI NOR boot + - AEMIF NAND boot + +Supported image formats:- + - u-boot.bin: for loading and running u-boot.bin through Texas instruments + code composure studio (CCS) + - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot + +Build instructions: +=================== + +To build u-boot.bin + >make k2hk_evm_config + >make u-boot-spi.gph + +To build u-boot-spi.gph + >make k2hk_evm_config + >make u-boot-spi.gph + +To build u-boot-nand.gph + >make k2hk_evm_config + >make u-boot-nand.gph + +Load and Run U-Boot on K2HK EVM using CCS +========================================= + +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +on EVM. See instructions at below link for installing CCS on a Windows PC. +http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# +Installing_Code_Composer_Studio +Use u-boot.bin from the build folder for loading annd running u-boot binary +on EVM. Follow instructions at +http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" +and Power ON the EVM. Follow instructions to connect serial port of EVM to +PC and start TeraTerm or Hyper Terminal. + +Start CCS on a Windows machine and Launch Target +configuration as instructed at http://processors.wiki.ti.com/index.php/ +MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. +The instructions provided in the above link uses a script for +loading the u-boot binary on the target EVM. Instead do the following:- + +1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D + isconnected: Unknown)" at the debug window (This is created once Target + configuration is launched) and select "Connect Target". +2. Once target connect is successful, choose Tools->Load Memory option from the + top level menu. At the Load Memory window, choose the file u-boot.bin + through "Browse" button and click "next >" button. In the next window, enter + Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" + button. +3. Click View -> Registers from the top level menu to view registers window. +4. From Registers, window expand "Core Registers" to view PC. Edit PC value + to be 0xc001000. From the "Run" top level menu, select "Free Run" +5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as + below and type any key to stop autoboot as instructed := + +U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) + +I2C: ready +Detected SO-DIMM [SQR-SD3T-2G1333SED] +DRAM: 1.1 GiB +NAND: 512 MiB +Net: K2HK_EMAC +Warning: K2HK_EMAC using MAC address from net device +, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 +Hit any key to stop autoboot: 0 + +SPI NOR Flash programming instructions +====================================== +U-Boot image can be flashed to first 512KB of the NOR flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv addr_uboot 0x87000000 + setenv filesize + run burn_uboot_spi + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "SPI Little Endian Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. + +AEMIF NAND Flash programming instructions +====================================== +U-Boot image can be flashed to first 1024KB of the NAND flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv filesize + run burn_uboot_nand + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "ARM NAND Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c new file mode 100644 index 0000000000..dfe7be60e7 --- /dev/null +++ b/board/ti/ks2_evm/board.c @@ -0,0 +1,229 @@ +/* + * Keystone : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "board.h" +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct aemif_config aemif_configs[] = { + { /* CS0 */ + .mode = AEMIF_MODE_NAND, + .wr_setup = 0xf, + .wr_strobe = 0x3f, + .wr_hold = 7, + .rd_setup = 0xf, + .rd_strobe = 0x3f, + .rd_hold = 7, + .turn_around = 3, + .width = AEMIF_WIDTH_8, + }, +}; + +int dram_init(void) +{ + ddr3_init(); + + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +int get_eth_env_param(char *env_name) +{ + char *env; + int res = -1; + + env = getenv(env_name); + if (env) + res = simple_strtol(env, NULL, 0); + + return res; +} + +int board_eth_init(bd_t *bis) +{ + int j; + int res; + int port_num; + char link_type_name[32]; + + port_num = get_num_eth_ports(); + + for (j = 0; j < port_num; j++) { + sprintf(link_type_name, "sgmii%d_link_type", j); + res = get_eth_env_param(link_type_name); + if (res >= 0) + eth_priv_cfg[j].sgmii_link_type = res; + + keystone2_emac_initialize(ð_priv_cfg[j]); + } + + return 0; +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int lpae; + char *env; + char *endp; + int nbanks; + u64 size[2]; + u64 start[2]; + char name[32]; + int nodeoffset; + u32 ddr3a_size; + int unitrd_fixup = 0; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + env = getenv("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); + + ddr3a_size = 0; + if (lpae) { + env = getenv("ddr3a_size"); + if (env) + ddr3a_size = simple_strtol(env, NULL, 10); + if ((ddr3a_size != 8) && (ddr3a_size != 4)) + ddr3a_size = 0; + } + + nbanks = 1; + start[0] = bd->bi_dram[0].start; + size[0] = bd->bi_dram[0].size; + + /* adjust memory start address for LPAE */ + if (lpae) { + start[0] -= CONFIG_SYS_SDRAM_BASE; + start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + } + + if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { + size[1] = ((u64)ddr3a_size - 2) << 30; + start[1] = 0x880000000; + nbanks++; + } + + /* reserve memory at start of bank */ + sprintf(name, "mem_reserve_head"); + env = getenv(name); + if (env) { + start[0] += ustrtoul(env, &endp, 0); + size[0] -= ustrtoul(env, &endp, 0); + } + + sprintf(name, "mem_reserve"); + env = getenv(name); + if (env) + size[0] -= ustrtoul(env, &endp, 0); + + fdt_fixup_memory_banks(blob, start, size, nbanks); + + /* Fix up the initrd */ + if (lpae && unitrd_fixup) { + int err; + u32 *prop1, *prop2; + u64 initrd_start, initrd_end; + + nodeoffset = fdt_path_offset(blob, "/chosen"); + if (nodeoffset >= 0) { + prop1 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-start", NULL); + prop2 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-end", NULL); + if (prop1 && prop2) { + initrd_start = __be32_to_cpu(*prop1); + initrd_start -= CONFIG_SYS_SDRAM_BASE; + initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start = __cpu_to_be64(initrd_start); + initrd_end = __be32_to_cpu(*prop2); + initrd_end -= CONFIG_SYS_SDRAM_BASE; + initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end = __cpu_to_be64(initrd_end); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-start"); + if (err < 0) + puts("error deleting initrd-start\n"); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-end"); + if (err < 0) + puts("error deleting initrd-end\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-start", + &initrd_start, + sizeof(initrd_start)); + if (err < 0) + puts("error adding initrd-start\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-end", + &initrd_end, + sizeof(initrd_end)); + if (err < 0) + puts("error adding linux,initrd-end\n"); + } + } + } +} + +void ft_board_setup_ex(void *blob, bd_t *bd) +{ + int lpae; + u64 size; + char *env; + u64 *reserve_start; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + + if (lpae) { + /* + * the initrd and other reserved memory areas are + * embedded in in the DTB itslef. fix up these addresses + * to 36 bit format + */ + reserve_start = (u64 *)((char *)blob + + fdt_off_mem_rsvmap(blob)); + while (1) { + *reserve_start = __cpu_to_be64(*reserve_start); + size = __cpu_to_be64(*(reserve_start + 1)); + if (size) { + *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start += + CONFIG_SYS_LPAE_SDRAM_BASE; + *reserve_start = + __cpu_to_be64(*reserve_start); + } else { + break; + } + reserve_start += 2; + } + } +} +#endif diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h new file mode 100644 index 0000000000..d91ef73612 --- /dev/null +++ b/board/ti/ks2_evm/board.h @@ -0,0 +1,19 @@ +/* + * K2HK EVM : Board common header + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KS2_BOARD +#define _KS2_BOARD + +#include + +extern struct eth_priv_t eth_priv_cfg[]; + +int get_num_eth_ports(void); + +#endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c new file mode 100644 index 0000000000..a369d6bd63 --- /dev/null +++ b/board/ti/ks2_evm/board_k2hk.c @@ -0,0 +1,81 @@ +/* + * K2HK EVM : Board initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 125000000, + [pa_clk] = 122880000, + [tetris_clk] = 125000000, + [ddr3a_clk] = 100000000, + [ddr3b_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_srio_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, + [rp1_clk] = 123456789 +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1228, + PASS_PLL_983, + TETRIS_PLL_1200, +}; + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2HK_EMAC", + .rx_flow = 22, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC1", + .rx_flow = 23, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC2", + .rx_flow = 24, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2HK_EMAC3", + .rx_flow = 25, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c new file mode 100644 index 0000000000..31e9c31ea2 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -0,0 +1,349 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1600_64A = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1600_64 = { + .sdcfg = 0x6200CE6aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001869ul, +}; + +static struct ddr3_phy_config ddr3phy_1600_32 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1600_32 = { + .sdcfg = 0x6200DE6aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1333_64A = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | + NOSRA_MASK | UDIMM_MASK), + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1333_64 = { + .sdcfg = 0x62008C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001457ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_32 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | + NOSRA_MASK | UDIMM_MASK), + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1333_32 = { + .sdcfg = 0x62009C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0xf0073200ul, + .sdrfc = 0x00001457ul, +}; + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1333_64 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; +/******************************************************/ + +/* DDR PHY Configs Updated for PG 2.0 + * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ +static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +int get_dimm_params(char *dimm_name) +{ + u8 spd_params[256]; + int ret; + int old_bus; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, spd_params, 256); + + i2c_set_bus_num(old_bus); + + dimm_name[0] = '\0'; + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + /* + * We need to convert spd data to dimm parameters + * and to DDR3 EMIF and PHY regirsters values. + * For now we just return DIMM type string value. + * Caller may use this value to choose appropriate + * a pre-set DDR3 configuration + */ + + strncpy(dimm_name, (char *)&spd_params[0x80], 18); + dimm_name[18] = '\0'; + + return 0; +} + +struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); +struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); +struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); +struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); + +void ddr3_init(void) +{ + char dimm_name[32]; + + get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + init_pll(&ddr3a_400); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_64A); + } + + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_64); + printf("DRAM: Capacity 8 GiB (includes reported below)\n"); + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_32); + printf("DRAM: Capacity 4 GiB (includes reported below)\n"); + } + } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { + init_pll(&ddr3a_333); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_64A_pg2); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_64A); + } + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_64); + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_32); + } + } else { + printf("Unknown SO-DIMM. Cannot configure DDR3\n"); + while (1) + ; + } + + init_pll(&ddr3b_333); + ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); + ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); +} diff --git a/boards.cfg b/boards.cfg index 6f8d168cf1..f7fbd54890 100644 --- a/boards.cfg +++ b/boards.cfg @@ -300,7 +300,7 @@ Active arm armv7 exynos samsung trats Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak Active arm armv7 highbank - highbank highbank - Rob Herring -Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov +Active arm armv7 keystone ti ks2_evm k2hk_evm - Vitaly Andrianov Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index bacf3bca9d..f727882d0b 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -258,6 +258,7 @@ #define CONFIG_OF_BOARD_SETUP #define CONFIG_SYS_BARGSIZE 1024 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) +#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) #define CONFIG_SUPPORT_RAW_INITRD -- cgit v1.2.1 From 8dfc15f56c2b39fb5d542cf67857f5ad36575234 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 9 Jul 2014 23:44:47 +0300 Subject: ARM: keystone: clock: move K2HK SoC dependent code in separate file This patch in general spit SoC type clock dependent code and general clock code. Before adding keystone II Edison k2e SoC which has slightly different dpll set, move k2hk dependent clock code to separate clock-k2hk.c file. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Makefile | 1 + arch/arm/cpu/armv7/keystone/clock-k2hk.c | 113 ++++++++++++++++++ arch/arm/cpu/armv7/keystone/clock.c | 148 ++++-------------------- arch/arm/include/asm/arch-keystone/clock-k2hk.h | 21 ---- arch/arm/include/asm/arch-keystone/clock.h | 28 +++++ 5 files changed, 166 insertions(+), 145 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2hk.c diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index 64e42a6e23..74c516013a 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -8,6 +8,7 @@ obj-y += init.o obj-y += psc.o obj-y += clock.o +obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o obj-y += cmd_clock.o obj-y += cmd_mon.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c new file mode 100644 index 0000000000..96a9f72886 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2hk.c @@ -0,0 +1,113 @@ +/* + * Keystone2: get clk rate for K2HK + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, + [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, + [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case TETRIS_PLL: + ret = external_clk[tetris_clk]; + reg = KS2_ARMPLLCTL0; + break; + case DDR3A_PLL: + ret = external_clk[ddr3a_clk]; + reg = KS2_DDR3APLLCTL0; + break; + case DDR3B_PLL: + ret = external_clk[ddr3b_clk]; + reg = KS2_DDR3BPLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); + case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); + case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index f905fdcf0d..42b664b576 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -8,9 +8,6 @@ */ #include -#include -#include -#include #include #include @@ -24,106 +21,6 @@ static void wait_for_completion(const struct pll_init_data *data) } } -struct pll_regs { - u32 reg0, reg1; -}; - -static const struct pll_regs pll_regs[] = { - [CORE_PLL] = { KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, - [PASS_PLL] = { KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, - [TETRIS_PLL] = { KS2_ARMPLLCTL0, KS2_ARMPLLCTL1}, - [DDR3A_PLL] = { KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, - [DDR3B_PLL] = { KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1}, -}; - -/* Fout = Fref * NF(mult) / NR(prediv) / OD */ -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, output_div = 2; - unsigned long ret; - u32 tmp, reg; - - if (pll == CORE_PLL) { - ret = external_clk[sys_clk]; - if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { - /* PLL mode */ - tmp = __raw_readl(KS2_MAINPLLCTL0); - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | - (pllctl_reg_read(pll, mult) & - PLLM_MULT_LO_MASK)) + 1; - output_div = ((pllctl_reg_read(pll, secctl) >> - PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; - - ret = ret / prediv / output_div * mult; - } - } else { - switch (pll) { - case PASS_PLL: - ret = external_clk[pa_clk]; - reg = KS2_PASSPLLCTL0; - break; - case TETRIS_PLL: - ret = external_clk[tetris_clk]; - reg = KS2_ARMPLLCTL0; - break; - case DDR3A_PLL: - ret = external_clk[ddr3a_clk]; - reg = KS2_DDR3APLLCTL0; - break; - case DDR3B_PLL: - ret = external_clk[ddr3b_clk]; - reg = KS2_DDR3BPLLCTL0; - break; - default: - return 0; - } - - tmp = __raw_readl(reg); - - if (!(tmp & PLLCTL_BYPASS)) { - /* Bypass disabled */ - prediv = (tmp & PLL_DIV_MASK) + 1; - mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; - output_div = ((tmp >> PLL_CLKOD_SHIFT) & - PLL_CLKOD_MASK) + 1; - ret = ((ret / prediv) * mult) / output_div; - } - } - - return ret; -} - -unsigned long clk_get_rate(unsigned int clk) -{ - switch (clk) { - case core_pll_clk: return pll_freq_get(CORE_PLL); - case pass_pll_clk: return pll_freq_get(PASS_PLL); - case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); - case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); - case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); - case sys_clk0_1_clk: - case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); - case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); - case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); - case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); - case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; - case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; - case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; - case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; - case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; - case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; - case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; - case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; - case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; - case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; - case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; - default: - break; - } - return 0; -} - void init_pll(const struct pll_init_data *data) { u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj; @@ -139,7 +36,7 @@ void init_pll(const struct pll_init_data *data) tmp = pllctl_reg_read(data->pll, secctl); if (tmp & (PLLCTL_BYPASS)) { - setbits_le32(pll_regs[data->pll].reg1, + setbits_le32(keystone_pll_regs[data->pll].reg1, BIT(MAIN_ENSAT_OFFSET)); pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | @@ -159,21 +56,24 @@ void init_pll(const struct pll_init_data *data) pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); - clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK, - (pllm << 6)); + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLLM_MULT_HI_SMASK, (pllm << 6)); /* Set the BWADJ (12 bit field) */ tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */ - clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK, + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLL_BWADJ_LO_SMASK, (tmp_ctl << PLL_BWADJ_LO_SHIFT)); - clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK, + clrsetbits_le32(keystone_pll_regs[data->pll].reg1, + PLL_BWADJ_HI_MASK, (tmp_ctl >> 8)); /* * Set the pll divider (6 bit field) * * PLLD[5:0] is located in MAINPLLCTL0 */ - clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld); + clrsetbits_le32(keystone_pll_regs[data->pll].reg0, + PLL_DIV_MASK, plld); /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */ pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK, @@ -209,14 +109,14 @@ void init_pll(const struct pll_init_data *data) } else if (data->pll == TETRIS_PLL) { bwadj = pllm >> 1; /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ - setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + setbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); /* * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass) * only applicable for Kepler */ clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */ - setbits_le32(pll_regs[data->pll].reg1 , + setbits_le32(keystone_pll_regs[data->pll].reg1 , PLL_PLLRST | PLLCTL_ENSAT); /* @@ -229,13 +129,13 @@ void init_pll(const struct pll_init_data *data) (pllm << 6) | (plld & PLL_DIV_MASK) | (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS; - __raw_writel(tmp, pll_regs[data->pll].reg0); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); /* Set BWADJ[11:8] bits */ - tmp = __raw_readl(pll_regs[data->pll].reg1); + tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); tmp &= ~(PLL_BWADJ_HI_MASK); tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK); - __raw_writel(tmp, pll_regs[data->pll].reg1); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); /* * 5 Wait for at least 5 us based on the reference * clock (PLL reset time) @@ -243,26 +143,26 @@ void init_pll(const struct pll_init_data *data) sdelay(21000); /* Wait for a minimum of 7 us*/ /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */ - clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST); + clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST); /* * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1) * (PLL lock time) */ sdelay(105000); /* 8 disable bypass */ - clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); /* * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass) * only applicable for Kepler */ setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); } else { - setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT); + setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); /* * process keeps state of Bypass bit while programming * all other DDR PLL settings */ - tmp = __raw_readl(pll_regs[data->pll].reg0); + tmp = __raw_readl(keystone_pll_regs[data->pll].reg0); tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */ /* @@ -274,10 +174,10 @@ void init_pll(const struct pll_init_data *data) (pllm << PLL_MULT_SHIFT) | (plld & PLL_DIV_MASK) | (pllod << PLL_CLKOD_SHIFT); - __raw_writel(tmp, pll_regs[data->pll].reg0); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg0); /* Set BWADJ[11:8] bits */ - tmp = __raw_readl(pll_regs[data->pll].reg1); + tmp = __raw_readl(keystone_pll_regs[data->pll].reg1); tmp &= ~(PLL_BWADJ_HI_MASK); tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); @@ -285,20 +185,20 @@ void init_pll(const struct pll_init_data *data) if (data->pll == PASS_PLL) tmp |= PLLCTL_PAPLL; - __raw_writel(tmp, pll_regs[data->pll].reg1); + __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); /* Reset bit: bit 14 for both DDR3 & PASS PLL */ tmp = PLL_PLLRST; /* Set RESET bit = 1 */ - setbits_le32(pll_regs[data->pll].reg1, tmp); + setbits_le32(keystone_pll_regs[data->pll].reg1, tmp); /* Wait for a minimum of 7 us*/ sdelay(21000); /* Clear RESET bit */ - clrbits_le32(pll_regs[data->pll].reg1, tmp); + clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp); sdelay(105000); /* clear BYPASS (Enable PLL Mode) */ - clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS); sdelay(21000); /* Wait for a minimum of 7 us*/ } diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h index ed1225c298..784a0be567 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h @@ -10,10 +10,6 @@ #ifndef __ASM_ARCH_CLOCK_K2HK_H #define __ASM_ARCH_CLOCK_K2HK_H -#include - -#ifndef __ASSEMBLY__ - enum ext_clk_e { sys_clk, alt_core_clk, @@ -66,15 +62,6 @@ enum pll_type_e { DDR3A_PLL, DDR3B_PLL, }; -#define MAIN_PLL CORE_PLL - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int pll_m; /* PLL Multiplier */ - int pll_d; /* PLL divider */ - int pll_od; /* PLL output divider */ -}; #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} @@ -98,12 +85,4 @@ struct pll_init_data { #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} -void init_plls(int num_pll, struct pll_init_data *config); -void init_pll(const struct pll_init_data *data); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); - -#endif - #endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h index 324501b75a..c7da3520c4 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -10,8 +10,36 @@ #ifndef __ASM_ARCH_CLOCK_H #define __ASM_ARCH_CLOCK_H +#ifndef __ASSEMBLY__ + #ifdef CONFIG_SOC_K2HK #include #endif +#define MAIN_PLL CORE_PLL + +#include + +struct keystone_pll_regs { + u32 reg0; + u32 reg1; +}; + +/* PLL configuration data */ +struct pll_init_data { + int pll; + int pll_m; /* PLL Multiplier */ + int pll_d; /* PLL divider */ + int pll_od; /* PLL output divider */ +}; + +extern const struct keystone_pll_regs keystone_pll_regs[]; + +void init_plls(int num_pll, struct pll_init_data *config); +void init_pll(const struct pll_init_data *data); +unsigned long clk_get_rate(unsigned int clk); +unsigned long clk_round_rate(unsigned int clk, unsigned long hz); +int clk_set_rate(unsigned int clk, unsigned long hz); + +#endif #endif -- cgit v1.2.1 From 2221cd12cddeecd88ae2d8d6ec4e5ca390b14dc7 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 23:44:48 +0300 Subject: configs: k2hk_evm: config: add common EVM configuration header This patch adds a common config header file for all the Keystone II EVM platforms. It combines a lot of general definitions in one file. The common header included in the EVM should be specific configuration header. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- include/configs/k2hk_evm.h | 258 +++--------------------------------------- include/configs/ks2_evm.h | 275 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 289 insertions(+), 244 deletions(-) create mode 100644 include/configs/ks2_evm.h diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index f727882d0b..8aa616da0e 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -14,257 +14,27 @@ #define CONFIG_SOC_K2HK #define CONFIG_K2HK_EVM -/* U-Boot Build Configuration */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ -#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SYS_THUMB_BUILD - -/* SoC Configuration */ -#define CONFIG_ARMV7 -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_TEXT_BASE 0x0c001000 -#define CONFIG_SPL_TARGET "u-boot-spi.gph" -#define CONFIG_SYS_DCACHE_OFF - -/* Memory Configuration */ -#define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 -#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ - GENERATED_GBL_DATA_SIZE) - -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_TEXT_BASE 0x0c200000 -#define CONFIG_SPL_PAD_TO 65536 -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) -#define CONFIG_SPL_STACK_SIZE (8 * 1024) -#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ - CONFIG_SYS_SPL_MALLOC_SIZE + \ - CONFIG_SPL_STACK_SIZE - 4) -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SPL_FRAMEWORK - -/* UART Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE -#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* SPI Configuration */ -#define CONFIG_SPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI0 -#define CONFIG_SYS_SPI_BASE KS2_SPI_BASE -#define CONFIG_SYS_SPI0_NUM_CS 4 -#define CONFIG_SYS_SPI1 -#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE -#define CONFIG_SYS_SPI1_NUM_CS 4 -#define CONFIG_SYS_SPI2 -#define CONFIG_SYS_SPI2_NUM_CS 4 -#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE -#define CONFIG_CMD_SPI -#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2HK EVM # " -/* I2C Configuration */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_DAVINCI -#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ -#define I2C_BUS_MAX 3 +#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" -/* EEPROM definitions */ -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0" +#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0" +#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0" +#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0" +#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0" -/* Network Configuration */ -#define CONFIG_DRIVER_TI_KEYSTONE_NET -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 32 -#define CONFIG_NET_MULTI -#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 -#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 -#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 -#define CONFIG_SYS_SGMII_RATESCALE 2 +#include -/* AEMIF */ -#define CONFIG_TI_AEMIF -#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c200000 /* NAND Configuration */ -#define CONFIG_NAND_DAVINCI -#define CONFIG_KEYSTONE_RBL_NAND -#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_MASK_CLE 0x4000 -#define CONFIG_SYS_NAND_MASK_ALE 0x2000 - -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x100000 -#define CONFIG_MTD_PARTITIONS -#define CONFIG_MTD_DEVICE -#define CONFIG_RBTREE -#define CONFIG_LZO -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" -#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro," \ - "-(ubifs)" -/* U-Boot command configuration */ -#include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_I2C -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_NAND -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_CMD_SF -#define CONFIG_CMD_EEPROM - -/* U-Boot general configuration */ -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SYS_PROMPT "K2HK EVM # " -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE 2048 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_CMDLINE_EDITING -#define CONFIG_VERSION_VARIABLE -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "boot=ramfs\0" \ - "tftp_root=/\0" \ - "nfs_root=/export\0" \ - "mem_lpae=1\0" \ - "mem_reserve=512M\0" \ - "addr_fdt=0x87000000\0" \ - "addr_kern=0x88000000\0" \ - "addr_mon=0x0c5f0000\0" \ - "addr_uboot=0x87000000\0" \ - "addr_fs=0x82000000\0" \ - "addr_ubi=0x82000000\0" \ - "fdt_high=0xffffffff\0" \ - "name_fdt=uImage-k2hk-evm.dtb\0" \ - "name_fs=arago-console-image.cpio.gz\0" \ - "name_kern=uImage-keystone-evm.bin\0" \ - "name_mon=skern-keystone-evm.bin\0" \ - "name_uboot=u-boot-spi-keystone-evm.gph\0" \ - "name_ubi=keystone-evm-ubifs.ubi\0" \ - "run_mon=mon_install ${addr_mon}\0" \ - "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ - "init_net=run args_all args_net\0" \ - "init_ubi=run args_all args_ubi; " \ - "ubi part ubifs; ubifsmount boot\0" \ - "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ - "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ - "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ - "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ - "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ - "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ - "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ - "sf write ${addr_uboot} 0 ${filesize}\0" \ - "burn_uboot_nand=nand erase 0 0x100000; " \ - "nand write ${addr_uboot} 0 ${filesize}\0" \ - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ - "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ - "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ - "${nfs_options} ip=dhcp\0" \ - "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ - "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ - "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ - "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ - "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ - "burn_ubi=nand erase.part ubifs; " \ - "nand write ${addr_ubi} ubifs ${filesize}\0" \ - "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ - "args_ramfs=setenv bootargs ${bootargs} earlyprintk " \ - "rdinit=/sbin/init rw root=/dev/ram0 " \ - "initrd=0x802000000,9M\0" \ - "no_post=1\0" \ - "mtdparts=mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0" -#define CONFIG_BOOTCOMMAND \ - "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ - "get_kern_${boot} run_mon run_kern" -#define CONFIG_BOOTARGS \ - -/* Linux interfacing */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_SYS_BARGSIZE 1024 -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) -#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) - -#define CONFIG_SUPPORT_RAW_INITRD - -/* we may include files below only after all above definitions */ -#include -#include -#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) +/* Network */ +#define CONFIG_DRIVER_TI_KEYSTONE_NET #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h new file mode 100644 index 0000000000..29f0b9b621 --- /dev/null +++ b/include/configs/ks2_evm.h @@ -0,0 +1,275 @@ +/* + * Common configuration header file for all Keystone II EVM platforms + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_KS2_EVM_H +#define __CONFIG_KS2_EVM_H + +#define CONFIG_SOC_KEYSTONE + +/* U-Boot Build Configuration */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ +#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_THUMB_BUILD + +/* SoC Configuration */ +#define CONFIG_ARMV7 +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0x0c001000 +#define CONFIG_SPL_TARGET "u-boot-spi.gph" +#define CONFIG_SYS_DCACHE_OFF + +/* Memory Configuration */ +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ +#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ + GENERATED_GBL_DATA_SIZE) + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_PAD_TO 65536 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SPL_MAX_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) +#define CONFIG_SPL_STACK_SIZE (8 * 1024) +#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SPL_STACK_SIZE - 4) +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SPL_FRAMEWORK + +/* UART Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE +#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* SPI Configuration */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_DAVINCI_SPI +#define CONFIG_CMD_SPI +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_SYS_SPI0 +#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE +#define CONFIG_SYS_SPI0_NUM_CS 4 +#define CONFIG_SYS_SPI1 +#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE +#define CONFIG_SYS_SPI1_NUM_CS 4 +#define CONFIG_SYS_SPI2 +#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE +#define CONFIG_SYS_SPI2_NUM_CS 4 + +/* Network Configuration */ +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 32 +#define CONFIG_NET_MULTI +#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 +#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 +#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 +#define CONFIG_SYS_SGMII_RATESCALE 2 + +/* AEMIF */ +#define CONFIG_TI_AEMIF +#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE + +/* I2C Configuration */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ +#define I2C_BUS_MAX 3 + +/* EEPROM definitions */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_ENV_EEPROM_IS_ON_I2C + +/* NAND Configuration */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_KEYSTONE_RBL_NAND +#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET +#define CONFIG_SYS_NAND_MASK_CLE 0x4000 +#define CONFIG_SYS_NAND_MASK_ALE 0x2000 +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST + +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" +#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro," \ + "-(ubifs)" + +/* U-Boot command configuration */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_SF +#define CONFIG_CMD_EEPROM + +/* U-Boot general configuration */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE 2048 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_TIMESTAMP + +/* EDMA3 */ +#define CONFIG_TI_EDMA3 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "boot=ramfs\0" \ + "tftp_root=/\0" \ + "nfs_root=/export\0" \ + "mem_lpae=1\0" \ + "mem_reserve=512M\0" \ + "addr_fdt=0x87000000\0" \ + "addr_kern=0x88000000\0" \ + KS2_ADDR_MON \ + "addr_uboot=0x87000000\0" \ + "addr_fs=0x82000000\0" \ + "addr_ubi=0x82000000\0" \ + "addr_secdb_key=0xc000000\0" \ + "fdt_high=0xffffffff\0" \ + KS2_FDT_NAME \ + "name_fs=arago-console-image.cpio.gz\0" \ + "name_kern=uImage\0" \ + KS2_NAME_MON \ + NAME_UBOOT \ + NAME_UBI \ + "run_mon=mon_install ${addr_mon}\0" \ + "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ + "init_net=run args_all args_net\0" \ + "init_ubi=run args_all args_ubi; " \ + "ubi part ubifs; ubifsmount boot;" \ + "ubifsload ${addr_secdb_key} securedb.key.bin;\0" \ + "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ + "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ + "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ + "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ + "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ + "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ + "sf write ${addr_uboot} 0 ${filesize}\0" \ + "burn_uboot_nand=nand erase 0 0x100000; " \ + "nand write ${addr_uboot} 0 ${filesize}\0" \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ + KS2_ARGS_UBI \ + "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ + "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ + "${nfs_options} ip=dhcp\0" \ + "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ + "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ + "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ + "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ + "burn_ubi=nand erase.part ubifs; " \ + "nand write ${addr_ubi} ubifs ${filesize}\0" \ + "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ + "args_ramfs=setenv bootargs ${bootargs} " \ + "rdinit=/sbin/init rw root=/dev/ram0 " \ + "initrd=0x802000000,9M\0" \ + "no_post=1\0" \ + "mtdparts=mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" + +#define CONFIG_BOOTCOMMAND \ + "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ + "get_kern_${boot} run_mon run_kern" + +#define CONFIG_BOOTARGS \ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_SYS_BARGSIZE 1024 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) +#define CONFIG_LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) + +#define CONFIG_SUPPORT_RAW_INITRD + +/* we may include files below only after all above definitions */ +#include +#include +#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) + +/* Maximum memory size for relocated U-boot at the end of the DDR3 memory + which is NOT applicable for DDR ECC test */ +#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */ + +#endif /* __CONFIG_KS2_EVM_H */ -- cgit v1.2.1 From b1babef856f936278d24bd0bf84f9cf702df2392 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 9 Jul 2014 23:44:49 +0300 Subject: keystone: ddr3: move K2HK DDR3 configuration to a common file It's convenient to hold configurations for DDR3 PHY and EMIF in separate common place. This patch moves K2HK DDR3 PHY and EMIF configuration data with different rates and memory size to a common ddr3_cfg.c file. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/ks2_evm/Makefile | 1 + board/ti/ks2_evm/ddr3_cfg.c | 130 ++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.h | 21 +++ board/ti/ks2_evm/ddr3_k2hk.c | 305 +++---------------------------------------- 4 files changed, 172 insertions(+), 285 deletions(-) create mode 100644 board/ti/ks2_evm/ddr3_cfg.c create mode 100644 board/ti/ks2_evm/ddr3_cfg.h diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 58d77dcae5..774a7d526c 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -6,5 +6,6 @@ # obj-y += board.o +obj-y += ddr3_cfg.o obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c new file mode 100644 index 0000000000..6e55af924f --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -0,0 +1,130 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* DDR3 PHY configuration data with 1600M rate, 8GB size */ +struct ddr3_phy_config ddr3phy_1600_8g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, 8GB size */ +struct ddr3_emif_config ddr3_1600_8g = { + .sdcfg = 0x6200CE6Aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001869ul, +}; + +#ifdef CONFIG_K2HK_EVM +/* DDR3 PHY configuration data with 1333M rate, and 2GB size */ +struct ddr3_phy_config ddr3phy_1333_2g = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */ +struct ddr3_emif_config ddr3_1333_2g = { + .sdcfg = 0x62008C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001457ul, +}; +#endif + +int ddr3_get_dimm_params(char *dimm_name) +{ + int ret; + int old_bus; + u8 spd_params[256]; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, spd_params, 256); + + i2c_set_bus_num(old_bus); + + dimm_name[0] = '\0'; + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + /* + * We need to convert spd data to dimm parameters + * and to DDR3 EMIF and PHY regirsters values. + * For now we just return DIMM type string value. + * Caller may use this value to choose appropriate + * a pre-set DDR3 configuration + */ + + strncpy(dimm_name, (char *)&spd_params[0x80], 18); + dimm_name[18] = '\0'; + + return 0; +} diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h new file mode 100644 index 0000000000..d14bac3640 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -0,0 +1,21 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR3_CFG_H +#define __DDR3_CFG_H + +extern struct ddr3_phy_config ddr3phy_1600_8g; +extern struct ddr3_emif_config ddr3_1600_8g; + +extern struct ddr3_phy_config ddr3phy_1333_2g; +extern struct ddr3_emif_config ddr3_1333_2g; + +int ddr3_get_dimm_params(char *dimm_name); + +#endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index 31e9c31ea2..21a5a0a252 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -8,287 +8,18 @@ */ #include +#include "ddr3_cfg.h" #include #include -#include -#include - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1600_64A = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_64 = { - .sdcfg = 0x6200CE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001869ul, -}; - -static struct ddr3_phy_config ddr3phy_1600_32 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x12868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1600_32 = { - .sdcfg = 0x6200DE6aul, - .sdtim1 = 0x16709C55ul, - .sdtim2 = 0x00001D4Aul, - .sdtim3 = 0x435DFF54ul, - .sdtim4 = 0x553F0CFFul, - .zqcfg = 0x70073200ul, - .sdrfc = 0x00001869ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64A = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_64 = { - .sdcfg = 0x62008C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xF0073200ul, - .sdrfc = 0x00001457ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_32 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | - NOSRA_MASK | UDIMM_MASK), - .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_emif_config ddr3_1333_32 = { - .sdcfg = 0x62009C62ul, - .sdtim1 = 0x125C8044ul, - .sdtim2 = 0x00001D29ul, - .sdtim3 = 0x32CDFF43ul, - .sdtim4 = 0x543F0ADFul, - .zqcfg = 0xf0073200ul, - .sdrfc = 0x00001457ul, -}; - -/************************* *****************************/ -static struct ddr3_phy_config ddr3phy_1333_64 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), - .dcr_val = ((1 << 10) | (1 << 27)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x12857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0000005Dul, - .zq1cr1 = 0x0000005Bul, - .zq2cr1 = 0x0000005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; -/******************************************************/ - -/* DDR PHY Configs Updated for PG 2.0 - * zq0,1,2cr1 are updated for PG 2.0 specific configs *_pg2 */ -static struct ddr3_phy_config ddr3phy_1600_64A_pg2 = { - .pllcr = 0x0001C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0D861A80ul, - .ptr4 = 0x0C827100ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0xA19DBB66ul, - .dtpr1 = 0x32868300ul, - .dtpr2 = 0x50035200ul, - .mr0 = 0x00001C70ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000018ul, - .dtcr = 0x730035C7ul, - .pgcr2 = 0x00F07A12ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -static struct ddr3_phy_config ddr3phy_1333_64A_pg2 = { - .pllcr = 0x0005C000ul, - .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), - .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), - .ptr0 = 0x42C21590ul, - .ptr1 = 0xD05612C0ul, - .ptr2 = 0, /* not set in gel */ - .ptr3 = 0x0B4515C2ul, - .ptr4 = 0x0A6E08B4ul, - .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), - .dcr_val = ((1 << 10)), - .dtpr0 = 0x8558AA55ul, - .dtpr1 = 0x32857280ul, - .dtpr2 = 0x5002C200ul, - .mr0 = 0x00001A60ul, - .mr1 = 0x00000006ul, - .mr2 = 0x00000010ul, - .dtcr = 0x710035C7ul, - .pgcr2 = 0x00F065B8ul, - .zq0cr1 = 0x0001005Dul, - .zq1cr1 = 0x0001005Bul, - .zq2cr1 = 0x0001005Bul, - .pir_v1 = 0x00000033ul, - .pir_v2 = 0x0000FF81ul, -}; - -int get_dimm_params(char *dimm_name) -{ - u8 spd_params[256]; - int ret; - int old_bus; - - i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); - - old_bus = i2c_get_bus_num(); - i2c_set_bus_num(1); - - ret = i2c_read(0x53, 0, 1, spd_params, 256); - - i2c_set_bus_num(old_bus); - - dimm_name[0] = '\0'; - - if (ret) { - puts("Cannot read DIMM params\n"); - return 1; - } - - /* - * We need to convert spd data to dimm parameters - * and to DDR3 EMIF and PHY regirsters values. - * For now we just return DIMM type string value. - * Caller may use this value to choose appropriate - * a pre-set DDR3 configuration - */ - - strncpy(dimm_name, (char *)&spd_params[0x80], 18); - dimm_name[18] = '\0'; - - return 0; -} struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); -struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); -struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); void ddr3_init(void) { char dimm_name[32]; - get_dimm_params(dimm_name); + ddr3_get_dimm_params(dimm_name); printf("Detected SO-DIMM [%s]\n", dimm_name); @@ -299,21 +30,25 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A_pg2); + &ddr3phy_1600_8g); } else { /* PG 1.1 */ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1600_64A); + &ddr3phy_1600_8g); } ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_64); + &ddr3_1600_8g); printf("DRAM: Capacity 8 GiB (includes reported below)\n"); } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_1600_8g.sdcfg |= 0x1000; ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1600_32); + &ddr3_1600_8g); printf("DRAM: Capacity 4 GiB (includes reported below)\n"); } } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { @@ -323,27 +58,27 @@ void ddr3_init(void) /* PG 2.0 */ /* Reset DDR3A PHY after PLL enabled */ ddr3_reset_ddrphy(); + ddr3phy_1333_2g.zq0cr1 |= 0x10000; + ddr3phy_1333_2g.zq1cr1 |= 0x10000; + ddr3phy_1333_2g.zq2cr1 |= 0x10000; ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A_pg2); + &ddr3phy_1333_2g); } else { /* PG 1.1 */ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, - &ddr3phy_1333_64A); + &ddr3phy_1333_2g); } ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_64); + &ddr3_1333_2g); } else { - ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); + ddr3_1333_2g.sdcfg |= 0x1000; ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, - &ddr3_1333_32); + &ddr3_1333_2g); } } else { printf("Unknown SO-DIMM. Cannot configure DDR3\n"); while (1) ; } - - init_pll(&ddr3b_333); - ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64); - ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); } -- cgit v1.2.1 From 5c76f78858054e27c6c21e34307003b3649c61ae Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 16 Jul 2014 00:59:22 +0300 Subject: ARM: keystone2: add K2E SoC hardware definitions This patch adds hardware definitions specific to Keystone II K2E device. It has a lot common definitions with k2hk SoC, so move them to common hardware.h. This is preparation patch for adding K2E SoC support. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 44 ++++++++++++++++ arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 44 ---------------- arch/arm/include/asm/arch-keystone/hardware.h | 61 ++++++++++++++++++++++ 3 files changed, 105 insertions(+), 44 deletions(-) create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2e.h diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h new file mode 100644 index 0000000000..62172a4b84 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -0,0 +1,44 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index e7dff059b8..eb132f73e6 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -10,46 +10,16 @@ #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define KS2_PLL_CNTRL_BASE 0x02310000 -#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE -#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) -#define KS2_RSTCTRL_KEY 0x5a69 -#define KS2_RSTCTRL_MASK 0xffff0000 -#define KS2_RSTCTRL_SWRST 0xfffe0000 - -#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 -#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) -#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) - #define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) #define KS2_ARM_PLL_EN BIT(13) -#define KS2_SPI0_BASE 0x21000400 -#define KS2_SPI1_BASE 0x21000600 -#define KS2_SPI2_BASE 0x21000800 -#define KS2_SPI_BASE KS2_SPI0_BASE - -/* Chip configuration unlock codes and registers */ -#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) -#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) -#define KS2_KICK0_MAGIC 0x83e70b13 -#define KS2_KICK1_MAGIC 0x95a4f1e0 - /* PA SS Registers */ #define KS2_PASS_BASE 0x02000000 /* PLL control registers */ -#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) -#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) -#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) -#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) -#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) -#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) #define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) -#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) -#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_MOD 0 @@ -106,25 +76,11 @@ #define KS2_LPSC_XGE 50 #define KS2_LPSC_ARM_SREFLEX 51 -/* DDR3A definitions */ -#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 -#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 -#define KS2_DDR3A_DDRPHYC 0x02329000 /* DDR3B definitions */ #define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000 #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 #define KS2_DDR3B_DDRPHYC 0x02328000 -/* Queue manager */ -#define KS2_QM_MANAGER_BASE 0x02a02000 -#define KS2_QM_DESC_SETUP_BASE 0x02a03000 -#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 -#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 -#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 - -/* MSMC control */ -#define KS2_MSMC_CTRL_BASE 0x0bc00000 - /* Number of DSP cores */ #define KS2_NUM_DSPS 8 diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 133edadc2a..9c86b695b4 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -69,6 +69,11 @@ typedef volatile unsigned int *dv_reg_p; #define NOSRA_MASK 0x08000000 #define ECC_MASK 0x00000001 +/* DDR3 definitions */ +#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000 +#define KS2_DDR3A_DDRPHYC 0x02329000 + #define KS2_DDR3_MIDR_OFFSET 0x00 #define KS2_DDR3_STATUS_OFFSET 0x04 #define KS2_DDR3_SDCFG_OFFSET 0x08 @@ -85,12 +90,46 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 +/* Boot Config */ +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) + /* PSC */ #define KS2_PSC_BASE 0x02350000 #define KS2_LPSC_GEM_0 15 #define KS2_LPSC_TETRIS 52 #define KS2_TETRIS_PWR_DOMAIN 31 +/* Chip configuration unlock codes and registers */ +#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KS2_KICK0_MAGIC 0x83e70b13 +#define KS2_KICK1_MAGIC 0x95a4f1e0 + +/* PLL control registers */ +#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) + +#define KS2_PLL_CNTRL_BASE 0x02310000 +#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 + +/* SPI */ +#define KS2_SPI0_BASE 0x21000400 +#define KS2_SPI1_BASE 0x21000600 +#define KS2_SPI2_BASE 0x21000800 +#define KS2_SPI_BASE KS2_SPI0_BASE + /* AEMIF */ #define KS2_AEMIF_CNTRL_BASE 0x21000a00 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE @@ -98,10 +137,24 @@ typedef volatile unsigned int *dv_reg_p; /* Flag from ks2_debug options to check if DSPs need to stay ON */ #define DBG_LEAVE_DSPS_ON 0x1 +/* Queue manager */ +#define KS2_QM_MANAGER_BASE 0x02a02000 +#define KS2_QM_DESC_SETUP_BASE 0x02a03000 +#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 +#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 + +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc00000 + #ifdef CONFIG_SOC_K2HK #include #endif +#ifdef CONFIG_SOC_K2E +#include +#endif + #ifndef __ASSEMBLY__ static inline int cpu_is_k2hk(void) { @@ -111,6 +164,14 @@ static inline int cpu_is_k2hk(void) return (part_no == 0xb981) ? 1 : 0; } +static inline int cpu_is_k2e(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a6) ? 1 : 0; +} + static inline int cpu_revision(void) { unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); -- cgit v1.2.1 From 4dca7f0acc88708100a2b25b019befc9eea02f45 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 16 Jul 2014 00:59:23 +0300 Subject: ARM: keystone2: clock: add K2E clock support This patch adds clock definitions and commands to support Keystone2 K2E SOC. Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Makefile | 1 + arch/arm/cpu/armv7/keystone/clock-k2e.c | 101 +++++++++++++++++++++++++ arch/arm/cpu/armv7/keystone/clock.c | 2 + arch/arm/cpu/armv7/keystone/cmd_clock.c | 31 ++++++-- arch/arm/include/asm/arch-keystone/clock-k2e.h | 68 +++++++++++++++++ arch/arm/include/asm/arch-keystone/clock.h | 4 + include/configs/ks2_evm.h | 2 +- 7 files changed, 203 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index 74c516013a..f8519c0403 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -9,6 +9,7 @@ obj-y += init.o obj-y += psc.o obj-y += clock.o obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o +obj-$(CONFIG_SOC_K2E) += clock-k2e.o obj-y += cmd_clock.o obj-y += cmd_mon.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c new file mode 100644 index 0000000000..42092e1060 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c @@ -0,0 +1,101 @@ +/* + * Keystone2: get clk rate for K2E + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +const struct keystone_pll_regs keystone_pll_regs[] = { + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1}, + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1}, + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1}, +}; + +/** + * pll_freq_get - get pll frequency + * Fout = Fref * NF(mult) / NR(prediv) / OD + * @pll: pll identifier + */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(KS2_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = KS2_PASSPLLCTL0; + break; + case DDR3_PLL: + ret = external_clk[ddr3_clk]; + reg = KS2_DDR3APLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + + return 0; +} diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index 42b664b576..03c1d9f660 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -106,6 +106,7 @@ void init_pll(const struct pll_init_data *data) tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); +#ifndef CONFIG_SOC_K2E } else if (data->pll == TETRIS_PLL) { bwadj = pllm >> 1; /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ @@ -156,6 +157,7 @@ void init_pll(const struct pll_init_data *data) * only applicable for Kepler */ setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN); +#endif } else { setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT); /* diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c index afd30f3853..d97c95be11 100644 --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c @@ -14,10 +14,10 @@ #include struct pll_init_data cmd_pll_data = { - .pll = MAIN_PLL, - .pll_m = 16, - .pll_d = 1, - .pll_od = 2, + .pll = MAIN_PLL, + .pll_m = 16, + .pll_d = 1, + .pll_od = 2, }; int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (strncmp(argv[1], "pa", 2) == 0) cmd_pll_data.pll = PASS_PLL; +#ifndef CONFIG_SOC_K2E else if (strncmp(argv[1], "arm", 3) == 0) cmd_pll_data.pll = TETRIS_PLL; +#endif +#ifdef CONFIG_SOC_K2HK else if (strncmp(argv[1], "ddr3a", 5) == 0) cmd_pll_data.pll = DDR3A_PLL; else if (strncmp(argv[1], "ddr3b", 5) == 0) cmd_pll_data.pll = DDR3B_PLL; +#else + else if (strncmp(argv[1], "ddr3", 4) == 0) + cmd_pll_data.pll = DDR3_PLL; +#endif else goto pll_cmd_usage; @@ -51,11 +58,20 @@ pll_cmd_usage: return cmd_usage(cmdtp); } +#ifdef CONFIG_SOC_K2HK U_BOOT_CMD( pllset, 5, 0, do_pll_cmd, "set pll multiplier and pre divider", "
\n" ); +#endif +#ifdef CONFIG_SOC_K2E +U_BOOT_CMD( + pllset, 5, 0, do_pll_cmd, + "set pll multiplier and pre divider", + "
\n" +); +#endif int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -79,7 +95,12 @@ U_BOOT_CMD( getclk, 2, 0, do_getclk_cmd, "get clock rate", "\n" - "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n" +#ifdef CONFIG_SOC_K2HK + "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n" +#endif +#ifdef CONFIG_SOC_K2E + "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n" +#endif ); int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h new file mode 100644 index 0000000000..41478110e5 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h @@ -0,0 +1,68 @@ +/* + * K2E: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2E_H +#define __ASM_ARCH_CLOCK_K2E_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + ddr3_clk, + mcm_clk, + pcie_clk, + sgmii_clk, + xgmii_clk, + usb_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +enum clk_e { + core_pll_clk, + pass_pll_clk, + ddr3_pll_clk, + sys_clk0_clk, + sys_clk0_1_clk, + sys_clk0_2_clk, + sys_clk0_3_clk, + sys_clk0_4_clk, + sys_clk0_6_clk, + sys_clk0_8_clk, + sys_clk0_12_clk, + sys_clk0_24_clk, + sys_clk1_clk, + sys_clk1_3_clk, + sys_clk1_4_clk, + sys_clk1_6_clk, + sys_clk1_12_clk, + sys_clk2_clk, + sys_clk3_clk +}; + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + DDR3_PLL, +}; + +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2} +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2} +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h index c7da3520c4..1513c76b6a 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -16,6 +16,10 @@ #include #endif +#ifdef CONFIG_SOC_K2E +#include +#endif + #define MAIN_PLL CORE_PLL #include diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 29f0b9b621..43db581c75 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -80,7 +80,7 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI #define CONFIG_CMD_SPI -#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI) +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #define CONFIG_SYS_SPI0 -- cgit v1.2.1 From 20187fd11c37226fac8661bbac96ddd4fdf507b1 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 16 Jul 2014 00:59:24 +0300 Subject: ARM: keystone2: add MSMC cache coherency support for K2E SOC This patch adds Keystone2 K2E SOC specific code to support MSMC cache coherency. Also create header file for msmc to hold its API. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/init.c | 12 +++++++----- arch/arm/cpu/armv7/keystone/msmc.c | 4 ++-- arch/arm/include/asm/arch-keystone/hardware.h | 1 - arch/arm/include/asm/arch-keystone/msmc.h | 17 +++++++++++++++++ 4 files changed, 26 insertions(+), 8 deletions(-) create mode 100644 arch/arm/include/asm/arch-keystone/msmc.h diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c index f4c293aa89..a8f8aee8ab 100644 --- a/arch/arm/cpu/armv7/keystone/init.c +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -24,11 +25,12 @@ int arch_cpu_init(void) chip_configuration_unlock(); icache_enable(); -#ifdef CONFIG_SOC_K2HK - share_all_segments(8); - share_all_segments(9); - share_all_segments(10); /* QM PDSP */ - share_all_segments(11); /* PCIE */ + msmc_share_all_segments(8); /* TETRIS */ + msmc_share_all_segments(9); /* NETCP */ + msmc_share_all_segments(10); /* QM PDSP */ + msmc_share_all_segments(11); /* PCIE 0 */ +#ifdef CONFIG_SOC_K2E + msmc_share_all_segments(13); /* PCIE 1 */ #endif /* diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c index af858fa758..7d8e5978df 100644 --- a/arch/arm/cpu/armv7/keystone/msmc.c +++ b/arch/arm/cpu/armv7/keystone/msmc.c @@ -8,7 +8,7 @@ */ #include -#include +#include struct mpax { u32 mpaxl; @@ -56,7 +56,7 @@ struct msms_regs { }; -void share_all_segments(int priv_id) +void msmc_share_all_segments(int priv_id) { struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE; int j; diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 9c86b695b4..bcfb5517ea 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -180,7 +180,6 @@ static inline int cpu_revision(void) return rev; } -void share_all_segments(int priv_id); int cpu_to_bus(u32 *ptr, u32 length); void sdelay(unsigned long); diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h new file mode 100644 index 0000000000..c320db5b65 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/msmc.h @@ -0,0 +1,17 @@ +/* + * MSMC controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MSMC_H_ +#define _MSMC_H_ + +#include + +void msmc_share_all_segments(int priv_id); + +#endif -- cgit v1.2.1 From 7c387646060c6221836b332f5d0e0c9771ab99c1 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 16 Jul 2014 00:59:25 +0300 Subject: keystone2: use CONFIG_SOC_KEYSTONE in common places Use CONFIG_SOC_KEYSTONE in common places instead of defining a lot of "if def .. || if def " for different Keystone2 SoC types. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- common/image-fdt.c | 2 +- drivers/serial/ns16550.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common/image-fdt.c b/common/image-fdt.c index 9fc7481fd8..7795b80ccf 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -492,7 +492,7 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, if (!ft_verify_fdt(blob)) return -1; -#ifdef CONFIG_SOC_K2HK +#if defined(CONFIG_SOC_KEYSTONE) if (IMAGE_OF_BOARD_SETUP) ft_board_setup_ex(blob, gd->bd); #endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index f26979dbe1..8e7052dda7 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -30,7 +30,7 @@ #define serial_in(y) readb(y) #endif -#if defined(CONFIG_K2HK_EVM) +#if defined(CONFIG_SOC_KEYSTONE) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) #undef UART_MCRVAL @@ -88,7 +88,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif /* CONFIG_OMAP */ -#if defined(CONFIG_K2HK_EVM) +#if defined(CONFIG_SOC_KEYSTONE) serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); #endif } -- cgit v1.2.1 From 1284246eb97769b0da5483fb92a8c0940b46b739 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 16 Jul 2014 00:59:26 +0300 Subject: ARM: keystone2: spl: add K2E SoC support Keystone2 K2E SoC has slightly different spl pll settings then K2HK, so correct this. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/spl.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv7/keystone/spl.c b/arch/arm/cpu/armv7/keystone/spl.c index e07b64db9e..d4b0e9b163 100644 --- a/arch/arm/cpu/armv7/keystone/spl.c +++ b/arch/arm/cpu/armv7/keystone/spl.c @@ -18,10 +18,18 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_K2HK_EVM static struct pll_init_data spl_pll_config[] = { CORE_PLL_799, TETRIS_PLL_500, }; +#endif + +#ifdef CONFIG_K2E_EVM +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_800, +}; +#endif void spl_init_keystone_plls(void) { -- cgit v1.2.1 From a906847966fd097835712b2ad3b5bac340793d43 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 16 Jul 2014 00:59:27 +0300 Subject: board: k2e-evm: add board support This patch adds Keystone2 k2e_evm evaluation board support. Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/hardware.h | 1 + board/ti/ks2_evm/Makefile | 2 + board/ti/ks2_evm/board_k2e.c | 39 +++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.c | 40 +++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.h | 3 ++ board/ti/ks2_evm/ddr3_k2e.c | 55 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/k2e_evm.h | 37 ++++++++++++++++++ 8 files changed, 178 insertions(+) create mode 100644 board/ti/ks2_evm/board_k2e.c create mode 100644 board/ti/ks2_evm/ddr3_k2e.c create mode 100644 include/configs/k2e_evm.h diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index bcfb5517ea..ddeb06e7bb 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -119,6 +119,7 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_PLL_CNTRL_BASE 0x02310000 #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE +#define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) #define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) #define KS2_RSTCTRL_KEY 0x5a69 #define KS2_RSTCTRL_MASK 0xffff0000 diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 774a7d526c..00f1164833 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -9,3 +9,5 @@ obj-y += board.o obj-y += ddr3_cfg.o obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o +obj-$(CONFIG_K2E_EVM) += board_k2e.o +obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c new file mode 100644 index 0000000000..d2499b7244 --- /dev/null +++ b/board/ti/ks2_evm/board_k2e.c @@ -0,0 +1,39 @@ +/* + * K2E EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 100000000, + [alt_core_clk] = 100000000, + [pa_clk] = 100000000, + [ddr3_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1200, + PASS_PLL_1000, +}; + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index 6e55af924f..f7da9f2bcb 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -93,6 +93,46 @@ struct ddr3_emif_config ddr3_1333_2g = { }; #endif +#ifdef CONFIG_K2E_EVM +/* DDR3 PHY configuration data with 1600M rate, and 4GB size */ +struct ddr3_phy_config ddr3phy_1600_4g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x08861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D9CBB66ul, + .dtpr1 = 0x12840300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */ +struct ddr3_emif_config ddr3_1600_4g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x421DFF53ul, + .sdtim4 = 0x543F07FFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; +#endif + int ddr3_get_dimm_params(char *dimm_name) { int ret; diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h index d14bac3640..15fcf52ef1 100644 --- a/board/ti/ks2_evm/ddr3_cfg.h +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -16,6 +16,9 @@ extern struct ddr3_emif_config ddr3_1600_8g; extern struct ddr3_phy_config ddr3phy_1333_2g; extern struct ddr3_emif_config ddr3_1333_2g; +extern struct ddr3_phy_config ddr3phy_1600_4g; +extern struct ddr3_emif_config ddr3_1600_4g; + int ddr3_get_dimm_params(char *dimm_name); #endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c new file mode 100644 index 0000000000..40fd96607d --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -0,0 +1,55 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "ddr3_cfg.h" +#include + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + char dimm_name[32]; + + if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) + init_pll(&ddr3_400); + + ddr3_get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + /* 8G SO-DIMM */ + ddr3_size = 8; + printf("DRAM: 8 GiB\n"); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); + } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) { + /* 4G SO-DIMM */ + ddr3_size = 4; + printf("DRAM: 4 GiB\n"); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); + } +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/boards.cfg b/boards.cfg index f7fbd54890..6ff8e8c618 100644 --- a/boards.cfg +++ b/boards.cfg @@ -301,6 +301,7 @@ Active arm armv7 exynos samsung trats2 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak Active arm armv7 highbank - highbank highbank - Rob Herring Active arm armv7 keystone ti ks2_evm k2hk_evm - Vitaly Andrianov +Active arm armv7 keystone ti ks2_evm k2e_evm - Vitaly Andrianov Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h new file mode 100644 index 0000000000..3502d10472 --- /dev/null +++ b/include/configs/k2e_evm.h @@ -0,0 +1,37 @@ +/* + * Configuration header file for TI's k2e-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2E_EVM_H +#define __CONFIG_K2E_EVM_H + +/* Platform type */ +#define CONFIG_SOC_K2E +#define CONFIG_K2E_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2E EVM # " + +#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" + +#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0" +#define KS2_ADDR_MON "addr_mon=0x0c140000\0" +#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0" +#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0" +#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0" + +#include + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c100000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_2K + +#endif /* __CONFIG_K2E_EVM_H */ -- cgit v1.2.1 From 8c16dd6fa7de448b36778275b456bf4ea53c3306 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Fri, 18 Jul 2014 11:18:48 +0530 Subject: ARM: OMAP: Fix handling of errata i727 The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5 ES 1.0 devices. The current revision check erroneously implements this on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance) infact causes an asynchronous abort and ends up masking it in CPSR, only to be uncovered once the kernel switches to userspace. Signed-off-by: Rajendra Nayak Signed-off-by: Sricharan R Signed-off-by: Lokesh Vutla --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 3 ++- arch/arm/include/asm/omap_common.h | 8 ++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 5f50a19801..1b4477f469 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -123,7 +123,8 @@ void s_init(void) hw_data_init(); #ifdef CONFIG_SPL_BUILD - if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) + if (warm_reset() && + (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0))) force_emif_self_refresh(); #endif watchdog_init(); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index d1344ee94c..183823404d 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -595,6 +595,14 @@ static inline u32 omap_revision(void) return *omap_si_rev; } +#define OMAP44xx 0x44000000 + +static inline u8 is_omap44xx(void) +{ + extern u32 *const omap_si_rev; + return (*omap_si_rev & 0xFF000000) == OMAP44xx; +}; + #define OMAP54xx 0x54000000 static inline u8 is_omap54xx(void) -- cgit v1.2.1 From 77cd89e75563742aa32cf3d216ac9ff649d1d70e Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 18 Jul 2014 17:59:40 +0530 Subject: ARM: omap: fix GPMC address-map size for NAND and NOR devices Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform 1) NAND device are not directly memory-mapped to CPU address-space, they are indirectly accessed via following GPMC registers: - GPMC_NAND_COMMAND_x - GPMC_NAND_ADDRESS_x - GPMC_NAND_DATA_x Therefore from CPU's point of view, NAND address-map can be limited to just above register addresses. But GPMC chip-select address-map can be configured in granularity of 16MB only. So this patch uses GPMC_SIZE_16M for all NAND devices. 2) NOR device are directly memory-mapped to CPU address-space, so its address-map size depends on actual addressable region in NOR FLASH device. So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map size configuration. Signed-off-by: Pekon Gupta --- arch/arm/cpu/armv7/omap-common/mem-common.c | 9 +++++++-- include/configs/am335x_evm.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index ba26cd1fdb..e9da70fe70 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -87,8 +87,12 @@ void gpmc_init(void) STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; - u32 size = GPMC_SIZE_16M; u32 base = CONFIG_SYS_FLASH_BASE; + u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + /* min 16MB */ GPMC_SIZE_16M))); #elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) /* configure GPMC for NAND */ const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, @@ -99,8 +103,9 @@ void gpmc_init(void) M_NAND_GPMC_CONFIG6, 0 }; - u32 size = GPMC_SIZE_256M; u32 base = CONFIG_SYS_NAND_BASE; + u32 size = GPMC_SIZE_16M; + #elif defined(CONFIG_CMD_ONENAND) const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, ONENAND_GPMC_CONFIG2, diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index a48b386477..c1a6ada0a8 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -453,6 +453,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_FLASH_BASE (0x08000000) #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_FLASH_SIZE 0x01000000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Reduce SPL size by removing unlikey targets */ #ifdef CONFIG_NOR_BOOT -- cgit v1.2.1 From 222a3113b46c4a16de3f51747201ca6565c8ee6a Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 18 Jul 2014 17:59:41 +0530 Subject: ARM: omap: clean redundant PISMO_xx macros used in OMAP3 PISMO_xx macros were used to define 'Platform Independent Storage MOdule' related GPMC configurations. This patch - Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided by current u-boot infrastructure. - Removes unused redundant macros, which are no longer required after merging of common platform code in following commit commit a0a37183bd75e74608bc78c8d0e2a34454f95a91 ARM: omap: merge GPMC initialization code for all platform +-----------------+-----------------------------------------------------------+ | Macro | Reason for removal | +-----------------+-----------------------------------------------------------+ | PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE | +-----------------+-----------------------------------------------------------+ | PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so | | | configuring GPMC chip-select for smallest allowable | | | segment (GPMC_SIZE_16M) is enough. | +-----------------+-----------------------------------------------------------+ | PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of | | | 128MB (GPMC_SIZE_128M) | +-----------------+-----------------------------------------------------------+ +-----------------+-----------------------------------------------------------+ | PISMO1_NOR | Unused Macros | | PISMO1_NAND | | | PISMO2_CS0 | | | PISMO2_CS1 | | | PISMO1_ONENAND | | | PISMO2_NAND_CS0 | | | PISMO2_NAND_CS1 | | | PISMO1_NOR_BASE | | | PISMO1_NAND_BASE| | | PISMO2_CS0_BASE | | +-----------------+-----------------------------------------------------------+ Signed-off-by: Pekon Gupta --- arch/arm/cpu/armv7/omap-common/mem-common.c | 4 ++-- arch/arm/include/asm/arch-am33xx/mem.h | 7 ------- arch/arm/include/asm/arch-omap3/cpu.h | 1 - arch/arm/include/asm/arch-omap3/mem.h | 13 ------------- include/configs/am3517_crane.h | 7 +------ include/configs/am3517_evm.h | 7 +------ include/configs/cm_t35.h | 3 --- include/configs/devkit8000.h | 2 -- include/configs/dig297.h | 4 ---- include/configs/mcx.h | 4 ---- include/configs/nokia_rx51.h | 2 -- include/configs/omap3_beagle.h | 7 +------ include/configs/omap3_evm_common.h | 7 ++----- include/configs/omap3_igep00x0.h | 3 --- include/configs/omap3_logic.h | 8 ++------ include/configs/omap3_overo.h | 6 +----- include/configs/omap3_pandora.h | 7 +------ include/configs/omap3_zoom1.h | 7 +------ include/configs/tam3517-common.h | 4 ---- include/configs/tao3530.h | 7 +------ include/configs/tricorder.h | 2 -- 21 files changed, 13 insertions(+), 99 deletions(-) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index e9da70fe70..fc4290c3c4 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -115,8 +115,8 @@ void gpmc_init(void) ONENAND_GPMC_CONFIG6, 0 }; - u32 base = PISMO1_ONEN_BASE; - u32 size = PISMO1_ONEN_SIZE; + u32 size = GPMC_SIZE_128M; + u32 base = CONFIG_SYS_ONENAND_BASE; #else const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; u32 size = 0; diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index e7e8c58b00..b2412b56e1 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -59,13 +59,6 @@ /* max number of GPMC regs */ #define GPMC_MAX_REG 7 -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 #define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 #endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 4d06ef83fe..53cc2b098a 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -98,7 +98,6 @@ struct ctrl_id { #define DEBUG_BASE 0x08000000 /* debug board */ #define NAND_BASE 0x30000000 /* NAND addr */ /* (actual size small port) */ -#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ #define ONENAND_MAP 0x20000000 /* OneNand addr */ /* (actual size small port) */ /* SMS */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index d2dfb1e19a..0b78c1ca60 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -427,20 +427,7 @@ enum { /* max number of GPMC regs */ #define GPMC_MAX_REG 7 -#define PISMO1_NOR 1 -#define PISMO1_NAND 2 -#define PISMO2_CS0 3 -#define PISMO2_CS1 4 -#define PISMO1_ONENAND 5 #define DBG_MPDB 6 -#define PISMO2_NAND_CS0 7 -#define PISMO2_NAND_CS1 8 - -/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE NAND_BASE -#define PISMO2_CS0_BASE PISMO2_MAP1 -#define PISMO1_ONEN_BASE ONENAND_MAP #define DBG_MPDB_BASE DEBUG_BASE #ifndef __ASSEMBLY__ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index ad4cbd88b8..d826214efe 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -252,17 +252,12 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 0102ff5b7f..a9c5a8f3af 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -259,18 +259,13 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 5c484ef078..d8d71a94ee 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -258,9 +258,6 @@ */ /* **** PISMO SUPPORT *** */ -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 5308790fe6..cc53fc9cd7 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -262,8 +262,6 @@ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* NAND and environment organization */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_ENV_IS_IN_NAND 1 diff --git a/include/configs/dig297.h b/include/configs/dig297.h index ce205e9b3e..7e47c56453 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -251,10 +251,6 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 47244c0034..75abb602cf 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -316,10 +316,6 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index e0c0fac8e1..216dbef192 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -220,8 +220,6 @@ #ifdef ONENAND_SUPPORT -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c02348354a..e951389d3b 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -265,13 +265,8 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index ae4ce63f67..739d392edc 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -95,9 +95,6 @@ /* * PISMO support */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - /* Monitor at start of flash - Reserve 2 sectors */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -205,12 +202,12 @@ * NAND / OneNAND */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #endif diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 79daabd6bb..0bb79ab6b5 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -146,8 +146,6 @@ */ #ifdef CONFIG_BOOT_ONENAND -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */ - #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -158,7 +156,6 @@ #endif #ifdef CONFIG_NAND -#define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 8dcbba3c40..717c935d2c 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -277,16 +277,12 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP #endif /* Monitor at start of flash */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index f7483a0827..38f8dabb2d 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -173,12 +173,8 @@ 0x01F00000) /* 31MB */ /* FLASH and environment organization */ -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index da67787e69..c22c1fc6aa 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -220,15 +220,10 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 3efe4cf815..236281aa0f 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -165,13 +165,8 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #endif /* Monitor at start of flash */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 0c2f0f19c8..aa0ea162d2 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -181,10 +181,6 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_ENV_IS_IN_NAND diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 62613e1eaa..9fc31bed6a 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -254,13 +254,8 @@ */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define PISMO1_ONEN_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 847e099512..6c2f65305f 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -317,8 +317,6 @@ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* NAND and environment organization */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -- cgit v1.2.1 From 434f2cfcad9f70231ad5a096325ba72ef0d2a2cc Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 18 Jul 2014 17:59:42 +0530 Subject: ARM: omap: move board specific NAND configs out from ti_armv7_common.h This patch moves some board specific NAND configs: - FROM: generic config file 'ti_armv7_common.h' - TO: individual board config files using these configs. So that each board can independently set the value as per its design. Following configs are affected in this patch: CONFIG_SYS_NAND_U_BOOT_OFFS: CONFIG_CMD_SPL_NAND_OFS: CONFIG_SYS_NAND_SPL_KERNEL_OFFS: CONFIG_CMD_SPL_WRITE_SIZE: This patch also updates documentation for few of above NAND configs. Signed-off-by: Pekon Gupta --- doc/README.nand | 12 ++++++++++++ include/configs/am335x_evm.h | 5 +++++ include/configs/cm_t335.h | 5 +++++ include/configs/omap3_beagle.h | 6 ++++++ include/configs/omap3_igep00x0.h | 7 +++++++ include/configs/omap3_overo.h | 6 ++++++ include/configs/omap3_zoom1.h | 6 ++++++ include/configs/pengwyn.h | 6 ++++++ include/configs/ti_armv7_common.h | 8 -------- 9 files changed, 53 insertions(+), 8 deletions(-) diff --git a/doc/README.nand b/doc/README.nand index 70cf768d23..e29188f1ec 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -89,6 +89,10 @@ Commands: Configuration Options: + CONFIG_SYS_NAND_U_BOOT_OFFS + NAND Offset from where SPL will read u-boot image. This is the starting + address of u-boot MTD partition in NAND. + CONFIG_CMD_NAND Enables NAND support and commmands. @@ -226,6 +230,14 @@ Platform specific options detection. However ECC calculation on such plaforms would still be done by GPMC controller. + CONFIG_SPL_NAND_AM33XX_BCH + Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based + hardware ECC correction. This is useful for platforms which have ELM + hardware engine and use NAND boot mode. + Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine, + so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling + SPL-NAND driver with software ECC correction support. + CONFIG_NAND_OMAP_ECCSCHEME On OMAP platforms, this CONFIG specifies NAND ECC scheme. It can take following values: diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c1a6ada0a8..f5bfd5d627 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -254,6 +254,11 @@ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os parameters */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif #endif diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 4d1dd28a91..a3e6452ec1 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -150,6 +150,11 @@ #define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_SYS_NAND_ONFI_DETECTION +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x400000 /* un-assigned: (using dtb) */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* GPIO pin + bank to pin ID mapping */ #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index e951389d3b..fe07990640 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -303,5 +303,11 @@ #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 0bb79ab6b5..006c9a9c0d 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -196,6 +196,13 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif #endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 38f8dabb2d..e66f30655d 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -216,5 +216,11 @@ #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 236281aa0f..93f4d627a1 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -70,6 +70,12 @@ "4m(kernel),-(fs)" #if defined(CONFIG_CMD_NAND) +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ #endif diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 85104057a9..4684ad6852 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -159,6 +159,12 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* un-assigned */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif /* * USB configuration. We enable MUSB support, both for host and for diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 6e0bf09058..85c027c1d2 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -243,13 +243,6 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ -/* NAND */ -#ifdef CONFIG_NAND -#define CONFIG_CMD_SPL_NAND_OFS 0x240000 /* end of u-boot */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 -#endif - /* spl export command */ #define CONFIG_CMD_SPL #endif @@ -275,7 +268,6 @@ #define CONFIG_SPL_NAND_ECC #define CONFIG_SPL_MTD_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif #endif /* !CONFIG_NOR_BOOT */ -- cgit v1.2.1 From c19e0dd7412f5c4bce8c5057c40e747b1acb39e2 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:23:58 +0100 Subject: ARM: HYP/non-sec: move switch to non-sec to the last boot phase Having the switch to non-secure in the "prep" phase is causing all kind of troubles, as that stage can be called multiple times. Instead, move the switch to non-secure to the last possible phase, when there is no turning back anymore. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/lib/bootm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 47ee070593..304210effd 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -242,7 +242,6 @@ static void boot_prep_linux(bootm_headers_t *images) printf("FDT and ATAGS support not compiled in - hanging\n"); hang(); } - do_nonsec_virt_switch(); } /* Subcommand: GO */ @@ -260,8 +259,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) announce_and_cleanup(fake); - if (!fake) + if (!fake) { + do_nonsec_virt_switch(); kernel_entry(images->ft_addr); + } #else unsigned long machid = gd->bd->bi_arch_number; char *s; @@ -287,8 +288,10 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) else r2 = gd->bd->bi_boot_params; - if (!fake) + if (!fake) { + do_nonsec_virt_switch(); kernel_entry(0, machid, r2); + } #endif } -- cgit v1.2.1 From 800c83522ca6a7d6fd0b058f423501b4cc52d6d6 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:23:59 +0100 Subject: ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/nonsec_virt.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 6367e09612..12de5c2d17 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -46,6 +46,7 @@ _secure_monitor: #endif mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) + isb #ifdef CONFIG_ARMV7_VIRT mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value -- cgit v1.2.1 From 64fd44dcae0daafb011f98d4b2d4e1f28036b99e Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:00 +0100 Subject: ARM: non-sec: reset CNTVOFF to zero Before switching to non-secure, make sure that CNTVOFF is set to zero on all CPUs. Otherwise, kernel running in non-secure without HYP enabled (hence using virtual timers) may observe timers that are not synchronized, effectively seeing time going backward... Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/nonsec_virt.S | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 12de5c2d17..b5c946fc4e 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -38,10 +38,10 @@ _secure_monitor: bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits orr r1, r1, #0x31 @ enable NS, AW, FW bits -#ifdef CONFIG_ARMV7_VIRT mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) +#ifdef CONFIG_ARMV7_VIRT orreq r1, r1, #0x100 @ allow HVC instruction #endif @@ -52,7 +52,14 @@ _secure_monitor: mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR #endif + bne 1f + @ Reset CNTVOFF to 0 before leaving monitor mode + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + ands r0, r0, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits + movne r0, #0 + mcrrne p15, 4, r0, r0, c14 @ Reset CNTVOFF to zero +1: movs pc, lr @ return to non-secure SVC _hyp_trap: -- cgit v1.2.1 From b726d22da9aed61462e36aa722fa4e6fd0aec9f1 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:01 +0100 Subject: ARM: add missing HYP mode constant In order to be able to use the various mode constants (far more readable than random hex values), add the missing HYP and A values. Also update arm/lib/interrupts.c to display HYP instead of an unknown value. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/include/asm/proc-armv/ptrace.h | 2 ++ arch/arm/lib/interrupts.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/proc-armv/ptrace.h b/arch/arm/include/asm/proc-armv/ptrace.h index 21aef58b7b..71df5a9e25 100644 --- a/arch/arm/include/asm/proc-armv/ptrace.h +++ b/arch/arm/include/asm/proc-armv/ptrace.h @@ -38,12 +38,14 @@ struct pt_regs { #define IRQ_MODE 0x12 #define SVC_MODE 0x13 #define ABT_MODE 0x17 +#define HYP_MODE 0x1a #define UND_MODE 0x1b #define SYSTEM_MODE 0x1f #define MODE_MASK 0x1f #define T_BIT 0x20 #define F_BIT 0x40 #define I_BIT 0x80 +#define A_BIT 0x100 #define CC_V_BIT (1 << 28) #define CC_C_BIT (1 << 29) #define CC_Z_BIT (1 << 30) diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 758b01371e..f6b7c03578 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -103,7 +103,7 @@ void show_regs (struct pt_regs *regs) "UK12_26", "UK13_26", "UK14_26", "UK15_26", "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32", "UK6_32", "ABT_32", - "UK8_32", "UK9_32", "UK10_32", "UND_32", + "UK8_32", "UK9_32", "HYP_32", "UND_32", "UK12_32", "UK13_32", "UK14_32", "SYS_32", }; -- cgit v1.2.1 From bf433afd60ce2ccd1bec3cf14150323be8272ac3 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:02 +0100 Subject: ARM: HYP/non-sec: add separate section for secure code In anticipation of refactoring the HYP/non-secure code to run from secure RAM, add a new linker section that will contain that code. Nothing is using it just yet. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/config.mk | 2 +- arch/arm/cpu/u-boot.lds | 30 ++++++++++++++++++++++++++++++ arch/arm/lib/sections.c | 2 ++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 5fa182536d..c3b8289dcf 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -113,7 +113,7 @@ endif ifdef CONFIG_ARM64 OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn else -OBJCOPYFLAGS += -j .text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn +OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j .got.plt -j .u_boot_list -j .rel.dyn endif ifdef CONFIG_OF_EMBED diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index a7728e0a2d..7336162d80 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -7,6 +7,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include + OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) ENTRY(_start) @@ -23,6 +25,34 @@ SECTIONS *(.text*) } +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) || defined(CONFIG_ARMV7_PSCI) + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define CONFIG_ARMV7_SECURE_BASE +#endif + + .__secure_start : { + . = ALIGN(0x1000); + *(.__secure_start) + } + + .secure_text CONFIG_ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + . = LOADADDR(.__secure_start) + + SIZEOF(.__secure_start) + + SIZEOF(.secure_text); + + __secure_end_lma = .; + .__secure_end : AT(__secure_end_lma) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index 5b30bcb9a5..a1205c370d 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -25,4 +25,6 @@ char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); +char __secure_start[0] __attribute__((section(".__secure_start"))); +char __secure_end[0] __attribute__((section(".__secure_end"))); char _end[0] __attribute__((section(".__end"))); -- cgit v1.2.1 From f510aeae689925a660bff14683eef4147785d271 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:03 +0100 Subject: ARM: HYP/non-sec: allow relocation to secure RAM The current non-sec switching code suffers from one major issue: it cannot run in secure RAM, as a large part of u-boot still needs to be run while we're switched to non-secure. This patch reworks the whole HYP/non-secure strategy by: - making sure the secure code is the *last* thing u-boot executes before entering the payload - performing an exception return from secure mode directly into the payload - allowing the code to be dynamically relocated to secure RAM before switching to non-secure. This involves quite a bit of horrible code, specially as u-boot relocation is quite primitive. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/nonsec_virt.S | 161 +++++++++++++++++++-------------------- arch/arm/cpu/armv7/virt-v7.c | 59 +++++--------- arch/arm/include/asm/armv7.h | 10 ++- arch/arm/include/asm/secure.h | 26 +++++++ arch/arm/lib/bootm.c | 22 +++--- 5 files changed, 138 insertions(+), 140 deletions(-) create mode 100644 arch/arm/include/asm/secure.h diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index b5c946fc4e..2a43e3c81e 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -10,10 +10,13 @@ #include #include #include +#include .arch_extension sec .arch_extension virt + .pushsection ._secure.text, "ax" + .align 5 /* the vector table for secure state and HYP mode */ _monitor_vectors: @@ -22,51 +25,86 @@ _monitor_vectors: adr pc, _secure_monitor .word 0 .word 0 - adr pc, _hyp_trap + .word 0 .word 0 .word 0 +.macro is_cpu_virt_capable tmp + mrc p15, 0, \tmp, c0, c1, 1 @ read ID_PFR1 + and \tmp, \tmp, #CPUID_ARM_VIRT_MASK @ mask virtualization bits + cmp \tmp, #(1 << CPUID_ARM_VIRT_SHIFT) +.endm + /* * secure monitor handler * U-boot calls this "software interrupt" in start.S * This is executed on a "smc" instruction, we use a "smc #0" to switch * to non-secure state. - * We use only r0 and r1 here, due to constraints in the caller. + * r0, r1, r2: passed to the callee + * ip: target PC */ _secure_monitor: - mrc p15, 0, r1, c1, c1, 0 @ read SCR - bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits - orr r1, r1, #0x31 @ enable NS, AW, FW bits + mrc p15, 0, r5, c1, c1, 0 @ read SCR + bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits + orr r5, r5, #0x31 @ enable NS, AW, FW bits - mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 - and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits - cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) + mov r6, #SVC_MODE @ default mode is SVC + is_cpu_virt_capable r4 #ifdef CONFIG_ARMV7_VIRT - orreq r1, r1, #0x100 @ allow HVC instruction + orreq r5, r5, #0x100 @ allow HVC instruction + moveq r6, #HYP_MODE @ Enter the kernel as HYP #endif - mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) + mcr p15, 0, r5, c1, c1, 0 @ write SCR (with NS bit set) isb -#ifdef CONFIG_ARMV7_VIRT - mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value - mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR -#endif bne 1f @ Reset CNTVOFF to 0 before leaving monitor mode - mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 - ands r0, r0, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits - movne r0, #0 - mcrrne p15, 4, r0, r0, c14 @ Reset CNTVOFF to zero + mrc p15, 0, r4, c0, c1, 1 @ read ID_PFR1 + ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits + movne r4, #0 + mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero 1: - movs pc, lr @ return to non-secure SVC - -_hyp_trap: - mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 - mov pc, lr @ do no switch modes, but - @ return to caller - + mov lr, ip + mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F + tst lr, #1 @ Check for Thumb PC + orrne ip, ip, #T_BIT @ Set T if Thumb + orr ip, ip, r6 @ Slot target mode in + msr spsr_cxfs, ip @ Set full SPSR + movs pc, lr @ ERET to non-secure + +ENTRY(_do_nonsec_entry) + mov ip, r0 + mov r0, r1 + mov r1, r2 + mov r2, r3 + smc #0 +ENDPROC(_do_nonsec_entry) + +.macro get_cbar_addr addr +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + ldr \addr, =CONFIG_ARM_GIC_BASE_ADDRESS +#else + mrc p15, 4, \addr, c15, c0, 0 @ read CBAR + bfc \addr, #0, #15 @ clear reserved bits +#endif +.endm + +.macro get_gicd_addr addr + get_cbar_addr \addr + add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset +.endm + +.macro get_gicc_addr addr, tmp + get_cbar_addr \addr + is_cpu_virt_capable \tmp + movne \tmp, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 + moveq \tmp, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 + add \addr, \addr, \tmp +.endm + +#ifndef CONFIG_ARMV7_PSCI /* * Secondary CPUs start here and call the code for the core specific parts * of the non-secure and HYP mode transition. The GIC distributor specific @@ -74,31 +112,21 @@ _hyp_trap: * Then they go back to wfi and wait to be woken up by the kernel again. */ ENTRY(_smp_pen) - mrs r0, cpsr - orr r0, r0, #0xc0 - msr cpsr, r0 @ disable interrupts - ldr r1, =_start - mcr p15, 0, r1, c12, c0, 0 @ set VBAR + cpsid i + cpsid f bl _nonsec_init - mov r12, r0 @ save GICC address -#ifdef CONFIG_ARMV7_VIRT - bl _switch_to_hyp -#endif - - ldr r1, [r12, #GICC_IAR] @ acknowledge IPI - str r1, [r12, #GICC_EOIR] @ signal end of interrupt adr r0, _smp_pen @ do not use this address again b smp_waitloop @ wait for IPIs, board specific ENDPROC(_smp_pen) +#endif /* * Switch a core to non-secure state. * * 1. initialize the GIC per-core interface * 2. allow coprocessor access in non-secure modes - * 3. switch the cpu mode (by calling "smc #0") * * Called from smp_pen by secondary cores and directly by the BSP. * Do not assume that the stack is available and only use registers @@ -108,38 +136,23 @@ ENDPROC(_smp_pen) * though, but we check this in C before calling this function. */ ENTRY(_nonsec_init) -#ifdef CONFIG_ARM_GIC_BASE_ADDRESS - ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS -#else - mrc p15, 4, r2, c15, c0, 0 @ read CBAR - bfc r2, #0, #15 @ clear reserved bits -#endif - add r3, r2, #GIC_DIST_OFFSET @ GIC dist i/f offset + get_gicd_addr r3 + mvn r1, #0 @ all bits to 1 str r1, [r3, #GICD_IGROUPRn] @ allow private interrupts - mrc p15, 0, r0, c0, c0, 0 @ read MIDR - ldr r1, =MIDR_PRIMARY_PART_MASK - and r0, r0, r1 @ mask out variant and revision + get_gicc_addr r3, r1 - ldr r1, =MIDR_CORTEX_A7_R0P0 & MIDR_PRIMARY_PART_MASK - cmp r0, r1 @ check for Cortex-A7 - - ldr r1, =MIDR_CORTEX_A15_R0P0 & MIDR_PRIMARY_PART_MASK - cmpne r0, r1 @ check for Cortex-A15 - - movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 - moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 - add r3, r2, r1 @ r3 = GIC CPU i/f addr - - mov r1, #1 @ set GICC_CTLR[enable] + mov r1, #3 @ Enable both groups str r1, [r3, #GICC_CTLR] @ and clear all other bits mov r1, #0xff str r1, [r3, #GICC_PMR] @ set priority mask register + mrc p15, 0, r0, c1, c1, 2 movw r1, #0x3fff - movt r1, #0x0006 - mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + movt r1, #0x0004 + orr r0, r0, r1 + mcr p15, 0, r0, c1, c1, 2 @ NSACR = all copros to non-sec /* The CNTFRQ register of the generic timer needs to be * programmed in secure state. Some primary bootloaders / firmware @@ -157,21 +170,9 @@ ENTRY(_nonsec_init) adr r1, _monitor_vectors mcr p15, 0, r1, c12, c0, 1 @ set MVBAR to secure vectors - - mrc p15, 0, ip, c12, c0, 0 @ save secure copy of VBAR - isb - smc #0 @ call into MONITOR mode - - mcr p15, 0, ip, c12, c0, 0 @ write non-secure copy of VBAR - - mov r1, #1 - str r1, [r3, #GICC_CTLR] @ enable non-secure CPU i/f - add r2, r2, #GIC_DIST_OFFSET - str r1, [r2, #GICD_CTLR] @ allow private interrupts mov r0, r3 @ return GICC address - bx lr ENDPROC(_nonsec_init) @@ -183,18 +184,10 @@ ENTRY(smp_waitloop) ldr r1, [r1] cmp r0, r1 @ make sure we dont execute this code beq smp_waitloop @ again (due to a spurious wakeup) - mov pc, r1 + mov r0, r1 + b _do_nonsec_entry ENDPROC(smp_waitloop) .weak smp_waitloop #endif -ENTRY(_switch_to_hyp) - mov r0, lr - mov r1, sp @ save SVC copy of LR and SP - isb - hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1 - mov sp, r1 - mov lr, r0 @ restore SVC copy of LR and SP - - bx lr -ENDPROC(_switch_to_hyp) + .popsection diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 2cd604f97f..650003084e 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -13,17 +13,10 @@ #include #include #include +#include unsigned long gic_dist_addr; -static unsigned int read_cpsr(void) -{ - unsigned int reg; - - asm volatile ("mrs %0, cpsr\n" : "=r" (reg)); - return reg; -} - static unsigned int read_id_pfr1(void) { unsigned int reg; @@ -72,6 +65,18 @@ static unsigned long get_gicd_base_address(void) #endif } +static void relocate_secure_section(void) +{ +#ifdef CONFIG_ARMV7_SECURE_BASE + size_t sz = __secure_end - __secure_start; + + memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); + flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, + CONFIG_ARMV7_SECURE_BASE + sz + 1); + invalidate_icache_all(); +#endif +} + static void kick_secondary_cpus_gic(unsigned long gicdaddr) { /* kick all CPUs (except this one) by writing to GICD_SGIR */ @@ -83,35 +88,7 @@ void __weak smp_kick_all_cpus(void) kick_secondary_cpus_gic(gic_dist_addr); } -int armv7_switch_hyp(void) -{ - unsigned int reg; - - /* check whether we are in HYP mode already */ - if ((read_cpsr() & 0x1f) == 0x1a) { - debug("CPU already in HYP mode\n"); - return 0; - } - - /* check whether the CPU supports the virtualization extensions */ - reg = read_id_pfr1(); - if ((reg & CPUID_ARM_VIRT_MASK) != 1 << CPUID_ARM_VIRT_SHIFT) { - printf("HYP mode: Virtualization extensions not implemented.\n"); - return -1; - } - - /* call the HYP switching code on this CPU also */ - _switch_to_hyp(); - - if ((read_cpsr() & 0x1F) != 0x1a) { - printf("HYP mode: switch not successful.\n"); - return -1; - } - - return 0; -} - -int armv7_switch_nonsec(void) +int armv7_init_nonsec(void) { unsigned int reg; unsigned itlinesnr, i; @@ -147,11 +124,13 @@ int armv7_switch_nonsec(void) for (i = 1; i <= itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); - smp_set_core_boot_addr((unsigned long)_smp_pen, -1); +#ifndef CONFIG_ARMV7_PSCI + smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); smp_kick_all_cpus(); +#endif /* call the non-sec switching code on this CPU also */ - _nonsec_init(); - + relocate_secure_section(); + secure_ram_addr(_nonsec_init)(); return 0; } diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 395444ee4f..11476ddd16 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -78,13 +78,17 @@ void v7_outer_cache_inval_range(u32 start, u32 end); #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) -int armv7_switch_nonsec(void); -int armv7_switch_hyp(void); +int armv7_init_nonsec(void); /* defined in assembly file */ unsigned int _nonsec_init(void); +void _do_nonsec_entry(void *target_pc, unsigned long r0, + unsigned long r1, unsigned long r2); void _smp_pen(void); -void _switch_to_hyp(void); + +extern char __secure_start[]; +extern char __secure_end[]; + #endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */ #endif /* ! __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h new file mode 100644 index 0000000000..effdb1858d --- /dev/null +++ b/arch/arm/include/asm/secure.h @@ -0,0 +1,26 @@ +#ifndef __ASM_SECURE_H +#define __ASM_SECURE_H + +#include + +#ifdef CONFIG_ARMV7_SECURE_BASE +/* + * Warning, horror ahead. + * + * The target code lives in our "secure ram", but u-boot doesn't know + * that, and has blindly added reloc_off to every relocation + * entry. Gahh. Do the opposite conversion. This hack also prevents + * GCC from generating code veeners, which u-boot doesn't relocate at + * all... + */ +#define secure_ram_addr(_fn) ({ \ + DECLARE_GLOBAL_DATA_PTR; \ + void *__fn = _fn; \ + typeof(_fn) *__tmp = (__fn - gd->reloc_off); \ + __tmp; \ + }) +#else +#define secure_ram_addr(_fn) (_fn) +#endif + +#endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 304210effd..a08586f1eb 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) @@ -184,27 +185,17 @@ static void setup_end_tag(bd_t *bd) __weak void setup_board_tags(struct tag **in_params) {} +#ifdef CONFIG_ARM64 static void do_nonsec_virt_switch(void) { -#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) - if (armv7_switch_nonsec() == 0) -#ifdef CONFIG_ARMV7_VIRT - if (armv7_switch_hyp() == 0) - debug("entered HYP mode\n"); -#else - debug("entered non-secure state\n"); -#endif -#endif - -#ifdef CONFIG_ARM64 smp_kick_all_cpus(); flush_dcache_all(); /* flush cache before swtiching to EL2 */ armv8_switch_to_el2(); #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 armv8_switch_to_el1(); #endif -#endif } +#endif /* Subcommand: PREP */ static void boot_prep_linux(bootm_headers_t *images) @@ -289,8 +280,13 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) r2 = gd->bd->bi_boot_params; if (!fake) { - do_nonsec_virt_switch(); +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + armv7_init_nonsec(); + secure_ram_addr(_do_nonsec_entry)(kernel_entry, + 0, machid, r2); +#else kernel_entry(0, machid, r2); +#endif } #endif } -- cgit v1.2.1 From ecf07a7930e9e9558bff70698515279f5a2c40d4 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:04 +0100 Subject: ARM: HYP/non-sec: add generic ARMv7 PSCI code Implement core support for PSCI. As this is generic code, it doesn't implement anything really useful (all the functions are returning Not Implemented). Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/Makefile | 4 ++ arch/arm/cpu/armv7/psci.S | 102 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/psci.h | 35 +++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 arch/arm/cpu/armv7/psci.S create mode 100644 arch/arm/include/asm/psci.h diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 232118d7f4..735c4ad37e 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -23,6 +23,10 @@ obj-y += nonsec_virt.o obj-y += virt-v7.o endif +ifneq ($(CONFIG_ARMV7_PSCI),) +obj-y += psci.o +endif + obj-$(CONFIG_KONA) += kona-common/ obj-$(CONFIG_OMAP_COMMON) += omap-common/ obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S new file mode 100644 index 0000000000..bf11a34e54 --- /dev/null +++ b/arch/arm/cpu/armv7/psci.S @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2013,2014 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + .globl _psci_vectors +_psci_vectors: + b default_psci_vector @ reset + b default_psci_vector @ undef + b _smc_psci @ smc + b default_psci_vector @ pabort + b default_psci_vector @ dabort + b default_psci_vector @ hyp + b default_psci_vector @ irq + b psci_fiq_enter @ fiq + +ENTRY(psci_fiq_enter) + movs pc, lr +ENDPROC(psci_fiq_enter) +.weak psci_fiq_enter + +ENTRY(default_psci_vector) + movs pc, lr +ENDPROC(default_psci_vector) +.weak default_psci_vector + +ENTRY(psci_cpu_suspend) +ENTRY(psci_cpu_off) +ENTRY(psci_cpu_on) +ENTRY(psci_migrate) + mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) + mov pc, lr +ENDPROC(psci_migrate) +ENDPROC(psci_cpu_on) +ENDPROC(psci_cpu_off) +ENDPROC(psci_cpu_suspend) +.weak psci_cpu_suspend +.weak psci_cpu_off +.weak psci_cpu_on +.weak psci_migrate + +_psci_table: + .word ARM_PSCI_FN_CPU_SUSPEND + .word psci_cpu_suspend + .word ARM_PSCI_FN_CPU_OFF + .word psci_cpu_off + .word ARM_PSCI_FN_CPU_ON + .word psci_cpu_on + .word ARM_PSCI_FN_MIGRATE + .word psci_migrate + .word 0 + .word 0 + +_smc_psci: + push {r4-r7,lr} + + @ Switch to secure + mrc p15, 0, r7, c1, c1, 0 + bic r4, r7, #1 + mcr p15, 0, r4, c1, c1, 0 + isb + + adr r4, _psci_table +1: ldr r5, [r4] @ Load PSCI function ID + ldr r6, [r4, #4] @ Load target PC + cmp r5, #0 @ If reach the end, bail out + moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid) + beq 2f + cmp r0, r5 @ If not matching, try next entry + addne r4, r4, #8 + bne 1b + + blx r6 @ Execute PSCI function + + @ Switch back to non-secure +2: mcr p15, 0, r7, c1, c1, 0 + + pop {r4-r7, lr} + movs pc, lr @ Return to the kernel + + .popsection diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h new file mode 100644 index 0000000000..704b4b0018 --- /dev/null +++ b/arch/arm/include/asm/psci.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ARM_PSCI_H__ +#define __ARM_PSCI_H__ + +/* PSCI interface */ +#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) + +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) + +#define ARM_PSCI_RET_SUCCESS 0 +#define ARM_PSCI_RET_NI (-1) +#define ARM_PSCI_RET_INVAL (-2) +#define ARM_PSCI_RET_DENIED (-3) + +#endif /* __ARM_PSCI_H__ */ -- cgit v1.2.1 From 38510a4b34a699a534121ad3cb9096cc0fd7a86e Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:05 +0100 Subject: ARM: HYP/non-sec: add the option for a second-stage monitor Allow the switch to a second stage secure monitor just before switching to non-secure. This allows a resident piece of firmware to be active once the kernel has been entered (the u-boot monitor is dead anyway, its pages being reused). Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/nonsec_virt.S | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 2a43e3c81e..745670e549 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -44,10 +44,19 @@ _monitor_vectors: * ip: target PC */ _secure_monitor: +#ifdef CONFIG_ARMV7_PSCI + ldr r5, =_psci_vectors @ Switch to the next monitor + mcr p15, 0, r5, c12, c0, 1 + isb + + @ Obtain a secure stack, and configure the PSCI backend + bl psci_arch_init +#endif + mrc p15, 0, r5, c1, c1, 0 @ read SCR - bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits + bic r5, r5, #0x4a @ clear IRQ, EA, nET bits orr r5, r5, #0x31 @ enable NS, AW, FW bits - + @ FIQ preserved for secure mode mov r6, #SVC_MODE @ default mode is SVC is_cpu_virt_capable r4 #ifdef CONFIG_ARMV7_VIRT -- cgit v1.2.1 From e29607ed972056723e4bf0ac90767421cf0f0b78 Mon Sep 17 00:00:00 2001 From: Ma Haijun Date: Sat, 12 Jul 2014 14:24:06 +0100 Subject: ARM: convert arch_fixup_memory_node to a generic FDT fixup function Some architecture needs extra device tree setup. Instead of adding yet another hook, convert arch_fixup_memory_node to be a generic FDT fixup function. [maz: collapsed 3 patches into one, rewrote commit message] Signed-off-by: Ma Haijun Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/lib/bootm-fdt.c | 2 +- arch/arm/lib/bootm.c | 2 +- common/image-fdt.c | 7 +++++-- include/common.h | 6 +++--- 4 files changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index e40691d15f..8394e15b7e 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; -int arch_fixup_memory_node(void *blob) +int arch_fixup_fdt(void *blob) { bd_t *bd = gd->bd; int bank; diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index a08586f1eb..178e8fb9e4 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -359,7 +359,7 @@ void boot_prep_vxworks(bootm_headers_t *images) if (images->ft_addr) { off = fdt_path_offset(images->ft_addr, "/memory"); if (off < 0) { - if (arch_fixup_memory_node(images->ft_addr)) + if (arch_fixup_fdt(images->ft_addr)) puts("## WARNING: fixup memory failed!\n"); } } diff --git a/common/image-fdt.c b/common/image-fdt.c index 7795b80ccf..db6e395562 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -450,7 +450,7 @@ __weak int ft_verify_fdt(void *fdt) return 1; } -__weak int arch_fixup_memory_node(void *blob) +__weak int arch_fixup_fdt(void *blob) { return 0; } @@ -467,7 +467,10 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, puts(" - must RESET the board to recover.\n"); return -1; } - arch_fixup_memory_node(blob); + if (arch_fixup_fdt(blob) < 0) { + puts("ERROR: arch specific fdt fixup failed"); + return -1; + } if (IMAGE_OF_BOARD_SETUP) ft_board_setup(blob, gd->bd); fdt_fixup_ethernet(blob); diff --git a/include/common.h b/include/common.h index a75fc25c5f..1d6cb48ff0 100644 --- a/include/common.h +++ b/include/common.h @@ -318,14 +318,14 @@ int arch_early_init_r(void); void board_show_dram(ulong size); /** - * arch_fixup_memory_node() - Write arch-specific memory information to fdt + * arch_fixup_fdt() - Write arch-specific information to fdt * - * Defined in arch/$(ARCH)/lib/bootm.c + * Defined in arch/$(ARCH)/lib/bootm-fdt.c * * @blob: FDT blob to write to * @return 0 if ok, or -ve FDT_ERR_... on failure */ -int arch_fixup_memory_node(void *blob); +int arch_fixup_fdt(void *blob); /* common/flash.c */ void flash_perror (int); -- cgit v1.2.1 From e771a3d538a4fbe235864061ff3c81a8acb11082 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:07 +0100 Subject: ARM: HYP/non-sec/PSCI: emit DT nodes Generate the PSCI node in the device tree. Also add a reserve section for the "secure" code that lives in in normal RAM, so that the kernel knows it'd better not trip on it. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/Makefile | 1 + arch/arm/cpu/armv7/virt-dt.c | 100 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/armv7.h | 1 + arch/arm/lib/bootm-fdt.c | 12 +++++- 4 files changed, 112 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/virt-dt.c diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 735c4ad37e..703ce8c640 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -21,6 +21,7 @@ endif ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) obj-y += nonsec_virt.o obj-y += virt-v7.o +obj-y += virt-dt.o endif ifneq ($(CONFIG_ARMV7_PSCI),) diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c new file mode 100644 index 0000000000..0b0d6a76fc --- /dev/null +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int fdt_psci(void *fdt) +{ +#ifdef CONFIG_ARMV7_PSCI + int nodeoff; + int tmp; + + nodeoff = fdt_path_offset(fdt, "/cpus"); + if (nodeoff < 0) { + printf("couldn't find /cpus\n"); + return nodeoff; + } + + /* add 'enable-method = "psci"' to each cpu node */ + for (tmp = fdt_first_subnode(fdt, nodeoff); + tmp >= 0; + tmp = fdt_next_subnode(fdt, tmp)) { + const struct fdt_property *prop; + int len; + + prop = fdt_get_property(fdt, tmp, "device_type", &len); + if (!prop) + continue; + if (len < 4) + continue; + if (strcmp(prop->data, "cpu")) + continue; + + fdt_setprop_string(fdt, tmp, "enable-method", "psci"); + } + + nodeoff = fdt_path_offset(fdt, "/psci"); + if (nodeoff < 0) { + nodeoff = fdt_path_offset(fdt, "/"); + if (nodeoff < 0) + return nodeoff; + + nodeoff = fdt_add_subnode(fdt, nodeoff, "psci"); + if (nodeoff < 0) + return nodeoff; + } + + tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci"); + if (tmp) + return tmp; + tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc"); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE); + if (tmp) + return tmp; +#endif + return 0; +} + +int armv7_update_dt(void *fdt) +{ +#ifndef CONFIG_ARMV7_SECURE_BASE + /* secure code lives in RAM, keep it alive */ + fdt_add_mem_rsv(fdt, (unsigned long)__secure_start, + __secure_end - __secure_start); +#endif + + return fdt_psci(fdt); +} diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 11476ddd16..323f282fb7 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -79,6 +79,7 @@ void v7_outer_cache_inval_range(u32 start, u32 end); #if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) int armv7_init_nonsec(void); +int armv7_update_dt(void *fdt); /* defined in assembly file */ unsigned int _nonsec_init(void); diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 8394e15b7e..d4f1578e9e 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -17,13 +17,14 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; int arch_fixup_fdt(void *blob) { bd_t *bd = gd->bd; - int bank; + int bank, ret; u64 start[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; @@ -32,5 +33,12 @@ int arch_fixup_fdt(void *blob) size[bank] = bd->bi_dram[bank].size; } - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + ret = fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) + if (ret) + return ret; + + ret = armv7_update_dt(blob); +#endif + return ret; } -- cgit v1.2.1 From 9d195a546179bc732aba9eacccf0a9a3db591288 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sat, 12 Jul 2014 14:24:08 +0100 Subject: ARM: HYP/non-sec: remove MIDR check to validate CBAR Having a form of whitelist to check if we know of a CPU core and and obtain CBAR is a bit silly. It doesn't scale (how about A12, A17, as well as other I don't know about?), and is actually a property of the SoC, not the core. So either it works and everybody is happy, or it doesn't and the u-boot port to this SoC is providing the real address via a configuration option. The result of the above is that this code doesn't need to exist, is thus forcefully removed. Signed-off-by: Marc Zyngier Acked-by: Ian Campbell --- arch/arm/cpu/armv7/virt-v7.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 650003084e..651ca4015d 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -30,25 +30,8 @@ static unsigned long get_gicd_base_address(void) #ifdef CONFIG_ARM_GIC_BASE_ADDRESS return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else - unsigned midr; unsigned periphbase; - /* check whether we are an Cortex-A15 or A7. - * The actual HYP switch should work with all CPUs supporting - * the virtualization extension, but we need the GIC address, - * which we know only for sure for those two CPUs. - */ - asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); - switch (midr & MIDR_PRIMARY_PART_MASK) { - case MIDR_CORTEX_A9_R0P1: - case MIDR_CORTEX_A15_R0P0: - case MIDR_CORTEX_A7_R0P0: - break; - default: - printf("nonsec: could not determine GIC address.\n"); - return -1; - } - /* get the GIC base address from the CBAR register */ asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); -- cgit v1.2.1