From 0ddc5a2dee424be8522fa1d68685dd2eb91f9887 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 2 Sep 2015 11:10:59 +0200 Subject: arm: spear: Add BCH4 SW support to SPEAr600 x600 board This board is equipped with a Micron NAND chip (MT29F1G08ABADAH4) that needs 4-bit ECC. But the SPEAr600 only supports 1-bit HW ECC internally. This patch enables the SW 4-bit BCH support for this board. Signed-off-by: Stefan Roese Cc: Viresh Kumar --- include/configs/x600.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/x600.h b/include/configs/x600.h index 6a5738863a..f672485d69 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -67,6 +67,8 @@ #define CONFIG_MTD_ECC_SOFT #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_NAND_ECC_BCH +#define CONFIG_BCH /* UBI/UBI config options */ #define CONFIG_MTD_DEVICE -- cgit v1.2.1