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* nand_spl: change out_be32 to raw_writel and depend on subsequent syncMatthew McClintock2012-08-233-73/+71
| | | | | | | | | | | | | This change reduces the SPL size by removing the redundant syncs produced by out_be32 and just replies on one final sync Done with: sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/` Signed-off-by: Matthew McClintock <msm@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* nand_spl: p1023rds: wait before enabling DDR controllerMatthew McClintock2012-08-232-5/+20
| | | | | | | | We have a requirement to wait a period of time before enabling the DDR controller Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* nand_spl: update udelay for Freescale boardsMatthew McClintock2012-08-235-15/+60
| | | | | | | | | | | | | | Let's use the more appropriate udelay for the nand_spl. While we can't make use of u-boot's full udelay we can atl east use a for loop that won't get optimized away .Since we have the bus clock we can use the timebase to calculate wall time. Looked at reusing the u-boot udelay functions but it pulls in a lot of code and would require quite a bit of work to keep us within the very small space constrains we currently have Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p1010rdb: nandboot: compare SVR properlyMatthew McClintock2012-08-231-1/+2
| | | | | | | | | | | | | | | | We were not comparing the SVRs properly previously. This comparison will properly shift the SVR and mask off the E bit This fixes the boot output to show the correct DDR bus width: 512 MiB (DDR3, 16-bit, CL=5, ECC off) instead of 512 MiB (DDR3, 32-bit, CL=5, ECC off) Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* p1014rdb: set ddr bus width properly depending on SVRMatthew McClintock2012-08-231-0/+11
| | | | | | | | | | Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-10-044-0/+542
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
| * powerpc/85xx: Add NAND/NAND_SPL support to P1010RDBDipen Dudhat2011-09-292-0/+271
| | | | | | | | | | | | | | | | | | And various defines to enable NAND support and NAND spl code for the P1010RDB platform. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support for new P102x/P2020 RDB style boardsLi Yang2011-09-292-0/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following boards share a common design but with minor variations between them: P1020MSBG-PC P1020RDB-PC P1020UTM-PC P1021RDB-PC P1024RDB P1025RDB P2020RDB-PC The P1020RDB-PC shares its roots in the existing P1020RDB board design, however uses DDR3 instead of DDR2. P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK. Key features on these boards include: * DDR3 * NOR flash * NAND flash (on RDB's only) * SPI flash (on RDB's only) * SDHC/MMC card slot * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB) * PCIE slot and mini-PCIE slots As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM is used to store SPD data. In case of absent or corrupted SPD, falling back to timing data embedded in the source code will be used. Raw timing data is extracted from DDR chip datasheet. Different speeds of DDR are supported with this approach. ODT option is forced to fit this set of boards, again because they don't have regular DIMMs. CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification for writing timing. VSC firmware Address is defined by default in config file for eTSEC1. SD width is based off DIP switch. DIP switch is detected on the board by reading i2c bus and setting the appropriate mux values. Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have pins multiplexing. QE function needs to be disabled to access Nor Flash and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe" in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD. 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Zhao Chenhui <b26998@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
* | MX31: mx31pdk: Remove nand_spl config.mk fileFabio Estevam2011-09-302-2/+1
|/ | | | | | | No need to have a config.mk to only store a single line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* replace CONFIG_PRELOADER with CONFIG_SPL_BUILDAneesh V2011-07-261-2/+2
| | | | | | replace all occurences of CONFIG_PRELOADER with CONFIG_SPL_BUILD Signed-off-by: Aneesh V <aneesh@ti.com>
* powerpc/85xx: Add basic support for P1023RDS boardRoy Zang2011-07-112-0/+231
| | | | | | | | | | | | | | The P1023RDS board is the reference board for the P1023 SoC. Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe, UART, I2C, etc. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MX31: mx31pdk: fix nand_splStefano Babic2011-04-271-0/+2
| | | | | | | | | | Commit f326cbba98bae21d41df8daac0bd78121d557af1 breaks mx31pdk, as the _end section in u-boot.lds is missing for the nand_spl production. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* powerpc/85xx: Modify NAND loader makefiles to compile NAND_SPL linker scriptDipen Dudhat2011-04-154-16/+28
| | | | | | | | | Modify eLBC based platform's NAND loader Makefile to preprocess nand loader linker script and then use it. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix build issues cause by LDFLAGS_FINAL changesWolfgang Denk2011-03-317-21/+21
| | | | | | | | | | | Commit 6dc1ece "Introduce a new linker flag LDFLAGS_FINAL" modified a number of Makefiles in a way that broke out-of-tree builds. The problem was that $(nandobj) was used before it got defined. Fix this. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* rename _end to __bss_end__Po-Yu Chuang2011-03-273-5/+5
| | | | | | | Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* Introduce a new linker flag LDFLAGS_FINALHaiying Wang2011-03-227-9/+14
| | | | | | | | | | | | | | | commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* mx31pdk: Use the new relocation schemeFabio Estevam2011-02-211-7/+52
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* powerpc/85xx: Add support for booting from NAND on MPC8572DSKumar Gala2011-01-142-0/+215
| | | | | | | | Mimic support that exists on MPC8536DS on the MPC8572DS to allow booting from NAND. Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PowerPC, nand_spl: Add relocation support for -fpicJoakim Tjernlund2010-12-172-2/+6
| | | | | | | | | | | By rearranging the linker script we get support for relocation of -fpic for free. Move __got2_entries outside _GOT2_TABLE_ defining scope matching the rest of PowerPC Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* powerpc/nand spl: link libgccScott Wood2010-12-162-2/+2
| | | | | | | | | | | | | | | | Recent GCC (4.4+) performs out-of-line epilogues in some cases, when optimizing for size. It causes a link error for _restgpr_30_x (and similar) if libgcc is not linked. It actually increases size with very small binaries, due to the fixed size of the out-of-line code, and not having any functions that actually need to restore more than 2 or 3 registers. But I don't see a way to turn it off, other than asking GCC to optimize for speed -- which may also increase size for some boards. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* 83xx: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-272-6/+8
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Haiying Wang <r54964@freescale.com>
* 83xx: Fix NAND_SPL link addressScott Wood2010-11-272-4/+4
| | | | | | | | | | | | | | | | | Apply the same fix for 83xx as was done for 85xx in commit 96196a1f7546904563994d2d041804a816d7c139. Without this, NAND SPLs are built with the text base intended for the main image, resulting in a broken, very large u-boot-nand.bin. The block of defines for NAND boot is moved closer to where CONFIG_SYS_TEXT_BASE is defined. We can't directly use CONFIG_SYS_NAND_U_BOOT_DST in the definition of CONFIG_SYS_TEXT_BASE because autoconf.mk will include the literal text "CONFIG_SYS_NAND_U_BOOT_DST", but at least keep them close and point out that they're supposed to be the same. Signed-off-by: Scott Wood <scottwood@freescale.com>
* powerpc/85xx: add CONFIG_SYS_TEXT_BASE_SPL for 85xx nand spl buildHaiying Wang2010-11-123-6/+6
| | | | | | | | | | Introduce a SPL specific CONFIG_SYS_TEXT_BASE_SPL define to be used by the linker. This has similiar semantics to CONFIG_SYS_TEXT_BASE however since SPL is a unqiue image we introduce a new variable to control its text base address. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Rename TEXT_BASE into CONFIG_SYS_TEXT_BASEWolfgang Denk2010-10-186-11/+11
| | | | | | | | | | | | The change is currently needed to be able to remove the board configuration scripting from the top level Makefile and replace it by a simple, table driven script. Moving this configuration setting into the "CONFIG_*" name space is also desirable because it is needed if we ever should move forward to a Kconfig driven configuration system. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-161-3/+2
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Move arch/ppc to arch/powerpcStefan Roese2010-04-215-28/+28
| | | | | | | | | | | | | | | | | As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
* arm: Move cpu/$CPU to arch/arm/cpu/$CPUPeter Tyser2010-04-131-2/+2
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-135-19/+19
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>"Peter Tyser2010-04-132-2/+2
| | | | | | | | | | The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Move lib_$ARCH directories to arch/$ARCH/libPeter Tyser2010-04-135-9/+9
| | | | | | | | | Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk This change is intended to clean up the top-level directory structure and more closely mimic Linux's directory organization. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Create CPUDIR variablePeter Tyser2010-04-133-6/+6
| | | | | | | | | | | | The CPUDIR variable points to the location of a target's CPU directory. Currently, it is set to cpu/$CPU. However, using $CPUDIR will allow for more flexibility in the future. It lays the groundwork for reorganizing U-Boot's directory structure to support a layout such as: arch/$ARCH/cpu/$CPU/* (architecture with multiple CPU types) arch/$ARCH/cpu/* (architecture with one CPU type) Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* mpc83xx: fix out-of-tree mpc8315 nand buildKim Phillips2010-03-022-0/+160
| | | | | | | | | | | | | | | | commit 2e95004deb6e33e33bf1b8a92a38cd2115bac4c2 "mpc83xx: Add NAND boot support for MPC8315E-RDB boards" symlinked nand_spl/board/freescale/mpc8315erdb to mpc8313erdb in order to not duplicate code. Since the main makefile builds nand_spl/board/$(BOARDDIR) (which makes sense), and the board Makefile and linker script are the only two necessary files to enable out-of-tree building, and other boards have duplicated nand makefiles (e.g. 8536ds & 8569mds), it only seems prudent to copy these two files in the name of the 8315 too. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com> Cc: Wolfgang Denk <wd@denx.de>
* Nand boot: Add nand boot support for MPC8569mds boardLiu Yu2010-01-272-0/+208
| | | | | | This patch add nand boot support for MPC8569mds board. Signed-off-by: Liu Yu <yu.liu@freescale.com>
* ppc/85xx: Fix compiler warning in nand_spl/.../p1_p2_rdb/nand_boot.cKumar Gala2009-10-261-1/+1
| | | | | | | nand_boot.c: In function 'board_init_f': nand_boot.c:44: warning: 'sys_clk' may be used uninitialized in this function Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix building NAND_SPL out of treeKumar Gala2009-10-262-0/+12
| | | | | | | We need to source files to exist in the O=<FOO> nand_spl dir when we build out of tree. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/P1_P2_RDB: NAND Boot SupportDipen Dudhat2009-10-162-0/+224
| | | | | | | | | NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* NAND boot: MPC8536DS supportMingkai Hu2009-09-302-0/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix all linker scripts for older binutils versions (pre-2.16)Wolfgang Denk2009-08-212-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f62fb99941c6 fixed handling of all rodata sections by using a wildcard combined with calls to ld's builtin functions SORT_BY_ALIGNMENT() and SORT_BY_NAME(). Unfortunately these functions were only introduced with biunutils version 2.16, so the modification broke building with all tool chains using older binutils. This patch makes it work again. This is done by omitting the use of these functions for such old tool chains. This will result in slightly larger target binaries, as the rodata sections are no longer in optimal order alignment-wise which reauls in unused gaps, but the effect was found to be insignificant - especially compared to the fact that you cannot build U-Boot at all in the current state. As ld seems to have no support for conditionals we run the linker script through the C preprocessor which can be easily used to remove the unwanted function calls. Note that the C preprocessor must be run with the "-ansi" (or a "-std=") option to make sure all the system-specific predefined macros outside the reserved namespace are suppressed. Otherise, cpp might for example substitute "powerpc" to "1", thus corrupting for example "OUTPUT_ARCH(powerpc)" etc. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org>
* MX31: Add NAND SPL boot support to i.MX31 PDK board.Magnus Lilja2009-07-063-0/+91
| | | | Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* NAND: Fix cache and memory inconsistency issueDave Liu2009-01-231-1/+5
| | | | | | | | | | | | | | | | | | We load the secondary stage u-boot image from NAND to system memory by nand_load, but we did not flush d-cache to memory, nor invalidate i-cache before we jump to RAM. When the system has cache enabled and the TLB/page attribute of system memory is cacheable, it will cause issues. - 83xx family is using the d-cache lock, so all of d-cache access is cache-inhibited. so you can't see the issue. - 85xx family is using d-cache, i-cache enable, partial cache lock. you will see the issue. This patch fixes the cache issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND boot: MPC8313ERDB supportScott Wood2008-08-122-0/+153
Note that with older board revisions, NAND boot may only work after a power-on reset, and not after a warm reset. I don't have a newer board to test on; if you have a board with a 33MHz crystal, please let me know if it works after a warm reset. Signed-off-by: Scott Wood <scottwood@freescale.com>
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