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* nand-spl: Use scripts/Makefile.buildMasahiro Yamada2014-02-191-8/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* nand_spl: trivial refactoring of makefilesMasahiro Yamada2013-11-251-24/+21
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-243-51/+3
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Replace __bss_end__ with __bss_endSimon Glass2013-03-151-1/+1
| | | | | | | | | | | | | Note this is a tree-wide change affecting multiple architectures. At present we use __bss_start, but mostly __bss_end__. This seems inconsistent and in a number of places __bss_end is used instead. Change to use __bss_end for the BSS end symbol throughout U-Boot. This makes it possible to use the asm-generic/sections.h file on all archs. Signed-off-by: Simon Glass <sjg@chromium.org>
* Fix build issues cause by LDFLAGS_FINAL changesWolfgang Denk2011-03-311-3/+3
| | | | | | | | | | | Commit 6dc1ece "Introduce a new linker flag LDFLAGS_FINAL" modified a number of Makefiles in a way that broke out-of-tree builds. The problem was that $(nandobj) was used before it got defined. Fix this. Signed-off-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* rename _end to __bss_end__Po-Yu Chuang2011-03-271-1/+1
| | | | | | | Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
* Introduce a new linker flag LDFLAGS_FINALHaiying Wang2011-03-221-1/+2
| | | | | | | | | | | | | | | commit 8aba9dceebb14144e07d19593111ee3a999c37fc Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS breaks the usage of --gc-section to build nand_spl. We still need linker option --gc-section for every uboot image, not only the main one. LDFLAGS_FINAL passes the --gc-sections to each uboot image. To get the proper linker flags, we use LDFLAGS and LDFLAGS_FINAL to replace PLATFORM_LDFLAGS in the Makefile of each nand_spl board. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* powerpc/nand spl: link libgccScott Wood2010-12-161-1/+1
| | | | | | | | | | | | | | | | Recent GCC (4.4+) performs out-of-line epilogues in some cases, when optimizing for size. It causes a link error for _restgpr_30_x (and similar) if libgcc is not linked. It actually increases size with very small binaries, due to the fixed size of the out-of-line code, and not having any functions that actually need to restore more than 2 or 3 registers. But I don't see a way to turn it off, other than asking GCC to optimize for speed -- which may also increase size for some boards. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Cleanup for partial linking and --gc-sectionsWolfgang Denk2010-11-271-1/+1
| | | | | | | | | | | | | | | | | This commit adapts 4xx boards for partial linking with --gc-sections. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: David Updegraff <dave@cray.com> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Larry Johnson <lrj@acm.org> Cc: Peter De Schrijver <p2@mind.be> Cc: Niklaus Giger <niklaus.giger@netstal.com> Cc: Daniel Poirot <dan.poirot@windriver.com> Acked-by: Stefan Roese <sr@denx.de>
* Rename TEXT_BASE into CONFIG_SYS_TEXT_BASEWolfgang Denk2010-10-182-5/+5
| | | | | | | | | | | | The change is currently needed to be able to remove the board configuration scripting from the top level Makefile and replace it by a simple, table driven script. Moving this configuration setting into the "CONFIG_*" name space is also desirable because it is needed if we ever should move forward to a Kconfig driven configuration system. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Move arch/ppc to arch/powerpcStefan Roese2010-04-211-4/+4
| | | | | | | | | | | | | | | | | As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-131-4/+4
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Fix all linker scripts for older binutils versions (pre-2.16)Wolfgang Denk2009-08-211-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit f62fb99941c6 fixed handling of all rodata sections by using a wildcard combined with calls to ld's builtin functions SORT_BY_ALIGNMENT() and SORT_BY_NAME(). Unfortunately these functions were only introduced with biunutils version 2.16, so the modification broke building with all tool chains using older binutils. This patch makes it work again. This is done by omitting the use of these functions for such old tool chains. This will result in slightly larger target binaries, as the rodata sections are no longer in optimal order alignment-wise which reauls in unused gaps, but the effect was found to be insignificant - especially compared to the fact that you cannot build U-Boot at all in the current state. As ld seems to have no support for conditionals we run the linker script through the C preprocessor which can be easily used to remove the unwanted function calls. Note that the C preprocessor must be run with the "-ansi" (or a "-std=") option to make sure all the system-specific predefined macros outside the reserved namespace are suppressed. Otherise, cpp might for example substitute "powerpc" to "1", thus corrupting for example "OUTPUT_ARCH(powerpc)" etc. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org>
* nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directoryStefan Roese2009-07-161-1/+1
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-181-0/+1
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-181-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Remove shell variable UNDEF_SYM.Kenneth Johansson2008-06-031-1/+1
| | | | | | | UNDEF_SYM is a shell variable in the main Makefile used to force the linker to add all u-boot commands to the final image. It has no use here. Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-121-1/+1
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* fix comments with new drivers organizationMarcel Ziswiler2008-01-091-1/+1
| | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* Merge commit 'u-boot/master' into for-1.3.1Stefan Roese2007-12-111-1/+1
|\ | | | | | | | | | | Conflicts: drivers/rtc/Makefile
| * drivers/mtd : move mtd drivers to drivers/mtdJean-Christophe PLAGNIOL-VILLARD2007-11-251-1/+1
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ppc4xx: Fix acadia_nand build problemStefan Roese2007-10-311-1/+5
|/ | | | | | | Since the cache handling functions were moved from start.S into cache.S the acadia NAND booting Makfile needs to be adapted accordingly. Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-193-5/+15
| | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-063-0/+214
This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
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