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* fsl_esdhc: Deal with watermark level register related changesPriyanka Jain2011-04-101-1/+14
| | | | | | | | | | | | | P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: PIO Support for FSL eSDHC Controller DriverDipen Dudhat2010-04-231-0/+2
| | | | | | | On some Freescale SoC Internal DMA of eSDHC controller has bug. So PIO Mode has been introduced to do data transfer using CPU. Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
* fsl_esdhc: Only modify the field we are changing in WMLRoy Zang2010-04-071-0/+2
| | | | | | | | | When we set the read or write watermark in WML we should maintain the rest of the register as is, rather than using some hard coded value. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add function to reset the eSDHC controllerJerry Huang2010-04-071-0/+1
| | | | | | | | | | | | To support multiple block read command we must set abort or use auto CMD12. If we booted from eSDHC controller neither of these are used and thus we need to reset the controller to allow multiple block read to function. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Always stop clock before changing frequencyKumar Gala2010-04-071-2/+1
| | | | | | | | We need to stop the clocks on 83xx/85xx as well as imx. No need to make this code conditional to just imx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefano Babic <sbabic@denx.de>
* fsl_esdhc: add support for mx51 processorStefano Babic2010-03-071-0/+27
| | | | | | | | | The esdhc controller in the mx51 processor is quite the same as the one in some powerpc processors (MPC83xx, MPC85xx). This patches adapts the driver to support the arm mx51. Signed-off-by: Stefano Babic <sbabic@denx.de>
* fsl_esdhc: fix wrong clock maskLi Yang2010-01-251-1/+1
| | | | | | | | Fix typo in SYSCTL_CLOCK_MASK, which caused residual in high bits of SDCLKFS. Signed-off-by: Jin Qing <B24347@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add device tree fixupsAnton Vorontsov2009-07-161-0/+8
| | | | | | | | | | | This patch implements fdt_fixup_esdhc() function that is used to fixup the device tree. The function adds status = "disabled" propery if esdhc pins muxed away, otherwise it fixups clock-frequency for esdhc nodes. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* Add support for the Freescale eSDHC found on 8379 and 8536 SoCsAndy Fleming2009-02-161-0/+145
This uses the new MMC framework Some contributions by Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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