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* Coding style cleanup; update CHANGELOGWolfgang Denk2009-07-071-2/+3
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Add pci e1000 Ethernet support for P2020 boardRoy Zang2009-06-301-0/+1
| | | | | Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Fix PCI bus address setup for 36-bit configsKumar Gala2009-06-301-3/+3
| | | | | | | | | | | We want the outbound PCI memory map to end at the 4G boundary so we can maximize the amount of space available for inbound mappings if we have large amounts of memory. This matches the device tree setup in the kernel for the 36-bit physical configs for the platforms that have one (MPC8641 HPCN & MPC8572 DS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add P2020DS supportSrikanth Srinivasan2009-06-121-0/+741
The patch adds support for P2020DS reference platform. DDR3 interface uses hard-coded initialization rather than SPD for now and was tested at 667Mhz. Some PIXIS register definitions and associated code sections need to be fixed. TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all tested under u-boot. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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