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* palmas: use palmas_i2c_[read|write]_u8Nishanth Menon2013-05-101-24/+2
| | | | | | | | | | | | | | | | | commit 21144298 (power: twl6035: add palmas PMIC support) introduced twl6035_i2c_[read|write]_u8 Then, commit dd23e59d (omap5: pbias ldo9 turn on) introduced palmas_[read|write]_u8 for precisely the same access function. TWL6035 belongs to the palmas family, so instead of having an twl6035 API, we could use an generic palmas API instead. To stay consistent with the function naming of twl4030,6030 accessors, we use palmas_i2c_[read|write]_u8 Cc: Balaji T K <balajitk@ti.com> Cc: Sricharan R <r.sricharan@ti.com> Reported-by: Ruchika Kharwar <ruchika@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* palmas: rename twl6035_mmc1_poweron_ldo with an palmas generic functionNishanth Menon2013-05-102-2/+2
| | | | | | | | Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs, rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo function. Signed-off-by: Nishanth Menon <nm@ti.com>
* palmas: rename init_settings to an generic palmas initNishanth Menon2013-05-101-1/+1
| | | | | | | Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs, rename twl6035_init_settings with an more generic palmas_init_settings Signed-off-by: Nishanth Menon <nm@ti.com>
* twl6035: rename to palmasNishanth Menon2013-05-103-6/+6
| | | | | | | | | | | TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs Rename twl6035 to palmas to allow reuse across multiple current and future platforms As part of this change, change the CONFIG_TWL6035_POWER to CONFIG_PALMAS_POWER and update usage of header file accordingly. Signed-off-by: Nishanth Menon <nm@ti.com>
* twl6030: move twl6030 register access functions to common header fileNishanth Menon2013-05-101-11/+0
| | | | | | | | twl6030_i2c_[read|write]_u8 can be used else where to access multi-function device such as twl6030, so move the register access functions to the common twl6030.h header file. Signed-off-by: Nishanth Menon <nm@ti.com>
* twl6030: twl6030_i2c_[read|write]_u8 prototype consistentNishanth Menon2013-05-101-34/+34
| | | | | | | | | | | | | | | u-boot standard i2c register access prototype is i2c_read(addr, reg, 1, &buf, 1) i2c_reg_write(u8 addr, u8 reg, u8 val) twl6030_i2c_read_u8(u8 addr, u8 *val, u8 reg) twl6030_i2c_write_u8(u8 addr, u8 val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl6030_i2c_read_u8(u8 addr, u8 reg, u8 *val) twl6030_i2c_write_u8(u8 addr, u8 reg, u8 val) Signed-off-by: Nishanth Menon <nm@ti.com>
* twl4030: make twl4030_i2c_read_u8 prototype consistentNishanth Menon2013-05-102-3/+3
| | | | | | | | | | | | u-boot standard i2c read prototype is i2c_read(addr, reg, 1, &buf, 1) twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val) Signed-off-by: Nishanth Menon <nm@ti.com>
* twl4030: make twl4030_i2c_write_u8 prototype consistentNishanth Menon2013-05-103-31/+31
| | | | | | | | | | | | u-boot standard i2c register write prototype is i2c_reg_write(u8 addr, u8 reg, u8 val) twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg) does not provide consistency, so switch the prototype to be consistent with rest of u-boot i2c operations: twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val) Signed-off-by: Nishanth Menon <nm@ti.com>
* phy: add support for ET1011C physMatt Porter2013-05-103-0/+114
| | | | | | | | | | | | Adds an ET1011C PHY driver which is derived from the Linux kernel PHY driver (drivers/net/phy/et1011c.c) from the v3.9-rc2 tag. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the PG1.0 TI814X EVM. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* cpsw: add support for TI814x slave_regs differencesMatt Porter2013-05-101-0/+6
| | | | | | | | TI814x's version 1 CPSW has a different slave_regs layout. Add support for the differing registers. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* i2c: zynq: Add support for Xilinx ZynqMichal Simek2013-04-302-0/+307
| | | | | | | | | Support Xilinx Zynq i2c controller. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
* mmc: Add support for Xilinx Zynq sdhci controllerMichal Simek2013-04-302-0/+41
| | | | | | | Add support for SD, MMC and eMMC card on Xilinx Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Add support for phy autodetectionMichal Simek2013-04-301-0/+51
| | | | | | | Autodetect phy if phyaddress is setup to -1. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Preserve clk on emio interfaceDavid Andrey2013-04-301-3/+9
| | | | | | | | | | | Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL if the Ethernet interface is connect on EMIO Do not enable emio for this standard board configuration for now. Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Pass phy address to initDavid Andrey2013-04-301-6/+2
| | | | | | | | | Pass the PHY address to the driver init to allow parallel use of both interfaces Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-301-15/+38
| | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Do not initialize BDs againMichal Simek2013-04-301-39/+47
| | | | | | | | | | | BDs can be correctly setup just once and init function performs only phy autodetection and enabling RX/TX. RX/TX are disabled in halt function. This patch solves the problem with repeatable tftp transfers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Simplify return path in zynq_gem_recvMichal Simek2013-04-301-3/+1
| | | | | | | Remove one return from the code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Remove WRAP bit from TX buffer descriptionMichal Simek2013-04-301-2/+1
| | | | | | | | | | | | Removing this bit causes that frame is sent only once. (With wrap big one packet has been sent several times which dramatically decrease throughput) TRM: (Table 16-3: Tx Buffer Descriptor Entry) Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: phy: Define Marvell 88e1518 phyMichal Simek2013-04-301-0/+11
| | | | | | | | This phy is used on zedboard (xilinx zynq platform). Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* mmc: check the revision for sd3.0Jaehoon Chung2013-04-171-0/+2
| | | | | | | | Support to check whether the SD3.0 or not. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Rommel Custodio <sessyargc@gmail.com>
* mmc: support the correct card version for eMMCJaehoon Chung2013-04-171-0/+18
| | | | | | | | | | | eMMC vesrion is supported up to v4.5. But bootloader isn't saw the exact eMMC version. After applied this patch, if use the mmcinfo command, then can see the exactly mmc version. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rommel Custodio <sessyargc@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-04-1531-915/+1948
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| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-141-5/+3
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| | * fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov2013-04-141-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| | * fsl_esdhc: flush cache after IO completionEric Nelson2013-04-141-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
| * | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-141-8/+9
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| | * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-131-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-1296-977/+2396
| |\ \ | | | | | | | | | | | | | | | | Conflicts: drivers/video/exynos_fb.c
| * | | kirkwood_nand: allow usage of NAND_ECC_SOFT_BCHGerlando Falauto2013-04-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of the 1-bit error correction code on the NAND device. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | arm: Remove support for unused s3c64xxBenoît Thébaudeau2013-04-1210-593/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so remove associated code. It will still be possible to restore it later from the Git history if necessary. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | nand: mxc: Switch NAND SPL to generic SPLBenoît Thébaudeau2013-04-124-5/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | nand: mxc: Use appropriate page number in syndrome functionsBenoît Thébaudeau2013-04-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The syndrome functions should use the page number passed as argument instead of the page number saved upon NAND_CMD_READ0. This does not make any difference if the NAND_NO_AUTOINCR option is set, but otherwise this fixes accesses to the wrong pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome()Benoît Thébaudeau2013-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did not match the page being worked on. By the way, replace the GCC-specific __FUNCTION__ with __func__. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | | nand: mxc: Add support for i.MX5Benoît Thébaudeau2013-04-121-11/+108
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | nand: mxc: Prepare to add support for i.MX5Benoît Thébaudeau2013-04-121-46/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some abstraction to NFC definitions so that some parts of the current code can also be used for future i.MX5 code. Clean up a few things by the way. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mtd: nand: mxc_nand: Fix is_16bit_nand()Fabio Estevam2013-04-121-34/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently is_16bit_nand() is a per SoC function and it decides the bus nand width by reading some boot related registers. This method works when NAND is the boot medium, but does not work if another boot medium is used. For example: booting from a SD card and then using NAND to store the environment variables, would lead to the following error: NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width. If it is defined in the board file, then consider 16-bit NAND bus-width, otherwise assume 8-bit NAND is used. This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which states: nand-bus-width : 8 or 16 bus width if not present 8 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BITFabio Estevam2013-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller drivers could use it when a 16-bit NAND is deployed. drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that other NAND drivers could reuse the same symbol. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | | omap_gpmc: add support for hw assisted BCH8Andreas Bießmann2013-04-081-91/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel states: ---8<--- The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not provide automatic error location and correction: this step is implemented using the BCH library. --->8--- And we do so in u-boot. This implementation uses the same layout for BCH8 but it is fix. The current provided layout does only work with 64 Byte OOB. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mansoor Ahamed <mansoor.ahamed@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
| * | | omap_gpmc: change nandecc commandAndreas Bießmann2013-04-081-26/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
| * | | asm/omap_gpmc.h: consolidate common definesAndreas Bießmann2013-04-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/arch-am33xx/omap_gpmc.h and arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate the common parts into a new header. Introduce a new asm/omap_gpmc.h which defines the command part and pulls in the architecture specific one. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | | omap3_beagle: Flush UART3 xmit on enable if TEMT is brokenManfred Huber2013-04-081-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flush UART3 xmit on enable if TEMT is broken On some OMAP3 devices when UART3 is configured for boot mode before SPL starts only THRE bit is set. We have to empty the transmitter before initialization starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT. Signed-off-by: Manfred Huber <man.huber@arcor.de> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | musb: set MUSB speed based on CONFIGBin Liu2013-04-082-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not config MUSB to highspeed mode if CONFIG_USB_GADGET_DUALSPEED is not set, in which case Ether gadget only operates in fullspeed. Reviewed-by: Tom Rini <trini@ti.com> Signed-off-by: Bin Liu <b-liu@ti.com>
| * | | musb: am335x: disable bulk split-combine featureBin Liu2013-04-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On TI AM335x devices, MUSB has bulk split/combine feature enabled in the ConfigData register, but the current MUSB driver does not support it yet. Therefore, disable the feature for now, until the driver adds the support. One usecase which is broken because of this feature is that Ether gadget stops working in Fullspeed mode (by un-defining CONFIG_USB_GADGET_DUALSPEED) After desabled this feature, MUSB driver send packets in proper size (no more than 64 bytes) in Fullspeed mode. This has been validated with Ether gadget in Fullspeed mode on AM335x EVM. Signed-off-by: Bin Liu <b-liu@ti.com>
| * | | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-049-88/+832
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| | * | | Exynos: Add hardware accelerated SHA256 and SHA1Akshay Saraswat2013-03-293-0/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SHA-256 and SHA-1 accelerated using ACE hardware. Signed-off-by: ARUN MANKUZHI <arun.m@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org>
| | * | | spi: exynos: Fix compiler warnings for non-dt systemsVivek Gautam2013-03-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enclosing process_nodes() and spi_get_config() inside CONFIG_OF_CONTROL, since they are compiled only for DT systems. This fixes following warning: exynos_spi.c:391:12: warning: 'process_nodes' defined but not used [-Wunused-function] Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_dp: Add function to parse DP DT nodeAjay Kumar2013-03-272-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function to parse the required platform data fron DP DT node and fill the edp_info structure. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_dp: Make dp_regs globalAjay Kumar2013-03-273-45/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dp_regs variable was redundantly defined across all the functions in the driver even though it contains just the same address. We make it global and initialize it once using exynos_dp_set_base_addr(). >From then on, other funtions can use the address stored in the global variable. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | | video: exynos_fb: add DT support for FIMD driverAjay Kumar2013-03-272-0/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function to parse FIMD data from device tree. The driver still supports non-DT case. Define panel_info statically in some file if you are not using DT. If you have defined DT node for FIMD, panel_info will be filled using the bindings of FIMD DT node. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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