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* Merge branch 'next' of git://git.denx.de/u-bootWolfgang Denk2012-07-3011-261/+378
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot: MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c doc: cleanup - move board READMEs into respective board directories net: sh_eth: add support for SH7757's GETHER net: sh_eth: modify the definitions of regsiter net: sh_eth: add SH_ETH_TYPE_ condition net: sh_eth: clean up for the SH7757's code net: fec_mxc: Fix MDC for xMII net: fec_mxc: Fix setting of RCR for xMII net: nfs: make NFS_TIMEOUT configurable net: Inline the new eth_setenv_enetaddr_by_index function net: allow setting env enetaddr from net device setting net/designware: Consecutive writes to the same register to be avoided CACHE: net: asix: Fix asix driver to work with data cache on net: phy: micrel: make ksz9021 phy accessible net: abort network initialization if the PHY driver fails phylib: phy_startup() should return an error code on failure net: tftp: fix type of block arg to store_block Signed-off-by: Wolfgang Denk <wd@denx.de>
| * net: sh_eth: add support for SH7757's GETHERYoshihiro Shimoda2012-07-231-0/+9
| | | | | | | | | | | | | | | | | | SH7757 has 2 ETHERs and 2 GETHERs. This patch supports the SH7757's GETHER. If CONFIG_SH_ETHER_USE_GETHER is defined using SH7757, the driver handles the GETHER. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * net: sh_eth: modify the definitions of regsiterYoshihiro Shimoda2012-07-232-181/+258
| | | | | | | | | | | | | | | | | | The previous code had many similar definitions in each CPU. This patch borrows from the sh_eth driver of Linux kernel. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * net: sh_eth: add SH_ETH_TYPE_ conditionYoshihiro Shimoda2012-07-232-33/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, the driver supports the following CPUs: - GETHER (Gigabit Ethernet) : SH7763, SH7734 - ETHER (Fast Ethernet) : SH7724, SH7757 And the driver had the following "#if": #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734) #if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724) - Those are for GETHER #if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757) - This is for ETHER So, for clean up the code, this patch adds SH_ETH_TYPE_GETHER and SH_ETH_TYPE_ETHER. And then, the patch modifies the above "#if". Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * net: sh_eth: clean up for the SH7757's codeYoshihiro Shimoda2012-07-232-20/+3
| | | | | | | | | | | | | | | | The SH7757's ETHER can work using the SH7724's setting. So, the patch modifies it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * net: fec_mxc: Fix MDC for xMIIbenoit.thebaudeau@advans2012-07-191-1/+1
| | | | | | | | | | | | | | | | | | The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so mii_speed has to be set for all these interfaces, and not only for MII. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * net: fec_mxc: Fix setting of RCR for xMIIbenoit.thebaudeau@advans2012-07-191-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least on i.MX25, the RMII mode did not work, which is fixed by this patch. The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set it accordingly. According to the xMII and 7-wire (aka GPSI) standards, full duplex should be available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may support full duplex for 7-wire too, but the reference manual does not say that, so avoid an invalid assumption. Actually, the choice between half and full duplex also depends on the endpoint/switch/repeater configuration, so a config option could be added for that, but there has been no need for it so far. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * Merge branch 'next' of git://git.denx.de/u-boot-net into nextWolfgang Denk2012-07-1210-24/+75
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot-net: net: Inline the new eth_setenv_enetaddr_by_index function net: allow setting env enetaddr from net device setting net/designware: Consecutive writes to the same register to be avoided CACHE: net: asix: Fix asix driver to work with data cache on net: phy: micrel: make ksz9021 phy accessible net: abort network initialization if the PHY driver fails phylib: phy_startup() should return an error code on failure net: tftp: fix type of block arg to store_block Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * net/designware: Consecutive writes to the same register to be avoidedDinh Nguyen2012-07-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay. According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required: DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1. GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Matthew Gerlach <mgerlach@altera.com> Acked-by: Amit Virdi <amit.virdi@st.com>
| | * CACHE: net: asix: Fix asix driver to work with data cache onMarek Vasut2012-07-111-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | The asix driver did not align buffers, therefore it didn't work with data cache enabled. Fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
| | * net: phy: micrel: make ksz9021 phy accessibleTroy Kisky2012-07-111-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Micrel accidentally used the same part number for the KS8721 and KSZ9021. So, both cannot be in the same build of u-boot. Add a config option to handle this. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com>
| | * net: abort network initialization if the PHY driver failsTimur Tabi2012-07-116-6/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that phy_startup() can return an actual error code, check for that error code and abort network initialization if the PHY fails. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Nobuhiro Iwamamatsu <nobuhiro.iwamatsu.yj@renesas.com> (sh_eth part) Acked-by: Stephan Linz <linz@li-pro.net> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac) Reviewed-by: Marek Vasut <marex@denx.de> (FEC part)
| | * phylib: phy_startup() should return an error code on failureTimur Tabi2012-07-111-1/+4
| | | | | | | | | | | | | | | | | | | | | phy_startup() calls the PHY driver's startup function, but it ignores the return code from that function, and so it never returns any failures. Signed-off-by: Timur Tabi <timur@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2012-07-204-51/+61
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-usb: usb_storage: fix ehci driver max transfer size smsc95xx: align buffers to cache line size ehci-hcd: change debug() to printf() in case of errors usb: check return value of submit_{control, bulk}_msg usb: pass cache-aligned buffer to usb_get_descriptor() ehci-hcd: fix external buffer cache handling ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment ehci-hcd: program asynclistaddr before every transfer common.h: Introduce DEFINE_CACHE_ALIGN_BUFFER ehci-omap: Do not call dcache_off from omap_ehci_hcd_init Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | smsc95xx: align buffers to cache line sizeIlya Yanok2012-07-181-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Align buffers passed to the USB code to cache line size so they can be DMAed safely. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | | ehci-hcd: change debug() to printf() in case of errorsIlya Yanok2012-07-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Printing message could be useful if something goes really wrong. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | | ehci-hcd: fix external buffer cache handlingIlya Yanok2012-07-181-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Buffer coming from upper layers should be cacheline aligned/padded to perform safe cache operations. For now we don't do bounce buffering so getting unaligned buffer is an upper layer error. We can't check if the buffer is properly padded with current interface so just assume it is (consider changing with in the future). The following changes are done: 1. Remove useless length alignment check. We get actual transfer length not the size of the underlying buffer so it's perfectly valid for it to be unaligned. 2. Move flush_dcache_range() out of while loop or it will flush too much. 3. Don't try to fix buffer address before calling invalidate: if it's unaligned it's an error anyway so let cache subsystem cry about that. 4. Fix end buffer address to be cacheline aligned assuming upper layer reserved enough space. This is potentially dangerous operation so upper layers should be careful about that. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | | ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignmentTom Rini2012-07-182-30/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB spec says that 32 bytes is the minimum required alignment. However on some platforms we have a larger minimum requirement for cache coherency. In those cases, use that value rather than the USB spec minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here as we are not allowed to have tests inside of align(...). Signed-off-by: Tom Rini <trini@ti.com> [marek.vasut]: introduce some crazy macro voodoo Signed-off-by: Marek Vasut <marex@denx.de> [ilya.yanok]: moved external buffer fixes to separate patch, we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN for qh_list, qh and qtd structures to make sure they are proper aligned for both controller and cache operations. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | | ehci-hcd: program asynclistaddr before every transferIlya Yanok2012-07-181-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move or_asynclistaddr programming to ehci_submit_async() function to make sure queue head is properly programmed before every transfer. This solves the problem with changing qh address. Also remove unneeded qh_list->qh_link reprogramming at the end of transfer. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| * | | ehci-omap: Do not call dcache_off from omap_ehci_hcd_initTom Rini2012-07-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has never been completely sufficient and now happens too late to paper over the cache coherency problems with the current USB stack. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | | | Merge branch 'sf' of git://git.denx.de/u-boot-blackfinWolfgang Denk2012-07-208-97/+23
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'sf' of git://git.denx.de/u-boot-blackfin: sf: spansion: inline useless id defines sf: drop unused/duplicate command defines Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | sf: spansion: inline useless id definesMike Frysinger2012-07-201-22/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need for dedicated defines when these really only get used once. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | | | sf: drop unused/duplicate command definesMike Frysinger2012-07-208-75/+11
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | In an effort to unify the spi flash drivers further, drop all the unused and/or duplicate command defines. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | | Blackfin: bfin_mac: drop volatile markings on packet buffersMike Frysinger2012-07-191-2/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that common code doesn't declare these as volatile, we don't need to either anymore. This fixes the build warning: bfin_mac.c: In function 'bfin_EMAC_recv': bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Merge branch 'next' of git://git.denx.de/u-boot-videoWolfgang Denk2012-07-185-9/+33
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.denx.de/u-boot-video: ipu_common: Add ldb_clk for use in parenting the pixel clock ipu_common: Do not hardcode the ipu_clk frequency ipu_common: Rename MXC_CCM_BASE ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53 ipu_common: Only apply the erratum to MX51 video: Rename CONFIG_VIDEO_MX5 mx6: Allow mx6 to access the IPUv3 registers common lcd: minor coding style changes Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | ipu_common: Add ldb_clk for use in parenting the pixel clockEric Nelson2012-07-102-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ldb_clk for use in parenting the pixel clock. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | ipu_common: Do not hardcode the ipu_clk frequencyFabio Estevam2012-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Do not hardcode the ipu_clk frequency and let the board file pass this value. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | ipu_common: Rename MXC_CCM_BASEFabio Estevam2012-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53Fabio Estevam2012-07-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The registers accessed inside clk_ipu_enable/disable are not present on MX6, so make sure they only run on MX51 and MX53. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | ipu_common: Only apply the erratum to MX51Fabio Estevam2012-07-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following erratum : "ENGcm08316 IPU: Clarification regarding the bypass mode registers setup for display and camera interfaces" only applies to mx51, so restrict its usage for this SoC only. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | video: Rename CONFIG_VIDEO_MX5Fabio Estevam2012-07-102-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Rename CONFIG_VIDEO_MX5 as this driver can also be used on mx6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | | mx6: Allow mx6 to access the IPUv3 registersFabio Estevam2012-07-101-1/+11
| | |/ | |/| | | | | | | | | | | | | Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | | FSL/eSDHC: enable the clock to detect the SD cardJerry Huang2012-07-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For FSL low-end processors (VVN2.2), in order to detect the SD card, we should enable PEREN, HCKEN and IPGEN to enable the clock. Otherwise, after booting the u-boot, and then inserting the SD card, the SD card can't be detected. For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used. And when accessing to these reserved bit, no any impact happened. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | SD/MMC: check the card status during erase operationJerry Huang2012-07-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the function 'mmc_send_status' to check the card status. only when the card is ready, driver can send the next erase command to the card, otherwise, the erase will failed: => mmc erase 0 1 MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK => mmc erase 0 2 MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed 1 blocks erase: ERROR => mmc erase 0 4 MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed 1 blocks erase: ERROR Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> CC: Andy Fleming <afleming@gmail.com> CC: Marek Vasut <marex@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | mmc:fix Call mmc_init() when executing mmc_get_dev()Łukasz Majewski2012-07-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code adds call to mmc_init(), for partition related commands (e.g. fatls, fatinfo etc.). It is safe to call mmc_init() multiple times since mmc->has_init flag prevents from multiple initialization. The FAT related code calls get_dev high level method and then uses elements from mmc->block_dev, which is uninitialized until the mmc_init (and thereof mmc_startup) is called. This problem appears on boards, which don't use mmc as the default place for envs Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | mmc: remove the hard setting for tran_speedJaehoon Chung2012-07-131-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_set_clock is set to the hard-coding. But i think good that use the tran_speed value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | i.MX: fsl_esdhc: allow use with cache enabled.Eric Nelson2012-07-131-1/+16
| |/ |/| | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2012-07-122-28/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-i2c: mx28evk: Add I2C support mxs-i2c: Fix internal address byte order mxc_i2c: remove setting speed at each start mx6qsabrelite: add i2c support mxc_i2c: specify i2c base address in config file Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | mxs-i2c: Fix internal address byte orderTorsten Fleischer2012-07-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory. These devices require that the high byte of the internal address has to be written first. The mxs_i2c driver currently writes the address' low byte first. The following patch fixes the byte order of the internal address that should be written to the I2C device. Signed-off-by: Torsten Fleischer <to-fleischer@t-online.de> CC: Marek Vasut <marex@denx.de> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mxc_i2c: remove setting speed at each startTroy Kisky2012-07-111-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other then being very weird, this code was also wrong. For example, say I set speed to 100K. I'll read back the speed as 85937. But the speed is really 85937.5, so we I reset the speed to 85937, I'll get 73660.7. After a couple of transactions my speed is now exactly 68750 so it will remain there. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | mxc_i2c: specify i2c base address in config fileTroy Kisky2012-07-111-21/+4
| |/ | | | | | | | | | | | | | | | | The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd and mx53loco. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | net/sh-ether: Fix build by removing ECSIPR_BRCRXIP and otherNobuhiro Iwamatsu2012-07-101-4/+3
|/ | | | | | | | When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed. Therefore SH7757 and SH7724 can not build. This revise this probelem. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-07-101-1/+17
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: tegra: define fdt_load/fdt_high variables tegra: enable bootz command tegra: usb: Fix device enumeration problem of USB1 tegra: trimslice: set up serial flash pinmux tegra: add pin_mux_spi() board initialization function tegra: add GMC/GMD funcmux entry for SFLASH tegra: bootcmd: start USB only when needed tegra: bootcmd enhancements tegra: add enterrcm command tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG Add env vars describing U-Boot target board tegra: usb: fix wrong error check tegra: add ULPI on USB2 funcmux entry tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches tegra: Add Tamonten Evaluation Carrier support tegra: Use SD write-protect GPIO on Tamonten tegra: Implement gpio_early_init() on Tamonten tegra: Allow boards to perform early GPIO setup tegra: plutux: Add device tree support tegra: medcom: Add device tree support tegra: Rework Tamonten support beagle: add eeprom expansion board info for bct brettl4 Signed-off-by: Wolfgang Denk <wd@denx.de>
| * tegra: usb: Fix device enumeration problem of USB1Jim Lin2012-07-091-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A known hardware issue of USB1 port where bit 1 (connect status change) of PORTSC register will be set after issuing Port Reset (like "usb reset" in u-boot command line). This will be treated as an error and stops later device enumeration. Therefore we clear that bit after Port Reset in order to proceed later device enumeration. Signed-off-by: Jim Lin <jilin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | EXYNOS: Add power Enable/Disable for USB-EHCIRajeshwari Shinde2012-07-091-0/+5
| | | | | | | | | | | | | | | | | | This patch adds functions to enable/disable the power of USB host controller for EXYNOS5. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* | USB: EXYNOS: Set USB 2.0 HOST Link modeRajeshwari Shinde2012-07-091-0/+3
| | | | | | | | | | | | | | This patch adds a function to set usb host mode to USB 2.0 HOST Link for EXYNOS5 Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* | USB: EXYNOS: Incorporate EHCI review commentsRajeshwari Shinde2012-07-092-10/+10
|/ | | | | | | This patch incorates the review comments given by Minkyu Kang for EHCI support on EXYNOS Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* Remove remaining mdelay() macrosAnatolij Gustschin2012-07-082-2/+0
| | | | | | | Drop mdelay() macros since we already have a common mdelay() func. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* MTD: SPEAr SMI: Add write support for length < 4 bytesStefan Roese2012-07-071-4/+18
| | | | | | | | Needed for redundant environment for example. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
* i2c: designware_i2c.c: Add support for the "i2c probe" commandStefan Roese2012-07-071-6/+10
| | | | | | | | | | | | | | | i2c_probe() is changed to reinit the i2c bus upon read failure. This is naturally the case upon i2c bus probing. Also, some printf messages upon read failure are removed. As they would interfere with the "i2c probe" command. Additionally, i2c_set_bus_speed() now returns 0, so that the "i2c speed" command can be used. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
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