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* usb: CONFIG_USB_FASTBOOT prefix replacement for consistencyPaul Kocialkowski2015-07-221-4/+4
| | | | | | | | | | FASTBOOT is defined both by CONFIG_USB_FUNCTION_FASTBOOT AND CONFIG_CMD_FASTBOOT, so it doesn't make much sense to have a CONFIG_USB_FASTBOOT prefix for fastboot-specific options, especially given that other config options for fastboot use the CONFIG_FASTBOOT prefix. This replaces the CONFIG_USB_FASTBOOT prefix with CONFIG_FASTBOOT, for consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* implement Fastboot via USB OTG on bcm28155_ap boardsJiandong Zheng2015-07-221-0/+1
| | | | | Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* usb: gadget: bcm_udc_otg filesJiandong Zheng2015-07-222-0/+73
| | | | | | | Add the required files for the Broadcom UDC OTG interface. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* usb: gadget: fastboot: Dequeue the previous IN request for the current requestPaul Kocialkowski2015-07-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent versions of the fastboot tool will query the partition type before doing an operation on a partition (such as erase, flash, etc). It will then submit the operation as soon as the response for the partition type is received. Usually, the MUSB controller will see that the partition type request return status was read by the host at the very same time as the actual operation request is submitted by the host. However, the operation will be read first (int_rx is handled first in musb_interrupt) and after it is completed, the fastboot USB gadget driver will send another return status. Hence, this happens before the musb gadget framework has had a chance to handle the previous acknowledgement that the host read the return status and dequeue the request. The host will then usually empty the FIFO by the time musb_interrupt gets around handling the return status acknowledgement (for the previous request, this is still on the same musb_interrupt call), so no other interrupt is generated and the most recent return status acknowledgement remains unaccounted for. It will then be used as a response for the next command, and the proper response for it will be delayed to the next command, and so on. Dequeuing the previous IN request in the fastboot code ensures that no previous return status remains. It is acceptable to do it since there is no callback to it anyways. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* usb: gadget: fastboot: Request status and length check in rx handlerPaul Kocialkowski2015-07-221-5/+6
| | | | | | | | | This avoids handling requests that have an error status or no data. In particular, this avoids showing unnecessary error messages when the USB gadget gets disconnected (e.g. with fastboot continue) and the fastboot USB gadget driver sends an error back to the host (that has disconnected already). Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* usb: gadget: Weak board_usb_init/cleanup definitions in USB download gadget codePaul Kocialkowski2015-07-221-0/+13
| | | | | | | | | | | | Weak versions of board_usb_init and board_usb_cleanup are defined in common USB host code, but it is also used for USB device gadgets, so we also need a weak definition of it when there is no USB host enabled. Both weak definitions do not conflict. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* usb: Fastboot function config for better consistency with other functionsPaul Kocialkowski2015-07-221-1/+1
| | | | | | | | | | | | USB download gadget functions such as thor and dfu have a separate config option for the USB gadget part of the code, independent from the command part. This switches the fastboot USB gadget to the same scheme, for better consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* usb: USB download gadget and functions config options coherent namingPaul Kocialkowski2015-07-222-5/+5
| | | | | | | | | | | | This introduces a coherent scheme for naming USB download gadget and functions config options. The download USB gadget config option is moved to CONFIG_USB_GADGET_DOWNLOAD for better consistency with other gadgets and each function's config option is moved to a CONFIG_USB_FUNCTION_ prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
* drivers: usb: fsl: Remove LS102XA immap inclusionNikhil Badola2015-07-221-1/+0
| | | | | | | | Remove LS102XA immap header inclusion from xhci fsl driver. It removes redefinition warnings when built for platforms other than LS102XA Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* drivers: usb: fsl: Implement Erratum A-009116 for XHCI controllerNikhil Badola2015-07-222-0/+9
| | | | | | | This adjusts (micro)frame length to appropriate value thus avoiding USB devices to time out over a longer run Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* drivers: usb: fsl: Remove warnings for 64-bit architecturesNikhil Badola2015-07-221-4/+4
| | | | | | | Replace uint32_t with uintptr_t to remove compilation warnings for 64-bit architectures. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
* usb: fsl: Add XHCI driver supportRamneek Mehresh2015-07-222-0/+110
| | | | | | Add xhci driver support for all FSL socs Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: xhci: keystone: Remove common dwc3 drv functions callsRamneek Mehresh2015-07-221-88/+0
| | | | | | | Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: xhci: omap: Remove common dwc3 drv functions callsRamneek Mehresh2015-07-222-78/+0
| | | | | | | Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: xhci: exynos: Remove common dwc3 drv functions callsRamneek Mehresh2015-07-221-78/+0
| | | | | | | Remove all redundant dwc3 driver function calls that are defined by dwc3 driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* usb: dwc3: Add DWC3 controller driver supportRamneek Mehresh2015-07-222-0/+92
| | | | | | Add support for DWC3 XHCI controller driver Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-07-2010-185/+266
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| * driver/ldpaa_eth:Avoid infinite loop in ldpaa_eth_rxPrabhakar Kushwaha2015-07-201-1/+8
| | | | | | | | | | | | | | | | Change infinite loop mechanism to timer based polling for QBMAN release in ldpaa_eth_rx. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth: Avoid TX conf framesPrabhakar Kushwaha2015-07-202-111/+4
| | | | | | | | | | | | | | | | | | | | | | Polling of TX conf frames is not a mandatory option. Packets can be transferred via WRIOP without TX conf frame. Configure ldpaa_eth driver to use TX path without confirmation frame Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth: Add timeout handling DQRR entry readPrabhakar Kushwaha2015-07-201-14/+22
| | | | | | | | | | | | | | | | | | | | | | Volatile command does not return frame immidiately, need to wait till a frame is available in DQRR. Ideally it should be a blocking call. Add timeout handling for DQRR frame instead of retry counter. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth: Retry enqueue if portal was busyPrabhakar Kushwaha2015-07-201-2/+30
| | | | | | | | | | | | | | | | | | | | | | Do not immediately return if the enqueue function returns -EBUSY; re-try mulitple times. if timeout occures, release the buffer. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder2015-07-201-0/+62
| | | | | | | | | | | | | | | | | | | | | | This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: dynamically create ICID pool in DPCStuart Yoder2015-07-201-0/+36
| | | | | | | | | | | | | | | | | | | | delete any existing ICID pools in the DPC and create a new one based on the stream ID partitioning for the SoC Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl-lsch3: partition stream IDsStuart Yoder2015-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Stream IDs on ls2085a devices are not hardwired and are programmed by sw. There are a limited number of stream IDs available, and the partitioning of them is scenario dependent. This header defines the partitioning between legacy, PCI, and DPAA2 devices. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Return error for major version mismatchPrabhakar Kushwaha2015-07-201-2/+7
| | | | | | | | | | | | | | | | | | | | Management complex major version should match to the firmware present in flash. Return error during mismatch of major version. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Update qbman driverPrabhakar Kushwaha2015-07-203-37/+53
| | | | | | | | | | | | | | | | | | | | | | | | Update qbman driver - As per latest available qbman driver - Use of atomic APIs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Geoff Thorpe <Geoff.Thorpe@freescale.com> CC: Haiying Wang <Haiying.Wang@freescale.com> CC: Roy Pledge <Roy.Pledge@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers: fsl-mc: Update flibs to mc-0.6.0.1Prabhakar Kushwaha2015-07-202-6/+8
| | | | | | | | | | | | | | | | | | | | Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in dpio_attr. These are now offsets from the SoC QBMan portals base. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Autoload AOIP image from NOR flashJ. German Rivera2015-07-201-0/+23
| | | | | | | | | | | | | | | | | | Load AIOP image from NOR flash into DDR so that the MC firmware the MC fw can start it at boot time Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ldpaa_eth:Flush buffer before seeding BMAN after TX_confPrabhakar Kushwaha2015-07-201-0/+1
| | | | | | | | | | | | | | | | Flush buffer before releasing to BMan after TX_conf to ensure, the core does not have any cachelines that the WRIOP will DMA to. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * drivers/fsl-mc: Make MC boot error messages more readableJ. German Rivera2015-07-201-18/+13
| | | | | | | | | | | | | | | | | | Make it easier for the user to notice when the MC firmware had problems booting. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/fsl_debug_server: Fix the DDR hide logic for LS2085aBhupesh Sharma2015-07-202-8/+5
| | | | | | | | | | | | | | | | | | | | This patch fixes the DDR hide logic for LS2085a, correcting the way the Debug Server FW and MC FW images are placed on the top of system DDR and how the rest of the system DDR space is made visibile to Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver/ddr/fsl: Add a hook to update SPD addressYork Sun2015-07-201-0/+8
| | | | | | | | | | | | | | | | In case SPD address changes between board revisions, updating SPD address can be called from board file. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
* | fdt: armv8: Fix build warnings on armv8Haikun Wang2015-07-201-2/+2
|/ | | | | | | | | | | | | | | | | | | Fix below build warnings on armv8, drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’: drivers/spi/fsl_dspi.c:667:2: warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 2 has type ‘fdt_addr_t’ [-Wformat=] debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n", ^ lib/fdtdec.c: In function ‘fdtdec_get_addr_size’: lib/fdtdec.c:105:4: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘fdt_size_t’ [-Wformat=] debug("addr=%08lx, size=%08lx\n", ^ Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-07-1512-963/+314
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| * pci: Disable expansion ROM address decoding when signature check failsBin Meng2015-07-141-0/+4
| | | | | | | | | | | | | | | | | | | | We should not leave the expansion ROM address window open when there is not a valid ROM. Suggested-by: Matt Porter <mporter@konsulko.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * pci: Configure expansion ROM during auto config processBin Meng2015-07-142-31/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * drivers: block: Remove the ata_piix driverBin Meng2015-07-143-789/+0
| | | | | | | | | | | | | | | | | | | | | | This driver was originally added to support the native IDE mode for Intel chipset, however it has some bugs like not supporting ATAPI devices, endianness issue, or even broken build when CONFIG_LAB48. Given no board is using this driver as of today, rather than fixing all these issues we just remove it from the source tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-141-2/+6
| | | | | | | | | | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: pci: Tidy up the generic x86 PCI driverSimon Glass2015-07-141-5/+8
| | | | | | | | | | | | | | | | This driver should use the x86 PCI configuration functions. Also adjust its compatible string to something generic (i.e. without a vendor name). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: spi: Correct BIOS protection logic for ICH9Simon Glass2015-07-141-5/+4
| | | | | | | | | | | | | | | | | | The logic is incorrect and currently has no effect. Fix it so that we can write to SPI flash, since by default it is write-protected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
| * dm: spi: Correct status register access widthSimon Glass2015-07-141-1/+5
| | | | | | | | | | | | | | | | | | The status register on ICH9 is a single byte, so use byte access when writing to it, to avoid updating the control register also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * x86: Configure VESA parameters before loading Linux kernelBin Meng2015-07-141-0/+28
| | | | | | | | | | | | | | | | | | Store VESA parameters to Linux setup header so that vesafb driver in the kernel could work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
| * x86: Move VGA option rom macros to KconfigBin Meng2015-07-141-2/+2
| | | | | | | | | | | | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * video: Add 32-bit color depth support for VBEJian Luo2015-07-141-0/+1
| | | | | | | | | | | | | | | | | | | | The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * video: vesa_fb: Look up VGA device by class instead of idBin Meng2015-07-141-14/+2
| | | | | | | | | | | | | | | | | | Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-141-1/+1
| | | | | | | | | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-142-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: rtc: Support mc146818 driver in driver modelBin Meng2015-07-141-108/+204
| | | | | | | | | | | | | | | | Add driver model support to the mc146818 rtc driver. Also clean up the driver a little bit for coding convention issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Move MP initialization codes into a common placeBin Meng2015-07-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the new 'get_count' method for baytrail and cpu_x86 drivers. Now we call cpu_get_count() in mp_init() to get the number of CPUs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: cpu: Add a new get_count method to cpu uclassBin Meng2015-07-141-0/+10
| | | | | | | | | | | | | | | | Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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