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| * | usb: gadget: mv_udc: zero transfer descriptor memory on probeTroy Kisky2013-10-201-0/+1
| | | | | | | | | | | | | | | | | | Since we flush the TD, we may as well set it to a known value. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | usb: gadget: mv_udc: flush item before headTroy Kisky2013-10-201-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Make sure the transfer descriptor is flushed before the queue is updated so that the controller will not see old information. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | usb: gadget: mv_udc: set is_dualspeed = 1Troy Kisky2013-10-201-0/+1
| | | | | | | | | | | | | | | | | | This controller support full and high speed. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | usb: gadget: mv_udc: fix typo in error messageTroy Kisky2013-10-201-2/+2
| | | | | | | | | | | | | | | | | | Change 'nfo=' to 'info=' Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | usb: gadget: ether: return error from rx_submit if no requestTroy Kisky2013-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This prevents a crash if tftpboot is given a bad filename. rx_req will be released by eth_reset_config which is called by eth_disconnect, which is called using the .disconnect member of usb_gadget_driver by mv_pullup in mv_udc which is called using the .pullup member of usb_gadget_ops by usb_gadget_disconnect which is called by usb_eth_halt which is called using the .halt member of eth_device by eth_halt which is called by TftpHandler when TFTP_ERR_FILE_NOT_FOUND or TFTP_ERR_ACCESS_DENIED occurs I trigger this with the following commands setenv ipaddr 10.0.0.2 && setenv netmask 255.255.255.0 && setenv serverip 10.0.0.1 setenv usbnet_devaddr 00:11:22:33:44:55 && setenv usbnet_hostaddr 00:aa:bb:cc:dd:ee setenv ethprime usb_ether && setenv ethact usb_ether && setenv ncip 10.0.0.1 tftpboot 10800000 10.0.0.1:missing_file Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | usb: gadget: ether set wMaxPacketSizeTroy Kisky2013-10-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set wMaxPacketSize for full speed descriptors fs_source_desc, fs_sink_desc to 64. Full-speed bulk endpoint can have a maximum packet size of 8, 16, 32, or 64 bytes, so choice 64. The hs_source_desc, hs_sink_desc, already have their wMaxPacketSize set to 512. That is the only legal value for high speed bulk endpoints. Strictly speaking, this patch is not needed because usb_ep_autoconfig will call ep_matches which will override wMaxPacketSize for BULK endpoints only with the size associated with the endpoint setup by the udc driver. But if you want to rely on this, you may as well combine the full speed descriptor with the high speed descriptor to minimize confusion. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * | OMAP5: USB: Add OMAP xHCI file and headerDan Murphy2013-10-202-0/+327
| | | | | | | | | | | | | | | | | | | | | | | | Add the OMAP file for the xHCI Host controller This code will initilialize the proper components within the OMAP5 to enable the xHCI host controller. Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | ARM: OMAP5: Power: Add new function to turn on SMPS10Dan Murphy2013-10-201-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Add new functionality to turn on SMPS10 regulator. This supplies the VBUS to devices connected to the USB host ports Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | exynos: usb: Switch USB VBUS GPIOs to be device tree configuredJulius Werner2013-10-202-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some Exynos boards, such as the SMDK5250, control USB port power through a GPIO pin. For now this had been hardcoded in the exynos5-dt board file, but not all boards use the same pin, requiring local changes to support different boards. This patch moves the GPIO initialization into the USB host controller drivers which they belong to, and uses the samsung,vbus-gpio parameter in the device tree to configure it. Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de>
| * | USB: XHCI: Add xHCI host controller support for Exynos5Vivek Gautam2013-10-202-0/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds driver layer for xHCI controller in Samsung's exynos5 soc. This interacts with xHCI host controller stack. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | USB: xHCI: Add stack support for xHCIVivek Gautam2013-10-205-0/+3947
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds stack layer for eXtensible Host Controller Interface which facilitates use of USB 3.0 in host mode. Adapting xHCI host controller driver in linux-kernel by Sarah Sharp to needs in u-boot. Initial porting from Linux kernel version 3.4, with following top commit history of drivers/usb/host/xhci* : cf84055 xHCI: Cleanup isoc transfer ring when TD length mismatch found This adds the basic xHCI host controller driver with bare minimum features: - Control/Bulk transfer support has been added with required infrastructure for necessary xHC data structures. - Stream protocol hasn't been supported yet. - No support for quirky devices has been added. Signed-off-by: Vikas C Sajjan <vikas.sajjan@samsung.com> Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
| * | usb: Move 'bmRequestType' USB device request macros from EHCI headerVivek Gautam2013-10-201-16/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Macros defining bmRequestType field of USB device request, given in table 9.2 USB 2.0 spec, are rather generic macros which can be further used by other Host controller stacks. So moving them to usb_defs header. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Cc: Julius Werner <jwerner@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Dan Murphy <dmurphy@ti.com> Cc: Marek Vasut <marex@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-10-177-246/+1104
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| * | i2c: eliminate warnings in i2c_reloc_fixup functionMasahiro Yamada2013-10-171-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | The prototype of handlers had changed. This commit uses cast with (void *) rather than the handler-specific prototype. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | i2c: s3c24xx: add hsi2c controller supportNaveen Krishna Ch2013-10-172-51/+616
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for hsi2c controller available on exynos5420. Note: driver currently supports only fast speed mode 100kbps Change-Id: I02555b1dc8f4ac21c50aa5158179768563c92f43 Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: R. Chandrasekar <rc.sekar@samsung.com>
| * | exynos: i2c: Change FDT bus setup code to enumerate ports correctlySimon Glass2013-10-172-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the i2c ports are enumerated in a strange way - the fdtdec_find_aliases_for_id() function is used, but then the ID returned is ignored and the ports are renumbered. The effect is the same provided that the device tree has the ports in the same order, or uses aliases, and has no gaps, but it is not correct. Adjust the code to use the function as intended. This will allows device tree aliases to change the device order if required. As a result, the i2c_busses variable is dropped. We can't be sure that there are no 'holes' in the list of buses, so must check the whole array. Note: it seems that non-FDT operation is now broken in this drive and will need to be reinstated for upstream. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59369 Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
| * | exynos: i2c: Fix i2c driver to handle NACKs properlyNaveen Krishna Ch2013-10-171-124/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Exynos5 i2c driver does not handle NACKs properly. This change: - fixes the NACK processing problem (do not continue transaction if address cycle was NACKed) - eliminates a fair amount of duplicate code Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Simon Glass <sjg@google.com> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
| * | Fix: nommu I2C adapter relocation errorJens Scharsig (BuS Elektronik)2013-10-171-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NoMMU systems have a access violation problem with i2c_reloc_fixup. Blame for it is a double relocation of the adapter itself. The i2c_adap_p is already relocated, if i2c_reloc_fixup is called. This patch removes the relocation of i2c_adap_p from i2c_reloc_fixup to fix this. Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
| * | i2c: sh_i2c: Avoid using I2C prior to relocationNobuhiro Iwamatsu2013-10-171-2/+8
| | | | | | | | | | | | | | | | | | | | | If user uses the I2C in before the relocation, board of sh and rmobile will not start. This will solve this problem. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | i2c, core: optimze i2c_set_bus_num()Heiko Schocher2013-10-171-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | check first, if we are on the bus, we want to enable. If so, return immediately, do not calc max adapter number, nor check other things. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
| * | i2c: Add support for Renesas rcarNobuhiro Iwamatsu2013-10-172-0/+289
| | | | | | | | | | | | | | | | | | | | | This supports i2c controller for Renesas rcar. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | i2c: Zynq: Support for TI PCA9548 bus multiplexerMichael Burr2013-10-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | (Interface is not quite the same as Phillips PCA9547.) Signed-off-by: Michael Burr <michael.burr@logicpd.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <monstr@monstr.eu>
| * | i2c: mxc: move to new subsystemtrem2013-10-172-60/+79
| |/ | | | | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* | PCIe:change the method to get the address of a requested capability in ↵Zhao Qiang2013-10-162-12/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* | powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha2013-10-162-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
* | SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII modeZhao Qiang2013-10-162-0/+45
|/ | | | | | | | | | | | | | | | | | | | | Fix PHY addresses for QSGMII Riser Card working in SGMII mode on board P3041/P5020/P4080/P5040/B4860. QSGMII Riser Card can work in SGMII mode, but having the different PHY addresses. So the following steps should be done: 1. Confirm whether QSGMII Riser Card is used. 2. If yes, set the proper PHY address. Generally, the function is_qsgmii_riser_card() is for step 1, and set_sgmii_phy() for step 2. However, there are still some special situations, take P5040 and B4860 as examples, the PHY addresses need to be changed when serdes protocol is changed, so it is necessary to confirm the protocol before setting PHY addresses. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* microblaze: Fix watchdog initializationMichal Simek2013-10-161-4/+2
| | | | | | | | | | | The patch: "blackfin: Move blackfin watchdog driver out of the blackfin arch folder." (sha1: e9a389a18477c1c57a0b30e9ea8f4d38c6e26e63) changed hw_watchdog_init() prototype which didn't match with Microblaze one. This patch fixes the driver and Microblaze initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spi: mxc_spi: Fix double incrementing read pointer for unaligned buffersTimo Herbrecher2013-10-161-1/+1
| | | | | | | | If dout buffer is not 32 bit-aligned or data to transmit is not multiple of 32 bit the read data pointer is already incremented on single byte reads. Signed-off-by: Timo Herbrecher <t.herbrecher@gateware.de> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Add missing Atmel at25df321 flashBo Shen2013-10-161-0/+1
| | | | | | | | | As the spi flash transfer to multiple parts, it is forgot to add Atmel AT25DF321 spi flash support, which broken several Atmel EK boards which this chip. So, add it Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: Add GPL-2.0+ SPDX-License-Identifier for missing filesJagannadha Sutradharudu Teki2013-10-165-5/+5
| | | | | | | Added GPL-2.0+ SPDX-License-Identifier for missed spi source files. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add GPL-2.0+ SPDX-License-Identifier for missing onesJagannadha Sutradharudu Teki2013-10-164-4/+4
| | | | | | | | Added GPL-2.0+ SPDX-License-Identifier for missed sf source files. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Bo Shen <voice.shen@atmel.com>
* sf: Minor cleanups.Jagannadha Sutradharudu Teki2013-10-163-6/+7
| | | | | | | | | - Add comments. - Renamed few macros. - Add tabs. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Bo Shen <voice.shen@atmel.com>
* sf_ops: Unify bank_sel calculation codeJagannadha Sutradharudu Teki2013-10-161-16/+20
| | | | | | | Unified the bank_sel calculation code for erase and write ops. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Coding Style cleanup: drop some excessive empty linesWolfgang Denk2013-10-141-5/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: remove trailing empty linesWolfgang Denk2013-10-143-3/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup: replace leading SPACEs by TABsWolfgang Denk2013-10-1412-31/+31
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-1434-34/+34
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-146-0/+411
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| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-10-116-0/+411
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| | * power:battery: add battery support for Trats2 boardPiotr Wilczek2013-09-252-0/+66
| | | | | | | | | | | | | | | | | | Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * drivers:power:max77693: add support for new multi function pmic max77693Piotr Wilczek2013-09-254-0/+345
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add support for new multi function pmic max77693. The driver is split into three modules: pmic, muic and fuelgage. Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-10-144-12/+35
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| * | | mtd: driver _read() returns max_bitflips; mtd_read() returns -EUCLEANPaul Burton2013-10-094-12/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux modified the MTD driver interface in commit edbc4540 (with the same name as this commit). The effect is that calls to mtd_read will not return -EUCLEAN if the number of ECC-corrected bit errors is below a certain threshold, which defaults to the strength of the ECC. This allows -EUCLEAN to stop indicating "some bits were corrected" and begin indicating "a large number of bits were corrected, the data held in this region of flash may be lost soon". UBI makes use of this and when -EUCLEAN is returned from mtd_read it will move data to another block of flash. Without adopting this interface change UBI on U-boot attempts to move data between blocks every time a single bit is corrected using the ECC, which is a very common occurance on some devices. For some devices where bit errors are common enough, UBI can get stuck constantly moving data around because each block it attempts to use has a single bit error. This condition is hit when wear_leveling_worker attempts to move data from one PEB to another in response to an -EUCLEAN/UBI_IO_BITFLIPS error. When this happens ubi_eba_copy_leb is called to perform the data copy, and after the data is written it is read back to check its validity. If that read returns UBI_IO_BITFLIPS (in response to an MTD -EUCLEAN) then ubi_eba_copy_leb returns 1 to wear_leveling worker, which then proceeds to schedule the destination PEB for erasure. This leads to erase_worker running on the PEB, and following a successful erase wear_leveling_worker is called which begins this whole cycle all over again. The end result is that (without UBI debug output enabled) the boot appears to simply hang whilst in reality U-boot busily works away at destroying a block of the NAND flash. Debug output from this situation: UBI DBG: ensure_wear_leveling: schedule scrubbing UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083 UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 1027 UBI DBG: ubi_io_read: read 4096 bytes from PEB 1027:4096 UBI DBG: ubi_eba_copy_leb: copy LEB 0:0, PEB 1027 to PEB 4083 UBI DBG: ubi_eba_copy_leb: read 1040384 bytes of data UBI DBG: ubi_io_read: read 1040384 bytes from PEB 1027:8192 UBI: fixable bit-flip detected at PEB 1027 UBI DBG: ubi_io_write_vid_hdr: write VID header to PEB 4083 UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:4096 UBI DBG: ubi_io_read_vid_hdr: read VID header from PEB 4083 UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:4096 UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:8192 UBI DBG: ubi_io_read: read 4096 bytes from PEB 4083:8192 UBI: fixable bit-flip detected at PEB 4083 UBI DBG: schedule_erase: schedule erasure of PEB 4083, EC 55, torture 0 UBI DBG: erase_worker: erase PEB 4083 EC 55 UBI DBG: sync_erase: erase PEB 4083, old EC 55 UBI DBG: do_sync_erase: erase PEB 4083 UBI DBG: sync_erase: erased PEB 4083, new EC 56 UBI DBG: ubi_io_write_ec_hdr: write EC header to PEB 4083 UBI DBG: ubi_io_write: write 4096 bytes to PEB 4083:0 UBI DBG: ensure_wear_leveling: schedule scrubbing UBI DBG: wear_leveling_worker: scrub PEB 1027 to PEB 4083 ... This patch adopts the interface change as in Linux commit edbc4540 in order to avoid such situations. Given that none of the drivers under drivers/mtd return -EUCLEAN, this should only affect those using software ECC. I have tested that it works on a board which is currently out of tree, but which I hope to be able to begin upstreaming soon. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stefan Roese <sr@denx.de>
* | | | usb: Prevent using reserved registers on DM36x usbAndrew Murray2013-10-101-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The musb driver defines and uses MUSB_CSR0_H_DIS_PING, however this bit is reserved on the DM36x. Thus this patch ensures that the reserved bit is not accesssed. It has been observed that some USB devices will fail to enumerate with errors such as 'error in inquiry' without this patch. See http://www.ti.com/litv/pdf/sprufh9a for details. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Acked-by: Marek Vasut <marex@denx.de>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-081-5/+5
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| * | | usb: Fix error handling in musb_hcd.cAndrew Murray2013-10-071-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The wait_until_[rx|tx]ep_ready functions return a u8 to indicate success containing the value 0, 1 or -1. This patch changes the return type to an int to accommodate the negative return values. These functions are used in the file using calls such as if (!wait_until... Where a -1 is returned it is mishandled and treated as success instead of a CRC error. This patch addresses this. Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk> Acked-by: Marek Vasut <marex@denx.de>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-10-0818-2205/+1417
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| * | | spi: exynos: Support word transfersRajeshwari Shinde2013-10-081-15/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since SPI register access is so expensive, it is worth transferring data a word at a time if we can. This complicates the driver unfortunately. Use the byte-swapping feature to avoid having to convert to/from big endian in software. This change increases speed from about 2MB/s to about 4.5MB/s. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | spi: exynos: Minimise access to SPI FIFO levelRajeshwari Shinde2013-10-081-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Accessing SPI registers is slow, but access to the FIFO level register in particular seems to be extraordinarily expensive (I measure up to 600ns). Perhaps it is required to synchronise with the SPI byte output logic which might run at 1/8th of the 40MHz SPI speed (just a guess). Reduce access to this register by filling up and emptying FIFOs more completely, rather than just one word each time around the inner loop. Since the rxfifo value will now likely be much greater that what we read before we fill the txfifo, we only fill the txfifo halfway. This is because if the txfifo is empty, but the rxfifo has data in it, then writing too much data to the txfifo may overflow the rxfifo as data arrives. This speeds up SPI flash reading from about 1MB/s to about 2MB/s on snow. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | spi: exynos: Support a delay after deactivateRajeshwari Shinde2013-10-081-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For devices that need some time to react after a spi transaction finishes, add the ability to set a delay. Implement this as a delay on the first/next transaction to avoid any delay in the fairly common case where a SPI transaction is followed by other processing. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
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