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| * spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependencyBoris Brezillon2016-06-191-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced to explicitly depend on platforms that are not already defining it in their include/configs/<board>.h header. Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS depends on it, remove the dependency on NAND_SUNXI and make it dependent on SPL selection. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: remove support for so-called 'syndrome' modeBoris Brezillon2016-06-191-42/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi SPL NAND controller driver supports use 'BootROM'-like configs, that is, configs where the ECC bytes and real data are interleaved in the page instead of putting ECC bytes in the OOB area. Doing that has several drawbacks: - since you're interleaving data and ECC bytes you can't use the whole page otherwise you might override the bad block marker with non-FF bytes. - to solve the bad block marker problem, the ROM code supports partially using the page, but this introduces a huge penalty both in term of read speed and NAND memory usage. While this is fine for rather small binaries(like the SPL one which is at maximum 24KB large), it becomes non-negligible for the bootloader image (several hundred of KB). - auto-detection of the page size is not reliable (this is in my opinion the biggest problem). If you get the page size wrong, you'll end up reading data at a different offset than what was specified by the caller and the reading may succeed (if valid data were written at this address). For all those reasons I think it's wiser to completely remove support for 'syndrome' configs. If we ever need to support it again, then I'd recommend specifying all the config parameters through Kconfig options. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | mmc: add MMC_VERSION_5_1Stefan Wahren2016-06-201-0/+3
| | | | | | | | Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
* | clk: convert API to match reset/mailbox styleStephen Warren2016-06-1924-388/+462
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | reset: implement a reset testStephen Warren2016-06-194-0/+173
| | | | | | | | | | | | | | | | | | This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Add a reset driver framework/uclassStephen Warren2016-06-195-0/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | mailbox: add Tegra186 HSP driverStephen Warren2016-06-193-0/+171
| | | | | | | | | | | | | | | | | | | | Tegra186's HSP module implements doorbells, mailboxes, semaphores, and shared interrupts. This patch provides a driver for HSP, and hooks it into the mailbox API. Currently, only doorbells are supported. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | mailbox: rename headersStephen Warren2016-06-193-4/+4
| | | | | | | | | | | | | | | | Rename mailbox*.h to match the naming convention requested during review of the new reset subsystem. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | gpio: pca953x: Fix register reading past 8th GPIOmario.six@gdsys.cc2016-06-191-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | A bug in the pca953x driver prevents correct reading of GPIO input values beyond the 8th GPIO; all values are reported as zero. Setting of GPIO output values is not affected. This patch fixes the reading behavior. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Peng Fan <van.freenix@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: add manual relocation for devicesAngelo Dureghello2016-06-191-0/+15
| | | | | | | | | | | | | | | | Some architectures as m68k still need to use CONFIG_NEEDS_MANUAL_RELOC, and are not still using the device tree. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-06-187-39/+299
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
| * | usb: ehci: only shutdown opened controllerPeng Fan2016-06-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the usb controller is not running, no need to shutdown it, otherwise `usb stop` complains about: "EHCI failed to shut down host controller". To i.MX7D SDB, there are two usb ports, one Host, one OTG. If we only plug one udisk to the Host port and then `usb start`, the OTG controller for OTG port does not run actually. Then, if `usb stop`, the OTG controller for OTG port will also be shutdown, but it is not running. This patch adds a check to only shutdown the running controller. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: "Stefan Brüns" <stefan.bruens@rwth-aachen.de> Cc: Stephen Warren <swarren@nvidia.com>
| * | usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash2016-06-133-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | fsl: usb: make errata function common for PPC and ARMSriram Dash2016-06-133-2/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following things: 1. Makes the errata checking code common for PPC and ARM 2. Moves all these static inline functions into a dedicated C file Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | usb: xhci: fsl: code cleanup for device tree fixup for fsl usb controllersSriram Dash2016-06-131-38/+56
| | | | | | | | | | | | | | | | | | | | | | | | Performs code cleanup for device tree fixup for fsl usb controllers by making functions to handle these similar errata checking code. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
| * | usb: dwc2_udc_otg: support 8-bit interfaceSteve Rae2016-06-132-0/+14
| | | | | | | | | | | | | | | | | | | | | Define CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 to allow the physical interface to be 8-bit (rather than 16-bit). Signed-off-by: Steve Rae <srae@broadcom.com>
* | | armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* | | serial: Introduce linflex uart supportStoica Cosmin-Stefan2016-06-132-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linflex module is integrated on some NXP automotive SoCs part of the former Freescale portfolio, like S32V234, an SoC for Advanced Driver Assistance Systems. Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Chircu Bogdan <Bogdan.Chircu@freescale.com> Original-signed-off-by: Depons Eric <eric.depons@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-135-117/+435
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| * | | serial: atmel_usart: Add device tree supportWenyou Yang2016-06-121-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree support. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | at91: video: Support driver-model for the LCD driverSimon Glass2016-06-121-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver-model support to this driver. Most features can be controlled from the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | at91: video: Prepare for driver-model conversionSimon Glass2016-06-121-36/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the driver to use struct display_timing for its display timing. This is what is used by driver-model and allows the LCD init code to be common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | at91: nand: Set up the ECC strength correctlyAndre Renaud2016-06-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This needs to be set to avoid a fatal error when ECC is used. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | at91: Correct NAND ECC register accessAndre Renaud2016-06-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the wrote base register value. Fix it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | net: macb: Convert to driver modelSimon Glass2016-06-121-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver-model support to this driver. The old code remains for now so that we can convert boards one at a time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | net: macb: Flush correct cache portion when sendingSimon Glass2016-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The end address of the cache flush must be cache-line-aligned since otherwise (at least on ARM926-EJS) the request is ignored. When the cache is enabled this means that packets are not sent. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | net: macb: Prepare for driver-model conversionSimon Glass2016-06-121-75/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust this driver to avoid using struct netdev in functions that driver model will call. Also refactor the receive function to be compatible with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | gpio: at91: Fix pullup/pulldown configuration on PIO3Marek Vasut2016-06-121-3/+8
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On systems with PIO3 (SAMA5D3/D4/..), the pullup and pulldown configuration is mutualy exclusive. This patch assures that the opposite pull resistor gets disabled before the requested pull resistor is enabled. This changes behavior of at91_set_pio_pulldown() such that the pullup is only disabled if pulldown is to be enabled. This changes behavior of at91_set_pio_pullup() such that the pulldown is only disabled if pullup is to be enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | verified-boot: Minimal support for booting U-Boot proper from SPLTeddy Reed2016-06-122-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows a board to configure verified boot within the SPL using a FIT or FIT with external data. It also allows the SPL to perform signature verification without needing relocation. The board configuration will need to add the following feature defines: CONFIG_SPL_CRYPTO_SUPPORT CONFIG_SPL_HASH_SUPPORT CONFIG_SPL_SHA256 In this example, SHA256 is the only selected hashing algorithm. And the following booleans: CONFIG_SPL=y CONFIG_SPL_DM=y CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_LIBFDT=y CONFIG_SPL_FIT_SIGNATURE=y Signed-off-by: Teddy Reed <teddy.reed@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Acked-by: Sumit Garg <sumit.garg@nxp.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-06-121-0/+7
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| * | | sunxi: musb: Properly turn of musb controller before bootingHans de Goede2016-06-101-0/+7
| |/ / | | | | | | | | | | | | | | | | | | | | | Turn of the clock and assert the reset when musb_stop gets called, so that the os gets the musb controller in a pristine state. This fixes a spurious VBus error interrupt triggering as soon as the Linux musb driver loads. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-06-123-0/+457
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| * | | spi: pic32_spi: add SPI master driver for PIC32 SoC.Purna Chandra Mandal2016-06-103-0/+457
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver implements SPI protocol in master mode to communicate with the SPI device connected on SPI bus. It handles /CS explicitly by controlling respective pin as gpio ('cs-gpios' property in dt node) and uses PIO mode for SPI transaction. It is configurable based on driver-model only. Cc: Jagan Teki <jteki@openedev.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-124-5/+5
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| * | | block: dwc_ahsata: support i.MX6DQPlusPeng Fan2016-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX6DQPlus support sata interface, so not return failure when CPU is i.MX6DQPlus. In this patch, also use simpler runtime cpu dections macros to replace is_cpu_type. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tang Yuantian <Yuantian.Tang@freescale.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Bin Meng <bmeng.cn@gmail.com>
| * | | net: fec_mxc: use simpler runtime cpu dection macrosPeng Fan2016-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * | | ocotp: mxc: use simpler runtime cpu dection macrosPeng Fan2016-05-241-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | mtd: nand: mxs: use simpler runtime cpu dection macrosPeng Fan2016-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Scott Wood <oss@buserror.net>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-06-122-12/+0
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| * | | | x86: broadwell: gpio: Remove the codes to set up pin controlBin Meng2016-06-121-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have set up pin control in cpu_init_r(), remove the duplicated codes in the broadwell gpio driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | x86: Probe pinctrl driver in cpu_init_r()Bin Meng2016-06-121-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present pinctrl driver gets probed in ich6_gpio driver's probe routine, which has two issues: - Pin's PADs only gets configured when GPIO driver is probed, which is not done by default. This leaves the board in a partially functional state as we must initialize PADs correctly to get perepherals fully working. - The probe routine of pinctrl driver is called multiple times, as normally there are multiple GPIO controllers. It should really be called just once. Move the call to syscon_get_by_driver_data() from ich6_gpio driver to cpu_init_r(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com>
| * | | | x86: ich6_gpio: Output return value of syscon_get_by_driver_data()Bin Meng2016-06-121-1/+3
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to syscon_get_by_driver_data() does not save its return value. Print it out to aid debugging. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | | drivers: i2c: mxc: Add early initYuan Yao2016-06-102-0/+32
|/ / / | | | | | | | | | | | | | | | | | | | | | Add early i2c init function with conservative divider when the exact clock rate is not available. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | dfu, nand, ubi: fix erasing after write finishHeiko Schocher2016-06-091-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | writting to ubi nand partitions need after write ends an erase of the remaining sectors. This fail, if dfu write size was not a multiple of erasesize, example log: Failure erase: -1 Fix this error. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | mtd: nand: omap: allow to switch to BCH16Heiko Schocher2016-06-091-0/+4
| | | | | | | | | | | | | | | | | | | | | support in omap_nand_switch_ecc() also an eccstrength from 16. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | nand: add nand mtd concat supportHeiko Schocher2016-06-091-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | add for nand devices mtd concat support. Generic MTD concat support is already ported to mainline, and used in the cfi_mtd driver. This patch adds it similiar for nand devices. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | mmc: omap_hsmmc: enable 8bit interface for eMMC for AM33xxHeiko Schocher2016-06-091-0/+1
| | | | | | | | | | | | | | | | | | | | | Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | mmc: revert mmc: Handle switch error status bit in MMC card statusHeiko Schocher2016-06-091-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | revert patch: commit: 6b2221b008e0: mmc: Handle switch error status bit in MMC card status to get eMMC working on shc board Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge http://git.denx.de/u-boot-samsungTom Rini2016-06-0637-1275/+2166
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
| * | | exynos: video: Drop old unused codeSimon Glass2016-05-252-74/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we are using driver model, we can drop the weak functions and LCD init in the board file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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