summaryrefslogtreecommitdiffstats
path: root/drivers/spi
Commit message (Collapse)AuthorAgeFilesLines
* spi: altera_spi: minor clean upThomas Chou2015-11-061-2/+2
| | | | | | | - Remove the penultimate comma in of_match ids Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: cadence_qspi: Ensure check for max frequency in placeChin Liang See2015-11-051-0/+3
| | | | | | | | | | | | | | | Ensure the intended SCLK frequency not exceeding the maximum frequency. If that happen, SCLK will set to maximum frequency. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* spi: cadence_qspi: Fix fdt read of spi-max-frequencyChin Liang See2015-11-051-4/+4
| | | | | | | | | | | | | | | | | Fix the fdt read for spi-max-frequency as it's contained in the child node. Current state of code is always returning default value. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
* spi: cadence_qspi: Ensure spi_calibration is run when sclk changeChin Liang See2015-11-052-9/+14
| | | | | | | | | | | | | | | | | Ensuring spi_calibration is run when there is a change of sclk frequency. This will ensure the qspi flash access works for high sclk frequency Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vikas Manocha <vikas.manocha@st.com> Cc: Jagannadh Teki <jteki@openedev.com> Cc: Pavel Machek <pavel@denx.de> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-10-2821-261/+894
|\
| * spi: altera_spi: Minor cleanupJagan Teki2015-10-281-5/+5
| | | | | | | | | | | | | | | | | | - Moved macro definitions to top - Give tab space to CONFIG_ALTERA_SPI_IDLE_VAL value - Re-arrange header includes ascending order Acked-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: altera_spi: Use BIT macroJagan Teki2015-10-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in altera_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Marek Vasut <marex@denx.de> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: xilinx_spi: Use GENMASKJagan Teki2015-10-271-7/+7
| | | | | | | | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in xilinx_spi Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: tegra: Use GENMASKJagan Teki2015-10-273-9/+9
| | | | | | | | | | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in tegra*.c Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: omap3_spi: Use GENMASKJagan Teki2015-10-271-5/+5
| | | | | | | | | | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in omap3_spi Cc: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: fsl_qspi: Use GENMASKJagan Teki2015-10-271-1/+1
| | | | | | | | | | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in fsl_qspi Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: designware_spi: Use GENMASKJagan Teki2015-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in designware_spi Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: atmel_spi: Use GENMASKJagan Teki2015-10-271-1/+1
| | | | | | | | | | | | | | | | | | Replace numeric mask hexcodes with GENMASK macro in atmel_spi Cc: Bo Shen <voice.shen@atmel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: xilinx_spi: Use BIT macroJagan Teki2015-10-271-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in xilinx_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: ti_qspi: Use BIT macroJagan Teki2015-10-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in ti_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: tegra: Use BIT macroJagan Teki2015-10-273-86/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in tegra*.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Warren <twarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: sh_qspi: Use BIT macroJagan Teki2015-10-271-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in sh_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: omap3_spi: Use BIT macroJagan Teki2015-10-271-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in omap3_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: mpc8xxx_spi: Use BIT macroJagan Teki2015-10-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in mpc8xxx_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: ich: Use BIT macroJagan Teki2015-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in ich :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: fsl: Use BIT macroJagan Teki2015-10-273-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in fsl_*spi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: York Sun <yorksun@freescale.com> Cc: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: designware_spi: Use BIT macroJagan Teki2015-10-271-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in designware_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: cadence_qspi_apb: Use BIT macroJagan Teki2015-10-271-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in cadence_qspi_apb :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: bfin_spi6xx: Use BIT macroJagan Teki2015-10-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in bfin_spi6xx :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: atmel_spi: Use BIT macroJagan Teki2015-10-271-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in atmel_spi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Bo Shen <voice.shen@atmel.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_[q]spi: Use GENMASK macroJagan Teki2015-10-272-7/+7
| | | | | | | | | | | | | | | | | | | | | | GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_[q]spi: Use BIT macroJagan Teki2015-10-272-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | Used BIT macro on zynq_spi.c and zynq_qspi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_qspi: Minor cleanupsJagan Teki2015-10-251-5/+3
| | | | | | | | | | | | | | | | - Use __func__ on debug - Removed unnecessary comment - Fix function name in debug as zynq_qspi_xfer instead of spi_xfer Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_spi: Remove unneeded headersJagan Teki2015-10-251-5/+1
| | | | | | | | | | | | | | | | | | - Removed unneeded inclusion of header files - Add "Xilinx" on license text Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_qspi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-251-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_spi: Store cs value into private dataJagan Teki2015-10-251-3/+5
| | | | | | | | | | | | | | Store cs value into private data and use it while activating chipselect instead of passing through function. Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_spi: Rename baudrate divisor mask nameJagan Teki2015-10-251-2/+2
| | | | | | | | | | | | | | Rename ZYNQ_SPI_CR_BRD_MASK to ZYNQ_SPI_CR_BAUD_MASK for more readable. Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: zynq_spi: Add config reg shift named macrosJagan Teki2015-10-251-3/+7
| | | | | | | | | | | | | | Update the numerical values for baudrate and chipselect with config reg shift named macro's Signed-off-by: Jagan Teki <jteki@openedev.com>
| * spi: Kconfig: Add Zynq QSPI controller entryJagan Teki2015-10-251-0/+9
| | | | | | | | | | | | | | | | | | Add Zynq QSPI controller Kconfig entry. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
| * spi: Add zynq qspi controller driverJagan Teki2015-10-252-0/+623
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support. => sf probe SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000 => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000 device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK => cmp.b 0x3000000 0x100 0x1000000 Total of 16777216 byte(s) were the same Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-10-274-7/+7
|\ \ | |/ |/|
| * dm: Rename dev_get_parentdata() to dev_get_parent_priv()Simon Glass2015-10-234-7/+7
| | | | | | | | | | | | | | | | The current name is inconsistent with other driver model data access functions. Rename it and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | spi : convert altera_spi to driver modelThomas Chou2015-10-232-86/+119
|/ | | | | | | Convert altera_spi to driver model Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
* x86: spi: Add support for Wildcat PointGeorge McCollister2015-10-211-1/+2
| | | | | | | Add the Wildcat Point ID so Broadwell U based boards can use SPI. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* spi: tegra20: Add support for mode selectionMirza Krak2015-10-111-0/+21
| | | | | | | Respect the mode passed in set_mode ops. Signed-off-by: Mirza Krak <mirza.krak@hostmobility.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_spi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-111-3/+4
| | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: xilinx_spi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-111-5/+5
| | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* bitops: introduce BIT() definitionHeiko Schocher2015-09-112-4/+0
| | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-111-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add SPI driverSimon Glass2015-09-024-0/+507
| | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Use dev_get_addr() where possibleSimon Glass2015-08-317-7/+7
| | | | | | | | | | This is a convenient way for a driver to get the hardware address of a device, when regmap or syscon are not being used. Change existing callers to use it as an example to others. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-08-181-1/+26
|\
| * spi: ti_qspi: Use DMA to read from qspi flashVignesh R2015-08-171-0/+25
| | | | | | | | | | | | | | | | ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ti: qspi: set flash quad bit based on quad support flagvishalm@ti.com2015-08-171-1/+1
| | | | | | | | | | | | | | | | Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | ARM: exynos: move SoC sources to mach-exynosThomas Abraham2015-08-171-1/+1
|/ | | | | | | | | | | | | | Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
OpenPOWER on IntegriCloud