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* driver: qspi: correct QSPI disable CS reset valuePraneeth Bajjuri2016-07-011-1/+1
| | | | | | | | | | | Correcting QSPI disable/unselect CS reset value. CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8] This is not causing any issue, but its better to untouch the reserved bits. Praneeth Bajjuri <praneeth@ti.com> Signed-off-by: Ravi Babu <ravibabu@ti.com>
* dm: ti_qspi: Fix conversion of address to a pointerLokesh Vutla2016-03-121-3/+7
| | | | | | | | | | | | | | TI QSPI driver directly typecasts fdt_addr_t to a pointer. This is not strictly correct, as it gives a build warning when fdt_addr_t is u64. So, use map_physmem for a proper typecasts. This is inspired by commit 167efe01bc5a9 ("dm: ns16550: Use an address instead of a pointer for the uart base") Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
* spi: ti_qspi: compile out spi_flash_copy_mmap when CONFIG_DMA is definedMugunthan V N2016-02-231-1/+1
| | | | | | | | | | When CONFIG_DMA is defined the default spi_flash_copy_mmap() can handle dma memory copy, so compile out spi_flash_copy_mmap() from ti_qspi driver when CONFIG_DMA config is defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Use 4-byte opcode for mmap readVignesh R2016-01-201-3/+3
| | | | | | | | | | | | ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB. Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB. Signed-off-by: Ravi Babu <ravibabu@ti.com> [vigneshr@ti.com: Re-word commit description] Signed-off-by: Vignesh R <vigneshr@ti.com>
* drivers: spi: ti_qspi: convert driver to adopt device driver modelMugunthan V N2016-01-131-0/+187
| | | | | | | | | adopt ti_qspi driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi: ti_qspi: prepare driver for DM conversionMugunthan V N2016-01-131-126/+153
| | | | | | | Prepare driver for DM conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi:ti_qspi: change ti_qspi_slave to ti_qspi_priv for driver model ↵Mugunthan V N2016-01-131-60/+60
| | | | | | | | | | | | conversion Changing the ti_qspi_priv structure and its instance names from to priv for driver mode conversion. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* drivers: spi: ti_qspi: do not hard code chip select for memory map configurationMugunthan V N2016-01-131-2/+2
| | | | | | | | | | | | To enable memory map in dra7xx, specific chip select must be written to control module register. But this hard coded to chip select 1, fixing it by writing the specific chip select value to control module register. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: Rename op_mode_rx to mode_rxJagan Teki2016-01-131-1/+1
| | | | | | | | | | | | | | Since spi rx mode macro's are renamed to simple and meaninfull, this patch will rename the respective structure members. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Rename SPI_OPM_RX_* to SPI_RX_*Jagan Teki2016-01-131-1/+1
| | | | | | | | | | | | | | | | SPI_OPM_RX_AS - SPI_RX_SLOW SPI_OPM_RX_AF - SPI_RX_FAST SPI_OPM_RX_DOUT - SPI_RX_DUAL SPI_OPM_RX_QOF - SPI_RX_QUAD Cc: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Fix SPI_3WIRE checking using modeJagan Teki2015-12-111-1/+1
| | | | | | | | | SPI_3WIRE is spi mode not spi flags, so this patch fixed the spi-3wire checking throgh mode instead of flags. Cc: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Add dummy readl for bus syncVignesh R2015-11-171-0/+2
| | | | | | | | | | | Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Use BIT macroJagan Teki2015-10-271-5/+5
| | | | | | | | | | | | Replace numerical bit shift with BIT macro in ti_qspi :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Reviewed-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: ti_qspi: Use DMA to read from qspi flashVignesh R2015-08-171-0/+25
| | | | | | | | ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* ti: qspi: set flash quad bit based on quad support flagvishalm@ti.com2015-08-171-1/+1
| | | | | | | | Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* qspi: dra7x: enable quad mode read for ti-qspi driverRavi Babu2015-03-301-0/+7
| | | | | | | | This patch enables QUAD read mode for qspi to improve the read performace while loading the binaries from qspi. Signed-off-by: Ravi Babu <ravibabu@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* arm: omap: add support for am57xx devicesFelipe Balbi2014-12-041-4/+4
| | | | | | | | just add a few ifdefs around because this device is very similar to dra7xxx. Signed-off-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* ti: qspi: populate slave device to set flash quad bit.Sourav Poddar2014-06-061-0/+1
| | | | | | | The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
* spi: ti_qspi: Add delay for successful bulk erase.Poddar, Sourav2014-04-171-0/+3
| | | | | | | | Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com>
* spi: ti_qspi: Add delay before xfer for am43xxSourav Poddar2014-02-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this delay, write/read is failing. Looks like, the WIP always remain set and hence a timeout occurs leading to the error. Without this patch, device does not get probed also. Here is the log. U-Boot# U-Boot# U-Boot# U-Boot# sf probe 0 SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff Failed to initialize SPI flash at 0:0 U-Boot# sf probe 0 While with this patch, log is U-Boot# sf probe 0 SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 U-Boot# sf erase 0 0x80000 SF: 524288 bytes @ 0x0 Erased: OK U-Boot# mw 81000000 0xdededede 0x40000 U-Boot# sf write 81000000 0 0x40000 SF: 262144 bytes @ 0x0 Written: OK U-Boot# sf read 82000000 0 0x40000 SF: 262144 bytes @ 0x0 Read: OK U-Boot# md 0x82000000 Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: ti_qspi: Add AM43xx specifics changesSourav Poddar2014-02-181-3/+23
| | | | | | | Add AM43xx specific changes. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* spi: add TI QSPI driverMatt Porter2013-10-071-0/+311
Adds a SPI master driver for the TI QSPI peripheral. - Added quad read support. - Added memory mapped support. Signed-off-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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