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* sf: sst: Add support for SST25WF080Jagannadha Sutradharudu Teki2013-08-071-0/+6
| | | | | | | Add support for SST25WF080 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: Fix code cleanupsJagannadha Sutradharudu Teki2013-08-078-15/+16
| | | | | | | - CHECK: Alignment should match open parenthesis - trailing whitespace Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Fix code cleanupJagannadha Sutradharudu Teki2013-08-061-5/+6
| | | | | | | - line over 80 characters. - CHECK: Alignment should match open parenthesis Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: stmicro: Fix code cleanupJagannadha Sutradharudu Teki2013-08-061-4/+3
| | | | | | | | - line over 80 characters - foo * bar -> foo *bar - removed unnecessary for single statement blocks. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: sst: Fix code cleanupJagannadha Sutradharudu Teki2013-08-061-12/+20
| | | | | | | | - line over 80 characters - add spaces - add tabs Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: eon|spansion|ramtron: Fix code cleanupJagannadha Sutradharudu Teki2013-08-063-5/+7
| | | | | | | - line over 80 characters - insert the expression in same line Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-248-133/+8
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-06-245-135/+341
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| * sf: Warn to use BAR for > 16MiB flashesJagannadha Sutradharudu Teki2013-06-231-0/+6
| | | | | | | | | | | | Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add debug messages on spi_flash_read_commonJagannadha Sutradharudu Teki2013-06-231-1/+11
| | | | | | | | | | | | | | - Added debug's on spi_flash_read_common() - Added space Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Place the sf calls in proper orderJagannadha Sutradharudu Teki2013-06-231-92/+92
| | | | | | | | | | | | Placed the sf calls in proper order - erase/write/read Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Unify spi_flash write codeJagannadha Sutradharudu Teki2013-06-232-67/+63
| | | | | | | | | | | | | | Move common flash write code into spi_flash_write_common(). Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
| * sf: Add flag status register polling supportJagannadha Sutradharudu Teki2013-06-233-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | Flag status register polling is required for micron 512Mb flash devices onwards, for performing erase/program operations. Like polling for WIP(Write-In-Progress) bit in read status register, spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control) bit in flag status register. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: Remove spi_flash_cmd_poll_bit()Jagannadha Sutradharudu Teki2013-06-232-12/+3
| | | | | | | | | | | | | | | | | | There is no other call other than spi_flash_cmd_wait_ready(), hence removed spi_flash_cmd_poll_bit and use the poll status code spi_flash_cmd_wait_ready() itself. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: spansion: Add support for S25FL512S_64KJagannadha Sutradharudu Teki2013-06-231-0/+7
| | | | | | | | | | | | Add support for Spansion S25FL512S_64K SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: stmicro: Add support for N25Q1024AJagannadha Sutradharudu Teki2013-06-231-0/+6
| | | | | | | | | | | | Add support for Numonyx N25Q1024A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: stmicro: Add support for N25Q1024Jagannadha Sutradharudu Teki2013-06-231-0/+6
| | | | | | | | | | | | Add support for Numonyx N25Q1024 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: stmicro: Add support for N25Q512AJagannadha Sutradharudu Teki2013-06-231-0/+6
| | | | | | | | | | | | Add support for Numonyx N25Q512A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: stmicro: Add support for N25Q512Jagannadha Sutradharudu Teki2013-06-231-0/+6
| | | | | | | | | | | | Add support for Numonyx N25Q512 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Use spi_flash_addr() in write callJagannadha Sutradharudu Teki2013-06-231-5/+2
| | | | | | | | | | | | | | | | Use the existing spi_flash_addr() for 3-byte addressing cmd filling in write call. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: Add bank addr code in CONFIG_SPI_FLASH_BARJagannadha Sutradharudu Teki2013-06-232-10/+25
| | | | | | | | | | | | | | | | | | | | | | Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: Update sf read to support all sizes of flashesJagannadha Sutradharudu Teki2013-06-231-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updated the spi_flash read func to support all sizes of flashes using bank reg addr facility. The same support has been added in below patch for erase/write spi_flash functions: "sf: Support all sizes of flashes using bank addr reg facility" (sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415) With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~460 bytes. sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: Update sf to support all sizes of flashesJagannadha Sutradharudu Teki2013-06-231-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated the spi_flash framework to handle all sizes of flashes using bank/extd addr reg facility The current implementation in spi_flash supports 3-byte address mode due to this up to 16Mbytes amount of flash is able to access for those flashes which has an actual size of > 16MB. As most of the flashes introduces a bank/extd address registers for accessing the flashes in 16Mbytes of banks if the flash size is > 16Mbytes, this new scheme will add the bank selection feature for performing write/erase operations on all flashes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: Read flash bank addr register at probe timeJagannadha Sutradharudu Teki2013-06-232-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the flash bank addr register to get the state of bank in a perticular flash. and also bank write happens only when there is a change in bank selection from user. bank read only valid for flashes which has > 16Mbytes those are opearted in 3-byte addr mode, each bank occupies 16Mytes. Suppose if the flash has 64Mbytes size consists of 4 banks like bank0, bank1, bank2 and bank3. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: Discover the bank addr commandsJagannadha Sutradharudu Teki2013-06-232-0/+35
| | | | | | | | | | | | | | | | | | | | Bank/Extended addr commands are specific to particular flash vendor so discover them based on the idocode0. Assign the discovered bank commands to spi_flash members so-that the bank read/write will use their specific operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: Add bank address register writing supportJagannadha Sutradharudu Teki2013-06-232-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support to program a flash bank address register. extended/bank address register contains an information to access the 4th byte addressing in 3-byte address mode. reff' the spec for more details about bank addr register in Page-63, Table 8.16 http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * sf: winbond: Add support for W25QXXXFVJagannadha Sutradharudu Teki2013-06-221-6/+6
| | | | | | | | | | | | Add support for Winbond W25QXXXFV SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: winbond: Add support for W25Q16DWJagannadha Sutradharudu Teki2013-06-221-0/+5
| | | | | | | | | | | | Add support for Winbond W25Q16DW SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: winbond: Add support for W25Q128FWJagannadha Sutradharudu Teki2013-06-221-0/+5
| | | | | | | | | | | | Add support for Winbond W25Q128FW SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: winbond: Update the names for W25Q 0x40XX ID's flash partsJagannadha Sutradharudu Teki2013-06-221-5/+5
| | | | | | | | | | | | | | | | Use the exact names for W25Q 0x40XX ID's flash parts, as the same sizes of flashes comes with different ID's. so-that the distinguishes becomes easy with this change. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: spansion: Correct name of S25FL128S 64K Sector partJagannadha Sutradharudu Teki2013-06-221-1/+1
| | | | | | | | | | | | | | | | | | Corrected the name of S25FL128S 64K sector part SPI flash, S25FL128S supported has been added in below commit "sf: spansion: Add support for S25FL128S" (sha1: 1bfb9f156aa66cca6bb9c773867a1f02a84b14be) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-224-0/+86
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| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-194-0/+86
| |\ | | | | | | | | | | | | Conflicts: spl/Makefile
| | * SF: Add driver for Gigabyte device GD25LQ and GD25Q64BRajeshwari Shinde2013-05-204-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver for the gigabyte devices GD25LQ and GD25Q64B required for Snow Board. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-06-133-14/+37
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| * | sf: winbond: Correct the nr_blocks used for W25Q32DWJagannadha Sutradharudu Teki2013-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch corrected the nr_blocks used for W25Q32DW SPI flash. nr_blcoks are incorrectly assigned on below patch "sf: winbond: add W25Q32DW" (sha1: 772ba15474f73adc942e817cc072b6e9750836cc) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: winbond: Add support for W25Q80BWJagannadha Sutradharudu Teki2013-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Winbond W25Q80BW SPI flash. This patch corrected the flash name, nr_blocks and also commit message header from below patch. "sf: winbond: add W25Q32" (sha1: c969abc47033d6f810d3c9dbdb994ea9d691d038) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: spansion: Update the name for S25FL256S flashJagannadha Sutradharudu Teki2013-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | As the per the ID tabl the flash is under Uniform 64-kB sector architecture, hence updated with proper name. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | cmd_sf: Add print mesgs on sf read/write commandsJagannadha Sutradharudu Teki2013-06-031-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a print messages while using 'sf read' and 'sf write' commands to make sure that how many bytes read/written from/into flash device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Tom Rini <trini@ti.com>
| * | cmd_sf: Add print mesg for 'sf erase' commandJagannadha Sutradharudu Teki2013-06-031-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds a print messages while using 'sf erase' command to make sure that how many bytes erased in flash device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Tom Rini <trini@ti.com>
| * | sf: Fix sf read for memory-mapped SPI flashesJagannadha Sutradharudu Teki2013-06-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Missing return after memcpy is done for memory-mapped SPI flashes, hence added retun 0 after memcpy done. The return is missing in below patch "sf: Enable FDT-based configuration and memory mapping" (sha1: bb8215f437a7c948eec82a6abe754c226978bd6d) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | sf: winbond: Add support for W25PXX SPI flashKuo-Jung Su2013-05-281-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Winbond's W25PXX SPI flash. These devices is used on Faraday A369 evaluation board. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> CC: Tom Rini <trini@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | sf: winbond: Add support for W25Q256Jagannadha Sutradharudu Teki2013-05-281-0/+5
| | | | | | | | | | | | | | | | | | | | | Add support for Winbond W25Q256 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | sf: spansion: Add Spansion S25FL064P IDsMarek Vasut2013-05-281-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | This is a S25FL064A successor. It supports up to 104MHz bus speed. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Scott Wood <scottwood@freescale.com> Cc: Wolfgang Denk <wd@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | sf: spansion: Add support for S25FL128SXie Xiaobo2013-05-241-1/+1
|/ | | | | | | | | SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash memory have the same device ID and Memory architecture. So they can use the same config parameters. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-281-0/+5
|\ | | | | | | | | | | | | Conflicts: drivers/spi/tegra20_sflash.c include/fdtdec.h lib/fdtdec.c
| * sf: winbond: add W25Q32DWAllen Martin2013-03-251-0/+5
| | | | | | | | | | | | | | | | Add support for Winbond W25Q32DW 32Mbit part Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | sf: Enable FDT-based configuration and memory mappingSimon Glass2013-03-191-1/+45
| | | | | | | | | | | | | | Enable device tree control of SPI flash, and use this to implement memory-mapped SPI flash, which is supported on Intel chips. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sf: Respect maximum SPI write sizeSimon Glass2013-03-191-2/+8
| | | | | | | | | | | | | | | | Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of bytes that can be in a write transaction. Support this by breaking the writes into multiple transactions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sf: Use spi_flash_alloc() in each SPI flash driverSimon Glass2013-03-198-52/+8
| | | | | | | | | | | | | | | | Rather than each device having its own way to allocate a SPI flash structure, use the new allocation function everywhere. This will make it easier to extend the interface without breaking devices. Signed-off-by: Simon Glass <sjg@chromium.org>
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