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* mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_dataScott Wood2016-06-0330-307/+298
| | | | | | | | | These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
* nand: Embed mtd_info in struct nand_chipScott Wood2016-06-0317-165/+177
| | | | | | | | | | | | nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
* mtd: nand: Remove nand_info_t typedefScott Wood2016-06-036-90/+90
| | | | | | | This typedef serves no purpose other than causing confusion with struct nand_chip. Signed-off-by: Scott Wood <oss@buserror.net>
* mtd: nand: Remove docg4 driver and palmtreo680 flashing toolScott Wood2016-06-033-1251/+0
| | | | | | | | | | Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only user of the docg4 driver and the palmtreo680 image flashing tool. This patch removes them. Signed-off-by: Scott Wood <oss@buserror.net> Cc: Mike Dunn <mikedunn@newsguy.com> Cc: Simon Glass <sjg@chromium.org>
* mtd: nand: Remove jz4740 driverMarek Vasut2016-06-032-259/+0
| | | | | | | | | | | This driver is not used by anyone, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Scott Wood <oss@buserror.net> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Scott Wood <oss@buserror.net>
* mtd: nand: arasan_nfc: Correct nand ecc initializationSiva Durga Prasad Paladugu2016-06-031-9/+9
| | | | | | | | | | | Correct the nand ecc initialization code This fixes the issue of incorrect nand ecc init if no device is found in ecc_matrix then it endsup ecc init with junk initialization instead of the most suited one. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
* mtd: nand: am335x: spl: Fix copying of imageLokesh Vutla2016-05-271-1/+14
| | | | | | | | | When offset is not aligned to page address, it is possible that extra offset will be read from nand. Adjust the image such that first byte of the image is at load address after the first page is read. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Fix spelling of "occurred".Vagrant Cascadian2016-05-021-2/+2
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.Purna Chandra Mandal2016-04-101-8/+0
| | | | | | | Definition of writes{bwlq}, reads{bwlq} are now added into arch specific asm/io.h. So removing them from driver to fix re-definition error Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* kirkwood_nand: claim MPP pins on the flyChris Packham2016-04-061-0/+19
| | | | | | | | | | | Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stefan Roese <sr@denx.de>
* mtd: nand: denali: max_banks calculation changed in revision 5.1Graham Moore2016-04-012-1/+12
| | | | | | | | | | | | | | Read Denali hardware revision number and use it to calculate max_banks, The encoding of max_banks changed in Denali revision 5.1. [ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ] Signed-off-by: Graham Moore <grmoore@opensource.altera.com> [Brian: parentheses around macro arg] Signed-off-by: Brian Norris <computersforpeace@gmail.com> [Masahiro: import from Linux and adjust ioread32() to readl() ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mtd: denali: fix warning when compiled for 64bit systemMasahiro Yamada2016-03-241-3/+3
| | | | | | | | | | The 64-bit compiler (ex. aarch64) emits "warning: cast from pointer to integer of different size". Make it work with 64bit DMA address while I am here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arasan: nfc: Add initial nand driver support for arasanSiva Durga Prasad Paladugu2016-02-122-0/+1155
| | | | | | | | | | | Added initial nand driver support for arasan nand flash controller.This supports nand erase,nand read, nand write This uses the hardware ECC for read and write operations ZynqMP uses this driver. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [scottwood: Fix checkpatch warnings] Signed-off-by: Scott Wood <oss@buserror.net>
* zynqmp: nand: Add Nand driver support for zynqmpSiva Durga Prasad Paladugu2016-02-121-0/+7
| | | | | | | | | | Add nand driver support for zynqmp. The Nand controller used in ZynqMP is Arasan Nand Flash controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> [scottwood: Fix checkpatch warning] Signed-off-by: Scott Wood <oss@buserror.net>
* mtd: pxa3xx_nand: Don't alloc unneeded memoryKevin Smith2016-02-121-3/+3
| | | | | | | | | | | The allocation size is reduced from what was introduced from the Linux kernel, as U-boot uses the statically allocated nand_info instead of needing to dynamically allocate an mtd_info instance. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Scott Wood <scottwood@freescale.com>
* mtd: pxa3xx_nand: Correct offset calculationKevin Smith2016-02-121-2/+2
| | | | | | | | | | | Correct some pointer math in initialization. An offset was added to a struct-typed pointer instead of one casted to a byte-size, resulting in a much larger offset than intended. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Scott Wood <scottwood@freescale.com>
* mtd: pxa3xx_nand: Correct null dereferenceKevin Smith2016-02-121-7/+0
| | | | | | | | | | | | Correct a null pointer dereference in board_nand_init(). Zeroed memory was allocated, then immediately dereferenced. The dereference is completely removed, since this pointer is later initialized in alloc_nand_resources. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Scott Wood <scottwood@freescale.com>
* nand: mxs: fix error handling for mxs_nand_initPeng Fan2016-02-121-9/+15
| | | | | | | | | | | | | | | | | Fix error handling for mxs_nand_init. The original error handling is wrong for err2 and err1. Should first free desc[x], then free desc. This patch also correctly handle err3, should use MXS_DMA_CHANNEL_AHB_APBH_GPMI0 as the check point. Cc: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <Fabio.Estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Marek Vasut <marex@denx.de> Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de>
* Use correct spelling of "U-Boot"Bin Meng2016-02-063-3/+3
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* atmel_nand: Add 32 bit ecc support for sama5d2 chipJosh Wu2016-02-021-1/+9
| | | | | | | | | | Also if minimum ecc requirment is bigger then what we support, then just use our maxium pmecc support. But it is not safe, so we'll output a warning about this. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* atmel_nand_ecc: update pmecc registers according to sama5d2 chipJosh Wu2016-02-021-4/+32
| | | | | | | | | | 1. add the pmecc register mapping for sama5d2. 2. add the pmecc error location register mapping for sama5d2. 3. add some new field that is different from old ip. 4. add sama5d2 pmecc ip version number. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* atmel_nand: use the definition: PMECC_OOB_RESERVED_BYTES instead magic numberJosh Wu2016-01-271-1/+1
| | | | | | | | | As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the PMECC_OOB_RESERVED_BYTES. So use it in the driver. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* atmel_nand: add '\n' in the end of error message for better displayJosh Wu2016-01-271-2/+2
| | | | | | | | Also align the open parenthesis. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* atmel_nand: use nand ecc_{strength, step}_ds instead of our own functionJosh Wu2016-01-271-37/+7
| | | | | | | | | | Since ecc_{strength,step}_ds is introduced in nand_chip structure for minimum ecc requirements. So we can use them directly and remove our own get_onfi_ecc_param function. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
* imx: nand: update GPMI NAND driver to support MX7Peng Fan2016-01-241-2/+2
| | | | | | | Update GPMI NAND driver and BCH head file to support i.MX7 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-192-20/+2
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* Fix typo: firstly -> first.Vagrant Cascadian2015-12-051-1/+1
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Acked-by: Marek Vasut <marex@denx.de>
* Move console definitions into a new console.h fileSimon Glass2015-11-191-0/+1
| | | | | | | | The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-10-151-109/+138
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| * mtd: nand: vf610_nfc: resync with upstream Linux versionStefan Agner2015-10-151-109/+138
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This resyncs the driver changes with the Linux version of the driver. The driver received some feedback in the LKML and got recently acceppted, the latest version can be found here: https://lkml.org/lkml/2015/9/2/678 Notable changes are: - On ECC error, reread OOB and count bit flips in OOB too. If flipped bits are below threshold, also return an empty OOB buffer. - Return the amount of bit flips in vf610_nfc_read_page. - Use endianness aware vf610_nfc_read to read ECC status. - Do not enable IDLE IRQ (since we do not operate with an interrupt service routine). - Use type safe struct for buffer variants (vf610_nfc_alt_buf). - Renamed variables in struct vf610_nfc (column and page_sz) to reflect better what they really representing. The U-Boot version currently does not support RAW NAND write when using the HW ECC engine. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Scott Wood <scottwood@freescale.com>
* | nand: omap_gpmc: Change correctable bit-flips messages to debug()Ezequiel García2015-10-111-3/+3
| | | | | | | | | | | | | | | | Messages on corrected bit-flips are not really useful, as bit-flips are perfectly normal. Let's avoid cluttering the console and make them debug. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
* | sunxi_nand_spl: Be smarter about where to look for backup u-boot.binHans de Goede2015-09-291-6/+20
|/ | | | | | | | | | | | | | | | | | We know when u-boot is written to its own partition, in this case the layout always is: eb 0 spl eb 1 spl-backup eb 2 u-boot eb 3 u-boot-backup eb: erase-block So if we cannot load u-boot from its primary offset we know exactly where to look for it. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* mtd: nand: mxs check maximum ecc that platfrom supportsPeng Fan2015-09-201-1/+8
| | | | | | | | | | | | Check maximum ecc strength for each platfrom to avoid the calculated ecc exceed the limitation. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Han Xu <b45815@freescale.com> Tested-By: Tim Harvey <tharvey at gateworks.com> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()Stefan Roese2015-09-151-6/+15
| | | | | | | | | | | | | | | | | | | This patch addresses some comments raised by Scott in the last versions. Here the changes in detail: - Removed __maybe_unused as its not needed - Added check for strength == 4 and error out for the unsupported ECC strength values - Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this will be done in nand_scan_tail() - Set .caclulate back to fsmc_read_hwecc() in the HW case - Added comment that this function will only be called on SPEAr platforms, not supporting the BCH8 HW ECC (FSMC_VER8) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Scott Wood <scottwood@freescale.com>
* bitops: introduce BIT() definitionHeiko Schocher2015-09-111-1/+0
| | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-111-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* Move malloc_cache_aligned() to its own headerSimon Glass2015-09-111-0/+1
| | | | | | | | | | | | | | | | | | | At present malloc.h is included everywhere since it recently was added to common.h in this commit: 4519668 mtd/nand/ubi: assortment of alignment fixes This seems wasteful and unnecessary. We have been trying to trim down common.h and put separate functions into separate header files and that change goes in the opposite direction. Move malloc_cache_aligned() to a new header so that this can be avoided. The header would perhaps be better named as alignmem.h but it needs to be included after common.h and people might be confused by this. With the name memalign.h it fits nicely after malloc() in most cases. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600Stefan Roese2015-09-111-0/+40
| | | | | | | | | | | | | | | | | | | This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your config header: #define CONFIG_NAND_ECC_BCH #define CONFIG_BCH And use the command "nandecc bch4" to select this ECC scheme upon runtime. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
* arm: Remove nhk8815 boards and nomadik archSimon Glass2015-09-112-207/+0
| | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devicesStefan Roese2015-09-101-0/+1
| | | | | | | | | | This patch adds support for NAND chips with 4KiB page size and 24/1024 ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the ICnova-A20 SoM. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through KconfigHans de Goede2015-08-311-0/+9
| | | | | | | | | | | | | | Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends, to avoid double defining it for SoCs which have not yet moved to Kconfig for this. Having this in Kconfig is useful because this is something which may differ from one board to the other even when using the same SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Scott Wood <scottwood@freescale.com>
* sunxi_nand_spl: clear status flags in SPL implementationBoris Brezillon2015-08-311-3/+8
| | | | | | | | | | | Some status flags remain set until you explicetly clear the bit in the status register. Fix the SPL implementation to avoid false positive. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [hdegoede@redhat.com: Port from v2015.07 to v2015.10] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_ENDHans de Goede2015-08-312-10/+6
| | | | | | | | | | | | | | | | | We only ever use syndrome mode for the partitions which contain the SPL, as that is required for the BROM to be able to read the SPL. Instead of using some arbritray limit for deciding whether or not to use syndrome, be smart and check if u-boot-dtb.bin is directly behind the SPL, if it is not then it is on its own partition and we should not use syndrome. Note the reason why we only use syndrome mode for the SPL is because it comeswith weaker randomization, introducing a risk for more bit errors, so we want to avoid it when possible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXIHans de Goede2015-08-312-10/+10
| | | | | | | | | | | | | | | We eventually want to add full nand support, since it makes no sense to build SPL with nand support and u-boot without, or the other way around, a single option will suffice. Renaming the Kconfig option now makes things easier when we add full nand support in the future. The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an "ifdef CONFIG_SPL_BUILD" block in the Makefile. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Add support for backup boot partitionsHans de Goede2015-08-311-0/+16
| | | | | | | | | | | | | The BROM does not care / use bad page markings, instead it deals with any bad pages in the first erase-block by simply trying to load "boot0" from the next erase-block. This commit implements the same strategy for the sunxi spl nand code, allowing it to boot from the backup boot partition when the main boot partition is bad (tested by erasing the main boot partition). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Auto detect nand configuration parametersHans de Goede2015-08-312-29/+39
| | | | | | | | | | | | | | | | | | | Auto detect the nand configuration parameters, like the BROM does. This allows us to get rid of various Kconfig settings, and is necessary to support generic boards like the mk802 which have seen many production runs with different nands. The full blown u-boot/kernel nand driver uses the nand id to determine this info, for the SPL we do as the BROM does and simply try a few standard configs. Note the table only contains configs which are known to actually be used, rather then all the configs the BROM tries. This means that it may need to be updated in the future as we add support for nand on more boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Parametrize lowlevel read functionsHans de Goede2015-08-311-38/+48
| | | | | | | | | | | | Parametrize the lowlevel nand_read_page function, instead of directly using the CONFIG_foo settings for page-size, etc. there and add a few wrappers / helper functions for calling it. This is a preparation patch for adding auto-detecting of the nand parameters like the BROM does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Properly config page-size in the nand ctl registerHans de Goede2015-08-311-0/+5
| | | | | | | | | Properly config page-size in the nand ctl register, it seems that things work fine without doing this, but still lets play it safe and properly set the page-size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Add support for sun4i and sun5i SoCsHans de Goede2015-08-311-2/+2
| | | | | | | | | | | | Other then having a few less chip-select lines the nand controller on sun4i, sun5i and sun7i is identical. Note this patch also muxes GPC7 to the NAND on sun7i where as before it was not muxed this way. GPC7 is a standard NAND pin, so it should always be muxed to the NAND when in use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _offHans de Goede2015-08-311-46/+12
| | | | | | | | | Sync the code for figuring out the ecc_mode and ecc_offset with the linux kernel v4.1. Keeping this in sync seems like a good idea in general, and it fixes / adds support for ecc strengths of 56, 60 and 64 bits. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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