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path: root/drivers/mtd/nand/tegra_nand.c
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* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-111-0/+1
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* tegra: nand: disable subpage writesMarcel Ziswiler2015-08-131-0/+3
| | | | | | | | Disable subpage writes as we do not provide ecc->hwctl. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mtd/nand/tegra: alignment workaroundMarcel Ziswiler2015-08-131-51/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Integrate cache alignment bounce buffer to workaround issues as follows: Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)... ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Done Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ] Starting kernel ... undefined instruction pc : [<005ff03c>] lr : [<0000800c>] sp : 0144b6e8 ip : 01000188 fp : 0144a6c8 r10: 00000000 r9 : 411fc090 r8 : 00000100 r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000 r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: fix read_byte required for proper onfi detectionMarcel Ziswiler2015-08-131-31/+7
| | | | | | | | | | | | | | | | | | Fix PIO read_byte() implementation not only used for the legacy READ ID but also the PARAM command required for proper ONFI detection. This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late (not mainline yet but getting there soon I hope). I vaguely remember that those commands are special on 16-bit bus NAND (e.g. always return 8-bit data regardless) and later Linux MTD fixed/ changed the way this is handled which in turn broke once U-Boot pulled that in. Basically instead of doing PIO read regular DMA block read is now used which this patch actually fixes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* dm: tegra: nand: Remove use of fdtdec GPIO supportSimon Glass2015-01-291-5/+4
| | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* mtd: resync with Linux-3.7.1Sergey Lapin2013-05-311-15/+12
| | | | | | | | | | | | | | | | | | | | | | This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
* tegra: nand: make ONFI detection workLucas Stach2012-10-291-0/+36
| | | | | | | | | | | | Add the missing bits to the Tegra NAND driver to make ONFI detection work properly. Also add it to the Tegra default config, as it seems to be a reasonable thing to have it available on all boards that use any kind of NAND. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: add board pinmuxLucas Stach2012-10-151-1/+0
| | | | | | | | Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren2012-10-151-3/+2
| | | | | | | | | | | The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: Add Tegra NAND driverJim Lin2012-09-071-0/+1026
A device tree is used to configure the NAND, including memory timings and block/pages sizes. If this node is not present or is disabled, then NAND will not be initialized. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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