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* Minor coding style cleanup.Wolfgang Denk2011-05-191-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc/8xxx: Fix LAW init to respect pre-initialized entriesKumar Gala2011-04-041-0/+20
| | | | | | | | | | If some pre-boot or earlier stage bootloader (NAND SPL) has setup LAW entries consider them good and mark them used. In the NAND SPL case we skip re-initializing based on the law_table since the SPL phase already did that. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law: Fix LAW printing functionKumar Gala2011-02-221-1/+1
| | | | | | | | | | | | | We had an extra '0x' in the output of the LAWAR header that would cause output like: LAWBAR11: 0x00000000 LAWAR0x11: 0x80f0001d intead of: LAWBAR11: 0x00000000 LAWAR11: 0x80f0001d Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Introduce 85xx, 86xx, QorIQ config headersKumar Gala2011-01-191-21/+1
| | | | | | | | | | | Add new headers that capture common defines for a given SoC/processor rather than duplicating that information in board config.h and random other places. Eventually this should be handled by Kconfig & defconfigs Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de>
* powerpc/p2040: Add various p2040 specific informationKumar Gala2011-01-191-2/+2
| | | | | | | | | | Add P2040 SoC specific information: * SERDES Table * Added p2040 to cpu_type_list and SVR list * Added number of LAWs for p2040 * Set CONFIG_MAX_CPUS to 4 for p2040 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1014 ProcessorPoonam Aggrwal2011-01-191-1/+1
| | | | | | | | | | | | The P1014 is similar to the P1010 processor with the following differences: - 16bit DDR with ECC. (P1010 has 32bit DDR w/o ECC) - no eCAN interface. (P1010 has 2 eCAN interfaces) - Two SGMII interface (P1010 has 3 SGMII) - No secure boot Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add Support for Freescale P1010 ProcessorPoonam Aggrwal2011-01-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Key Features include of the P1010: * e500v2 core frequency operation of 500 to 800 MHz * Power consumption less than 5.0 W at 800 MHz core speed * Dual SATA 3 Gbps controllers with integrated PHY * Dual PCI Express controllers * Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSECs) * TCP/IP acceleration and classification capabilities * IEEE 1588 support * Lossless flow control * RGMII, SGMII * DDR3 with support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate 32/16-bit DDR3 memory controller * Dedicated security engine featuring trusted boot * TDM interface * Dual controller area networks (FlexCAN) controller * SD/MMC card controller supporting booting from Flash cards * USB 2.0 host and device controller with an on-chip, high-speed PHY * Integrated Flash controller (IFC) * Power Management Controller (PMC) * Four-channel, general-purpose DMA controller * I2C controller * Serial peripheral interface (SPI) controller with master and slave support * System timers including a periodic interrupt timer, real-time clock, software watchdog timer, and four general-purpose timers * Dual DUARTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p3041: Add various p3041 related definesKumar Gala2010-07-201-1/+2
| | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p3041 to cpu_type_list and SVR list * Added number of LAWs for p3041 * Set CONFIG_MAX_CPUS to 4 for p3041 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/p5020: Add various p5020 related defines (and p5010)Kumar Gala2010-07-201-1/+1
| | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p5020 & p5010 to cpu_type_list and SVR list * Added number of LAWs for p5020 * Set CONFIG_MAX_CPUS to 2 for p5020 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law.c: Add print_laws() for FSL_CORENET platforms.Becky Bruce2010-07-161-0/+6
| | | | | | | Add printing of LAWBARH/LAWBARL for FSL_CORENET platforms. Signed-off-by: Becky Bruce <Beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/misc/fsl_law.c: Rearrange code to avoid duplicationBecky Bruce2010-07-161-77/+48
| | | | | | | | The current code redefines functions based on FSL_CORENET_ vs not - create macros/inlines instead that hide the differences. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala2010-04-071-1/+3
| | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: get_law_entry isn't used in CONFIG_NAND_SPLKumar Gala2009-09-301-0/+4
| | | | | | | Don't include get_law_entry as part of the NAND_SPL build since the code isnt used. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-241-0/+2
| | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Add support for CoreNet style platform LAWsKumar Gala2009-09-241-11/+115
| | | | | | | | | | | | | | | | On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu2009-09-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: add register read-back to set_law()Timur Tabi2009-09-081-1/+2
| | | | | | | | | After programming a new LAW, we should read-back the LAWAR register so that we sync the writes. Otherwise, code that attempts to use the new LAW-mapped memory might fail right away. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-281-1/+2
| | | | | | | | P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-281-1/+1
| | | | | | | | | | | | | | P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law: Fix bug in calculation of LAW sizingKumar Gala2009-04-041-0/+3
| | | | | | | | In set_ddr_laws() when we determined how much of the size requested to be mapped was covered by the the first LAW we needed to recalculate the size based on what was actually mapped. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xx: Add MPC8569 CPU supportHaiying Wang2009-03-301-1/+1
| | | | | | | | | There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-161-1/+2
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_law clear enable before changing.Ed Swarthout2008-10-181-0/+1
| | | | | | | Debug sessions may have left enabled laws. Changing lawbar with an unkown enabled tgtid could cause problems. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-181-3/+3
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc85xx: Add support for the MPC8536Kumar Gala2008-08-271-1/+1
| | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
* FSL DDR: Provide a generic set_ddr_laws()Kumar Gala2008-08-271-0/+39
| | | | | | | Provide a helper function that will setup the last available LAWs (upto 2) for DDR. Useful for SPD/dyanmic DDR setting code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL LAW: Add new interface to use the last free LAWKumar Gala2008-06-111-0/+19
| | | | | | | | LAWs have the concept of priority so its useful to be able to allocate the lowest (highest number) priority. We will end up using this with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL LAW: Keep track of LAW allocationsKumar Gala2008-06-111-7/+39
| | | | | | | | | | | | | | | Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 86xx: Add print_laws function to fsl_law.cBecky Bruce2008-01-241-0/+19
| | | | | | | This can be used for debug, and will be used by board code to help implement reginfo. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 85xx: Move LAW init code into CKumar Gala2008-01-161-0/+70
Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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