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* dm: i2c: Move slave details to child platdataSimon Glass2015-01-296-87/+39
| | | | | | | | | | | | | | | | | At present we go through various contortions to store the I2C's chip address in its private data. This only exists when the chip is active so must be set up when it is probed. Until the device is probed we don't actually record what address it will appear on. However, now that we can support per-child platform data, we can use that instead. This allows us to set up the address when the child is bound, and avoid the messy contortions. Unfortunately this is a fairly large change and it seems to be difficult to break it down further. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* dm: core: Add a flag to control sequence numberingSimon Glass2015-01-291-0/+1
| | | | | | | | | | | | | | | | At present we try to use the 'reg' property and device tree aliases to give devices a sequence number. The 'reg' property is often actually a memory address, so the sequence numbers thus-obtained are not useful. It would be better if the devices were just sequentially numbered in that case. In fact neither I2C nor SPI use this feature, so drop it. Some devices need us to look up an alias to number them within the uclass. Add a flag to control this, so it is not done unless it is needed. Adjust the tests to test this new behaviour. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* dm: i2c: Provide an offset length parameter where neededSimon Glass2015-01-292-8/+10
| | | | | | | | | | Rather than assuming that the chip offset length is 1, allow it to be provided. This allows chips that don't use the default offset length to be used (at present they are only supported by the command line 'i2c' command which sets the offset length explicitly). Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* dm: i2c: Add a compatbility layerSimon Glass2015-01-292-0/+99
| | | | | | | | | | | | | For boards which use multiple I2C devices, or for SOCs which support multiple boards, we might want to convert these to driver model at different times. At present this is difficult because we need to either use CONFIG_DM_I2C for a board or not. Add a compatibility layer which implements the old API, thus allowing a board to move to driver model for I2C without requiring that everything it uses is moved in the same commit. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: i2c: Rename driver model I2C functions to permit compatibilitySimon Glass2015-01-291-4/+5
| | | | | | | | | | | Add a dm_ prefix to driver model I2C functions so that we can keep the old ones around. This is a little unfortunate, but on reflection it is too difficult to change the API. We can undo this rename when most boards and drivers are converted to use driver model for I2C. Signed-off-by: Simon Glass <sjg@chromium.org>
* i2c: UniPhier: add driver for UniPhier FIFO-builtin i2c controllerMasahiro Yamada2015-01-293-0/+388
| | | | | | | | | | This commit adds on-chip I2C driver used on newer SoCs of Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* i2c: UniPhier: add driver for UniPhier i2c controllerMasahiro Yamada2015-01-293-0/+248
| | | | | | | | | | This commit adds on-chip I2C driver used on some old Panasonic UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* i2c: add CONFIG_DM_I2C to KconfigMasahiro Yamada2015-01-291-0/+6
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* i2c:mxc fix array size of i2c_dataPeng Fan2015-01-081-11/+11
| | | | | | | | | | | We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3, there are 4 i2c interface, but not 3. So the size of i2c_data array should be calculated using "ARRAY_SIZE(i2c_bases)". To avoid compile error, move i2c_bases before sram_data structure which contains i2c_data array. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* dm: i2c: tegra: Convert to driver modelSimon Glass2014-12-111-247/+119
| | | | | | | | | | | | | | | | | | | | | | This converts all Tegra boards over to use driver model for I2C. The driver is adjusted to use driver model and the following obsolete CONFIGs are removed: - CONFIG_SYS_I2C_INIT_BOARD - CONFIG_I2C_MULTI_BUS - CONFIG_SYS_MAX_I2C_BUS - CONFIG_SYS_I2C_SPEED - CONFIG_SYS_I2C This has been tested on: - trimslice (no I2C) - beaver - Jetson-TK1 It has not been tested on Tegra 114 as I don't have that board. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: i2c: Add a sandbox I2C driverSimon Glass2014-12-112-1/+112
| | | | | | | | | This driver includes some test features such as only supporting certain bus speeds. It passes its I2C traffic through to an emulator. Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* dm: i2c: Add I2C emulation driver for sandboxSimon Glass2014-12-112-0/+15
| | | | | | | | | In order to test I2C we need some sort of emulation interface. Add hooks to allow a driver to emulate an I2C device for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* dm: i2c: Add a uclass for I2CSimon Glass2014-12-112-0/+467
| | | | | | | | | | | | | | The uclass implements the same operations as the current I2C framework but makes some changes to make it fit driver model better: - Remove the chip address from API calls - Remove the address length from API calls - Remove concept of 'current' I2C bus - Drop all existing init functions Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* i2c: Correct spelling errorMark Tomlinson2014-12-081-3/+3
| | | | | | "diconnect" and "disconnet" should both be "disconnect". Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
* i2c: Fix deselection of muxesMark Tomlinson2014-12-081-1/+1
| | | | | | | | | | | Due to an uninitialised variable, when muxes were deselected, any value could be written to the mux control register. On the PCA9548, this could result in multiple channels being selected, thus enabling multiple pull-up resistors, and much bus capacitance. The fix is simply to initialise the written value to zero. Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
* linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* blackfin: convert to use CONFIG_SYS_I2C frameworkScott Jiang2014-11-171-142/+60
| | | | Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
* adi_i2c: convert to use general io accessors.Scott Jiang2014-11-171-68/+77
| | | | Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
* blackfin: rename bfin-twi_i2c driver to adi_i2cScott Jiang2014-11-172-5/+4
| | | | Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
* i2c: rcar_i2c: Fix order of restart and clear statusNobuhiro Iwamatsu2014-11-101-2/+2
| | | | | | | | | | In case of repeated START condition, the restart has to be kicked before clear status (MSR register). If it is kicked after clear status, R-Car I2C may transfer data (TXD register) or receive data (RXD register) instead of transferring slave address (MAR register). Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* drivers/i2c/fsl_i2c: Change CONFIG_I2C_TIMEOUT to 100msShaveta Leekha2014-11-101-1/+1
| | | | | | | | | | | | | | Some slow I2C devices like Power Monitor(ZM7304) at times do not work well with low timeout value, so I2C bus get stuck during read cycle with this device, changing it to 100ms from 10ms works fine A lot of other i2c drivers like mxc and i2c drivers of BOOTROM also use relax timeouts to give sufficient ticks to work well with slower devices Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* ppc4xx: Handle i2c stuck on combined xferDirk Eibach2014-11-101-0/+21
| | | | | | | | | | | | ppc4xx i2c master gets stuck on errors while repeated start is active. Can be easily reproduced by "i2c md" on an unpopulated i2c address. There is not stop condition given, scl remains pulled low. The only way out seems to be doing a stop manually and then a soft reset. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix i2c repeated startDirk Eibach2014-11-101-4/+5
| | | | | | | | | | | | | Debugging some i2c trouble I saw on my scope that repeated start is not working properply. The 4xx even held clock pulled down after transfers. Having a look in the driver I realized that IIC_CNTL_RPST is set on that part of the transfer that should begin with a repeated start. But repeated start is about not sending a stop condition, so IIC_CNTL_RPST has to be set on the last transfer before the repeated start happens. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* i2c: use __weakJeroen Hofstee2014-11-041-6/+2
| | | | | Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* i2c: designware: Convert driver to multibus/multiadapter frameworkStefan Roese2014-10-292-167/+128
| | | | | | | | | | | | | | | | | | | | | In preparation for the SoCFPGA support of the designware I2C driver, convert this driver to the common CONFIG_SYS_I2C framework. This patch converts all users of this driver, this is: - ST spearxxx boards - AXS101 (ARC700 platform) I couldn't test this patch on those boards. Only compile tested for all spear boards. And tested on SoCFPGA. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
* i2c: mxs: Add support for I2C 1 on i.MX28Marek Vasut2014-10-291-1/+8
| | | | | | | | Add support for I2C bus 1 on the i.MX28. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: mxs: Pass the i2c_adapter aroundMarek Vasut2014-10-291-67/+67
| | | | | | | | | | | | This patch permeates the struct i2c_adapter throughout the driver, so that it can be used to determine which adapter should be used. Note that the driver still supports only one adapter. Note that the patch does shuffle mxs_i2c_set_bus_speed() to the top of the driver, but the function remains unchanged. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: mxs: Add basic support for i2c frameworkMarek Vasut2014-10-292-21/+30
| | | | | | | | | | | This patch just converts the function prototypes used throughout this driver to match those of the i2c framework. There is so far no functional change. This patch does not do the deeper integration of the framework bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: mxs: Consolidate hard-coded bus addressMarek Vasut2014-10-291-7/+12
| | | | | | | | | | This patch prepares the MXS I2C driver for the conversion to the new I2C driver framework by pulling out the hard-coded I2C0 address from all the places. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de>
* i2c: designware: add an implement i2c protosJeroen Hofstee2014-10-251-7/+12
| | | | | | | | | | | Include the i2c header and change the non confirming functions to do so. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Acked-by: Heiko Schocher <hs@denx.de> [trini: Fix i2c_get_bus_num prototype] Signed-off-by: Tom Rini <trini@ti.com>
* tegra: make local functions staticJeroen Hofstee2014-10-251-3/+4
| | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* i2c: mvtwsi: Add support for Marvell Armada XPStefan Roese2014-10-231-1/+1
| | | | | | | | To support the Armada XP SoC, we just need to include the correct header. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Luka Perkov <luka@openwrt.org>
* arm: marvell: Move arch/kirkwood.h to arch/soc.hStefan Roese2014-10-231-1/+1
| | | | | | | | | This move makes is possible to use this header not only from kirkwood platforms but from all Marvell mvebu platforms. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-241-2/+2
| | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kconfig: add blank Kconfig filesMasahiro Yamada2014-09-241-0/+0
| | | | | | | | This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* ls102xa: i2c: Add i2c support for LS102xAWang Huan2014-09-081-2/+2
| | | | | | | | | | | The existing i.MX's I2C driver mxc_i2c.c is compatible with the controller of LS102xA. As I2C's registers are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to use 8-bit driver. This patch is to add I2C 1,2,3 support for LS102xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-07-282-39/+51
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| * sunxi: Add i2c supportHans de Goede2014-07-181-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the i2c controller found on all Allwinner sunxi SoCs, this is the same controller as found on the Marvell orion5x and kirkwood SoC families, with a slightly different register layout, so this patch uses the existing mvtwsi code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Heiko Schocher <hs@denx.de> [ ijc -- updated u-boot-spl-fel.lds ]
| * mvtwsi: convert to CONFIG_SYS_I2C frameworkHans de Goede2014-07-162-39/+33
| | | | | | | | | | | | | | | | | | | | | | | | Note this has only been tested on Allwinner sunxi devices (support for which gets introduced by a later patch). The kirkwood changes have been compile tested using the wireless_space board config, the orion5x changes have been compile tested using the edminiv2 board config. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Heiko Schocher <hs@denx.de>
* | fsl_i2c: add support for 3rd and 4th I2CShengzhou Liu2014-07-161-2/+20
| | | | | | | | | | | | Add support for 3rd and 4th I2C. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* | i2c, omap24xx: add i2c deblock sequenzHeiko Schocher2014-07-161-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a bus busy is detected when intializing the driver, toggle 9 times the scl pin. Therefore enable the test mode of the controller, in which the scl, sda pins can be controlled manually. Tested on the siemens boards pxm2, rut and dxr2. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Hannes Petermaier <oe5hpm@oevsv.at> Cc: Lubomir Popov <lpopov@mm-sol.com> Cc: Steve Sakoman <steve@sakoman.com> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Vincent Stehlé <v-stehle@ti.com> Cc: Samuel Egli <samuel.egli@siemens.com>
* | board: gdsys: Make gdsys osd hardware detection more robustDirk Eibach2014-07-071-1/+0
| | | | | | | | Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | i2c: IHS I2C master driverDirk Eibach2014-07-072-0/+205
| | | | | | | | | | | | | | | | IHS I2C master support was merely a hack in the osd driver. Now it is a proper u-boot I2C framework driver, supporting the v2.00 master features. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-07-071-17/+27
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| * i2c: tegra: dump alen in debug statementsStephen Warren2014-07-031-4/+4
| | | | | | | | | | | | | | | | | | Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump the address length (alen) too, so the address value can be correctly interpreted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: write clean data to TX FIFOStephen Warren2014-07-031-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra I2C controller's TX FIFO contains 32-bit words. If the final FIFO entry of a transaction contains fewer than 4 bytes, the driver currently fills the unused FIFO bytes with uninitialized data. This can be confusing when reading back the FIFO content for debugging purposes. Solve this by explicitly initializing the variable containing FIFO data before filling it (partially) with data. With this change, send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e. read) branch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
| * i2c: tegra: use repeated start for readsStephen Warren2014-07-031-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C read transactions are typically implemented as follows: START(write) address REPEATED_START(read) data... STOP However, Tegra's I2C driver currently implements reads as follows: START(write) address STOP START(read) data... STOP This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board, leading to corrupted read data in some cases. Fix the driver to chain the transactions together using repeated starts to solve this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com>
* | ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-031-0/+5
|/ | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* i2c: kona: Resolve Kona I2C driver issueSteve Rae2014-06-121-1/+1
| | | | | | - "i2c mw" command hangs (with some compilers) Signed-off-by: Steve Rae <srae@broadcom.com>
* mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globalsHans de Goede2014-05-141-19/+4
| | | | | | | | | These are used only once, so their is no need to have them global. This also stops mvtwsi from using any bss vars making it easier to use before dram init (to talk to the pmic to set the dram voltage). Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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