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path: root/drivers/ddr/marvell/a38x/ddr3_training_ip.h
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* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-141-2/+0
| | | | | | | | | | | | | | | | | | gcc 5.1 generates this new warning (for Armada 38x platforms): drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result': drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument] memcpy(result, training_result, sizeof(result)); ^ drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]) ^ Since this functions is not referenced anywhere, lets just remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdrStefan Roese2015-07-231-0/+180
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
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