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* axs101: flush DMA buffer descriptors before DMA transactons startsAlexey Brodkin2014-03-281-0/+8
| | | | | | | | | | | | | | | | | CPU sets DMA buffer descriptors with data required for inetrnal DMA such as: * Ownership of BD * Buffer size * Pointer to data buffer in memory Then we need to make sure DMA engine of NAND controller gets proper data. For this we flush buffer rescriptor. Then we're ready for DMA transaction. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com>
* arc: add AXS101 board supportAlexey Brodkin2014-02-071-0/+226
AXS101 is a new generation of devlopment boards from Synopsys that houses ASIC with ARC700 and lots of DesignWare peripherals: * DW APB UART * DW Mobile Storage (MMC/SD) * DW I2C * DW GMAC Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Heiko Schocher <hs@denx.de>
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