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* | armv8/ls2085ardb: DSPI pin muxing configure through QIXIS CPLDHaikun.Wang@freescale.com2015-07-201-20/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS CPLD to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang <Haikun.Wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085aqds: DSPI pin muxing configure through QIXISHaikun Wang2015-07-201-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | DSPI has pin muxing with SDHC and other IPs, this patch check the value of RCW SPI_PCS_BASE and SPI_BASE_BASE fields, it also check the "hwconfig" variable. If those pins are configured to DSPI and "hwconfig" enable DSPI, set the BRDCFG5 of QIXIS FPGA to configure the routing to on-board SPI memory. Otherwise will configure to SDHC. DSPI is enabled in "hwconfig" by appending "dspi", eg. setenv hwconfig "$hwconfig;dspi" Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | arm/ls102xa: Add little-endian mode support for audio IPsAlison Wang2015-07-202-0/+6
| | | | | | | | | | | | | | | | As SCFG_ENDIANCR register is added to choose little-endian or big-endian for audio IPs on Rev2.0 silion, little-endian mode is selected. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/ls2085rdb: Export functions for standalone AQ FW load appsPrabhakar Kushwaha2015-07-201-0/+15
| | | | | | | | | | | | | | | | | | Export functions required by Aquntia PHY firmware load application. functions are memset, strcpy, mdelay, mdio_get_current_dev, phy_find_by_mask, mdio_phydev_for_ethname and miiphy_set_current_dev Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/fsl-lsch3: Support 256M mem split for MC & dbg-srvrPrabhakar Kushwaha2015-07-203-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | The agreed split of the top of memory is 256M for debug server and 256M for MC. This patch implements the split. In addition, the MC mem must be 512MB aligned, so the amount of memory to hide must be 512MB to achieve that alignment. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085a: Expose all DDR region(s) to LinuxBhupesh Sharma2015-07-206-18/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows u-boot to expose the complete DDR region(s) to Linux (after subtracting the memory hidden via MEM_TOP_HIDE mechanism). This allows the u-boot to support the 48-bit VA support provided by ARM64 Linux in flavors 3.18 and above, by passing the appropriate 'memory' DTS nodes. Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085ardb: Fix SPD address error on early boardsYork Sun2015-07-201-0/+19
| | | | | | | | | | | | | | | | | | Board rev C and earlier has duplicated SPD address on 2nd DDR controller slots. It is fixed on rev D and later. SPD addresses need to be updated accordingly. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
* | armv8/ls2085a: Avoid hard-coding for board name printPrabhakar Kushwaha2015-07-202-2/+9
| | | | | | | | | | | | | | | | | | | | | | LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A personlities. Instead of hard-coding, board name should change as per selected personality. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085RDB: Update board version print logicPrabhakar Kushwaha2015-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | As per updated board document, no need to substract 1 from arch[BRD] bit field. Default value + 'A' represents the board revision. So update board version print logic to reflect the same. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | board/fsl/common: Fix eeprom system version endiannessJaiprakash Singh2015-07-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | SYSTEM ID EPPROM always store SYSTEM version info in big endian format. SoC with ARM or PowerPC core should read/write version info from eeprom in BIG endian format. So use cpu-specific APIs to read SYSTEM version. Signed-off-by: Jaiprakash Singh <b44839 at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085qds: Update SFP TX bit as "0" to enable XFIPrabhakar Kushwaha2015-07-201-1/+1
| | | | | | | | | | | | | | | | FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports. Signed-off-by: Dai Haruki <Dai.Haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085aqds: Add support of SerDes protocol 0x49Prabhakar Kushwaha2015-07-201-0/+2
| | | | | | | | | | | | | | | | | | | | SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2. Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of ls2085aqds platform. Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085ardb: add hwconfig setting for eSDHCYangbo Lu2015-07-201-0/+36
| | | | | | | | | | | | | | | | | | Add hwconfig setting for eSDHC since it shares some pins with other IP block. Signed-off-by: Yangbo Lu <yangbo.lu at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | armv8/ls2085ardb: Add eth & phy firmware loading supportPrabhakar Kushwaha2015-07-203-14/+134
|/ | | | | | | | | | Add support for board eth initialization and support for loading phy firmware. PHY firmware needs to be loaded from board_eth_init() because all the MACs are not initialized by ldpaa_eth driver. Signed-off-by: pankaj chauhan <pankaj.chauhan at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-05-261-2/+2
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| * pmic: pfuze100 fix typoPeng Fan2015-05-191-2/+2
| | | | | | | | | | | | Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.hYork Sun2015-05-201-0/+1
|/ | | | | | | | | ccsr_ddr structure is already defined in fsl_immap.h. Remove this duplicated define. Move fixed timing into ls1021atwr.h. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-131-1/+1
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* powerpc/t4240qds: Update RCW, defconfig and maintainerShaohui Xie2015-05-042-4/+2
| | | | | | | | | | | | | | | | | 1. board/freescale/t4qds/t4_rcw.cfg 1.8GHz support is requested as default frequency, so update the rcw. 2. remove un-used configs configs/T4160QDS_SPIFLASH_defconfig configs/T4240QDS_SPIFLASH_defconfig SPI boot is not available on T4QDS, so the configs should be removed. 3. board/freescale/t4qds/MAINTAINERS Updated MAINTAINERS accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> [York Sun: revise subject] Reviewed-by: York Sun <yorksun@freescale.com>
* t2080rdb/rcw: update ddr frequency from 1600MT/s to 1867MT/sShengzhou Liu2015-05-041-1/+4
| | | | | | | | | T2080RDB RevC uses new SODIMM 1867MT/s instead of previous 1600MT/s. So update RCW to support new DDR frequency 1867MT/s by default. Reserve the old 1600MT/s in comment for users in needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: Add adapter card type identification supportYangbo Lu2015-05-041-0/+14
| | | | | | | | | | | | Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun <yorksun@freescale.com>
* board/t2080rdb: reset cs4315 phyShengzhou Liu2015-05-042-0/+10
| | | | | | | | CS4315 PHY doesn't support phy-reset by software, it needs to reset it by hardware via CPLD control. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/deepsleep: avoid the DDR restore from being optimized outTang Yuantian2015-05-041-4/+4
| | | | | | | | | | | Function dp_ddr_restore is to restore the first 128-byte space of DDR. However those codes may be optimized out by compiler since the destination address is at 0x0. In order to avoid compiler optimization, we restore the space from high address, which is not at 0x0, to low address. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t102x: use fdt_setprop_string instead of fdt_setpropShengzhou Liu2015-05-042-6/+7
| | | | | | | Use fdt_setprop_string instead of fdt_setprop to fix string length. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t1023rdb: Add T1023 RDB board supportShengzhou Liu2015-05-048-28/+286
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC. T1023RDB board Overview ----------------------- - T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz - CoreNet fabric supporting coherent and noncoherent transactions with prioritization and bandwidth allocation - Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC - Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC - Ethernet interfaces: - one 1G RGMII port on-board(RTL8211F PHY) - one 1G SGMII port on-board(RTL8211F PHY) - one 2.5G SGMII port on-board(AQR105 PHY) - PCIe: Two Mini-PCIe connectors on-board. - SerDes: 4 lanes up to 10.3125GHz - NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash - NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash - eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash. - USB: one Type-A USB 2.0 port with internal PHY - eSDHC: support SD/MMC card and eMMC on-board - 256Kbit M24256 I2C EEPROM - RTC: Real-time clock DS1339 on I2C bus - UART: one serial port on-board with RJ45 connector - Debugging: JTAG/COP for T1023 debugging As well updated T1024RDB to add T1023RDB. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix defconfig files] Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t4rdb: Add SD boot support for T4240RDB boardChunhe Lan2015-05-047-8/+117
| | | | | | | | | | | | This patch adds SD boot support for T4240RDB board. SPL framework is used. PBL initializes the internal RAM and copies SPL to it. Then SPL initializes DDR using SPD and copies u-boot from SD card to DDR, finally SPL transfers control to u-boot. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> [York Sun: Fix T4240RDB_SDCARD_defcofig] Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx/T4240EMU: Remove T4240EMU boardYork Sun2015-05-044-46/+0
| | | | | | | T4240 SoC has been available for a long time. Emulator support is no longer needed. Signed-off-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-282-10/+6
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| * mx6sabresd: Remove uneeded ifdefFabio Estevam2015-04-221-4/+0
| | | | | | | | | | | | RTT_NOM_120OHM is not defined, so remove its ifdef. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * mx6sabresd: Fix SPL memory descriptionFabio Estevam2015-04-221-4/+5
| | | | | | | | | | | | | | mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus and 2GiB, so fix the width and density fields accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * iMX: Fix compilation error when enabling SECURE_BOOTgaurav rana2015-04-221-2/+1
| | | | | | | | | | | | | | | | | | Move the compilation of file fsl_validate.c in MACRO CONFIG_CMD_ESBC_VALIDATE. This file should be compiled only when the above MACRO is defined This caused a break in compilation of iMX platforms when compiling for SECURE_BOOT Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-04-2429-70/+2067
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| * | armv8/ls2085ardb: Enable NAND SPL supportScott Wood2015-04-232-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | freescale/qixis: Add support for booting from NANDScott Wood2015-04-231-10/+21
| | | | | | | | | | | | | | | | | | | | | Use "qixis_reset nand" to reset the board to boot from NAND. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085aqds: NAND boot supportScott Wood2015-04-232-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
| * | driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-234-9/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | board/ls2085qds: Add support ethernetPrabhakar Kushwaha2015-04-234-13/+385
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of ethernet: - eth.c: mapping lane to slot for (0x2A, 0x07) - ls2085a.c: To enable/disable dpmac and get link type Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085ardb: Add support of LS2085ARDB platformYork Sun2015-04-238-0/+693
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun2015-04-238-0/+757
| | | | | | | | | | | | | | | | | | | | | | | | | | | The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
| * | fsl-lsch3: Introduce place for common early SoC initScott Wood2015-04-231-2/+2
| | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085a: Add support for reset requestpankaj chauhan2015-04-231-7/+0
| | | | | | | | | | | | | | | | | | | | | Add support for reset_cpu() by asserting RESET_REQ_B. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | armv8/ls2085a: Fix generic timer clock sourceYork Sun2015-04-231-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
| * | driver/fsl-mc: Add support of MC FlibsPrabhakar Kushwaha2015-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's Layerscape Management Complex (MC) provide support various objects like DPRC, DPNI, DPBP and DPIO. Where: DPRC: Place holdes for other MC objectes like DPNI, DPBP, DPIO DPBP: Management of buffer pool DPIO: Used for used to QBMan portal DPNI: Represents standard network interface These objects are used for DPAA ethernet drivers. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | armv8/fsl-lsch3: Add Freescale Debug Server driverBhupesh Sharma2015-04-211-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | QE/DeepSleep: add QE deepsleep support for armZhao Qiang2015-04-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | QE/DeepSleep: add QE deepsleep support for mpc85xxZhao Qiang2015-04-211-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | pci/layerscape: remove unnecessary pcie_layerscape.hMinghuan Lian2015-04-212-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch uses the common function name ft_pci_setup to replace ft_pcie_setup, then removes unnecessary pcie_layerscape.h because all the functions have been declared in common.h. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | Add bootscript support to esbc_validate.gaurav rana2015-04-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls102xa: ddr4: Use LPUART as console output to verify DCU driverAlison Wang2015-04-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | On QDS board with DDR4 DIMM, LPUART is used as console output to verify DCU driver. This patch adds ls1021aqds_ddr4_nor_lpuart_defconfig for this support. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | ls1021atwr: add hwconfig setting to do pin muxYao Yuan2015-04-211-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale LS1021ATWR share some pins. Hwconfig option is used to allows users to choose the pin functions. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> [York Sun: revised commit message] Reviewed-by: York Sun <yorksun@freescale.com>
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