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* Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xxYork Sun2013-11-251-1/+2
| | | | | | | Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-251-2/+2
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-141-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* 8xxx: Change all 8*xx_DDR addresses to 8xxxAndy Fleming2012-11-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warningKumar Gala2011-11-111-2/+0
| | | | | | | mpc8569mds.c: In function 'local_bus_init': mpc8569mds.c:306:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Change fsl_phy_enet_if to phy_interface_tAndy Fleming2011-04-201-1/+3
| | | | | | | | | | | | The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum. This meant that drivers which used fsl_phy_enet_if to deal with PHY interfaces would have to convert between the two (or we would have to have them mirror each other, and deal with the ensuing maintenance headache). Instead, we switch all clients of fsl_phy_enet_if over to phy_interface_t, which should become the standard, anyway. Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Detlev Zundel <dzu@denx.de>
* powerpc/85xx: Rework MPC8569MDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-141-38/+1
| | | | | | | | Remove duplicated code in MPC8569MDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx boards: initdram() cleanup/bugfixBecky Bruce2011-01-141-36/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configuredKumar Gala2011-01-141-1/+2
| | | | | | | Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Clean up printing of PCI boot infoPeter Tyser2010-11-141-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
* powerpc/8xxx: Add fdt_fixup_phy_connection helperKumar Gala2010-10-201-2/+2
| | | | | | | Add a common helper that will set the PHY connection type based on enum. We use this on eTSEC, UCC, and will with Fman in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc8569mds: fix consuming long time while relocating code.Haiying Wang2010-10-071-0/+26
| | | | | | | | | | | | The original code maps boot flash as non-cacheable region. When calling relocate_code in flash to copy u-boot from flash to ddr, every loop copy command is read from flash. The flash read speed will be the bottleneck, which consuming long time to do this operation. To resovle this, map the boot flash as write-through cache via tlb. And set tlb to remap the flash after code executing in ddr, to confirm flash erase operation properly done. Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliasesKumar Gala2010-07-201-4/+3
| | | | | | | | | | | Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Add PIB/ATM support for MPC8569mdsLiu Yu2010-01-251-0/+7
| | | | | Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-171-1/+1
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* mpc85xx: Add 4-bits eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2010-01-051-0/+14
| | | | | | | | | Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 0" document, which describes all eSDHC pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up MPC8569 MDS PCI setup codeKumar Gala2010-01-051-60/+26
| | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Configure QE USB for MPC8569E-MDS boardsAnton Vorontsov2009-10-271-0/+32
| | | | | | | | Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Configure QE UART for MPC8569E-MDS boardsAnton Vorontsov2009-10-271-21/+77
| | | | | | | | | | | | To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node. Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boardsAnton Vorontsov2009-10-271-0/+6
| | | | | | | | SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-271-0/+116
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-081-2/+2
| | | | | | | | | | | Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-281-3/+0
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-281-3/+1
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add RMII support for MPC8569MDSHaiying Wang2009-06-121-1/+95
| | | | | | | | | This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to enalbe_mpc8569mds_qe_uec which is more accurate. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add UEC3 and UEC4 support for MPC8569MDSHaiying Wang2009-06-121-0/+30
| | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add UART1 support for MPC8569MDSHaiying Wang2009-06-121-0/+6
| | | | | | | | MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define those pins before using UART1. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Move prototypes into fsl_pci.h and remove explicit externsKumar Gala2009-04-041-6/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala2009-04-041-1/+1
| | | | | | | Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xx: Add MPC8569MDS board supportHaiying Wang2009-03-301-0/+329
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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