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* Remove LBC_CACHE_BASE from 8544 DSAndy Fleming2008-07-141-1/+1
| | | | | | | | | | The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx/86xx: Move to dynamic mgmt of LAWsKumar Gala2008-06-111-8/+8
| | | | | | | | | | | With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* 85xx: convert MPC8544 DS over to use new LAW init codeKumar Gala2008-01-161-0/+42
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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