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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-7/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* mpc83xx: fix 837x MDS PCI HOST buildKim Phillips2010-10-181-1/+1
| | | | | | | | | | | | | | commit 6aa3d3bfaa986f1aff5e21a9b9f68d087715b1a9 "83xx: Remove warmboot parameter from PCI init functions" missed one mpc83xx_pcie_init callsite, causing this build error: Configuring for MPC837XEMDS_HOST board... pci.c: In function 'pci_init_board': pci.c:141: error: too many arguments to function 'mpc83xx_pcie_init' this patch extends the commit to include that callsite. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Remove warmboot parameter from PCI init functionsPeter Tyser2010-09-231-1/+1
| | | | | | | | | | | | | This change lays the groundwork for the BOOTFLAG_* flags being removed. This change has the small affect of delaying 100ms on PCI initialization after a warm boot as opposed to the optimal 1ms on some boards. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> included the mpc8308_p1m board. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* ppc: Split MPC83xx SERDES code from MPC85xx/MPC86xx/QorIQKumar Gala2010-04-261-1/+1
| | | | | | | | | The MPC83xx SERDES control is different from the other FSL PPC chips. For now lets split it out so we can standardize on interfaces for determining of a device on SERDES is configured. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: convert all remaining boards over to 83XX_GENERIC_PCIKim Phillips2009-07-181-3/+1
| | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: MPC837XEMDS: Initialize SerDes before negating PCIE reset signalAnton Vorontsov2009-03-051-7/+7
| | | | | | | | | | The SerDes initialization should be finished before negating the reset signal according to the reference manual. This isn't an issue on real hardware, but we'd better stick to the specifications anyway. Suggested-by: Liu Dave <DaveLiu@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: Add PCI-E support for MPC837XEMDS boardsAnton Vorontsov2009-01-211-1/+88
| | | | | | | | | | | MPC837XEMDS boards can support PCI-E via "PCI-E riser card". The card provides two PCI-E (x2) ports. Though, only one port can be used in x2 mode. Two ports can function simultaneously in x1 mode. PCI-E x1/x2 modes can be switched via "pex_x2" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boardsAnton Vorontsov2008-10-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB, standalone or acting as a PCI agent. User's Guide says: - When the CPLD recognizes its location on the PIB it automatically configures RCW to the PCI Host. - If the CPLD fails to recognize its location then it is automatically configured as an Agent and the PCI is configured to an external arbiter. This sounds good. Though in the standalone setup the CPLD sets PCI_HOST flag (it's ok, we can't act as PCI agents since we receive CLKIN, not PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without any arbiter bad things will happen (here the board hangs during any config space reads). In this situation we must disable the PCI. And in case of anybody really want to use an external arbiter, we provide "pci_external_aribter" environment variable. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-181-12/+12
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc83xx: Add the support of MPC837xEMDS boardDave Liu2008-01-081-0/+65
The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
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