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* Cleaned up some 85xx PCI bugsAndy Fleming2007-05-021-3/+6
| | | | | | | | | | | * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming <afleming@freescale.com>
* u-boot: Fix CPU2 errata on MPC8548CDS boardZang Roy-r619112007-04-231-0/+7
| | | | | | This patch apply workaround of CPU2 errata on MPC8548CDS board. Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
* Fix compilation warnings on a few 85xx boards.Jon Loeliger2006-10-201-1/+1
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* * Fix a bunch of compiler warnings for gcc 4.0Jon Loeliger2006-10-191-2/+0
| | | | Signed-off-by: Matthew McClintock <msm@freescale.com>
* Add support for eTSEC 3 & 4 on 8548 CDSAndy Fleming2006-09-191-0/+32
| | | | | | | * Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems
* * Added VIA configuration tableMatthew McClintock2006-08-091-16/+16
| | | | | | | * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* * Patch by Jon Loeliger, 2005-05-05Jon Loeliger2005-07-251-0/+329
Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
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