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* | ARM: move #ifdef to match the error handling codeMasahiro Yamada2016-06-241-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | Match the #ifdef ... #endif and the code, ret = do_something(); if (ret) return ret; This will make it easier to add more #ifdef'ed code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | arm64: optimize smp_kick_all_cpusMasahiro Yamada2016-06-241-3/+1
| | | | | | | | | | | | | | | | gic_kick_secondary_cpus can directly return to the caller of smp_kick_all_cpus. We do not have to use x29 register here. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | board: amlogic: Rename folder for Amlogic boardsCarlo Caione2016-06-241-1/+1
| | | | | | | | | | | | | | | | | | s/hardkernel/amlogic/ to have a single place for all the amlogic-based boards. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com>
* | omap3: bugfix in timer on rolloverDaniel Gorsulowski2016-06-241-1/+1
|/ | | | Signed-off-by: Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
* Kconfig: Add a new DISTRO_DEFAULTS Kconfig optionHans de Goede2016-06-201-9/+0
| | | | | | | | | | | | | | | | | | | | | | DISTRO_DEFAULTS is intended to mirror / replace include/config_distro_defaults.h. The intend is for boards which include this file to select this from their Kconfig files and when moving setting to Kconfig which are #define-ed in config_distro_defaults.h to select this from DISTRO_DEFAULTS so that boards which have selected DISTRO_DEFAULTS will keep the same configuration as before without needing any defconfig file changes. The initial list of selected things matches all settings recently removed from config_distro_defaults.h because they have been converted to Kconfig, with the exception of CMD_ELF and CMD_NET, which have a default of y, if the default of these ever changes they should be selected by DISTRO_DEFAULTS too. For testing and example purposes this commit also converts ARCH_SUNXI to use DISTRO_DEFAULT instead of selecting everything it needs itself. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add PSCI implementation in CChen-Yu Tsai2016-06-205-504/+341
| | | | | | | | | | | | | | To make the PSCI backend more maintainable and easier to port to newer SoCs, rewrite the current PSCI implementation in C. Some inline assembly bits are required to access coprocessor registers. PSCI stack setup is the only part left completely in assembly. In theory this part could be split out of psci_arch_init into a separate common function, and psci_arch_init could be completely in C. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add base address for GICChen-Yu Tsai2016-06-203-4/+6
| | | | | | | | | Instead of hardcoding the GIC addresses in the PSCI implementation, provide a base address in the cpu header. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add CPUCFG debug lock and sun7i cpu power controlsChen-Yu Tsai2016-06-201-1/+6
| | | | | | | | | | | | CPUCFG has an unlisted debug control register, which is used to disable external debug access. Also, sun7i secondary core power controls are in CPUCFG, as there's no separate PRCM block. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Group cpu core related controls togetherChen-Yu Tsai2016-06-202-24/+16
| | | | | | | | | | | | | Instead of listing individual registers for controls to each processor core, list them as an array of registers. This makes accessing controls by core index easier. Also rename "cpucfg_sun6i.h" (which was unused anyway) to the more generic "cpucfg.h", and add packed attribute to struct sunxi_cpucfg. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add missing linux/types.h header for cpucfg_sun6i.hChen-Yu Tsai2016-06-201-0/+2
| | | | | | | | | cpucfg_sun6i.h includes a register definition for the CPUCFG register block. The types used are u32 and u8, which are defined in linux/types.h. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add packed attribute to struct sunxi_prcm_regChen-Yu Tsai2016-06-201-1/+3
| | | | | | | | | struct sunxi_prcm_reg is a representation of the PRCM registers. Add the packed attribute to prevent the compiler from doing funny things. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Make CPUCFG_BASE macro names the same across familiesChen-Yu Tsai2016-06-203-14/+25
| | | | | | | | | Use SUNXI_CPUCFG_BASE across all families. This makes writing common PSCI code easier. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: allocate extra space for PSCI stack in secure section during link phaseChen-Yu Tsai2016-06-201-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The PSCI implementation expects at most 2 pages worth of space reserved at the end of the secure section for its stacks. If PSCI is relocated to secure SRAM, then everything is fine. If no secure SRAM is available, and PSCI remains in main memory, the reserved memory space doesn't cover the space used by the stack. If one accesses PSCI after Linux has fully booted, the memory that should have been reserved for the PSCI stacks may have been used by the kernel or userspace, and would be corrupted. Observed after effects include the system hanging or telinit core dumping when trying to reboot. It seems the init process gets hit the most on my test bed. This fix allocates the space used by the PSCI stacks in the secure section by skipping pages in the linker script, but only when there is no secure SRAM, to avoid bloating the binary. This fix is only a stop gap. It would be better to rework the stack allocation mechanism, maybe with proper usage of CONFIG_ macros and an explicit symbol. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: export common PSCI function declarations for C codeChen-Yu Tsai2016-06-201-0/+7
| | | | | | | | | | | Some common PSCI functions are written in assembly, but it should be possible to use them from C code. Add function declarations for C code to consume. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: save and restore clobbered registers in v7_flush_dcache_allChen-Yu Tsai2016-06-201-0/+2
| | | | | | Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()Chen-Yu Tsai2016-06-201-9/+9
| | | | | | | | | | | For psci_get_cpu_stack_top() to be usable in C code, it must adhere to the ARM calling conventions. Since it could be called when the stack is still unavailable, and the entry code to linux also expects r1 and r2 to remain unchanged, stick to r0 and r3. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add defconfig and dts file for inet86dz boardHans de Goede2016-06-202-0/+294
| | | | | | | | | | | | | | | The inet86dz board is a board used in 7" tablets from various oems. These tablets are a23 based 7" tablets featuring a 1024x600 LCD, 512MB RAM, 4G NAND, rtl8188etv usb wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. The dts file this commit adds is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add defconfig and dts file for Polaroid MID2407PXE03 tabletHans de Goede2016-06-203-0/+303
| | | | | | | | | | | | The Polaroid MID2407PXE03 is an a23 based 7" tablet based on a M86_MB V2.0 PCB, featuring a 800x480 LCD, 512MB RAM, 4G NAND, esp8089 wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Select USE_TINY_PRINTFHans de Goede2016-06-201-0/+1
| | | | | | | | This gives us a bit more breathing room wrt our SPL size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-06-2013-61/+261
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| * clk: convert API to match reset/mailbox styleStephen Warren2016-06-199-55/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * reset: implement a reset testStephen Warren2016-06-192-0/+32
| | | | | | | | | | | | | | | | | | This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * mailbox: add Tegra186 HSP driverStephen Warren2016-06-192-0/+15
| | | | | | | | | | | | | | | | | | | | Tegra186's HSP module implements doorbells, mailboxes, semaphores, and shared interrupts. This patch provides a driver for HSP, and hooks it into the mailbox API. Currently, only doorbells are supported. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * sandbox: gpio: doc: Fix parameter documentationmario.six@gdsys.cc2016-06-191-6/+10
| | | | | | | | | | | | | | | | | | | | The documentation of parameters in arch/sandbox/include/asm/gpio.h is either missing or faulty. This patch corrects the documentation. Signed-off-by: Mario Six <mario.six@gdsys.cc> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: uniphier: reserve memory for DRAM PHY training on PH1-LD20Masahiro Yamada2016-06-203-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM PHY layer on PH1-LD20 is able to calibrate PHY parameters periodically. This compensates for the voltage and temperature deviation and improves the PHY parameter adjustment. Instead, it requires 64 byte scratch memory in each DRAM channel for the dynamic training. The memory regions must be reserved in DT before jumping to the kernel. The scratch area can be anywhere in each DRAM channel, but the DRAM init code in SPL currently assigns it at the end of each channel. So, it makes sense to reserve the regions on run-time by U-Boot instead of statically embedding it in the DT in Linux. Anyway, a boot-loader should know much more about memory initialization than the kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: move CONFIG_ARMV8_MULTIENTRY to KconfigMasahiro Yamada2016-06-201-0/+1
| | | | | | | | | | | | I just did not notice this option had an entry in Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: introduce CONFIG_ARM_UNIPHIER_{32, 64}BITMasahiro Yamada2016-06-201-8/+15
|/ | | | | | | This will make it easier to select config options specific to particular ARM processor generation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-06-183-4/+117
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| * ARM: socfpga: Sort Kconfig entriesMarek Vasut2016-06-081-4/+4
| | | | | | | | | | | | | | | | Just sort the board entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * ARM: socfpga: add support for IS1 boardPavel Machek2016-06-083-0/+113
| | | | | | | | | | | | | | | | This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-06-185-10/+15
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
| * | usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash2016-06-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | armv8/ls2080: Remove workaround for erratum A008751Sriram Dash2016-06-131-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This errata a008751 is applied on Soc specific file currently.This will be moved to a file where all the errata implementation will take place for usb for fsl. This patch removes the errata workaround from soc specific file for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | arm64: fsl-layerscape: add get_svr and IS_SVR_REV helperSriram Dash2016-06-134-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | | arm: Fix setjmpAlexander Graf2016-06-171-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The setjmp/longjmp implementation did not work on thumb1 implementations because it used instruction encodings that don't exist on thumb1 yet. This patch limits itself to thumb1 instruction set for 32bit arm and removes a superfluous printf along the way. Signed-off-by: Alexander Graf <agraf@suse.de>
* | | arm, am335x: siemens: enable DM/DTS supportHeiko Schocher2016-06-177-2/+1554
| | | | | | | | | | | | | | | | | | enable basic DM/DTS support for the siemens am335x based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | ARM: dts: AM572x-IDK Initial SupportSchuyler Patton2016-06-133-1/+393
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial DTS support for AM572-IDK evm. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | board: am57xx: Rename TARGET_BEAGLE_X15 as TARGET_AM57XX_EVMLokesh Vutla2016-06-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | board/am57xx supports all boards based on am57xx. Rename the taget as TARGET_AM57XX_EVM. Fixes: 74cc8b097d9af ("board: ti: beagle_x15: Rename to indicate support for TI am57xx evms") Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-1315-0/+1787
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* | | board: arm:: Add support for Broadcom BCM23550Steve Rae2016-06-1314-0/+1963
| | | | | | | | | | | | | | | | | | Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-arcTom Rini2016-06-132-21/+84
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| * | | arc: Update data accessors with use of memory barriersAlexey Brodkin2016-06-131-16/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory barriers are proven to be a requirement for both compiler and real hardware to properly serialize access to critical data. For example if CPU or data bus it uses may do reordering of data accesses absence of memory barriers might easily lead to very subtle and hard to debug data corruptions. This implementation was heavily borrowed from up to date Linux kernel. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc/cache: Flush & invalidate all caches right before enabling IOCAlexey Brodkin2016-06-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to ARC HS databook it is required to flush and disable caches prior programming IOC registers. Otherwise ongoing coherent memory operations may not observe the coherency protocols as expected. But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache) we're doing our best flushing and invalidating it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc/cache: really do invalidate_dcache_all() even if IOC existsAlexey Brodkin2016-06-131-5/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | invalidate_dcache_all() could be used in different use-cases and what is especially important most of those cases won't be related to DMAed data to or from peripherals, i.e. we'll be doing invalidation of data used purely by CPU cores. Given that IOC engine only snoops data that goes through DMA we need to care ourselves about data used only by CPU cores and so remove dependency on IOC from invalidate_dcache_all() and always do real invalidation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-1319-31/+1674
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| * | | ARM: at91: Fix PMC bit definitionsMarek Vasut2016-06-121-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing parenthesis around the variable into the macro. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | ARM: at91: sama5: Extend boot device autodetectionMarek Vasut2016-06-124-21/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the boot device autodetection from SAMA5D2 only to the entire SAMA5Dx family of microcontrollers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [minor compile fix for SAMA5D2] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
| * | | arm: at91: Add support for gurnardAndre Renaud2016-06-122-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is based on Snapper 9G45 which has an Atmel AT91SAM9G45 chip and 128MB of SDRAM. It includes a small LCD, 2xUSB host, SD card, Ethernet and two UARTs. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [apply CONFIG_BOOTDELAY transition] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
| * | | at91: Add driver-model GPIO devices for AT91SAM9G45Simon Glass2016-06-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add these definitions so that GPIOs can be used with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | arm: at91: Add a header file for the real-time clockAndre Renaud2016-06-121-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add register definitions for the AT91 RTC so that this can potentially be used in U-Boot. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
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