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* common: bootm: check return value of strict_strtoulPeng Fan2015-12-051-1/+4
| | | | | | | | | | | | | | Before continue, check return value of strict_strtoul. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of http://git.denx.de/u-boot-sparcTom Rini2015-12-0426-964/+551
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| * sparc: Remove non-generic board init files: board.c, time.cFrancois Retief2015-12-039-662/+7
| | | | | | | | | | | | | | Remove the board.c and time.c files and all associated non-generic board initialization code. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: leon3: Added busy wait function, made wait_ms() work when IRQ is disabledDaniel Hellstrom2015-12-031-2/+30
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: leon3: Added CPU count and frequency detection.Daniel Hellstrom2015-12-032-1/+58
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: Removed USB stop from linux bootm, arch-independent bootm stop USBDaniel Hellstrom2015-12-031-8/+0
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: Add CONFIG_DISPLAY_BOARDINFO variable to all LEON boardsFrancois Retief2015-12-032-0/+20
| | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Update PROM initialization code for generic boardFrancois Retief2015-12-034-28/+32
| | | | | | | | | | | | | | | | | | | | Fixed the prom_relocate() function in start.S file by reserving memory in the board_init_f sequence and saving the offset to the __prom_start_reloc variable. This value is used as the destination when relocating the PROM. Add the prom_init() function to the end of the board_init_r sequence. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Update cpu_init.c to use generic timer infrastructureFrancois Retief2015-12-035-74/+104
| | | | | | | | | | | | | | | | | | | | | | Introduce the CONFIG_SYS_TIMER_* macros in include/asm/config.h to make use of the generic timer infrastructure in lib/time.c. Created a timer_init() function to initialize the timer hardware and update the #ifdef in board_init_f to allow this function to be called during the start-up sequence. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: leon2: Updates for generic board initializationFrancois Retief2015-12-032-75/+107
| | | | | | | | | | | | | | | | | | | | Reworked the LEON2 start.S code to call board_init_f function at startup. Also implemented the relocate_code function in assembly to relocate the monitor and setup the stack pointer before calling relocated board_init_r. Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON2 boards. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: leon3: Updates for generic board initializationFrancois Retief2015-12-032-116/+143
| | | | | | | | | | | | | | | | | | | | Reworked the LEON3 start.S code to call board_init_f function at startup. Also implemented the relocate_code function in assembly to relocate the monitor and setup the stack pointer before calling relocated board_init_r. Add the CONFIG_SYS_GENERIC_BOARD variable to all the LEON3 boards. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: leon3: Clear all unused GPTIMER registers.Daniel Hellstrom2015-12-031-1/+9
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: leon3: Move ambapp_bus_init() call to arch_cpu_init() functionFrancois Retief2015-12-032-5/+6
| | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: leon3: Move snoop detection from startup.S to arch_cpu_init()Francois Retief2015-12-034-21/+21
| | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Initial ground work for generic board initializationFrancois Retief2015-12-038-25/+41
| | | | | | | | | | | | | | Initial ground work in preperation for generic board initialization code for the SPARC architecture. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Fix whitespace in cpu/leon2/cpu_init.cFrancois Retief2015-12-031-5/+5
| | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: leon3: Updated serial driver to use CONFIG_CONS_INDEXFrancois Retief2015-12-031-0/+5
| | | | | | | | | | | | | | Updated the LEON3 serial driver to make use of the CONFIG_CONS_INDEX option to select which serial port the console will use. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Serial baud rate register support multiple buses with different frequencyDaniel Hellstrom2015-12-033-4/+16
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: leon3: Clear GD_FLAG_SERIAL_READY flag on AMBA failureFrancois Retief2015-12-031-0/+1
| | | | | | | | | | | | | | | | Clear the GD_FLG_SERIAL_READY flag on AMBA P&P lookup failure so that the panic function can use DEBUG_UART driver. drivers/serial/serial.c set this flag before calling this function, preventing DEBUG_UART code from running. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Added function that checks if IRQ is on or offDaniel Hellstrom2015-12-032-0/+10
| | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * sparc: Remove version_string variable from start.S fileFrancois Retief2015-12-032-21/+6
| | | | | | | | | | | | | | Remove the version_string variable from start.S file. A weak variable is also set in the cmd_version.c file. No need for architecture override. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * sparc: Move SYS_SPARC_NWINDOWS to KconfigFrancois Retief2015-12-032-0/+14
| | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-044-3/+18
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| * ARM: mxs: fix VDDD brownout settingMichael Heimpold2015-12-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, the desired brownout is at 1.0V. However, this setting cannot be realized by hardware since we have only 3 bits to represent the voltage difference from the target value. Target value is 1500 mV, brownout target is 1000 mV, voltage steps are 25 mV. Register content calculation: (1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14 Register takes only 3 bits, that is 0x4. But 0x4 * 25 [mV] = 100 [mV], that means that actual brownout level is 1500 [mV] - 100 [mV] = 1.4 V. Minimum possible BO level is 1500 [mV] - 0x7 * 25 [mV] = 1315 [mV]. So lets use this value as desired BO value (which is also the same as FSL bootlets use). Signed-off-by: Michael Heimpold <mhei@heimpold.de> Cc: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * mx6: clock: Modify GPMI clock to support mx6sxYe.Li2015-11-251-0/+12
| | | | | | | | | | | | | | On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <B37916@freescale.com>
| * iomux-v3: Take MX6D in consideration for imx_iomux_v3_setup_pad()Otavio Salvador2015-11-251-1/+1
| | | | | | | | | | | | | | | | We should also take MX6D option in consideration when defining imx_iomux_v3_setup_pad(). Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * cgtqmx6eval: Add SPL supportOtavio Salvador2015-11-251-0/+3
| | | | | | | | | | | | | | | | | | Congatec has several MX6 boards based on quad, dual, dual-lite and solo. Add SPL support so that all the variants can be supported Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Revert "rockchip: Reconfigure the malloc based to point to system memory"Sjoerd Simons2015-12-011-7/+0
| | | | | | | | | | | | | | | | | | | | | | This patch was merged shortly before the v2015.10 as a minimal fix for booting on rockchip. Now that the patch series from Hans to do the relocation in generic code has been merged it can be dropped. This reverts commit b1f492ca9e0c090209824ff36456d4f131843190. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: move SYS_MALLOC_SIMPLE to mach-rockchip KconfigAriel D'Alessandro2015-12-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1eb0c03c2198a7ec9de456b83dacdc4831b96cbf added SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is evaluated. Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h board configs are now incorrect because CONFIG_SPL_BUILD is enabled so CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE instead of SYS_MALLOC_SIMPLE. This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig option by default in rockchip-mach. Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: Add max spl size & spl header configsJeffy Chen2015-12-013-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
* | rockchip: Add basic support for evb-rk3036 boardhuang lin2015-12-013-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
* | rockchip: rk3036: Add core Soc start-up codehuang lin2015-12-017-2/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288
* | rockchip: add rk3036 sdram driverhuang lin2015-12-013-0/+1107
| | | | | | | | | | | | | | add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add early uart driverhuang lin2015-12-013-0/+108
| | | | | | | | | | | | | | | | add early uart driver so we can print debug message in SPL stage Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin2015-12-011-0/+1
| | | | | | | | | | | | | | | | rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
* | rockchip: rk3036: Add a simple syscon driverhuang lin2015-12-012-1/+22
| | | | | | | | | | | | | | Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add Soc reset driverhuang lin2015-12-012-0/+55
| | | | | | | | | | | | | | | | We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add header files for GRFhuang lin2015-12-011-0/+493
| | | | | | | | | | | | | | GRF is the gereral register file. Add header files with register definitions. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rk3036: Add clock driverhuang lin2015-12-011-0/+168
| | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs, peripheral clocks and mmc clocks on RK3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: Bring in RK3036 device tree file includes and bindingshuang lin2015-12-011-0/+427
| | | | | | | | | | | | | | | | | | Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add config decide whether to build common.chuang lin2015-12-011-1/+1
| | | | | | | | | | | | | | | | some rockchips soc will not use uclass in SPL stage, so define config to decide whether to build common.c Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: rename board-spl.c to rk3288-board-spl.chuang lin2015-12-012-1/+1
| | | | | | | | | | | | | | | | since different rockchip soc need different spl file, so rename board-spl.c. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfighuang lin2015-12-012-3/+3
| | | | | | | | | | | | | | | | | | since different rockchip SOC have different size of SRAM, So the size SYS_MALLOC_F_LEN may different, so move this config to rk3288 own Kconfig Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | rockchip: add timer driverhuang lin2015-12-014-19/+73
| | | | | | | | | | | | | | | | some rockchip soc will not include lib/timer.c in SPL stage, so implement timer driver for some soc can use us delay function in SPL. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | dm: pci: Disable PCI compatibility functions by defaultSimon Glass2015-12-012-0/+4
| | | | | | | | | | | | | | | | | | We eventually need to drop the compatibility functions for driver model. As a first step, create a configuration option to enable them and hide them when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | dm: tegra: pci: Convert tegra boards to driver model for PCISimon Glass2015-12-012-0/+5
| | | | | | | | | | | | | | | | | | Adjust the Tegra PCI driver to support driver model and move all boards over at the same time. This can make use of some generic driver model code, such as the range-decoding logic. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* | ARM: tegra: refactor common Kconfig optionsStephen Warren2015-12-011-18/+20
| | | | | | | | | | | | | | | | | | | | | | This makes it easier to select common options in a single place, rather than having to add them separately for different SoCs or architectures. The lists of select statements are now also sorted for easy searching. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: tsc: Move tsc_timer.c to drivers/timerBin Meng2015-12-012-390/+0
| | | | | | | | | | | | | | | | To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: tsc: Remove legacy timer codesBin Meng2015-12-015-80/+0
| | | | | | | | | | | | | | | | | | | | | | Now that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver. Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option, as it is not needed with driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Convert to use driver model timerBin Meng2015-12-0118-39/+32
| | | | | | | | | | | | | | Convert all x86 boards to use driver model tsc timer. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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