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* powerpc/corenet2: Add SerDes for corenet2York Sun2012-10-227-9/+281
| | | | | | | | | | | | | | | | | | | | | Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2York Sun2012-10-221-5/+93
| | | | | | | | Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/e6500: Move QCSP registers for QMan v3York Sun2012-10-221-1/+12
| | | | | | | | The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: expand SERDES reference clock select bitYork Sun2012-10-221-1/+2
| | | | | | | | | | | | | Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2York Sun2012-10-222-26/+148
| | | | | | | | | | | | | | | | | | Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: check number of coresYork Sun2012-10-221-0/+5
| | | | | | | | Panic if the number of cores is more than CONFIG_MAX_CPUS because it will surely overflow gd structure. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2York Sun2012-10-222-1/+10
| | | | | | | | Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500York Sun2012-10-225-11/+163
| | | | | | | | | | | | | Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Introduce new macros to add and delete TLB entriesYork Sun2012-10-221-179/+130
| | | | | | | These assembly macros simplify codes to add and delete temporary TLB entries. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: Add determining and report IFC frequencyKumar Gala2012-10-222-0/+15
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/DPAA: Fix compiling errorYork Sun2012-10-221-2/+0
| | | | | | | | FSL_HW_PORTAL_PME is used even when CONFIG_SYS_DPAA_PME is not defined. Remove the #ifdef. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: Add P5040 processor supportTimur Tabi2012-10-2210-0/+372
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p5040ds: add per pci endpoint liodn offset listLaurentiu Tudor2012-10-221-0/+52
| | | | | | | | | | | | | | | | | | | | Add a new device tree property named "fsl,liodn-offset-list" holding a list of per pci endpoint permitted liodn offsets. This property is useful in virtualization scenarios that implement per pci endpoint partitioning. The final liodn of a partitioned pci endpoint is calculated by the hardware, by adding these offsets to pci controller's base liodn, stored in the "fsl,liodn" property of its node. The liodn offsets are interleaved to get better cache utilization. As an example, given 3 pci controllers, the following liodns are generated for the pci endpoints: pci0: 193 256 259 262 265 268 271 274 277 pci1: 194 257 260 263 266 269 272 275 278 pci2: 195 258 261 264 267 270 273 276 279 Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: define SRIO LIODN functions only if SRIO is definedTimur Tabi2012-10-222-1/+11
| | | | | | | | The P5040 does not have SRIO support, so there are no SRIO LIODNs. Therefore, the functions that set the SRIO LIODNs should not be compiled. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNsLaurentiu Tudor2012-10-222-1/+8
| | | | | | | | | | | | The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: fix Unicode characters in release.STimur Tabi2012-10-221-12/+12
| | | | | | | | Commit 709389b6 unintentionally used the Unicode version of the apostrophy. Replace it with the normal ASCII version. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/srio: Workaround for srio erratrm a004034Liu Gang2012-10-223-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum: A-004034 Affects: SRIO Description: During port initialization, the SRIO port performs lane synchronization (detecting valid symbols on a lane) and lane alignment (coordinating multiple lanes to receive valid data across lanes). Internal errors in lane synchronization and lane alignment may cause failure to achieve link initialization at the configured port width. An SRIO port configured as a 4x port may see one of these scenarios: 1. One or more lanes fails to achieve lane synchronization. Depending on which lanes fail, this may result in downtraining from 4x to 1x on lane 0, 4x to 1x on lane R (redundant lane). 2. The link may fail to achieve lane alignment as a 4x, even though all 4 lanes achieve lane synchronization, and downtrain to a 1x. An SRIO port configured as a 1x port may fail to complete port initialization (PnESCSR[PU] never deasserts) because of scenario 1. Impact: SRIO port may downtrain to 1x, or may fail to complete link initialization. Once a port completes link initialization successfully, it will operate normally. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8xxx: Fix USB device-tree fixupramneek mehresh2012-10-221-16/+34
| | | | | | | | | | | | | Fix usb device-tree fixup: - wrong modification of dr_mode and phy_type when "usb1" is not mentioned inside hwconfig string; now allows hwconfig strings like: "usb2:dr_mode=host,phy_type=ulpi" - add warning message for using usb_dr_mode and usb_phy_type env variables (if either is used) Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* P4080/esdhc: make the P4080 ESDHC13 errata workaround conditionalZang Roy-R619112012-10-223-7/+10
| | | | | | | | | | P4080 Rev3.0 fixes ESDHC13 errata, so update the code to make the workaround conditional. In formal release document, the errata number should be ESDHC13 instead of ESDHC136. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc mpc85xx: Only clear TSR:WIS in watchdog_reset.Mark Marshall2012-10-221-4/+1
| | | | | | | | | | | | We should only write TSR_WIS to the SPRN_TSR register in reset_85xx_watchdog. The old code would cause the timer interrupt to be acknowledged when the watchdog was reset, and we would then get no more timer interrupts. This bug would affect all mpc85xx boards that have the watchdog enabled. Signed-off-by: Mark Marshall <Mark.Marshall@omicron.at> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mpc85xx: make gpio_direction_output respect valueChris Packham2012-10-221-1/+4
| | | | | | | | | | | | | | Users of familiar with the Linux gpiolib API expect that value parameter to gpio_direction_output reflects the initial state of the output pin. gpio_direction_output was always driving the output low, now it drives it high or low according to the value provided. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Cc: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-10-1913-3337/+23
|\ | | | | | | | | | | | | Conflicts: drivers/serial/serial_lh7a40x.c Signed-off-by: Tom Rini <trini@ti.com>
| * arm: fdt: Relocate fdt along with other dataSimon Glass2012-10-191-0/+22
| | | | | | | | | | | | | | | | | | | | | | Rather than leave the fdt down next to the code/data, we really should relocate it along with everything else. For CONFIG_OF_EMBED this happens automatically, but for CONFIG_OF_SEPARATE it does not. Add code to copy the fdt and point to the new copy after relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
| * dm: Move s3c24xx USB driver to a proper placeMarek Vasut2012-10-184-2240/+0
| | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: David Müller <d.mueller@elsoft.ch> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
| * dm: wdt: arm: Move tnetv107x into drivers/watchdog/Marek Vasut2012-10-182-181/+1
| | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Oliver Brown <obrown@adventnetworks.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de>
| * Remove lh7a40x cpu and serial driverAlbert ARIBAUD2012-10-166-916/+0
| | | | | | | | | | | | | | Since commit 957731ed (ARM: remove broken "lpd7a40x" boards), lh7a40x cpu and serial driver have become unused. Remove them. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | sandbox: Change global data baudrate to intSimon Glass2012-10-191-1/+1
| | | | | | | | | | | | | | This doesn't need to be a long, so change it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | x86: Change global data baudrate to intSimon Glass2012-10-191-1/+1
| | | | | | | | | | | | | | This doesn't need to be a long, so change it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | nds32: Change global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | | | | | This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | mips: Change global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | | | | | This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | blackfin: Change global data baudrate to intSimon Glass2012-10-193-3/+3
| | | | | | | | | | | | | | | | | | This doesn't need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | arm: Change global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | | | | | This does not need to be a long, so change it. Also adjust bi_baudrate to be unsigned. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | sparc: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | powerpc: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | openrisc: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | nios2: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | microblaze: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | m68k: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | avr32: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Tom Rini <trini@ti.com>
* | sh: Change bi_baudrate and global data baudrate to intSimon Glass2012-10-192-2/+2
| | | | | | | | | | | | | | These don't need to be longs, so change them. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com>
* | m68k: Fix unused variable in board.cMarek Vasut2012-10-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | The following warning was produced, fix it: board.c: In function 'board_init_r': board.c:390:8: warning: unused variable 's' [-Wunused-variable] Signed-off-by: Marek Vasut <marex@denx.de> Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com> Cc: Jason Jin <jason.jin@freescale.com>
* | m68k: Fix unused variable warning in speed.cMarek Vasut2012-10-191-2/+7
| | | | | | | | | | | | | | | | | | | | | | The following warning was produced, fix it: speed.c: In function 'get_clocks': speed.c:94:15: warning: variable 'bPci' set but not used [-Wunused-but-set-variable] Signed-off-by: Marek Vasut <marex@denx.de> Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com> Cc: Jason Jin <jason.jin@freescale.com>
* | m68k: Fix unused variable warningMarek Vasut2012-10-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | The fbcs variable was unused, producing the following warning: cpu_init.c: In function 'cpu_init_f': cpu_init.c:52:10: warning: unused variable 'fbcs' [-Wunused-variable] Signed-off-by: Marek Vasut <marex@denx.de> Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com> Cc: Jason Jin <jason.jin@freescale.com>
* | m68k: Fix wrong assembler instruction in start.SMarek Vasut2012-10-194-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The jmp _fault generated the following error message, thus change it to bra _fault: start.S: Assembler messages: start.S:310: Error: Conversion of PC relative displacement to absolute Signed-off-by: Marek Vasut <marex@denx.de> Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com> Cc: Jason Jin <jason.jin@freescale.com>
* | m68k: Fix relocation errors in start.SPhilippe De Muyter2012-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the environment sectors in the flash are big, one get those errors : mcf547x_8x/start.S:173: relocation truncated to fit: R_68K_PC16 against symbol `cpu_init_f' defined in .text section in libmcf547x_8x.a(cpu_init.o) mcf547x_8x/start.S:174: relocation truncated to fit: R_68K_PC16 against symbol `board_init_f' defined in .text section in libm68k.a(board.o) Fix that. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Cc: "Jin Zhengxiong-R64188" <R64188@freescale.com> Cc: Jason Jin <jason.jin@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2012-10-1716-60/+884
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| * | MIPS: add board qemu-mips64 supportZhi-zhou Zhang2012-10-167-0/+802
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both big-endian and little-endian are tested with below commands: Rom version: (Default, Now we config it as rom version) qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic Ram version: qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: add support for 64 bit addressingZhi-zhou Zhang2012-10-163-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for upcoming mips64 support. This patch add mips64 address support. Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com> [daniel.schwierzeck@gmail.com: prefer _MIPS_SZLONG in posix_types.h to fix some warnings] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | MIPS: don't use camel-case styleZhi-zhou Zhang2012-10-166-59/+59
| |/ | | | | | | | | | | Replace camel-case style with upper-case style globally. Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
* | split AU1X00 specific code from cmd_ide.cPavel Herrmann2012-10-172-1/+33
| | | | | | | | | | | | move special case of ide_swap_read() for AU1X00 SoC into SoC-specific directory. Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
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