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* MX28: use a clear name for DDR2 initializationOtavio Salvador2012-09-011-6/+6
| | | | | | | | | The mx28 prefix has been added to the initialization data and function so it is clear by which SoC it is used as i.MX233 will have a specific one. While on that, we also change it to static. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
* MX28: extend print_cpuinfo() to use chip informationOtavio Salvador2012-09-012-2/+40
| | | | | | | The information now is gathered from HW_DIGCTL_CHIPID register and includes the chip modem and revision on the output. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* imx: Use a clear identification of an unidentified CPU typeOtavio Salvador2012-09-011-2/+2
| | | | | | | | | | In case an unidentified CPU type is detected it now returns i.MX??, in a const char. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* Enable the EMAC clock in at91_macb_hw_init().Markus Hubig2012-09-011-0/+4
| | | | | | Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* arm : Atmel : add at91sam9x5ek board supportBo Shen2012-09-017-2/+508
| | | | | | | | | | | | Add at91sam9x5ek board support, this board support the following SoCs AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35 Using at91sam9x5ek_nandflash to configure for the board Now only supports NAND with software ECC boot up Signed-off-by: Bo Shen <voice.shen@atmel.com> [move MAINTAINERS entry to right place] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* DaVinci DA8xx: fix set_cpu_clk_info()Laurence Withers2012-09-011-9/+14
| | | | | | | | | | | | | | | | | | | | | | For the DA8xx family of SoCs, the set_cpu_clk_info() function was not initialising the DSP frequency, leading to 'bdinfo' command output such as: [...snip...] ARM frequency = 300 MHz DSP frequency = -536870913 MHz DDR frequency = 300 MHz This commit provides a separate implementation of set_cpu_clk_info() for the DA8xx SoCs that initialises the DSP frequency to zero (since currently the DSP is not enabled by U-Boot on any DA8xx platform). The separate implementation is justified because there is no common code between DA8xx and the other SoC families. It is now much easier to understand the flow of the two separate functions. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Hadli, Manjunath <manjunath.hadli@ti.com> Cc: Heiko Schocher <hs@denx.de>
* DaVinci DA8xx: replace magic number for DDR speedLaurence Withers2012-09-012-1/+4
| | | | | | | | | | Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
* DaVinci DA850: UART2 clock ID comes from ASYNC3Laurence Withers2012-09-011-1/+3
| | | | | | | | | | On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
* DaVinci DA8xx: tidy up clock ID definitionLaurence Withers2012-09-011-16/+40
| | | | | | | | | | | Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
* dm: Move OMAP GPIO driver to drivers/gpio/Marek Vasut2012-09-012-246/+0
| | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework pinmux functionsTom Rini2012-09-013-53/+33
| | | | | | | | | | - Move definition of the EEPROM contents to <asm/arch/sys_proto.h> - Make some defines a little less generic now. - Pinmux must be done by done by SPL now. - Create 3 pinmux functions, uart0, i2c0 and board. - Add pinmux specific to Starter Kit EVM for MMC now. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx evm: Add CONFIG_CMD_EEPROM and relatedTom Rini2012-09-011-9/+4
| | | | | | | am33xx boards have at least one eeprom and in the case of beaglebones with capes, more. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add support for TI AM335x StarterKit EVMTom Rini2012-09-012-2/+40
| | | | | | | | | | - Board requires gpio0 #7 to be set to power DDR3. - Board uses DDR3, add a way to determine which DDR type to call config_ddr with. - Both of the above require filling in the header structure early, move it into the data section. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Remove board/ti/am335x/evm.cTom Rini2012-09-011-0/+173
| | | | | | | | | The intention has always been (and boards are to support) an i2c EEPROM that will identify what hardware they are, allowing a single binary to support multiple boards. As such, remove the 'evm.c' file as there is nothing EVM centric in it currently, only SoC peripheral configuration. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and supportTom Rini2012-09-013-0/+60
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_ddr to make DDR3 support easier.Tom Rini2012-09-011-14/+23
| | | | | | | | In order to support DDR3 as well as DDR2, we need to perform the same init sequence, but with different values. So change config_ddr() to toggle setting pointers/etc for what DDR2 wants, and then calling. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move some variables in emif4.c, mark them static.Tom Rini2012-09-011-4/+3
| | | | | | We need vtpreg and ddrctrl but no longer need a second ddrregs. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Correct and clean up ddr_regs structTom Rini2012-09-013-34/+20
| | | | | | | | | | | | | | The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Do not touch 'ratio1' fieldsTom Rini2012-09-013-35/+7
| | | | | | | | | The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework config_io_ctrl slightlyTom Rini2012-09-013-27/+8
| | | | | | | | | This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Use emif_regs struct for storing initialization valuesTom Rini2012-09-013-78/+31
| | | | | | | Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Turn a number of 'int' functions to 'void'Tom Rini2012-09-013-42/+15
| | | | | | | | A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Document what we're doing with ddrctrl->ddrckectrlTom Rini2012-09-012-4/+3
| | | | | | | | | - Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: Tom Rini <trini@ti.com>
* am335x: ddr_defs: Update EMIF parametersVaibhav Bedia2012-09-011-5/+5
| | | | | | | | | | | | | | | | | EMIF parameters are calculated based on the AC timing parameters from the SDRAM datasheet and the DDR frequency. Current values for these paramters in AM335x U-Boot code, though reliable, are not fully optimal. The most optimal settings can be derived based on the guidelines published at [1]. A pre-computed set of values with the most optimum settings for AM335x EVM and BeagleBone can be found at [2]. [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips [2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335x Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Clean up unused DDR defines, prefix more with 'DDR2'Tom Rini2012-09-012-43/+35
| | | | | | | - Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Move the call to ddr_pll_config, make it take the frequencyTom Rini2012-09-013-3/+5
| | | | | | | | Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Pass to config_ddr the type of memory that is connectedTom Rini2012-09-014-20/+31
| | | | | | | | | We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Make config_cmd_ctrl / config_ddr_data take const structsTom Rini2012-09-013-61/+48
| | | | | | | | | Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Rework DDR2 EMIF initalization slightlyTom Rini2012-09-011-15/+2
| | | | | | | With the previous bugfix we now don't need to set two different REF_CTRL values and instead set the final value. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Bugfix to config_sdram()Tom Rini2012-09-011-2/+1
| | | | | | | When we change SDRAM_CONFIG this triggers a refresh based on all of the parameters that we have programmed so we must do this last. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Remove extra check in enable_ddr_clocksTom Rini2012-09-011-5/+0
| | | | | | | We do not need to check for EMIF_GCLK and L3_GCLK being active. This was a hold-over from bringup and no longer required. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Convert to using <asm/emif.h> to describe the EMIFTom Rini2012-09-012-41/+15
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Remove DMM_BASE defineTom Rini2012-09-011-1/+0
| | | | | | The am33xx does not have a DMM, so don't define the base. Signed-off-by: Tom Rini <trini@ti.com>
* am33xx: Enable gpio0 clockTom Rini2012-09-011-0/+4
| | | | Signed-off-by: Tom Rini <trini@ti.com>
* OMAP3: mem: Add Numonyx OneNAND 200MHz timing informationJavier Martinez Canillas2012-09-011-0/+29
| | | | Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org>
* am33xx: pin mux defintions for CPSW switchChandan Nath2012-09-011-0/+2
| | | | | | | | | This patch adds pin mux settings for CPSW switch found on TI AM335X based boards (MII and RGMII modes). Signed-off-by: Chandan Nath <chandan.nath@ti.com> [Ilya: split pinmux into separate patch] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* am33xx: CPSW init and definitionsChandan Nath2012-09-013-1/+23
| | | | | | | | | This patch adds platform-specific initialization for CPSW switch on TI AM33XX SoCs. Signed-off-by: Chandan Nath <chandan.nath@ti.com> [Ilya: split init out of original patch] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* arm/davinci/da850: add uart0 pinmuxMikhail Kshevetskiy2012-09-013-0/+7
| | | | | Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Tested-by: Sughosh Ganu <urwithsughosh@gmail.com>
* arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138Mikhail Kshevetskiy2012-09-012-7/+20
| | | | | | | | | follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of OMAP-L138 DSP+ARM Processor Technical Reference Manual Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com> Acked-by: Christian Riesch <christian.riesch@omicron.at> Tested-by: Christian Riesch <christian.riesch@omicron.at>
* Revert "arm: armv7: add compile option -mno-unaligned-access if available"Albert ARIBAUD2012-09-011-2/+0
| | | | | | This reverts commit 5347560f5427bcdd48a563b62180481606ac8044, which was applied only to get release 2012.07 functional on as many ARM targets as possible despite mis-aligned accesses.
* omap: am335x_evm: enable i2c1 channelSteve Sakoman2012-09-011-0/+5
| | | | | | | This patch sets up pinmux, enables fclk, and defines CONFIG_I2C_MULTI_BUS Signed-off-by: Steve Sakoman <steve@sakoman.com>
* da850/omap-l138: Add support to read u-boot image from MMC/SDLad, Prabhakar2012-09-011-0/+5
| | | | | | | | | | | | | | | DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will be in SPI flash and U-Boot image will be in MMC/SD card. SPL will do the low level initialization and then loads the u-boot image from MMC/SD card. Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138 configuration file to enable this feature. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* arm, davinci: perform check for initializing global data and serial initLad, Prabhakar2012-09-011-6/+9
| | | | | | | | | | | initialize baudrate, flags, data and serial initialization, only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* da850/omap-l138: Add MMC support for DA850/OMAP-L138Lad, Prabhakar2012-09-013-0/+15
| | | | | | | | | This patch adds support for MMC/SD on DA850/OMAP-L138. Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
* omap: am33xx: enable gpio supportSteve Sakoman2012-09-015-1/+75
| | | | | | | | | | | This patch uses the code in omap-common to support gpio modules 1-3 on am33xx based boards. It adds base address and register definitions, enables clocks to the modules, and enables building the common gpio code for CONFIG_AM33XX as well as CONFIG_OMAP Signed-off-by: Steve Sakoman <steve@sakoman.com>
* Consolidate bootcount code into drivers/bootcountStefan Roese2012-09-018-218/+1
| | | | | | | | | | | | | | | | | | | This patch moves all bootcount implementations into a common directory: drivers/bootcount. The generic bootcount driver is now usable not only by powerpc platforms, but others as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Valentin Longchamp <valentin.longchamp@keymile.com> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Manfred Rudigier <manfred.rudigier@omicron.at> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de> Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com> Tested-by: Christian Riesch <christian.riesch@omicron.at> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* mpc5xxx: add GPIO port configurationAnatolij Gustschin2012-09-011-0/+14
| | | | | | | Add posibility for board specifig GPIO configurations using various CONFIG_SYS_ macros. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* sh: tmu: Removed arch/sh/include/asm/clk.hNobuhiro Iwamatsu2012-08-212-31/+0
| | | | | | | | | asm/clk.h was included get_peripheral_clk_rate function. But this is not used from anywhere. This removed asm/clk.h, and deleted include line from arch/sh/lib/time.c Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sh: tmu: Changed switch statement to shift operationNobuhiro Iwamatsu2012-08-211-30/+18
| | | | | | | | | Calculation of the bit position using switch statement can substitute shift operation using ffs. And removed unsed macro and variable. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sh: tmu: Changed TMU driver using array of structuresNobuhiro Iwamatsu2012-08-2114-151/+26
| | | | | | | | | This changed into access using array of structure from access to the register using the definition of the register by macro. And removed white space. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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