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* DTS: Add dts support for SMDK5420Rajeshwari Birje2013-12-303-190/+272
| | | | | | | | | | | This patch adds dts support for SMDK5420. exynos5.dtsi created is a common file which has the nodes common to both 5420 and 5250. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add support for 5420 in pinmux and gpioRajeshwari Birje2013-12-303-16/+390
| | | | | | | | | | Adds code in pinmux and gpio framework to support Exynos5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add DDR3 initialization for 5420Rajeshwari Birje2013-12-305-58/+484
| | | | | | | | | This patch intends to add DDR3 initialization code for Exynos5420. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add clock initialization for 5420Rajeshwari Birje2013-12-306-202/+1679
| | | | | | | | | | This patch adds code for clock initialization and clock settings of various IP's and controllers, required for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5420: Add dmc and phy_control register structureRajeshwari Birje2013-12-301-0/+167
| | | | | | | | Add dmc and phy_control register structure for 5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5420: Add power register structure.Rajeshwari Birje2013-12-301-0/+837
| | | | | | | | Add structure for power register for Exynos5420 Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos5420: Add base addresses for 5420Rajeshwari Birje2013-12-301-1/+48
| | | | | | | | | | Adds base addresses of various IPs and controllers required for Exynos5420. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Create a common board fileRajeshwari Birje2013-12-301-0/+17
| | | | | | | | | | | Create a common board.c file for all functions which are common across all EXYNOS5 platforms. exynos_init function is provided for platform specific code. Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* ARM: AM43xx: GP_EVM: Add support for DDR3Lokesh Vutla2013-12-185-16/+38
| | | | | | | | | | | | | | | | GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: EPOS_EVM: Add support for LPDDR2Lokesh Vutla2013-12-187-3/+190
| | | | | | | | | | | | | | | AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM33xx+: Update ioregs to pass different valuesLokesh Vutla2013-12-182-9/+23
| | | | | | | | | | | Currently same value is programmed for all ioregs. This is not the case for all SoC's like AM4372. So adding a structure for ioregs and updating in all board files. And also return from config_cmd_ctrl() and config_ddr_data() functions if data is not passed. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [trini: Fixup dxr2, cm_t335, adapt pcm051 rev3] Signed-off-by: Tom Rini <trini@ti.com>
* ARM: AM43xx: clocks: Update DPLL detailsLokesh Vutla2013-12-186-14/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the Multiplier and Dividers value for all DPLLs. Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value returned the MPU DPLL is locked. At different OPPs follwoing are the MPU locked frequencies. OPP50 300MHz OPP100 600MHz OPP120 720MHz OPPTB 800MHz OPPNT 1000MHz According to the latest DM following is the OPP table dependencies: VDD_CORE VDD_MPU OPP50 OPP50 OPP50 OPP100 OPP100 OPP50 OPP100 OPP100 OPP100 OPP120 So at different OPPs of MPU it is safest to lock CORE at OPP_NOM. Following are the DPLL locking frequencies at OPP NOM: Core locks at 1000MHz Per locks at 960MHz LPDDR2 locks at 266MHz DDR3 locks at 400MHz Touching AM33xx files also to get DPLL values specific to board but no functionality difference. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: mux: Update mux dataLokesh Vutla2013-12-181-0/+45
| | | | | | | Updating the mux data for UART, adding data for i2c0 and mmc. And also updating pad_signals structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Update Current Booting devices listLokesh Vutla2013-12-181-3/+10
| | | | | | | Current Booting devices list is different from that of AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Select clk source for Timer2Lokesh Vutla2013-12-181-0/+4
| | | | | | Selecting the Master osc clk as Timer2 clock source. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43XX: board: add support for reading onboard EEPROMSekhar Nori2013-12-181-0/+2
| | | | | | | | Add support for reading onboard EEPROM to enable board detection. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Adapt to ti_armv7_common.h config fileLokesh Vutla2013-12-181-1/+1
| | | | | | | Use ti_armv7_common.h config file to inclde the common configs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: AM43xx: Update the base addresses of modulesLokesh Vutla2013-12-184-13/+15
| | | | | | | PRCM, timer base addresses and offsets are different from AM33xx. Updating the same. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-181-0/+1
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| * ARM: pxa: prevent PXA270 occasional reboot freezesSergei Ianovich2013-12-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum 71 of PXA270M Processor Family Specification Update (April 19, 2010) explains that watchdog reset time is just 8us insead of 10ms in EMTS. If SDRAM is not reset, it causes memory bus congestion and the device hangs. We put SDRAM in selfresh mode before watchdog reset, removing potential freezes. Signed-off-by: Sergei Ianovich <ynvich@gmail.com> CC: Marek Vasut <marex@denx.de>
* | arm: tegra: Fix the CPU complex reset masksAlban Bedel2013-12-181-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swrren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | ARM: tegra: support SKU b1 of Tegra30Alban Bedel2013-12-182-0/+2
| | | | | | | | | | | | | | | | Add the Tegra30 SKU b1 and treat it like other Tegra30 chips. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Reviewed-by: Julian Scheel <julian.scheel@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra114: Do not program CPCON field for PLLXThierry Reding2013-12-181-1/+5
| | | | | | | | | | | | | | | | PLLX no longer has the CPCON field on Tegra114, so do not attempt to program it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Tegra114: Fix PLLX M, N, P init settingsJimmy Zhang2013-12-181-24/+59
|/ | | | | | | | | | | | The M, N and P width have been changed from Tegra30. The maximum value for N is limited to 255. So, the tegra_pll_x_table for Tegra114 should be set accordingly. Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Reviewed-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: OMAP5: clocks: Update MPU settings for OPP_NOMLokesh Vutla2013-12-121-12/+2
| | | | | | | | | | As per the latest 0.6 version of DM for OMAP5430 ES2.0, MPU_GCLK is given as 1000MHz. In order to achieve this DPLL_MPU should be locked at 2000MHz. Fixing the same and cleaning the previously used dpll values. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* ARM: DRA7xx: Change clk divider settingLokesh Vutla2013-12-121-5/+5
| | | | | | | | | Commit "armv7: hw_data: change clock divider setting" updates the setting for m6 divider for 20MHz sys_clk frequency. But missed to update for other sys_clk frequencies. Doing the same. Reported-by: Rajendran, Vinothkumar <vinothr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* arm: omap: abb: add missing includeNikita Kiryanov2013-12-121-0/+1
| | | | | | | | | | | ABB code uses LDELAY but does not include the header that provides its definition. Include the header. Cc: Tom Rini <trini@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Nishanth Menon <nm@ti.com>
* arm: am437: Fix offset for USB registersDan Murphy2013-12-121-2/+2
| | | | | | Fix the offset for the USB clock registers Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: OMAP4: Move TEXT_BASE down to non-HS limitLokesh Vutla2013-12-121-1/+1
| | | | | | | | | | | | | | | With the current scenario SPL size is being overlapped with the public stack and not allowing any OMAP4 device to boot. So the suggestion came up was to move the TEXT_BASE down to non-HS limit. Fixing the same and also moving the SRAM_SCRATCH_SPACE_ADDR up to the end of image downloadable area. Discussion on this can be seen here: https://www.mail-archive.com/u-boot@lists.denx.de/msg127147.html Tested on OMAP4460 PANDA. Reported-by: Chao Xu <caesarxuchao@gmail.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFFTom Rini2013-12-121-0/+8
| | | | | | | Test on Beaglebone white over cpsw, usb ether and SD card (read and write), performance increased, crc32 of data matches. Signed-off-by: Tom Rini <trini@ti.com>
* Revert "ARM: move interrupt_init to before relocation"Albert ARIBAUD2013-12-111-1/+2
| | | | | | | Revert commit 0f5141e9 which causes boards starting in FLASH to try and write to a FLASH location. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-12-1082-480/+6018
|\ | | | | | | | | | | | | | | Conflicts: board/samsung/trats2/trats2.c include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-1079-10441/+865
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * | at91: switch coloured LED to gpio APIAndreas Bießmann2013-12-091-9/+7
| | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | at91: redefine legacy GPIO PIN_BASEAndreas Bießmann2013-12-091-1/+1
| | | | | | | | | | | | | | | | | | | | | In order to get the very same value for legacy pin definitions and new gpio definitions set the legacy PIN_BASE to 0. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | at91: add new gpio pin definitionsAndreas Bießmann2013-12-091-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | This patch define new names for GPIO pins on at91 devices. Follow up patches will convert the whole infrastructure to use these new definitions. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Bo Shen <voice.shen@atmel.com>
| * | arm: keep all sections in ELF fileAlbert ARIBAUD2013-12-076-34/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current LDS files /DISCARD/ a lot of sections when linking ELF files, causing diagnostic tools such as readelf or objdump to produce partial output. Keep all section at link stage, filter only at objcopy time so that .bin remains minimal. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | ARM: align MVBAR on 32 byte boundaryMasahiro Yamada2013-12-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The lower 5 bit of MVBAR is UNK/SBZP. So, Monitor Vector Base Address must be 32-byte aligned. On the other hand, the secure monitor handler does not need 32-byte alignment. This commit moves ".algin 5" directive to the correct place. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: Andre Przywara <andre.przywara@linaro.org>
| * | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-068-12/+130
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| | * | arm: exynos: adds ifdef for spi bootMinkyu Kang2013-12-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix following errors and warnings spl_boot.c: In function 'exynos_spi_copy': spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function) spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function) spl_boot.c: In function 'copy_uboot_to_ram': spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable] spl_boot.c: At top level: spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function] Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
| | * | arm: exynos: remove the unused define.Jaehoon Chung2013-12-051-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These defines didn't use anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | arm: exynos/goni: fix the return type for s5p_mmc_initJaehoon Chung2013-12-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The "int" type is right. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | exynos: spl: Add a custom spi copy functionRajeshwari Shinde2013-12-033-4/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a custom spi_copy funtion to copy u-boot from SF to RAM. This is faster then iROM spi_copy funtion as this runs spi at 50Mhz and also in WORD mode of operation. Changed a printf in pinmux.c to debug just to avoid the compilation error in SPL. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | arm: exynos: fix the align for exynos4_power structureMinkyu Kang2013-12-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | res3 should be 4bytes Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Cc: Dominik Klein <dominik.klein@gmx.com>
| | * | arm: exynos: fix set_mmc_clk for exynos4x12Jaehoon Chung2013-12-031-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the set_mmc_clk() for exnos4x12. If board is exynos4x12, mmc clock should be set to wrong value. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-0623-148/+745
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| | * | | arm: omap3: Enable clocks for peripherals only if they are usedMichael Trimarchi2013-12-062-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch change the per_clocks_enable() function used in OMAP3 code to enable peripherals clocks. Only required clock should be activated. So if the board use the uart(x) as a console we need to activate it. The Board's config should include define to enable every subsystem that the board use. For a complete list of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER should be checked. Right now the bootloader can enable and disable clocks for: uart(x) using CONFIG_SYS_NS16550 gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 } i2c bus using CONFIG_DRIVER_OMAP34XX_I2C. Not required gptimer(x) and mcbsp(x) for booting are disabled by default and are not supported by any define. Their activation need to included in the per_clocks_enable if the peripheral is included. Not booting board should enable the peripheral clock connected to their driver Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| | * | | pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAMHardik Patel2013-12-042-2/+6
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Hardik Patel <hardik.patel@volansystech.com>
| | * | | davinci: fix Master Priority Registers locationViktar Palstsiuk2013-12-041-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at 0x01C14114 Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk@promwad.com>
| | * | | arm: omap3: Add uart4 omap3 adddressMichael Trimarchi2013-12-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the OMAP34XX_UART4 memory address Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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