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| * imx: mx6: crm_reg: add LCDIF related macrosPeng Fan2015-11-121-4/+30
| | | | | | | | | | | | | | | | | | Add i.MX6UL/SX LCDIF related macros. Discard uneccessary '#ifdef xxx'. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6: fix register addressPeng Fan2015-11-121-6/+12
| | | | | | | | | | | | | | | | | | | | | | 1. Move WDOG3_BASE_ADDR to '#if !(defined(__ASSEMBLY__))'. 2. Add i.MX6UL LCDIF register base address. And Introduce LCDIF1_BASE_ADDR to support runtime check. 3. include <asm/imx-common/regs-lcdif.h> for imx-regs.h to avoid building error for mxsfb.c, since mxsfb.c use imx-regs.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: lcdif: use one register structure for i.MXesPeng Fan2015-11-122-102/+22
| | | | | | | | | | | | | | | | | | Share one lcdif structure for i.MXes. 1. Discard struct mxs_lcdif_regs from imx-regs.h of i.MX7 2. Add i.MX6SX/6UL/7D support in imx-lcdif.h of imx-common Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: imx-common: move lcdif structure and macro definition to imx-commonPeng Fan2015-11-122-1/+1
| | | | | | | | | | | | | | | | Move 'struct mxs_lcdif_regs' and lcdif related macro definitions to arch/arm/include/asm/imx-common/regs-lcdif.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * imx: include linux/types.h for regs-common.hPeng Fan2015-11-121-0/+2
| | | | | | | | | | | | | | | | There are uint8_t, uint32_t types in regs-common.h, so include linux/types.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: regs-common.h must be wrapped with !__ASSEMBLY__Peng Fan2015-11-121-1/+1
| | | | | | | | | | | | | | regs-common.h must be wrapped with #ifndef __ASSEMBLY__ Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: add parameter base_addr for mxs_set_lcdclkPeng Fan2015-11-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | Change mxs_set_lcdclk prototype to add a new parameter base_addr. There are two LCD interfaces for i.MX6SX, we may support LCDIF1 or LCDIF2. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * mx7: psci: add basic psci supportPeng Fan2015-11-125-0/+139
| | | | | | | | | | | | | | | | | | | | | | | | 1. add basic psci support for imx7 chip. 2. support cpu_on and cpu_off. 3. switch to non-secure mode when boot linux kernel. 4. set csu allow accessing all peripherial register in non-secure mode. Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * arm: discard relocation entries for secure textPeng Fan2015-11-121-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code such as PSCI in section named secure is bundled with u-boot image, and when bootm, the code will be copied to their runtime address same to compliation/linking address - CONFIG_ARMV7_SECURE_BASE. When compile the PSCI code and link it into the u-boot image, there will be relocation entries in .rel.dyn section for PSCI. Actually, we do not needs these relocation entries. If still keep the relocation entries in .rel.dyn section, r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid address which may not support read/write for one SoC. 102 /* relative fix: increase location by offset */ 103 add r0, r0, r4 104 ldr r1, [r0] 105 add r1, r1, r4 106 str r1, [r0] So discard them to avoid touching the relocation entry in arch/arm/lib/relocate.S. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Tom Warren <twarren@nvidia.com> Cc: York Sun <yorksun@freescale.com> Cc: Hans De Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com> Cc: Jan Kiszka <jan.kiszka@siemens.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| * Merge git://git.denx.de/u-bootStefano Babic2015-11-12208-1954/+4699
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| * | imx: hab: add mx7 secure boot supportAdrian Alonso2015-10-301-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mx7 secure boot support, add helper macro IS_HAB_ENABLED_BIT to get the corresponding bit mask per SoC (mx7 or mx6) to identify if securue boot feature is enabled/disabled. On authenticate_image only check for mmu enabled on mx6 SoC to force pu_irom_mmu_enabled so ROM code can perform mmu cache flush mx7 SoC ROM code does not have this issue as ROM enables cache support based on fuse settings. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: hab: use read_fuse for secure boot settingsAdrian Alonso2015-10-301-5/+12
| | | | | | | | | | | | | | | | | | | | | Use read_fuse api fuction call to read secure boot fuse settings (enabled/disabled). Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | arm: imx: add secure boot fuse details for imx7 SoCAdrian Alonso2015-10-301-0/+8
| | | | | | | | | | | | | | | | | | | | | Add secure boot fuse details (location) bank = 1, word = 3; for imx7 SoC platforms. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | arm: imx: add secure boot fuse details for imx6 SoCAdrian Alonso2015-10-301-0/+8
| | | | | | | | | | | | | | | | | | | | | Add secure boot fuse details (location) bank = 0, word = 6; for imx6 SoC platforms. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: hab: add secure boot fuse detailsAdrian Alonso2015-10-301-0/+9
| | | | | | | | | | | | | | | | | | | | | Add secure boot fuse helper struct to abstract the way to find out secure boot settings per SoC iMX family Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: hab: rework unified rom section for mx7Adrian Alonso2015-10-301-0/+2
| | | | | | | | | | | | | | | | | | | | | Rework unified section macro select via Kconfig option instead of macro definition in mx7_common header file. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: hab: use unified rom section for mx6sx and mx6ulAdrian Alonso2015-10-303-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target platforms to resolve corresponding HAB_RVT_BASE base address, the RVT table contains pointers to the HAB API functions in ROM code. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: hab: rework secure boot support for imx6Adrian Alonso2015-10-304-2/+2
| | | | | | | | | | | | | | | | | | | | | Rework secure boot support for imx6, move existing hab support for imx6 into imx-common for SoC reuse. Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | imx: cpu: move common chip revision id'sAdrian Alonso2015-10-305-19/+13
| | | | | | | | | | | | | | | | | | | | | Move common chip revision id's to main cpu header file mx25 generic include cpu header for chip revision Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | arm, imx: add some gpr register definesHeiko Schocher2015-10-301-0/+35
| | | | | | | | | | | | | | | | | | add some missing gpr register defines. Signed-off-by: Heiko Schocher <hs@denx.de>
| * | imx-common: timer: clean up codePeng Fan2015-10-301-73/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can reuse common functions in lib/time.c, but not reimplement functions in imx-common/time.c. Only keep timer_init ,get_tbclk and implement timer_read_counter in imx-common/time.c. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* | | Merge branch 'series1_v2' of git://git.denx.de/u-boot-sparcTom Rini2015-11-1319-735/+2135
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| * | | sparc: leon3: Add debug_uart support to LEON3 serial driver.Francois Retief2015-11-132-2/+30
| | | | | | | | | | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | sparc: ambapp: Removed warning and unnecessary printout.Daniel Hellstrom2015-11-131-1/+2
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | sparc: leon3: Moved GRLIB core header files to common include/grlib directoryDaniel Hellstrom2015-11-134-17/+20
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | sparc: leon3: Added memory controller initialization using new AMBA PnP ↵Daniel Hellstrom2015-11-135-2/+621
| | | | | | | | | | | | | | | | | | | | | | | | routines. Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | sparc: leon3: Reimplemented AMBA Plug&Play scanning routines.Daniel Hellstrom2015-11-137-415/+1225
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
| * | | sparc: Update startup code to take PIC mode into accountFrancois Retief2015-11-132-38/+82
| | | | | | | | | | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | sparc: Update LEON serial drivers to use readl/writel macrosFrancois Retief2015-11-135-138/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the LEON2/3 serial driver to make use of the readl and writel macros as well as the WATCHDOG_RESET() macro. Add readl/writel and friends to the asm/io.h file. Introduce the gd->arch.uart variable to store register address. Lastly, remove baudrate scaler macro variables from board config. It is now calculated in the serial driver using the global data variable. Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | sparc: Add -mcpu= compiler flags for LEON2/LEON3Francois Retief2015-11-131-4/+10
| | | | | | | | | | | | | | | | Signed-off-by: Francois Retief <fgretief@spaceteq.co.za>
| * | | sparc: Fix broken files during license changesFrancois Retief2015-11-132-130/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes broken search and replaced license changes in files cpu/leon3/start.S and include/asm/winmacro.h from commit 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Signed-off-by: Francois Retief <fgretief@spaceteq.co.za> Series-to: u-boot Series-cc: Tom Rini <trini@konsulko.com> Series-version: 2 Cover-letter: sparc: Updates to SPARC architecture in preperation for generic board This patch series is a backlog of preparation work for upcomming generic board changes. I first want to get these reviewed and submitted to mainline before sending out more patches. END
* | | | x86: Remove legacy pci codesBin Meng2015-11-133-71/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have converted all x86 boards to use driver model pci, remove these legacy pci codes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: qemu: Convert to use driver model pciBin Meng2015-11-132-50/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to driver model for pci on QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: qemu: Move chipset-specific codes from pci.c to qemu.cBin Meng2015-11-132-72/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move chipset-specific codes such as PAM init, PCIe ECAM and MP table from pci.c to qemu.c, to prepare for DM PCI conversion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: qemu: Remove call to vgabios executionBin Meng2015-11-131-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The call to pci_run_vga_bios() is not needed as this is handled in the vesa_fb driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: queensbay: Really disable IGDBin Meng2015-11-132-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA display controller class in the PCI configuration space, and should also prevent it from responding to VGA legacy memory range and I/O addresses. However test result shows that with just VGA Disable bit set and a PCIe graphics card connected to one of the PCIe controllers on the E6xx, accessing the VGA legacy space still causes system hang. After a number of attempts, it turns out besides VGA Disable bit, the SDVO (D3:F0) device should be disabled to make it work. To simplify, use the Function Disable register (offset 0xc4) to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these two devices will be completely disabled (invisible in the PCI configuration space) unless a system reset is performed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Move CONFIG_8259_PIC and CONFIG_8254_TIMER to KconfigBin Meng2015-11-131-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Kconfig options for 8259 and 8254. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Rename pcat_ to i8254 and i8259 accordinglyBin Meng2015-11-136-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c, to match their header file names (i8254.h and i8259.h). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Initialize i8254 timer counter 1Bin Meng2015-11-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize counter 1, used to refresh request signal. This is required for legacy purpose as some codes like vgabios utilizes counter 1 to provide delay functionality. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Fix cosmetic issues in the i8254 and i8259 codesBin Meng2015-11-134-53/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleans up i8254 and i8259 codes to fix several cosmetic issues, like coding convention and some comments improvement. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Remove dead codes wrapped by PARANOID_IRQ_TRIGGERSBin Meng2015-11-131-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PARANOID_IRQ_TRIGGERS is not referenced anywhere in U-Boot. Remove these dead codes wrapped by it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | | x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQSBin Meng2015-11-133-12/+10
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_NUM_IRQS is actually not something we can configure, but an architecture defined number of ISA IRQs. Move it from x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-11-1215-634/+807
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| * | | ARM: tegra: note that p2371-2180 is Jetson TX1Stephen Warren2015-11-121-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p2371-2180 is the engineering board name for the Jetson TX1 developer kit. Update Kconfig description and help text to make this obvious to everyone. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: rename GPU functionsAlexandre Courbot2015-11-123-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename GPU functions to less generic names to avoid potential name collisions. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: simplify GPU setupAlexandre Courbot2015-11-121-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the GPU node in the system-wide ft_system_setup() hook instead of the board-specific ft_board_hook(). This allows us to enable GPU per SoC generation instead of per-board as we did initially. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: remove vpr_configured() functionAlexandre Courbot2015-11-122-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no justification for this function, especially in exported form. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: error check Tegra210 XUSB padctl waitsStephen Warren2015-11-121-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to detect timeouts when waiting for HW events such as PLL lock done. Any errors are logged and trigger an error return code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: add lane tables to Tegra210 XUSB padctlStephen Warren2015-11-122-6/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the tables defining which pads and mux options exist in the Tegra210 XUSB padctl hardware. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | | ARM: tegra: switch Tegra210 to common XUSB padctlStephen Warren2015-11-122-158/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change simply deletes code from the Tegra210 XUSB padctl driver that is already present in the common XUSB padctl code. Since all the arrays in tegra210_socdata are empty, this update may leave the Tegra210 XUSB padctl driver non-functional at run-time. However, (a) this driver is not used yet so no regression can be observed and (b) the next commit will immediately fix this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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