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* nios2: add flush_dcache_range functionStefan Kristiansson2012-02-231-0/+10
| | | | | | | | | exposes functionality to flush dcache according to the common.h API Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> Cc: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* Merge branch 'master' of git://git.denx.de/u-boot-mmcWolfgang Denk2012-02-174-4/+4
|\ | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mmc: mmc: make mmc_send_status() more reliable mmc: fix card busy polling Tegra: mmc: Fixed handling of interrupts in timeouts. omap_hsmmc: Wait for CMDI to be clear
| * omap_hsmmc: Wait for CMDI to be clearTom Rini2012-02-154-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before we can send a command we need both the DATI (command inhibit on mmc_dat line) bit and CMDI (command inhibit on mmc_cmd line) are clear. The previous behavior of only checking on DATI was insufficient on some cards and incorrect behavior in any case. This makes the code check for both bits being clear and makes the error print more clear as to what happened. DATI_CMDDIS is removed as it was unused elsewhere in the code and stood for 'DATI is set, cmds are disabled still'. Fix originally spotted by Peter Bigot. Tested-by: Peter A. Bigot <bigotp@acm.org> Tested-by: Robert Nelson <robertcnelson@gmail.com> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Andreas Müller <schnitzeltony@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2012-02-171-16/+31
|\ \ | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/8xxx:Add MPH controller support in USB device-tree fixup powerpc/8xxx: Cleanup USB device-tree fixup
| * | powerpc/8xxx:Add MPH controller support in USB device-tree fixupramneek mehresh2012-02-151-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add support for fixing usb mode and phy type for MPH(Multi Port Host) USB controllers in device-tree nodes. Required for socs like P3060, P5020, etc having MPH USB controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
| * | powerpc/8xxx: Cleanup USB device-tree fixupramneek mehresh2012-02-151-6/+12
| |/ | | | | | | | | | | | | | | | | Some code cleanup done for USB device-tree fixup: - handling error value returned from fdt_fixup_usb_mode_phy_type() - using ARRAY_SIZE macro - using snprintf instead of sprintf Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Wolfgang Denk2012-02-1721-513/+1152
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-x86: x86: Convert board_init_f_r to a processing loop x86: Split init functions out of board.c x86: Move relocation code out of board.c x86: Move setup_pcat_compatibility() out of board.c x86: Move do_go_exec() out of board.c CHECKPATCH: arch/x86/lib/* x86: Tweak IDT and GDT for alignment and readability x86: Allow cache before copy to RAM x86: Create weak init_cache() and default enable_caches() functions x86: Set GD_FLG_RELOC after entering in-RAM copy of U-Boot x86: Use fs for global data x86: Rework relocation calculations x86: Simplify Flash-to-RAM code execution transition x86: Rework Global Descriptor Table loading x86: Remove GDR related magic numbers x86: Speed up copy-to-RAM and clear BSS operations x86: Import glibc memcpy implementation
| * \ Merge branch 'staging'Graeme Russ2012-01-2121-513/+1152
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| | * | x86: Convert board_init_f_r to a processing loopGraeme Russ2012-01-045-125/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create an init function array for board_init_f_r - This finalises the migration to a purely array based initialisation mechanism Also tweak a few comments while we are at it so everything is 'correct' -- Changes for v2: - Renamed to a more apt name - Fix bug in set_reloc_flag_r - Re-instate gd->flags = boot_flags; in board_init_f - Added commit message
| | * | x86: Split init functions out of board.cGraeme Russ2012-01-046-221/+438
| | | | | | | | | | | | | | | | | | | | | | | | This patch moves towards reducing board.c to simply a set of init cores for the three initialisation phases (Flash, Flash/RAM, and RAM), a set of three init function arrays and a init function array processing function
| | * | x86: Move relocation code out of board.cGraeme Russ2012-01-043-67/+118
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| | * | x86: Move setup_pcat_compatibility() out of board.cGraeme Russ2012-01-042-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function simply does not belong in board.c -- Changes for v2: - Added commit message
| | * | x86: Move do_go_exec() out of board.cGraeme Russ2012-01-043-27/+65
| | | | | | | | | | | | | | | | | | | | | | | | -- Changes for v2: - None
| | * | CHECKPATCH: arch/x86/lib/*Graeme Russ2012-01-042-73/+122
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| | * | x86: Tweak IDT and GDT for alignment and readabilityGraeme Russ2012-01-042-13/+46
| | | | | | | | | | | | | | | | | | | | | | | | -- Changes for v2: - Renamed to better reflect nature of changes
| | * | x86: Allow cache before copy to RAMGraeme Russ2012-01-041-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | -- Changes for v2: - None
| | * | x86: Create weak init_cache() and default enable_caches() functionsGraeme Russ2012-01-043-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | -- Changes for v2: - Tweaked commit title
| | * | x86: Set GD_FLG_RELOC after entering in-RAM copy of U-BootGraeme Russ2012-01-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | -- Changes for v2: - None
| | * | x86: Use fs for global dataGraeme Russ2012-01-046-47/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the base address of the 'F' segment as a pointer to the global data structure. By adding the linear address (i.e. the 'D' segment address) as the first word of the global data structure, the address of the global data relative to the 'D' segment can be found simply, for example, by: fs movl 0, %eax This makes the gd 'pointer' writable prior to relocation (by reloading the Global Desctriptor Table) which brings x86 into line with all other arches NOTE: Writing to the gd 'pointer' is expensive (but we only do it twice) but using it to access global data members (read and write) is still fairly cheap -- Changes for v2: - Rebased against changes made to patch #3 - Removed extra indent - Tweaked commit message
| | * | x86: Rework relocation calculationsGraeme Russ2012-01-041-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces no functional changes - It simply re-arranges the calculations so that adding to them in future commits will be cleaner -- Changes for v2: - Fixed typo in title - Added commit message
| | * | x86: Simplify Flash-to-RAM code execution transitionGraeme Russ2012-01-043-19/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the relocation offset calculation out of assembler and into C. This also paves the way for the upcoming init sequence simplification by adding the board_init_f_r flash to RAM transitional function -- Changes for v2: - Added commit message - Minor adjustment to new stack address comment
| | * | x86: Rework Global Descriptor Table loadingGraeme Russ2012-01-041-29/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The inline assembler is ugly and uses hard coded magic numbers. Make it more elegant to allow cleaner implementation of future GDT related patches. The compiler seems smart enough to generate the same code anyway -- Changes for v2: - Rebased against revised patch #3 - Use GDT size define instead of magic number - Added commit message
| | * | x86: Remove GDR related magic numbersGraeme Russ2012-01-043-9/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -- Changes for v2: - Use an enum - Add defined for GDT size (previously added in patch 7) - Use X86_ namespace (as per Linux headers)
| | * | x86: Speed up copy-to-RAM and clear BSS operationsGraeme Russ2012-01-041-12/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementations of memcpy and memset are now the optimised versions from glibc, so use them instead of simple copy loops -- Changes for v2: - Removed unneeded brackets
| | * | x86: Import glibc memcpy implementationGraeme Russ2012-01-022-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Taken from glibc version 2.14.90 -- Changes for v2: - None
* | | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2012-02-137-53/+9
|\ \ \ \ | |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-blackfin: Blackfin: pata_bfin: fix printf warning Blackfin: bfin_nand: mark local func static linkage.h: move from blackfin to common includes Blackfin: br4: new board port Blackfin: add in/out le32 variants post: add blackfin to the post_time_ms list Blackfin: bf537-stamp: drop board reset workaround Blackfin: pr1: new board port
| * | | linkage.h: move from blackfin to common includesMacpaul Lin2012-02-126-53/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add linkage.h support from blackfin to common include, which is a reduced version from Linux. 2. Add architecture part support of linkage.h into blackfin 3. Fix include path of in blackfin related to linkage.h due to header file movement. Signed-off-by: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | | Blackfin: add in/out le32 variantsMike Frysinger2012-02-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These are rarely used, but the post code does currently, so add small redirect hacks for that. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | | Changes to move hawkboard to the new spl infrastructureSughosh Ganu2012-02-123-11/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves hawkboard to the new spl infrastructure from the older nand_spl one. Removed the hawkboard_nand_config build option -- The spl code now gets compiled with hawkboard_config, after building the main u-boot image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard to reflect the same. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Christian Riesch <christian.riesch@omicron.at> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: Christian Riesch <christian.riesch@omicron.at>
* | | | arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not definedChristian Riesch2012-02-121-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* | | | arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGHChristian Riesch2012-02-121-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The V bit of the c1 register of CP15 should not be cleared on DA850 SoCs since they have no valid memory at 0x00000000. This patch introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH that allows setting the correct value for the V bit. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Reported-by: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Sughosh Ganu <urwithsughosh@gmail.com> Cc: Heiko Schocher <hs@denx.de>
* | | | arm, arm926ejs: Flush the data cache before disabling itSughosh Ganu2012-02-121-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead. Also fix the comments to match code. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com> Rebased and corrected commit message. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* | | | arm, arm926ejs: Do cpu critical inits only for boards that require itChristian Riesch2012-02-121-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416 "arm, arm926ejs: always do cpu critical inits" since it impacts all arm926ejs based configurations and caused problems, e.g., with the hawkboard. Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines from the board configurations that need low level initialization. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* | | | arm, davinci: Add lowlevel_init for SoCs other than DM644XChristian Riesch2012-02-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X. Signed-off-by: Christian Riesch <christian.riesch@omicron.at> Cc: Tom Rini <trini@ti.com> Cc: Sergey Kubushyn <ksi@koi8.net> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* | | | ARMV7: Fix duplicate use of "b" parameter in ACTIM_CTRLA definitionPeter Barada2012-02-121-28/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACTIM_CTRLA macro errently passes "b" parameter to ACTIM_CTRLA_TRAS() instead of "c". To make usage more clear, replace all single-letter macro parameters with more descriptive parameter names. Signed-off-by: Peter Barada <peter.barada@logicpd.com>
* | | | OMAP4460: Reduce MPU clock speed from 920 to 700Aneesh V2012-02-121-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not have thermal management or Smartreflex enabled at U-Boot level. So, it's better to stick to OPP100 for MPU instead of the OPP Turbo that is used now. Adjust the VDD_MPU accordingly. Tested-by: Sebastien Jan <s-jan@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com>
* | | | davinci: add support for printing clock frequencyHadli, Manjunath2012-02-123-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for printing various clock frequency info found in SOC such as ARM core frequency, DSP core frequency and DDR frequency as part of bdinfo command. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com>
* | | | davinci: remove macro CONFIG_DISPLAY_CPUINFOHadli, Manjunath2012-02-121-44/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer required. This is because clock info will be printed as part 'bdinfo' command and also remove support print_cpuinfo() as it will no longer be called. Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com> Cc: Tom Rini <trini@ti.com>
* | | | omap3: fix comment typosPeter Meerwald2012-02-121-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
* | | | AM3517: Changed default clock rate for AM3517Schuyler Patton2012-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM3517: Changed default clock rate for AM3517 Changed #define MPU_M_13_ES2 from 0x1F4 to 0x258, this allows the AM3517 to boot up at 600MHz instead of 500 MHz Signed-off-by: Schuyler Patton <spatton@ti.com> CC: Tom Rini <tom.rini@gmail.com> CC: Simon Schwarz <simonschwarzcor@gmail.com> CC: Stefano Babic <sbabic@denx.de>
* | | | OMAP4: clock-common: Move the usb dppl configuration to new funcGovindraj.R2012-02-121-21/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usb dpll configuration is done only part of non-essential dppl configuration however if CONFIG_USB_EHCI_OMAP is defined we may have to configure usb dpll's for proper functioning of usb modules. So move the usb dppl configuration to a new func. and utilise the same during essential dpll configuration. Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* | | | OMAP3+: Clock: Adding ehci clock enablingGovindraj.R2012-02-124-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding ehci clock enabling mechanism part of clock framework. When essential clocks are enabled during init phase usb host clocks can also be enabled from clock framework. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com> Tested-by: Stefano Babic <sbabic@denx.de>
* | | | ehci-omap: Clean up added ehci-omap.cGovindraj.R2012-02-123-24/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up added ehci-omap.c and make it generic for re-use across omap-soc having same ehci ip block. Also pass the modes to be configured from board file and configure the ports accordingly. All usb layers are not cache aligned, till then keep cache off for usb ops as ehci will use internally dma for all usb ops. * Add a generic common header ehci-omap.h having common ip block data and reg shifts. * Rename and modify ehci-omap3 to ehci.h retain only conflicting sysc reg shifts remove others and move to common header file. * pass the board data for beagle/panda accordinly to use ehci ports. Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
* | | | ARM: EXYNOS: Add support for Exynos5 based SoCsChander Kashyap2012-02-126-12/+854
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macroChander Kashyap2012-02-121-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_CLK_FREQ_C210 macro giving notion of S5PC2XX (Exynos4) architecture. Replace CONFIG_SYS_CLK_FREQ_C210 with CONFIG_SYS_CLK_FREQ to make it generic for exynos architecture. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | S5P: support generic watchdog timerMinkyu Kang2012-02-125-1/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support the generic watchdog timer for s5pc1xx and exynos4 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: HeungJun, Kim <riverful.kim@samsung.com>
* | | | ARMV7: Exynos4: Add supoort power for Exynos4HeungJun, Kim2012-02-122-0/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds power.h and SAMSUNG_BASE() macro for using Exynos4 power. Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | ARMV7: Exynos4: Add watchdog.h for Exynos4HeungJun, Kim2012-02-121-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add watchdog.h for Exynos4 Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | Exynos: Fix ARM Clock frequency calculationChander Kashyap2012-02-121-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Earliar ARM clock frequency was calculated by: MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL. It is fixed by calculating it as follows: ARMCLK=MOUTCORE / (DIVCORE + 1) / (DIVCORE2 + 1) Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | | Exynos: PWM: Add TCMPB3 field in pwm structureChander Kashyap2012-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add TCMPB3 field in pwm structure, earliar this was res1. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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